xref: /linux/arch/arm64/boot/dts/sprd/sc9836.dtsi (revision b7019ac550eb3916f34d79db583e9b7ea2524afa) 
1/*
2 * Spreadtrum SC9836 SoC DTS file
3 *
4 * Copyright (C) 2014, Spreadtrum Communications Inc.
5 *
6 * This file is licensed under a dual GPLv2 or X11 license.
7 */
8
9#include "sharkl64.dtsi"
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12/ {
13	compatible = "sprd,sc9836";
14
15	cpus {
16		#address-cells = <2>;
17		#size-cells = <0>;
18
19		cpu0: cpu@0 {
20			device_type = "cpu";
21			compatible = "arm,cortex-a53";
22			reg = <0x0 0x0>;
23			enable-method = "psci";
24		};
25
26		cpu1: cpu@1 {
27			device_type = "cpu";
28			compatible = "arm,cortex-a53";
29			reg = <0x0 0x1>;
30			enable-method = "psci";
31		};
32
33		cpu2: cpu@2 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a53";
36			reg = <0x0 0x2>;
37			enable-method = "psci";
38		};
39
40		cpu3: cpu@3 {
41			device_type = "cpu";
42			compatible = "arm,cortex-a53";
43			reg = <0x0 0x3>;
44			enable-method = "psci";
45		};
46	};
47
48	etf@10003000 {
49		compatible = "arm,coresight-tmc", "arm,primecell";
50		reg = <0 0x10003000 0 0x1000>;
51		clocks = <&clk26mhz>;
52		clock-names = "apb_pclk";
53		in-ports {
54			port {
55				etf_in: endpoint {
56					remote-endpoint = <&funnel_out_port0>;
57				};
58			};
59		};
60	};
61
62	funnel@10001000 {
63		compatible = "arm,coresight-funnel", "arm,primecell";
64		reg = <0 0x10001000 0 0x1000>;
65		clocks = <&clk26mhz>;
66		clock-names = "apb_pclk";
67
68		out-ports {
69			port {
70				funnel_out_port0: endpoint {
71					remote-endpoint = <&etf_in>;
72				};
73			};
74		};
75
76		in-ports {
77			#address-cells = <1>;
78			#size-cells = <0>;
79
80			port@0 {
81				reg = <0>;
82				funnel_in_port0: endpoint {
83					remote-endpoint = <&etm0_out>;
84				};
85			};
86
87			port@1 {
88				reg = <1>;
89				funnel_in_port1: endpoint {
90					remote-endpoint = <&etm1_out>;
91				};
92			};
93
94			port@2 {
95				reg = <2>;
96				funnel_in_port2: endpoint {
97					remote-endpoint = <&etm2_out>;
98				};
99			};
100
101			port@3 {
102				reg = <3>;
103				funnel_in_port3: endpoint {
104					remote-endpoint = <&etm3_out>;
105				};
106			};
107
108			port@4 {
109				reg = <4>;
110				funnel_in_port4: endpoint {
111					remote-endpoint = <&stm_out>;
112				};
113			};
114			/* Other input ports aren't connected to anyone */
115		};
116	};
117
118	etm@10440000 {
119		compatible = "arm,coresight-etm4x", "arm,primecell";
120		reg = <0 0x10440000 0 0x1000>;
121
122		cpu = <&cpu0>;
123		clocks = <&clk26mhz>;
124		clock-names = "apb_pclk";
125		out-ports {
126			port {
127				etm0_out: endpoint {
128					remote-endpoint = <&funnel_in_port0>;
129				};
130			};
131		};
132	};
133
134	etm@10540000 {
135		compatible = "arm,coresight-etm4x", "arm,primecell";
136		reg = <0 0x10540000 0 0x1000>;
137
138		cpu = <&cpu1>;
139		clocks = <&clk26mhz>;
140		clock-names = "apb_pclk";
141		out-ports {
142			port {
143				etm1_out: endpoint {
144					remote-endpoint = <&funnel_in_port1>;
145				};
146			};
147		};
148	};
149
150	etm@10640000 {
151		compatible = "arm,coresight-etm4x", "arm,primecell";
152		reg = <0 0x10640000 0 0x1000>;
153
154		cpu = <&cpu2>;
155		clocks = <&clk26mhz>;
156		clock-names = "apb_pclk";
157		out-ports {
158			port {
159				etm2_out: endpoint {
160					remote-endpoint = <&funnel_in_port2>;
161				};
162			};
163		};
164	};
165
166	etm@10740000 {
167		compatible = "arm,coresight-etm4x", "arm,primecell";
168		reg = <0 0x10740000 0 0x1000>;
169
170		cpu = <&cpu3>;
171		clocks = <&clk26mhz>;
172		clock-names = "apb_pclk";
173		out-ports {
174			port {
175				etm3_out: endpoint {
176					remote-endpoint = <&funnel_in_port3>;
177				};
178			};
179		};
180	};
181
182	stm@10006000 {
183		compatible = "arm,coresight-stm", "arm,primecell";
184		reg = <0 0x10006000 0 0x1000>,
185		      <0 0x01000000 0 0x180000>;
186		reg-names = "stm-base", "stm-stimulus-base";
187		clocks = <&clk26mhz>;
188		clock-names = "apb_pclk";
189		out-ports {
190			port {
191				stm_out: endpoint {
192					remote-endpoint = <&funnel_in_port4>;
193				};
194			};
195		};
196	};
197
198	gic: interrupt-controller@12001000 {
199		compatible = "arm,gic-400";
200		reg = <0 0x12001000 0 0x1000>,
201		      <0 0x12002000 0 0x2000>,
202		      <0 0x12004000 0 0x2000>,
203		      <0 0x12006000 0 0x2000>;
204		#interrupt-cells = <3>;
205		interrupt-controller;
206		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
207	};
208
209	psci {
210		compatible	= "arm,psci";
211		method		= "smc";
212		cpu_on		= <0xc4000003>;
213		cpu_off		= <0x84000002>;
214		cpu_suspend	= <0xc4000001>;
215	};
216
217	timer {
218		compatible = "arm,armv8-timer";
219		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
220			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
221			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
222			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
223	};
224};
225