xref: /linux/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts (revision fa84cf094ef9667e2b91c104b0a788fd1896f482) 
1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Device Tree Source for UniPhier PXs3 Reference Board
4//
5// Copyright (C) 2017 Socionext Inc.
6//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7
8/dts-v1/;
9#include "uniphier-pxs3.dtsi"
10#include "uniphier-support-card.dtsi"
11
12/ {
13	model = "UniPhier PXs3 Reference Board";
14	compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
15
16	chosen {
17		stdout-path = "serial0:115200n8";
18	};
19
20	aliases {
21		serial0 = &serial0;
22		serial1 = &serial1;
23		serial2 = &serial2;
24		serial3 = &serial3;
25		i2c0 = &i2c0;
26		i2c1 = &i2c1;
27		i2c2 = &i2c2;
28		i2c3 = &i2c3;
29		i2c6 = &i2c6;
30	};
31
32	memory@80000000 {
33		device_type = "memory";
34		reg = <0 0x80000000 0 0xa0000000>;
35	};
36};
37
38&ethsc {
39	interrupts = <4 8>;
40};
41
42&serial0 {
43	status = "okay";
44};
45
46&serial2 {
47	status = "okay";
48};
49
50&serial3 {
51	status = "okay";
52};
53
54&gpio {
55	xirq4 {
56		gpio-hog;
57		gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
58		input;
59	};
60};
61
62&i2c0 {
63	status = "okay";
64};
65
66&i2c1 {
67	status = "okay";
68};
69
70&i2c2 {
71	status = "okay";
72};
73
74&i2c3 {
75	status = "okay";
76};
77
78&eth0 {
79	status = "okay";
80	phy-handle = <&ethphy0>;
81};
82
83&mdio0 {
84	ethphy0: ethphy@0 {
85		reg = <0>;
86	};
87};
88
89&eth1 {
90	status = "okay";
91	phy-handle = <&ethphy1>;
92};
93
94&mdio1 {
95	ethphy1: ethphy@0 {
96		reg = <0>;
97	};
98};
99
100&nand {
101	status = "okay";
102};
103