xref: /linux/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts (revision b8265621f4888af9494e1d685620871ec81bc33d) 
1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Device Tree Source for UniPhier PXs3 Reference Board
4//
5// Copyright (C) 2017 Socionext Inc.
6//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7
8/dts-v1/;
9#include "uniphier-pxs3.dtsi"
10#include "uniphier-support-card.dtsi"
11
12/ {
13	model = "UniPhier PXs3 Reference Board";
14	compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
15
16	chosen {
17		stdout-path = "serial0:115200n8";
18	};
19
20	aliases {
21		serial0 = &serial0;
22		serial1 = &serial1;
23		serial2 = &serial2;
24		serial3 = &serial3;
25		i2c0 = &i2c0;
26		i2c1 = &i2c1;
27		i2c2 = &i2c2;
28		i2c3 = &i2c3;
29		i2c6 = &i2c6;
30		spi0 = &spi0;
31		spi1 = &spi1;
32		ethernet0 = &eth0;
33		ethernet1 = &eth1;
34	};
35
36	memory@80000000 {
37		device_type = "memory";
38		reg = <0 0x80000000 0 0xa0000000>;
39	};
40};
41
42&ethsc {
43	interrupts = <4 8>;
44};
45
46&spi0 {
47	status = "okay";
48};
49
50&spi1 {
51	status = "okay";
52};
53
54&serial0 {
55	status = "okay";
56};
57
58&serial2 {
59	status = "okay";
60};
61
62&serial3 {
63	status = "okay";
64};
65
66&gpio {
67	xirq4 {
68		gpio-hog;
69		gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
70		input;
71	};
72};
73
74&i2c0 {
75	status = "okay";
76};
77
78&i2c1 {
79	status = "okay";
80};
81
82&i2c2 {
83	status = "okay";
84};
85
86&i2c3 {
87	status = "okay";
88};
89
90&sd {
91	status = "okay";
92};
93
94&eth0 {
95	status = "okay";
96	phy-handle = <&ethphy0>;
97};
98
99&mdio0 {
100	ethphy0: ethphy@0 {
101		reg = <0>;
102	};
103};
104
105&eth1 {
106	status = "okay";
107	phy-handle = <&ethphy1>;
108};
109
110&mdio1 {
111	ethphy1: ethphy@0 {
112		reg = <0>;
113	};
114};
115
116&usb0 {
117	status = "okay";
118};
119
120&usb1 {
121	status = "okay";
122};
123
124&pcie {
125	status = "okay";
126};
127
128&nand {
129	status = "okay";
130
131	nand@0 {
132		reg = <0>;
133	};
134};
135
136&pinctrl_ether_rgmii {
137	tx {
138		pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1",
139		       "RGMII0_TXD2", "RGMII0_TXD3", "RGMII0_TXCTL";
140		drive-strength = <9>;
141	};
142};
143
144&pinctrl_ether1_rgmii {
145	tx {
146		pins = "RGMII1_TXCLK", "RGMII1_TXD0", "RGMII1_TXD1",
147		       "RGMII1_TXD2", "RGMII1_TXD3", "RGMII1_TXCTL";
148		drive-strength = <9>;
149	};
150};
151