1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/power/rk3588-power.h> 10#include <dt-bindings/reset/rockchip,rk3588-cru.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/ata/ahci.h> 13 14/ { 15 compatible = "rockchip,rk3588"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 gpio2 = &gpio2; 25 gpio3 = &gpio3; 26 gpio4 = &gpio4; 27 i2c0 = &i2c0; 28 i2c1 = &i2c1; 29 i2c2 = &i2c2; 30 i2c3 = &i2c3; 31 i2c4 = &i2c4; 32 i2c5 = &i2c5; 33 i2c6 = &i2c6; 34 i2c7 = &i2c7; 35 i2c8 = &i2c8; 36 serial0 = &uart0; 37 serial1 = &uart1; 38 serial2 = &uart2; 39 serial3 = &uart3; 40 serial4 = &uart4; 41 serial5 = &uart5; 42 serial6 = &uart6; 43 serial7 = &uart7; 44 serial8 = &uart8; 45 serial9 = &uart9; 46 spi0 = &spi0; 47 spi1 = &spi1; 48 spi2 = &spi2; 49 spi3 = &spi3; 50 spi4 = &spi4; 51 }; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 57 cpu-map { 58 cluster0 { 59 core0 { 60 cpu = <&cpu_l0>; 61 }; 62 core1 { 63 cpu = <&cpu_l1>; 64 }; 65 core2 { 66 cpu = <&cpu_l2>; 67 }; 68 core3 { 69 cpu = <&cpu_l3>; 70 }; 71 }; 72 cluster1 { 73 core0 { 74 cpu = <&cpu_b0>; 75 }; 76 core1 { 77 cpu = <&cpu_b1>; 78 }; 79 }; 80 cluster2 { 81 core0 { 82 cpu = <&cpu_b2>; 83 }; 84 core1 { 85 cpu = <&cpu_b3>; 86 }; 87 }; 88 }; 89 90 cpu_l0: cpu@0 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a55"; 93 reg = <0x0>; 94 enable-method = "psci"; 95 capacity-dmips-mhz = <530>; 96 clocks = <&scmi_clk SCMI_CLK_CPUL>; 97 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; 98 assigned-clock-rates = <816000000>; 99 cpu-idle-states = <&CPU_SLEEP>; 100 i-cache-size = <32768>; 101 i-cache-line-size = <64>; 102 i-cache-sets = <128>; 103 d-cache-size = <32768>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 next-level-cache = <&l2_cache_l0>; 107 dynamic-power-coefficient = <228>; 108 #cooling-cells = <2>; 109 }; 110 111 cpu_l1: cpu@100 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a55"; 114 reg = <0x100>; 115 enable-method = "psci"; 116 capacity-dmips-mhz = <530>; 117 clocks = <&scmi_clk SCMI_CLK_CPUL>; 118 cpu-idle-states = <&CPU_SLEEP>; 119 i-cache-size = <32768>; 120 i-cache-line-size = <64>; 121 i-cache-sets = <128>; 122 d-cache-size = <32768>; 123 d-cache-line-size = <64>; 124 d-cache-sets = <128>; 125 next-level-cache = <&l2_cache_l1>; 126 dynamic-power-coefficient = <228>; 127 #cooling-cells = <2>; 128 }; 129 130 cpu_l2: cpu@200 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a55"; 133 reg = <0x200>; 134 enable-method = "psci"; 135 capacity-dmips-mhz = <530>; 136 clocks = <&scmi_clk SCMI_CLK_CPUL>; 137 cpu-idle-states = <&CPU_SLEEP>; 138 i-cache-size = <32768>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <128>; 141 d-cache-size = <32768>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <128>; 144 next-level-cache = <&l2_cache_l2>; 145 dynamic-power-coefficient = <228>; 146 #cooling-cells = <2>; 147 }; 148 149 cpu_l3: cpu@300 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a55"; 152 reg = <0x300>; 153 enable-method = "psci"; 154 capacity-dmips-mhz = <530>; 155 clocks = <&scmi_clk SCMI_CLK_CPUL>; 156 cpu-idle-states = <&CPU_SLEEP>; 157 i-cache-size = <32768>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <128>; 160 d-cache-size = <32768>; 161 d-cache-line-size = <64>; 162 d-cache-sets = <128>; 163 next-level-cache = <&l2_cache_l3>; 164 dynamic-power-coefficient = <228>; 165 #cooling-cells = <2>; 166 }; 167 168 cpu_b0: cpu@400 { 169 device_type = "cpu"; 170 compatible = "arm,cortex-a76"; 171 reg = <0x400>; 172 enable-method = "psci"; 173 capacity-dmips-mhz = <1024>; 174 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 175 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; 176 assigned-clock-rates = <816000000>; 177 cpu-idle-states = <&CPU_SLEEP>; 178 i-cache-size = <65536>; 179 i-cache-line-size = <64>; 180 i-cache-sets = <256>; 181 d-cache-size = <65536>; 182 d-cache-line-size = <64>; 183 d-cache-sets = <256>; 184 next-level-cache = <&l2_cache_b0>; 185 dynamic-power-coefficient = <416>; 186 #cooling-cells = <2>; 187 }; 188 189 cpu_b1: cpu@500 { 190 device_type = "cpu"; 191 compatible = "arm,cortex-a76"; 192 reg = <0x500>; 193 enable-method = "psci"; 194 capacity-dmips-mhz = <1024>; 195 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 196 cpu-idle-states = <&CPU_SLEEP>; 197 i-cache-size = <65536>; 198 i-cache-line-size = <64>; 199 i-cache-sets = <256>; 200 d-cache-size = <65536>; 201 d-cache-line-size = <64>; 202 d-cache-sets = <256>; 203 next-level-cache = <&l2_cache_b1>; 204 dynamic-power-coefficient = <416>; 205 #cooling-cells = <2>; 206 }; 207 208 cpu_b2: cpu@600 { 209 device_type = "cpu"; 210 compatible = "arm,cortex-a76"; 211 reg = <0x600>; 212 enable-method = "psci"; 213 capacity-dmips-mhz = <1024>; 214 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 215 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; 216 assigned-clock-rates = <816000000>; 217 cpu-idle-states = <&CPU_SLEEP>; 218 i-cache-size = <65536>; 219 i-cache-line-size = <64>; 220 i-cache-sets = <256>; 221 d-cache-size = <65536>; 222 d-cache-line-size = <64>; 223 d-cache-sets = <256>; 224 next-level-cache = <&l2_cache_b2>; 225 dynamic-power-coefficient = <416>; 226 #cooling-cells = <2>; 227 }; 228 229 cpu_b3: cpu@700 { 230 device_type = "cpu"; 231 compatible = "arm,cortex-a76"; 232 reg = <0x700>; 233 enable-method = "psci"; 234 capacity-dmips-mhz = <1024>; 235 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 236 cpu-idle-states = <&CPU_SLEEP>; 237 i-cache-size = <65536>; 238 i-cache-line-size = <64>; 239 i-cache-sets = <256>; 240 d-cache-size = <65536>; 241 d-cache-line-size = <64>; 242 d-cache-sets = <256>; 243 next-level-cache = <&l2_cache_b3>; 244 dynamic-power-coefficient = <416>; 245 #cooling-cells = <2>; 246 }; 247 248 idle-states { 249 entry-method = "psci"; 250 CPU_SLEEP: cpu-sleep { 251 compatible = "arm,idle-state"; 252 local-timer-stop; 253 arm,psci-suspend-param = <0x0010000>; 254 entry-latency-us = <100>; 255 exit-latency-us = <120>; 256 min-residency-us = <1000>; 257 }; 258 }; 259 260 l2_cache_l0: l2-cache-l0 { 261 compatible = "cache"; 262 cache-size = <131072>; 263 cache-line-size = <64>; 264 cache-sets = <512>; 265 cache-level = <2>; 266 cache-unified; 267 next-level-cache = <&l3_cache>; 268 }; 269 270 l2_cache_l1: l2-cache-l1 { 271 compatible = "cache"; 272 cache-size = <131072>; 273 cache-line-size = <64>; 274 cache-sets = <512>; 275 cache-level = <2>; 276 cache-unified; 277 next-level-cache = <&l3_cache>; 278 }; 279 280 l2_cache_l2: l2-cache-l2 { 281 compatible = "cache"; 282 cache-size = <131072>; 283 cache-line-size = <64>; 284 cache-sets = <512>; 285 cache-level = <2>; 286 cache-unified; 287 next-level-cache = <&l3_cache>; 288 }; 289 290 l2_cache_l3: l2-cache-l3 { 291 compatible = "cache"; 292 cache-size = <131072>; 293 cache-line-size = <64>; 294 cache-sets = <512>; 295 cache-level = <2>; 296 cache-unified; 297 next-level-cache = <&l3_cache>; 298 }; 299 300 l2_cache_b0: l2-cache-b0 { 301 compatible = "cache"; 302 cache-size = <524288>; 303 cache-line-size = <64>; 304 cache-sets = <1024>; 305 cache-level = <2>; 306 cache-unified; 307 next-level-cache = <&l3_cache>; 308 }; 309 310 l2_cache_b1: l2-cache-b1 { 311 compatible = "cache"; 312 cache-size = <524288>; 313 cache-line-size = <64>; 314 cache-sets = <1024>; 315 cache-level = <2>; 316 cache-unified; 317 next-level-cache = <&l3_cache>; 318 }; 319 320 l2_cache_b2: l2-cache-b2 { 321 compatible = "cache"; 322 cache-size = <524288>; 323 cache-line-size = <64>; 324 cache-sets = <1024>; 325 cache-level = <2>; 326 cache-unified; 327 next-level-cache = <&l3_cache>; 328 }; 329 330 l2_cache_b3: l2-cache-b3 { 331 compatible = "cache"; 332 cache-size = <524288>; 333 cache-line-size = <64>; 334 cache-sets = <1024>; 335 cache-level = <2>; 336 cache-unified; 337 next-level-cache = <&l3_cache>; 338 }; 339 340 l3_cache: l3-cache { 341 compatible = "cache"; 342 cache-size = <3145728>; 343 cache-line-size = <64>; 344 cache-sets = <4096>; 345 cache-level = <3>; 346 cache-unified; 347 }; 348 }; 349 350 firmware { 351 optee: optee { 352 compatible = "linaro,optee-tz"; 353 method = "smc"; 354 }; 355 356 scmi: scmi { 357 compatible = "arm,scmi-smc"; 358 arm,smc-id = <0x82000010>; 359 shmem = <&scmi_shmem>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 363 scmi_clk: protocol@14 { 364 reg = <0x14>; 365 #clock-cells = <1>; 366 }; 367 368 scmi_reset: protocol@16 { 369 reg = <0x16>; 370 #reset-cells = <1>; 371 }; 372 }; 373 }; 374 375 pmu-a55 { 376 compatible = "arm,cortex-a55-pmu"; 377 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; 378 }; 379 380 pmu-a76 { 381 compatible = "arm,cortex-a76-pmu"; 382 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; 383 }; 384 385 psci { 386 compatible = "arm,psci-1.0"; 387 method = "smc"; 388 }; 389 390 spll: clock-0 { 391 compatible = "fixed-clock"; 392 clock-frequency = <702000000>; 393 clock-output-names = "spll"; 394 #clock-cells = <0>; 395 }; 396 397 display_subsystem: display-subsystem { 398 compatible = "rockchip,display-subsystem"; 399 ports = <&vop_out>; 400 }; 401 402 timer { 403 compatible = "arm,armv8-timer"; 404 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 405 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 406 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 407 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, 408 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 409 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 410 }; 411 412 xin24m: clock-1 { 413 compatible = "fixed-clock"; 414 clock-frequency = <24000000>; 415 clock-output-names = "xin24m"; 416 #clock-cells = <0>; 417 }; 418 419 xin32k: clock-2 { 420 compatible = "fixed-clock"; 421 clock-frequency = <32768>; 422 clock-output-names = "xin32k"; 423 #clock-cells = <0>; 424 }; 425 426 pmu_sram: sram@10f000 { 427 compatible = "mmio-sram"; 428 reg = <0x0 0x0010f000 0x0 0x100>; 429 ranges = <0 0x0 0x0010f000 0x100>; 430 #address-cells = <1>; 431 #size-cells = <1>; 432 433 scmi_shmem: sram@0 { 434 compatible = "arm,scmi-shmem"; 435 reg = <0x0 0x100>; 436 }; 437 }; 438 439 usb_host0_ehci: usb@fc800000 { 440 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 441 reg = <0x0 0xfc800000 0x0 0x40000>; 442 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; 443 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 444 phys = <&u2phy2_host>; 445 phy-names = "usb"; 446 power-domains = <&power RK3588_PD_USB>; 447 status = "disabled"; 448 }; 449 450 usb_host0_ohci: usb@fc840000 { 451 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 452 reg = <0x0 0xfc840000 0x0 0x40000>; 453 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; 454 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 455 phys = <&u2phy2_host>; 456 phy-names = "usb"; 457 power-domains = <&power RK3588_PD_USB>; 458 status = "disabled"; 459 }; 460 461 usb_host1_ehci: usb@fc880000 { 462 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 463 reg = <0x0 0xfc880000 0x0 0x40000>; 464 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; 465 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 466 phys = <&u2phy3_host>; 467 phy-names = "usb"; 468 power-domains = <&power RK3588_PD_USB>; 469 status = "disabled"; 470 }; 471 472 usb_host1_ohci: usb@fc8c0000 { 473 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 474 reg = <0x0 0xfc8c0000 0x0 0x40000>; 475 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; 476 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 477 phys = <&u2phy3_host>; 478 phy-names = "usb"; 479 power-domains = <&power RK3588_PD_USB>; 480 status = "disabled"; 481 }; 482 483 usb_host2_xhci: usb@fcd00000 { 484 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 485 reg = <0x0 0xfcd00000 0x0 0x400000>; 486 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; 487 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, 488 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, 489 <&cru CLK_PIPEPHY2_PIPE_U3_G>; 490 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; 491 dr_mode = "host"; 492 phys = <&combphy2_psu PHY_TYPE_USB3>; 493 phy-names = "usb3-phy"; 494 phy_type = "utmi_wide"; 495 resets = <&cru SRST_A_USB3OTG2>; 496 snps,dis_enblslpm_quirk; 497 snps,dis-u2-freeclk-exists-quirk; 498 snps,dis-del-phy-power-chg-quirk; 499 snps,dis-tx-ipgap-linecheck-quirk; 500 snps,dis_rxdet_inp3_quirk; 501 status = "disabled"; 502 }; 503 504 pmu1grf: syscon@fd58a000 { 505 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; 506 reg = <0x0 0xfd58a000 0x0 0x10000>; 507 }; 508 509 sys_grf: syscon@fd58c000 { 510 compatible = "rockchip,rk3588-sys-grf", "syscon"; 511 reg = <0x0 0xfd58c000 0x0 0x1000>; 512 }; 513 514 vop_grf: syscon@fd5a4000 { 515 compatible = "rockchip,rk3588-vop-grf", "syscon"; 516 reg = <0x0 0xfd5a4000 0x0 0x2000>; 517 }; 518 519 vo1_grf: syscon@fd5a8000 { 520 compatible = "rockchip,rk3588-vo-grf", "syscon"; 521 reg = <0x0 0xfd5a8000 0x0 0x100>; 522 }; 523 524 php_grf: syscon@fd5b0000 { 525 compatible = "rockchip,rk3588-php-grf", "syscon"; 526 reg = <0x0 0xfd5b0000 0x0 0x1000>; 527 }; 528 529 pipe_phy0_grf: syscon@fd5bc000 { 530 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 531 reg = <0x0 0xfd5bc000 0x0 0x100>; 532 }; 533 534 pipe_phy2_grf: syscon@fd5c4000 { 535 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 536 reg = <0x0 0xfd5c4000 0x0 0x100>; 537 }; 538 539 usb2phy2_grf: syscon@fd5d8000 { 540 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 541 reg = <0x0 0xfd5d8000 0x0 0x4000>; 542 #address-cells = <1>; 543 #size-cells = <1>; 544 545 u2phy2: usb2-phy@8000 { 546 compatible = "rockchip,rk3588-usb2phy"; 547 reg = <0x8000 0x10>; 548 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 549 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 550 reset-names = "phy", "apb"; 551 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 552 clock-names = "phyclk"; 553 clock-output-names = "usb480m_phy2"; 554 #clock-cells = <0>; 555 status = "disabled"; 556 557 u2phy2_host: host-port { 558 #phy-cells = <0>; 559 status = "disabled"; 560 }; 561 }; 562 }; 563 564 usb2phy3_grf: syscon@fd5dc000 { 565 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 566 reg = <0x0 0xfd5dc000 0x0 0x4000>; 567 #address-cells = <1>; 568 #size-cells = <1>; 569 570 u2phy3: usb2-phy@c000 { 571 compatible = "rockchip,rk3588-usb2phy"; 572 reg = <0xc000 0x10>; 573 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 574 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 575 reset-names = "phy", "apb"; 576 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 577 clock-names = "phyclk"; 578 clock-output-names = "usb480m_phy3"; 579 #clock-cells = <0>; 580 status = "disabled"; 581 582 u2phy3_host: host-port { 583 #phy-cells = <0>; 584 status = "disabled"; 585 }; 586 }; 587 }; 588 589 ioc: syscon@fd5f0000 { 590 compatible = "rockchip,rk3588-ioc", "syscon"; 591 reg = <0x0 0xfd5f0000 0x0 0x10000>; 592 }; 593 594 system_sram1: sram@fd600000 { 595 compatible = "mmio-sram"; 596 reg = <0x0 0xfd600000 0x0 0x100000>; 597 ranges = <0x0 0x0 0xfd600000 0x100000>; 598 #address-cells = <1>; 599 #size-cells = <1>; 600 }; 601 602 cru: clock-controller@fd7c0000 { 603 compatible = "rockchip,rk3588-cru"; 604 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 605 assigned-clocks = 606 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 607 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 608 <&cru ACLK_CENTER_ROOT>, 609 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 610 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 611 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 612 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, 613 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 614 <&cru CLK_GPU>; 615 assigned-clock-rates = 616 <1100000000>, <786432000>, 617 <850000000>, <1188000000>, 618 <702000000>, 619 <400000000>, <500000000>, 620 <800000000>, <100000000>, 621 <400000000>, <100000000>, 622 <200000000>, <500000000>, 623 <375000000>, <150000000>, 624 <200000000>; 625 rockchip,grf = <&php_grf>; 626 #clock-cells = <1>; 627 #reset-cells = <1>; 628 }; 629 630 i2c0: i2c@fd880000 { 631 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 632 reg = <0x0 0xfd880000 0x0 0x1000>; 633 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; 634 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 635 clock-names = "i2c", "pclk"; 636 pinctrl-0 = <&i2c0m0_xfer>; 637 pinctrl-names = "default"; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 status = "disabled"; 641 }; 642 643 vop: vop@fdd90000 { 644 compatible = "rockchip,rk3588-vop"; 645 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; 646 reg-names = "vop", "gamma-lut"; 647 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 648 clocks = <&cru ACLK_VOP>, 649 <&cru HCLK_VOP>, 650 <&cru DCLK_VOP0>, 651 <&cru DCLK_VOP1>, 652 <&cru DCLK_VOP2>, 653 <&cru DCLK_VOP3>, 654 <&cru PCLK_VOP_ROOT>; 655 clock-names = "aclk", 656 "hclk", 657 "dclk_vp0", 658 "dclk_vp1", 659 "dclk_vp2", 660 "dclk_vp3", 661 "pclk_vop"; 662 iommus = <&vop_mmu>; 663 power-domains = <&power RK3588_PD_VOP>; 664 rockchip,grf = <&sys_grf>; 665 rockchip,vop-grf = <&vop_grf>; 666 rockchip,vo1-grf = <&vo1_grf>; 667 rockchip,pmu = <&pmu>; 668 status = "disabled"; 669 670 vop_out: ports { 671 #address-cells = <1>; 672 #size-cells = <0>; 673 674 vp0: port@0 { 675 #address-cells = <1>; 676 #size-cells = <0>; 677 reg = <0>; 678 }; 679 680 vp1: port@1 { 681 #address-cells = <1>; 682 #size-cells = <0>; 683 reg = <1>; 684 }; 685 686 vp2: port@2 { 687 #address-cells = <1>; 688 #size-cells = <0>; 689 reg = <2>; 690 }; 691 692 vp3: port@3 { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 reg = <3>; 696 }; 697 }; 698 }; 699 700 vop_mmu: iommu@fdd97e00 { 701 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 702 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 703 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 704 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 705 clock-names = "aclk", "iface"; 706 #iommu-cells = <0>; 707 power-domains = <&power RK3588_PD_VOP>; 708 status = "disabled"; 709 }; 710 711 uart0: serial@fd890000 { 712 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 713 reg = <0x0 0xfd890000 0x0 0x100>; 714 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 715 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 716 clock-names = "baudclk", "apb_pclk"; 717 dmas = <&dmac0 6>, <&dmac0 7>; 718 dma-names = "tx", "rx"; 719 pinctrl-0 = <&uart0m1_xfer>; 720 pinctrl-names = "default"; 721 reg-shift = <2>; 722 reg-io-width = <4>; 723 status = "disabled"; 724 }; 725 726 pwm0: pwm@fd8b0000 { 727 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 728 reg = <0x0 0xfd8b0000 0x0 0x10>; 729 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 730 clock-names = "pwm", "pclk"; 731 pinctrl-0 = <&pwm0m0_pins>; 732 pinctrl-names = "default"; 733 #pwm-cells = <3>; 734 status = "disabled"; 735 }; 736 737 pwm1: pwm@fd8b0010 { 738 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 739 reg = <0x0 0xfd8b0010 0x0 0x10>; 740 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 741 clock-names = "pwm", "pclk"; 742 pinctrl-0 = <&pwm1m0_pins>; 743 pinctrl-names = "default"; 744 #pwm-cells = <3>; 745 status = "disabled"; 746 }; 747 748 pwm2: pwm@fd8b0020 { 749 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 750 reg = <0x0 0xfd8b0020 0x0 0x10>; 751 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 752 clock-names = "pwm", "pclk"; 753 pinctrl-0 = <&pwm2m0_pins>; 754 pinctrl-names = "default"; 755 #pwm-cells = <3>; 756 status = "disabled"; 757 }; 758 759 pwm3: pwm@fd8b0030 { 760 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 761 reg = <0x0 0xfd8b0030 0x0 0x10>; 762 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 763 clock-names = "pwm", "pclk"; 764 pinctrl-0 = <&pwm3m0_pins>; 765 pinctrl-names = "default"; 766 #pwm-cells = <3>; 767 status = "disabled"; 768 }; 769 770 pmu: power-management@fd8d8000 { 771 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 772 reg = <0x0 0xfd8d8000 0x0 0x400>; 773 774 power: power-controller { 775 compatible = "rockchip,rk3588-power-controller"; 776 #address-cells = <1>; 777 #power-domain-cells = <1>; 778 #size-cells = <0>; 779 status = "okay"; 780 781 /* These power domains are grouped by VD_NPU */ 782 power-domain@RK3588_PD_NPU { 783 reg = <RK3588_PD_NPU>; 784 #power-domain-cells = <0>; 785 #address-cells = <1>; 786 #size-cells = <0>; 787 788 power-domain@RK3588_PD_NPUTOP { 789 reg = <RK3588_PD_NPUTOP>; 790 clocks = <&cru HCLK_NPU_ROOT>, 791 <&cru PCLK_NPU_ROOT>, 792 <&cru CLK_NPU_DSU0>, 793 <&cru HCLK_NPU_CM0_ROOT>; 794 pm_qos = <&qos_npu0_mwr>, 795 <&qos_npu0_mro>, 796 <&qos_mcu_npu>; 797 #power-domain-cells = <0>; 798 #address-cells = <1>; 799 #size-cells = <0>; 800 801 power-domain@RK3588_PD_NPU1 { 802 reg = <RK3588_PD_NPU1>; 803 clocks = <&cru HCLK_NPU_ROOT>, 804 <&cru PCLK_NPU_ROOT>, 805 <&cru CLK_NPU_DSU0>; 806 pm_qos = <&qos_npu1>; 807 #power-domain-cells = <0>; 808 }; 809 power-domain@RK3588_PD_NPU2 { 810 reg = <RK3588_PD_NPU2>; 811 clocks = <&cru HCLK_NPU_ROOT>, 812 <&cru PCLK_NPU_ROOT>, 813 <&cru CLK_NPU_DSU0>; 814 pm_qos = <&qos_npu2>; 815 #power-domain-cells = <0>; 816 }; 817 }; 818 }; 819 /* These power domains are grouped by VD_GPU */ 820 power-domain@RK3588_PD_GPU { 821 reg = <RK3588_PD_GPU>; 822 clocks = <&cru CLK_GPU>, 823 <&cru CLK_GPU_COREGROUP>, 824 <&cru CLK_GPU_STACKS>; 825 pm_qos = <&qos_gpu_m0>, 826 <&qos_gpu_m1>, 827 <&qos_gpu_m2>, 828 <&qos_gpu_m3>; 829 #power-domain-cells = <0>; 830 }; 831 /* These power domains are grouped by VD_VCODEC */ 832 power-domain@RK3588_PD_VCODEC { 833 reg = <RK3588_PD_VCODEC>; 834 #address-cells = <1>; 835 #size-cells = <0>; 836 #power-domain-cells = <0>; 837 838 power-domain@RK3588_PD_RKVDEC0 { 839 reg = <RK3588_PD_RKVDEC0>; 840 clocks = <&cru HCLK_RKVDEC0>, 841 <&cru HCLK_VDPU_ROOT>, 842 <&cru ACLK_VDPU_ROOT>, 843 <&cru ACLK_RKVDEC0>, 844 <&cru ACLK_RKVDEC_CCU>; 845 pm_qos = <&qos_rkvdec0>; 846 #power-domain-cells = <0>; 847 }; 848 power-domain@RK3588_PD_RKVDEC1 { 849 reg = <RK3588_PD_RKVDEC1>; 850 clocks = <&cru HCLK_RKVDEC1>, 851 <&cru HCLK_VDPU_ROOT>, 852 <&cru ACLK_VDPU_ROOT>, 853 <&cru ACLK_RKVDEC1>; 854 pm_qos = <&qos_rkvdec1>; 855 #power-domain-cells = <0>; 856 }; 857 power-domain@RK3588_PD_VENC0 { 858 reg = <RK3588_PD_VENC0>; 859 clocks = <&cru HCLK_RKVENC0>, 860 <&cru ACLK_RKVENC0>; 861 pm_qos = <&qos_rkvenc0_m0ro>, 862 <&qos_rkvenc0_m1ro>, 863 <&qos_rkvenc0_m2wo>; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 #power-domain-cells = <0>; 867 868 power-domain@RK3588_PD_VENC1 { 869 reg = <RK3588_PD_VENC1>; 870 clocks = <&cru HCLK_RKVENC1>, 871 <&cru HCLK_RKVENC0>, 872 <&cru ACLK_RKVENC0>, 873 <&cru ACLK_RKVENC1>; 874 pm_qos = <&qos_rkvenc1_m0ro>, 875 <&qos_rkvenc1_m1ro>, 876 <&qos_rkvenc1_m2wo>; 877 #power-domain-cells = <0>; 878 }; 879 }; 880 }; 881 /* These power domains are grouped by VD_LOGIC */ 882 power-domain@RK3588_PD_VDPU { 883 reg = <RK3588_PD_VDPU>; 884 clocks = <&cru HCLK_VDPU_ROOT>, 885 <&cru ACLK_VDPU_LOW_ROOT>, 886 <&cru ACLK_VDPU_ROOT>, 887 <&cru ACLK_JPEG_DECODER_ROOT>, 888 <&cru ACLK_IEP2P0>, 889 <&cru HCLK_IEP2P0>, 890 <&cru ACLK_JPEG_ENCODER0>, 891 <&cru HCLK_JPEG_ENCODER0>, 892 <&cru ACLK_JPEG_ENCODER1>, 893 <&cru HCLK_JPEG_ENCODER1>, 894 <&cru ACLK_JPEG_ENCODER2>, 895 <&cru HCLK_JPEG_ENCODER2>, 896 <&cru ACLK_JPEG_ENCODER3>, 897 <&cru HCLK_JPEG_ENCODER3>, 898 <&cru ACLK_JPEG_DECODER>, 899 <&cru HCLK_JPEG_DECODER>, 900 <&cru ACLK_RGA2>, 901 <&cru HCLK_RGA2>; 902 pm_qos = <&qos_iep>, 903 <&qos_jpeg_dec>, 904 <&qos_jpeg_enc0>, 905 <&qos_jpeg_enc1>, 906 <&qos_jpeg_enc2>, 907 <&qos_jpeg_enc3>, 908 <&qos_rga2_mro>, 909 <&qos_rga2_mwo>; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 #power-domain-cells = <0>; 913 914 915 power-domain@RK3588_PD_AV1 { 916 reg = <RK3588_PD_AV1>; 917 clocks = <&cru PCLK_AV1>, 918 <&cru ACLK_AV1>, 919 <&cru HCLK_VDPU_ROOT>; 920 pm_qos = <&qos_av1>; 921 #power-domain-cells = <0>; 922 }; 923 power-domain@RK3588_PD_RKVDEC0 { 924 reg = <RK3588_PD_RKVDEC0>; 925 clocks = <&cru HCLK_RKVDEC0>, 926 <&cru HCLK_VDPU_ROOT>, 927 <&cru ACLK_VDPU_ROOT>, 928 <&cru ACLK_RKVDEC0>; 929 pm_qos = <&qos_rkvdec0>; 930 #power-domain-cells = <0>; 931 }; 932 power-domain@RK3588_PD_RKVDEC1 { 933 reg = <RK3588_PD_RKVDEC1>; 934 clocks = <&cru HCLK_RKVDEC1>, 935 <&cru HCLK_VDPU_ROOT>, 936 <&cru ACLK_VDPU_ROOT>; 937 pm_qos = <&qos_rkvdec1>; 938 #power-domain-cells = <0>; 939 }; 940 power-domain@RK3588_PD_RGA30 { 941 reg = <RK3588_PD_RGA30>; 942 clocks = <&cru ACLK_RGA3_0>, 943 <&cru HCLK_RGA3_0>; 944 pm_qos = <&qos_rga3_0>; 945 #power-domain-cells = <0>; 946 }; 947 }; 948 power-domain@RK3588_PD_VOP { 949 reg = <RK3588_PD_VOP>; 950 clocks = <&cru PCLK_VOP_ROOT>, 951 <&cru HCLK_VOP_ROOT>, 952 <&cru ACLK_VOP>; 953 pm_qos = <&qos_vop_m0>, 954 <&qos_vop_m1>; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 #power-domain-cells = <0>; 958 959 power-domain@RK3588_PD_VO0 { 960 reg = <RK3588_PD_VO0>; 961 clocks = <&cru PCLK_VO0_ROOT>, 962 <&cru PCLK_VO0_S_ROOT>, 963 <&cru HCLK_VO0_S_ROOT>, 964 <&cru ACLK_VO0_ROOT>, 965 <&cru HCLK_HDCP0>, 966 <&cru ACLK_HDCP0>, 967 <&cru HCLK_VOP_ROOT>; 968 pm_qos = <&qos_hdcp0>; 969 #power-domain-cells = <0>; 970 }; 971 }; 972 power-domain@RK3588_PD_VO1 { 973 reg = <RK3588_PD_VO1>; 974 clocks = <&cru PCLK_VO1_ROOT>, 975 <&cru PCLK_VO1_S_ROOT>, 976 <&cru HCLK_VO1_S_ROOT>, 977 <&cru HCLK_HDCP1>, 978 <&cru ACLK_HDCP1>, 979 <&cru ACLK_HDMIRX_ROOT>, 980 <&cru HCLK_VO1USB_TOP_ROOT>; 981 pm_qos = <&qos_hdcp1>, 982 <&qos_hdmirx>; 983 #power-domain-cells = <0>; 984 }; 985 power-domain@RK3588_PD_VI { 986 reg = <RK3588_PD_VI>; 987 clocks = <&cru HCLK_VI_ROOT>, 988 <&cru PCLK_VI_ROOT>, 989 <&cru HCLK_ISP0>, 990 <&cru ACLK_ISP0>, 991 <&cru HCLK_VICAP>, 992 <&cru ACLK_VICAP>; 993 pm_qos = <&qos_isp0_mro>, 994 <&qos_isp0_mwo>, 995 <&qos_vicap_m0>, 996 <&qos_vicap_m1>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 #power-domain-cells = <0>; 1000 1001 power-domain@RK3588_PD_ISP1 { 1002 reg = <RK3588_PD_ISP1>; 1003 clocks = <&cru HCLK_ISP1>, 1004 <&cru ACLK_ISP1>, 1005 <&cru HCLK_VI_ROOT>, 1006 <&cru PCLK_VI_ROOT>; 1007 pm_qos = <&qos_isp1_mwo>, 1008 <&qos_isp1_mro>; 1009 #power-domain-cells = <0>; 1010 }; 1011 power-domain@RK3588_PD_FEC { 1012 reg = <RK3588_PD_FEC>; 1013 clocks = <&cru HCLK_FISHEYE0>, 1014 <&cru ACLK_FISHEYE0>, 1015 <&cru HCLK_FISHEYE1>, 1016 <&cru ACLK_FISHEYE1>, 1017 <&cru PCLK_VI_ROOT>; 1018 pm_qos = <&qos_fisheye0>, 1019 <&qos_fisheye1>; 1020 #power-domain-cells = <0>; 1021 }; 1022 }; 1023 power-domain@RK3588_PD_RGA31 { 1024 reg = <RK3588_PD_RGA31>; 1025 clocks = <&cru HCLK_RGA3_1>, 1026 <&cru ACLK_RGA3_1>; 1027 pm_qos = <&qos_rga3_1>; 1028 #power-domain-cells = <0>; 1029 }; 1030 power-domain@RK3588_PD_USB { 1031 reg = <RK3588_PD_USB>; 1032 clocks = <&cru PCLK_PHP_ROOT>, 1033 <&cru ACLK_USB_ROOT>, 1034 <&cru ACLK_USB>, 1035 <&cru HCLK_USB_ROOT>, 1036 <&cru HCLK_HOST0>, 1037 <&cru HCLK_HOST_ARB0>, 1038 <&cru HCLK_HOST1>, 1039 <&cru HCLK_HOST_ARB1>; 1040 pm_qos = <&qos_usb3_0>, 1041 <&qos_usb3_1>, 1042 <&qos_usb2host_0>, 1043 <&qos_usb2host_1>; 1044 #power-domain-cells = <0>; 1045 }; 1046 power-domain@RK3588_PD_GMAC { 1047 reg = <RK3588_PD_GMAC>; 1048 clocks = <&cru PCLK_PHP_ROOT>, 1049 <&cru ACLK_PCIE_ROOT>, 1050 <&cru ACLK_PHP_ROOT>; 1051 #power-domain-cells = <0>; 1052 }; 1053 power-domain@RK3588_PD_PCIE { 1054 reg = <RK3588_PD_PCIE>; 1055 clocks = <&cru PCLK_PHP_ROOT>, 1056 <&cru ACLK_PCIE_ROOT>, 1057 <&cru ACLK_PHP_ROOT>; 1058 #power-domain-cells = <0>; 1059 }; 1060 power-domain@RK3588_PD_SDIO { 1061 reg = <RK3588_PD_SDIO>; 1062 clocks = <&cru HCLK_SDIO>, 1063 <&cru HCLK_NVM_ROOT>; 1064 pm_qos = <&qos_sdio>; 1065 #power-domain-cells = <0>; 1066 }; 1067 power-domain@RK3588_PD_AUDIO { 1068 reg = <RK3588_PD_AUDIO>; 1069 clocks = <&cru HCLK_AUDIO_ROOT>, 1070 <&cru PCLK_AUDIO_ROOT>; 1071 #power-domain-cells = <0>; 1072 }; 1073 power-domain@RK3588_PD_SDMMC { 1074 reg = <RK3588_PD_SDMMC>; 1075 pm_qos = <&qos_sdmmc>; 1076 #power-domain-cells = <0>; 1077 }; 1078 }; 1079 }; 1080 1081 i2s4_8ch: i2s@fddc0000 { 1082 compatible = "rockchip,rk3588-i2s-tdm"; 1083 reg = <0x0 0xfddc0000 0x0 0x1000>; 1084 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; 1085 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 1086 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1087 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 1088 assigned-clock-parents = <&cru PLL_AUPLL>; 1089 dmas = <&dmac2 0>; 1090 dma-names = "tx"; 1091 power-domains = <&power RK3588_PD_VO0>; 1092 resets = <&cru SRST_M_I2S4_8CH_TX>; 1093 reset-names = "tx-m"; 1094 #sound-dai-cells = <0>; 1095 status = "disabled"; 1096 }; 1097 1098 i2s5_8ch: i2s@fddf0000 { 1099 compatible = "rockchip,rk3588-i2s-tdm"; 1100 reg = <0x0 0xfddf0000 0x0 0x1000>; 1101 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; 1102 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 1103 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1104 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 1105 assigned-clock-parents = <&cru PLL_AUPLL>; 1106 dmas = <&dmac2 2>; 1107 dma-names = "tx"; 1108 power-domains = <&power RK3588_PD_VO1>; 1109 resets = <&cru SRST_M_I2S5_8CH_TX>; 1110 reset-names = "tx-m"; 1111 #sound-dai-cells = <0>; 1112 status = "disabled"; 1113 }; 1114 1115 i2s9_8ch: i2s@fddfc000 { 1116 compatible = "rockchip,rk3588-i2s-tdm"; 1117 reg = <0x0 0xfddfc000 0x0 0x1000>; 1118 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; 1119 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 1120 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1121 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 1122 assigned-clock-parents = <&cru PLL_AUPLL>; 1123 dmas = <&dmac2 23>; 1124 dma-names = "rx"; 1125 power-domains = <&power RK3588_PD_VO1>; 1126 resets = <&cru SRST_M_I2S9_8CH_RX>; 1127 reset-names = "rx-m"; 1128 #sound-dai-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 qos_gpu_m0: qos@fdf35000 { 1133 compatible = "rockchip,rk3588-qos", "syscon"; 1134 reg = <0x0 0xfdf35000 0x0 0x20>; 1135 }; 1136 1137 qos_gpu_m1: qos@fdf35200 { 1138 compatible = "rockchip,rk3588-qos", "syscon"; 1139 reg = <0x0 0xfdf35200 0x0 0x20>; 1140 }; 1141 1142 qos_gpu_m2: qos@fdf35400 { 1143 compatible = "rockchip,rk3588-qos", "syscon"; 1144 reg = <0x0 0xfdf35400 0x0 0x20>; 1145 }; 1146 1147 qos_gpu_m3: qos@fdf35600 { 1148 compatible = "rockchip,rk3588-qos", "syscon"; 1149 reg = <0x0 0xfdf35600 0x0 0x20>; 1150 }; 1151 1152 qos_rga3_1: qos@fdf36000 { 1153 compatible = "rockchip,rk3588-qos", "syscon"; 1154 reg = <0x0 0xfdf36000 0x0 0x20>; 1155 }; 1156 1157 qos_sdio: qos@fdf39000 { 1158 compatible = "rockchip,rk3588-qos", "syscon"; 1159 reg = <0x0 0xfdf39000 0x0 0x20>; 1160 }; 1161 1162 qos_sdmmc: qos@fdf3d800 { 1163 compatible = "rockchip,rk3588-qos", "syscon"; 1164 reg = <0x0 0xfdf3d800 0x0 0x20>; 1165 }; 1166 1167 qos_usb3_1: qos@fdf3e000 { 1168 compatible = "rockchip,rk3588-qos", "syscon"; 1169 reg = <0x0 0xfdf3e000 0x0 0x20>; 1170 }; 1171 1172 qos_usb3_0: qos@fdf3e200 { 1173 compatible = "rockchip,rk3588-qos", "syscon"; 1174 reg = <0x0 0xfdf3e200 0x0 0x20>; 1175 }; 1176 1177 qos_usb2host_0: qos@fdf3e400 { 1178 compatible = "rockchip,rk3588-qos", "syscon"; 1179 reg = <0x0 0xfdf3e400 0x0 0x20>; 1180 }; 1181 1182 qos_usb2host_1: qos@fdf3e600 { 1183 compatible = "rockchip,rk3588-qos", "syscon"; 1184 reg = <0x0 0xfdf3e600 0x0 0x20>; 1185 }; 1186 1187 qos_fisheye0: qos@fdf40000 { 1188 compatible = "rockchip,rk3588-qos", "syscon"; 1189 reg = <0x0 0xfdf40000 0x0 0x20>; 1190 }; 1191 1192 qos_fisheye1: qos@fdf40200 { 1193 compatible = "rockchip,rk3588-qos", "syscon"; 1194 reg = <0x0 0xfdf40200 0x0 0x20>; 1195 }; 1196 1197 qos_isp0_mro: qos@fdf40400 { 1198 compatible = "rockchip,rk3588-qos", "syscon"; 1199 reg = <0x0 0xfdf40400 0x0 0x20>; 1200 }; 1201 1202 qos_isp0_mwo: qos@fdf40500 { 1203 compatible = "rockchip,rk3588-qos", "syscon"; 1204 reg = <0x0 0xfdf40500 0x0 0x20>; 1205 }; 1206 1207 qos_vicap_m0: qos@fdf40600 { 1208 compatible = "rockchip,rk3588-qos", "syscon"; 1209 reg = <0x0 0xfdf40600 0x0 0x20>; 1210 }; 1211 1212 qos_vicap_m1: qos@fdf40800 { 1213 compatible = "rockchip,rk3588-qos", "syscon"; 1214 reg = <0x0 0xfdf40800 0x0 0x20>; 1215 }; 1216 1217 qos_isp1_mwo: qos@fdf41000 { 1218 compatible = "rockchip,rk3588-qos", "syscon"; 1219 reg = <0x0 0xfdf41000 0x0 0x20>; 1220 }; 1221 1222 qos_isp1_mro: qos@fdf41100 { 1223 compatible = "rockchip,rk3588-qos", "syscon"; 1224 reg = <0x0 0xfdf41100 0x0 0x20>; 1225 }; 1226 1227 qos_rkvenc0_m0ro: qos@fdf60000 { 1228 compatible = "rockchip,rk3588-qos", "syscon"; 1229 reg = <0x0 0xfdf60000 0x0 0x20>; 1230 }; 1231 1232 qos_rkvenc0_m1ro: qos@fdf60200 { 1233 compatible = "rockchip,rk3588-qos", "syscon"; 1234 reg = <0x0 0xfdf60200 0x0 0x20>; 1235 }; 1236 1237 qos_rkvenc0_m2wo: qos@fdf60400 { 1238 compatible = "rockchip,rk3588-qos", "syscon"; 1239 reg = <0x0 0xfdf60400 0x0 0x20>; 1240 }; 1241 1242 qos_rkvenc1_m0ro: qos@fdf61000 { 1243 compatible = "rockchip,rk3588-qos", "syscon"; 1244 reg = <0x0 0xfdf61000 0x0 0x20>; 1245 }; 1246 1247 qos_rkvenc1_m1ro: qos@fdf61200 { 1248 compatible = "rockchip,rk3588-qos", "syscon"; 1249 reg = <0x0 0xfdf61200 0x0 0x20>; 1250 }; 1251 1252 qos_rkvenc1_m2wo: qos@fdf61400 { 1253 compatible = "rockchip,rk3588-qos", "syscon"; 1254 reg = <0x0 0xfdf61400 0x0 0x20>; 1255 }; 1256 1257 qos_rkvdec0: qos@fdf62000 { 1258 compatible = "rockchip,rk3588-qos", "syscon"; 1259 reg = <0x0 0xfdf62000 0x0 0x20>; 1260 }; 1261 1262 qos_rkvdec1: qos@fdf63000 { 1263 compatible = "rockchip,rk3588-qos", "syscon"; 1264 reg = <0x0 0xfdf63000 0x0 0x20>; 1265 }; 1266 1267 qos_av1: qos@fdf64000 { 1268 compatible = "rockchip,rk3588-qos", "syscon"; 1269 reg = <0x0 0xfdf64000 0x0 0x20>; 1270 }; 1271 1272 qos_iep: qos@fdf66000 { 1273 compatible = "rockchip,rk3588-qos", "syscon"; 1274 reg = <0x0 0xfdf66000 0x0 0x20>; 1275 }; 1276 1277 qos_jpeg_dec: qos@fdf66200 { 1278 compatible = "rockchip,rk3588-qos", "syscon"; 1279 reg = <0x0 0xfdf66200 0x0 0x20>; 1280 }; 1281 1282 qos_jpeg_enc0: qos@fdf66400 { 1283 compatible = "rockchip,rk3588-qos", "syscon"; 1284 reg = <0x0 0xfdf66400 0x0 0x20>; 1285 }; 1286 1287 qos_jpeg_enc1: qos@fdf66600 { 1288 compatible = "rockchip,rk3588-qos", "syscon"; 1289 reg = <0x0 0xfdf66600 0x0 0x20>; 1290 }; 1291 1292 qos_jpeg_enc2: qos@fdf66800 { 1293 compatible = "rockchip,rk3588-qos", "syscon"; 1294 reg = <0x0 0xfdf66800 0x0 0x20>; 1295 }; 1296 1297 qos_jpeg_enc3: qos@fdf66a00 { 1298 compatible = "rockchip,rk3588-qos", "syscon"; 1299 reg = <0x0 0xfdf66a00 0x0 0x20>; 1300 }; 1301 1302 qos_rga2_mro: qos@fdf66c00 { 1303 compatible = "rockchip,rk3588-qos", "syscon"; 1304 reg = <0x0 0xfdf66c00 0x0 0x20>; 1305 }; 1306 1307 qos_rga2_mwo: qos@fdf66e00 { 1308 compatible = "rockchip,rk3588-qos", "syscon"; 1309 reg = <0x0 0xfdf66e00 0x0 0x20>; 1310 }; 1311 1312 qos_rga3_0: qos@fdf67000 { 1313 compatible = "rockchip,rk3588-qos", "syscon"; 1314 reg = <0x0 0xfdf67000 0x0 0x20>; 1315 }; 1316 1317 qos_vdpu: qos@fdf67200 { 1318 compatible = "rockchip,rk3588-qos", "syscon"; 1319 reg = <0x0 0xfdf67200 0x0 0x20>; 1320 }; 1321 1322 qos_npu1: qos@fdf70000 { 1323 compatible = "rockchip,rk3588-qos", "syscon"; 1324 reg = <0x0 0xfdf70000 0x0 0x20>; 1325 }; 1326 1327 qos_npu2: qos@fdf71000 { 1328 compatible = "rockchip,rk3588-qos", "syscon"; 1329 reg = <0x0 0xfdf71000 0x0 0x20>; 1330 }; 1331 1332 qos_npu0_mwr: qos@fdf72000 { 1333 compatible = "rockchip,rk3588-qos", "syscon"; 1334 reg = <0x0 0xfdf72000 0x0 0x20>; 1335 }; 1336 1337 qos_npu0_mro: qos@fdf72200 { 1338 compatible = "rockchip,rk3588-qos", "syscon"; 1339 reg = <0x0 0xfdf72200 0x0 0x20>; 1340 }; 1341 1342 qos_mcu_npu: qos@fdf72400 { 1343 compatible = "rockchip,rk3588-qos", "syscon"; 1344 reg = <0x0 0xfdf72400 0x0 0x20>; 1345 }; 1346 1347 qos_hdcp0: qos@fdf80000 { 1348 compatible = "rockchip,rk3588-qos", "syscon"; 1349 reg = <0x0 0xfdf80000 0x0 0x20>; 1350 }; 1351 1352 qos_hdcp1: qos@fdf81000 { 1353 compatible = "rockchip,rk3588-qos", "syscon"; 1354 reg = <0x0 0xfdf81000 0x0 0x20>; 1355 }; 1356 1357 qos_hdmirx: qos@fdf81200 { 1358 compatible = "rockchip,rk3588-qos", "syscon"; 1359 reg = <0x0 0xfdf81200 0x0 0x20>; 1360 }; 1361 1362 qos_vop_m0: qos@fdf82000 { 1363 compatible = "rockchip,rk3588-qos", "syscon"; 1364 reg = <0x0 0xfdf82000 0x0 0x20>; 1365 }; 1366 1367 qos_vop_m1: qos@fdf82200 { 1368 compatible = "rockchip,rk3588-qos", "syscon"; 1369 reg = <0x0 0xfdf82200 0x0 0x20>; 1370 }; 1371 1372 pcie2x1l1: pcie@fe180000 { 1373 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1374 bus-range = <0x30 0x3f>; 1375 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 1376 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 1377 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; 1378 clock-names = "aclk_mst", "aclk_slv", 1379 "aclk_dbi", "pclk", 1380 "aux", "pipe"; 1381 device_type = "pci"; 1382 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, 1383 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, 1384 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, 1385 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, 1386 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; 1387 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1388 #interrupt-cells = <1>; 1389 interrupt-map-mask = <0 0 0 7>; 1390 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 1391 <0 0 0 2 &pcie2x1l1_intc 1>, 1392 <0 0 0 3 &pcie2x1l1_intc 2>, 1393 <0 0 0 4 &pcie2x1l1_intc 3>; 1394 linux,pci-domain = <3>; 1395 max-link-speed = <2>; 1396 msi-map = <0x3000 &its0 0x3000 0x1000>; 1397 num-lanes = <1>; 1398 phys = <&combphy2_psu PHY_TYPE_PCIE>; 1399 phy-names = "pcie-phy"; 1400 power-domains = <&power RK3588_PD_PCIE>; 1401 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, 1402 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, 1403 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; 1404 reg = <0xa 0x40c00000 0x0 0x00400000>, 1405 <0x0 0xfe180000 0x0 0x00010000>, 1406 <0x0 0xf3000000 0x0 0x00100000>; 1407 reg-names = "dbi", "apb", "config"; 1408 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; 1409 reset-names = "pwr", "pipe"; 1410 #address-cells = <3>; 1411 #size-cells = <2>; 1412 status = "disabled"; 1413 1414 pcie2x1l1_intc: legacy-interrupt-controller { 1415 interrupt-controller; 1416 #address-cells = <0>; 1417 #interrupt-cells = <1>; 1418 interrupt-parent = <&gic>; 1419 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; 1420 }; 1421 }; 1422 1423 pcie2x1l2: pcie@fe190000 { 1424 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1425 bus-range = <0x40 0x4f>; 1426 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 1427 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 1428 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; 1429 clock-names = "aclk_mst", "aclk_slv", 1430 "aclk_dbi", "pclk", 1431 "aux", "pipe"; 1432 device_type = "pci"; 1433 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, 1434 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, 1435 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, 1436 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, 1437 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; 1438 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1439 #interrupt-cells = <1>; 1440 interrupt-map-mask = <0 0 0 7>; 1441 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 1442 <0 0 0 2 &pcie2x1l2_intc 1>, 1443 <0 0 0 3 &pcie2x1l2_intc 2>, 1444 <0 0 0 4 &pcie2x1l2_intc 3>; 1445 linux,pci-domain = <4>; 1446 max-link-speed = <2>; 1447 msi-map = <0x4000 &its0 0x4000 0x1000>; 1448 num-lanes = <1>; 1449 phys = <&combphy0_ps PHY_TYPE_PCIE>; 1450 phy-names = "pcie-phy"; 1451 power-domains = <&power RK3588_PD_PCIE>; 1452 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 1453 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, 1454 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; 1455 reg = <0xa 0x41000000 0x0 0x00400000>, 1456 <0x0 0xfe190000 0x0 0x00010000>, 1457 <0x0 0xf4000000 0x0 0x00100000>; 1458 reg-names = "dbi", "apb", "config"; 1459 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; 1460 reset-names = "pwr", "pipe"; 1461 #address-cells = <3>; 1462 #size-cells = <2>; 1463 status = "disabled"; 1464 1465 pcie2x1l2_intc: legacy-interrupt-controller { 1466 interrupt-controller; 1467 #address-cells = <0>; 1468 #interrupt-cells = <1>; 1469 interrupt-parent = <&gic>; 1470 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; 1471 }; 1472 }; 1473 1474 dfi: dfi@fe060000 { 1475 reg = <0x00 0xfe060000 0x00 0x10000>; 1476 compatible = "rockchip,rk3588-dfi"; 1477 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, 1478 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, 1479 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, 1480 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1481 rockchip,pmu = <&pmu1grf>; 1482 }; 1483 1484 gmac1: ethernet@fe1c0000 { 1485 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1486 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1487 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, 1488 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 1489 interrupt-names = "macirq", "eth_wake_irq"; 1490 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 1491 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1492 <&cru CLK_GMAC1_PTP_REF>; 1493 clock-names = "stmmaceth", "clk_mac_ref", 1494 "pclk_mac", "aclk_mac", 1495 "ptp_ref"; 1496 power-domains = <&power RK3588_PD_GMAC>; 1497 resets = <&cru SRST_A_GMAC1>; 1498 reset-names = "stmmaceth"; 1499 rockchip,grf = <&sys_grf>; 1500 rockchip,php-grf = <&php_grf>; 1501 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1502 snps,mixed-burst; 1503 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1504 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1505 snps,tso; 1506 status = "disabled"; 1507 1508 mdio1: mdio { 1509 compatible = "snps,dwmac-mdio"; 1510 #address-cells = <0x1>; 1511 #size-cells = <0x0>; 1512 }; 1513 1514 gmac1_stmmac_axi_setup: stmmac-axi-config { 1515 snps,blen = <0 0 0 0 16 8 4>; 1516 snps,wr_osr_lmt = <4>; 1517 snps,rd_osr_lmt = <8>; 1518 }; 1519 1520 gmac1_mtl_rx_setup: rx-queues-config { 1521 snps,rx-queues-to-use = <2>; 1522 queue0 {}; 1523 queue1 {}; 1524 }; 1525 1526 gmac1_mtl_tx_setup: tx-queues-config { 1527 snps,tx-queues-to-use = <2>; 1528 queue0 {}; 1529 queue1 {}; 1530 }; 1531 }; 1532 1533 sata0: sata@fe210000 { 1534 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1535 reg = <0 0xfe210000 0 0x1000>; 1536 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; 1537 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1538 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, 1539 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; 1540 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1541 ports-implemented = <0x1>; 1542 #address-cells = <1>; 1543 #size-cells = <0>; 1544 status = "disabled"; 1545 1546 sata-port@0 { 1547 reg = <0>; 1548 hba-port-cap = <HBA_PORT_FBSCP>; 1549 phys = <&combphy0_ps PHY_TYPE_SATA>; 1550 phy-names = "sata-phy"; 1551 snps,rx-ts-max = <32>; 1552 snps,tx-ts-max = <32>; 1553 }; 1554 }; 1555 1556 sata2: sata@fe230000 { 1557 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1558 reg = <0 0xfe230000 0 0x1000>; 1559 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; 1560 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 1561 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, 1562 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; 1563 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1564 ports-implemented = <0x1>; 1565 #address-cells = <1>; 1566 #size-cells = <0>; 1567 status = "disabled"; 1568 1569 sata-port@0 { 1570 reg = <0>; 1571 hba-port-cap = <HBA_PORT_FBSCP>; 1572 phys = <&combphy2_psu PHY_TYPE_SATA>; 1573 phy-names = "sata-phy"; 1574 snps,rx-ts-max = <32>; 1575 snps,tx-ts-max = <32>; 1576 }; 1577 }; 1578 1579 sfc: spi@fe2b0000 { 1580 compatible = "rockchip,sfc"; 1581 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1582 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; 1583 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1584 clock-names = "clk_sfc", "hclk_sfc"; 1585 #address-cells = <1>; 1586 #size-cells = <0>; 1587 status = "disabled"; 1588 }; 1589 1590 sdmmc: mmc@fe2c0000 { 1591 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1592 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1593 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 1594 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 1595 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1596 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1597 fifo-depth = <0x100>; 1598 max-frequency = <200000000>; 1599 pinctrl-names = "default"; 1600 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1601 power-domains = <&power RK3588_PD_SDMMC>; 1602 status = "disabled"; 1603 }; 1604 1605 sdio: mmc@fe2d0000 { 1606 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1607 reg = <0x00 0xfe2d0000 0x00 0x4000>; 1608 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; 1609 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 1610 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1611 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1612 fifo-depth = <0x100>; 1613 max-frequency = <200000000>; 1614 pinctrl-names = "default"; 1615 pinctrl-0 = <&sdiom1_pins>; 1616 power-domains = <&power RK3588_PD_SDIO>; 1617 status = "disabled"; 1618 }; 1619 1620 sdhci: mmc@fe2e0000 { 1621 compatible = "rockchip,rk3588-dwcmshc"; 1622 reg = <0x0 0xfe2e0000 0x0 0x10000>; 1623 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 1624 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 1625 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1626 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1627 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1628 <&cru TMCLK_EMMC>; 1629 clock-names = "core", "bus", "axi", "block", "timer"; 1630 max-frequency = <200000000>; 1631 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 1632 <&emmc_cmd>, <&emmc_data_strobe>; 1633 pinctrl-names = "default"; 1634 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1635 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1636 <&cru SRST_T_EMMC>; 1637 reset-names = "core", "bus", "axi", "block", "timer"; 1638 status = "disabled"; 1639 }; 1640 1641 i2s0_8ch: i2s@fe470000 { 1642 compatible = "rockchip,rk3588-i2s-tdm"; 1643 reg = <0x0 0xfe470000 0x0 0x1000>; 1644 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; 1645 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1646 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1647 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1648 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 1649 dmas = <&dmac0 0>, <&dmac0 1>; 1650 dma-names = "tx", "rx"; 1651 power-domains = <&power RK3588_PD_AUDIO>; 1652 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1653 reset-names = "tx-m", "rx-m"; 1654 rockchip,trcm-sync-tx-only; 1655 pinctrl-names = "default"; 1656 pinctrl-0 = <&i2s0_lrck 1657 &i2s0_sclk 1658 &i2s0_sdi0 1659 &i2s0_sdi1 1660 &i2s0_sdi2 1661 &i2s0_sdi3 1662 &i2s0_sdo0 1663 &i2s0_sdo1 1664 &i2s0_sdo2 1665 &i2s0_sdo3>; 1666 #sound-dai-cells = <0>; 1667 status = "disabled"; 1668 }; 1669 1670 i2s1_8ch: i2s@fe480000 { 1671 compatible = "rockchip,rk3588-i2s-tdm"; 1672 reg = <0x0 0xfe480000 0x0 0x1000>; 1673 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; 1674 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1675 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1676 dmas = <&dmac0 2>, <&dmac0 3>; 1677 dma-names = "tx", "rx"; 1678 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1679 reset-names = "tx-m", "rx-m"; 1680 rockchip,trcm-sync-tx-only; 1681 pinctrl-names = "default"; 1682 pinctrl-0 = <&i2s1m0_lrck 1683 &i2s1m0_sclk 1684 &i2s1m0_sdi0 1685 &i2s1m0_sdi1 1686 &i2s1m0_sdi2 1687 &i2s1m0_sdi3 1688 &i2s1m0_sdo0 1689 &i2s1m0_sdo1 1690 &i2s1m0_sdo2 1691 &i2s1m0_sdo3>; 1692 #sound-dai-cells = <0>; 1693 status = "disabled"; 1694 }; 1695 1696 i2s2_2ch: i2s@fe490000 { 1697 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1698 reg = <0x0 0xfe490000 0x0 0x1000>; 1699 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; 1700 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1701 clock-names = "i2s_clk", "i2s_hclk"; 1702 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1703 assigned-clock-parents = <&cru PLL_AUPLL>; 1704 dmas = <&dmac1 0>, <&dmac1 1>; 1705 dma-names = "tx", "rx"; 1706 power-domains = <&power RK3588_PD_AUDIO>; 1707 rockchip,trcm-sync-tx-only; 1708 pinctrl-names = "default"; 1709 pinctrl-0 = <&i2s2m1_lrck 1710 &i2s2m1_sclk 1711 &i2s2m1_sdi 1712 &i2s2m1_sdo>; 1713 #sound-dai-cells = <0>; 1714 status = "disabled"; 1715 }; 1716 1717 i2s3_2ch: i2s@fe4a0000 { 1718 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1719 reg = <0x0 0xfe4a0000 0x0 0x1000>; 1720 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; 1721 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 1722 clock-names = "i2s_clk", "i2s_hclk"; 1723 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 1724 assigned-clock-parents = <&cru PLL_AUPLL>; 1725 dmas = <&dmac1 2>, <&dmac1 3>; 1726 dma-names = "tx", "rx"; 1727 power-domains = <&power RK3588_PD_AUDIO>; 1728 rockchip,trcm-sync-tx-only; 1729 pinctrl-names = "default"; 1730 pinctrl-0 = <&i2s3_lrck 1731 &i2s3_sclk 1732 &i2s3_sdi 1733 &i2s3_sdo>; 1734 #sound-dai-cells = <0>; 1735 status = "disabled"; 1736 }; 1737 1738 gic: interrupt-controller@fe600000 { 1739 compatible = "arm,gic-v3"; 1740 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 1741 <0x0 0xfe680000 0 0x100000>; /* GICR */ 1742 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 1743 interrupt-controller; 1744 mbi-alias = <0x0 0xfe610000>; 1745 mbi-ranges = <424 56>; 1746 msi-controller; 1747 ranges; 1748 #address-cells = <2>; 1749 #interrupt-cells = <4>; 1750 #size-cells = <2>; 1751 1752 its0: msi-controller@fe640000 { 1753 compatible = "arm,gic-v3-its"; 1754 reg = <0x0 0xfe640000 0x0 0x20000>; 1755 msi-controller; 1756 #msi-cells = <1>; 1757 }; 1758 1759 its1: msi-controller@fe660000 { 1760 compatible = "arm,gic-v3-its"; 1761 reg = <0x0 0xfe660000 0x0 0x20000>; 1762 msi-controller; 1763 #msi-cells = <1>; 1764 }; 1765 1766 ppi-partitions { 1767 ppi_partition0: interrupt-partition-0 { 1768 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 1769 }; 1770 1771 ppi_partition1: interrupt-partition-1 { 1772 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; 1773 }; 1774 }; 1775 }; 1776 1777 dmac0: dma-controller@fea10000 { 1778 compatible = "arm,pl330", "arm,primecell"; 1779 reg = <0x0 0xfea10000 0x0 0x4000>; 1780 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, 1781 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; 1782 arm,pl330-periph-burst; 1783 clocks = <&cru ACLK_DMAC0>; 1784 clock-names = "apb_pclk"; 1785 #dma-cells = <1>; 1786 }; 1787 1788 dmac1: dma-controller@fea30000 { 1789 compatible = "arm,pl330", "arm,primecell"; 1790 reg = <0x0 0xfea30000 0x0 0x4000>; 1791 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, 1792 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; 1793 arm,pl330-periph-burst; 1794 clocks = <&cru ACLK_DMAC1>; 1795 clock-names = "apb_pclk"; 1796 #dma-cells = <1>; 1797 }; 1798 1799 i2c1: i2c@fea90000 { 1800 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1801 reg = <0x0 0xfea90000 0x0 0x1000>; 1802 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1803 clock-names = "i2c", "pclk"; 1804 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; 1805 pinctrl-0 = <&i2c1m0_xfer>; 1806 pinctrl-names = "default"; 1807 #address-cells = <1>; 1808 #size-cells = <0>; 1809 status = "disabled"; 1810 }; 1811 1812 i2c2: i2c@feaa0000 { 1813 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1814 reg = <0x0 0xfeaa0000 0x0 0x1000>; 1815 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1816 clock-names = "i2c", "pclk"; 1817 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; 1818 pinctrl-0 = <&i2c2m0_xfer>; 1819 pinctrl-names = "default"; 1820 #address-cells = <1>; 1821 #size-cells = <0>; 1822 status = "disabled"; 1823 }; 1824 1825 i2c3: i2c@feab0000 { 1826 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1827 reg = <0x0 0xfeab0000 0x0 0x1000>; 1828 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1829 clock-names = "i2c", "pclk"; 1830 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; 1831 pinctrl-0 = <&i2c3m0_xfer>; 1832 pinctrl-names = "default"; 1833 #address-cells = <1>; 1834 #size-cells = <0>; 1835 status = "disabled"; 1836 }; 1837 1838 i2c4: i2c@feac0000 { 1839 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1840 reg = <0x0 0xfeac0000 0x0 0x1000>; 1841 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1842 clock-names = "i2c", "pclk"; 1843 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; 1844 pinctrl-0 = <&i2c4m0_xfer>; 1845 pinctrl-names = "default"; 1846 #address-cells = <1>; 1847 #size-cells = <0>; 1848 status = "disabled"; 1849 }; 1850 1851 i2c5: i2c@fead0000 { 1852 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1853 reg = <0x0 0xfead0000 0x0 0x1000>; 1854 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1855 clock-names = "i2c", "pclk"; 1856 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; 1857 pinctrl-0 = <&i2c5m0_xfer>; 1858 pinctrl-names = "default"; 1859 #address-cells = <1>; 1860 #size-cells = <0>; 1861 status = "disabled"; 1862 }; 1863 1864 timer0: timer@feae0000 { 1865 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 1866 reg = <0x0 0xfeae0000 0x0 0x20>; 1867 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; 1868 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 1869 clock-names = "pclk", "timer"; 1870 }; 1871 1872 wdt: watchdog@feaf0000 { 1873 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; 1874 reg = <0x0 0xfeaf0000 0x0 0x100>; 1875 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 1876 clock-names = "tclk", "pclk"; 1877 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; 1878 }; 1879 1880 spi0: spi@feb00000 { 1881 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1882 reg = <0x0 0xfeb00000 0x0 0x1000>; 1883 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; 1884 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1885 clock-names = "spiclk", "apb_pclk"; 1886 dmas = <&dmac0 14>, <&dmac0 15>; 1887 dma-names = "tx", "rx"; 1888 num-cs = <2>; 1889 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1890 pinctrl-names = "default"; 1891 #address-cells = <1>; 1892 #size-cells = <0>; 1893 status = "disabled"; 1894 }; 1895 1896 spi1: spi@feb10000 { 1897 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1898 reg = <0x0 0xfeb10000 0x0 0x1000>; 1899 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; 1900 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1901 clock-names = "spiclk", "apb_pclk"; 1902 dmas = <&dmac0 16>, <&dmac0 17>; 1903 dma-names = "tx", "rx"; 1904 num-cs = <2>; 1905 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 1906 pinctrl-names = "default"; 1907 #address-cells = <1>; 1908 #size-cells = <0>; 1909 status = "disabled"; 1910 }; 1911 1912 spi2: spi@feb20000 { 1913 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1914 reg = <0x0 0xfeb20000 0x0 0x1000>; 1915 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; 1916 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1917 clock-names = "spiclk", "apb_pclk"; 1918 dmas = <&dmac1 15>, <&dmac1 16>; 1919 dma-names = "tx", "rx"; 1920 num-cs = <2>; 1921 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 1922 pinctrl-names = "default"; 1923 #address-cells = <1>; 1924 #size-cells = <0>; 1925 status = "disabled"; 1926 }; 1927 1928 spi3: spi@feb30000 { 1929 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1930 reg = <0x0 0xfeb30000 0x0 0x1000>; 1931 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; 1932 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1933 clock-names = "spiclk", "apb_pclk"; 1934 dmas = <&dmac1 17>, <&dmac1 18>; 1935 dma-names = "tx", "rx"; 1936 num-cs = <2>; 1937 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 1938 pinctrl-names = "default"; 1939 #address-cells = <1>; 1940 #size-cells = <0>; 1941 status = "disabled"; 1942 }; 1943 1944 uart1: serial@feb40000 { 1945 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1946 reg = <0x0 0xfeb40000 0x0 0x100>; 1947 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; 1948 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1949 clock-names = "baudclk", "apb_pclk"; 1950 dmas = <&dmac0 8>, <&dmac0 9>; 1951 dma-names = "tx", "rx"; 1952 pinctrl-0 = <&uart1m1_xfer>; 1953 pinctrl-names = "default"; 1954 reg-io-width = <4>; 1955 reg-shift = <2>; 1956 status = "disabled"; 1957 }; 1958 1959 uart2: serial@feb50000 { 1960 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1961 reg = <0x0 0xfeb50000 0x0 0x100>; 1962 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; 1963 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1964 clock-names = "baudclk", "apb_pclk"; 1965 dmas = <&dmac0 10>, <&dmac0 11>; 1966 dma-names = "tx", "rx"; 1967 pinctrl-0 = <&uart2m1_xfer>; 1968 pinctrl-names = "default"; 1969 reg-io-width = <4>; 1970 reg-shift = <2>; 1971 status = "disabled"; 1972 }; 1973 1974 uart3: serial@feb60000 { 1975 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1976 reg = <0x0 0xfeb60000 0x0 0x100>; 1977 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; 1978 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1979 clock-names = "baudclk", "apb_pclk"; 1980 dmas = <&dmac0 12>, <&dmac0 13>; 1981 dma-names = "tx", "rx"; 1982 pinctrl-0 = <&uart3m1_xfer>; 1983 pinctrl-names = "default"; 1984 reg-io-width = <4>; 1985 reg-shift = <2>; 1986 status = "disabled"; 1987 }; 1988 1989 uart4: serial@feb70000 { 1990 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1991 reg = <0x0 0xfeb70000 0x0 0x100>; 1992 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; 1993 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1994 clock-names = "baudclk", "apb_pclk"; 1995 dmas = <&dmac1 9>, <&dmac1 10>; 1996 dma-names = "tx", "rx"; 1997 pinctrl-0 = <&uart4m1_xfer>; 1998 pinctrl-names = "default"; 1999 reg-io-width = <4>; 2000 reg-shift = <2>; 2001 status = "disabled"; 2002 }; 2003 2004 uart5: serial@feb80000 { 2005 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2006 reg = <0x0 0xfeb80000 0x0 0x100>; 2007 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; 2008 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2009 clock-names = "baudclk", "apb_pclk"; 2010 dmas = <&dmac1 11>, <&dmac1 12>; 2011 dma-names = "tx", "rx"; 2012 pinctrl-0 = <&uart5m1_xfer>; 2013 pinctrl-names = "default"; 2014 reg-io-width = <4>; 2015 reg-shift = <2>; 2016 status = "disabled"; 2017 }; 2018 2019 uart6: serial@feb90000 { 2020 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2021 reg = <0x0 0xfeb90000 0x0 0x100>; 2022 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; 2023 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2024 clock-names = "baudclk", "apb_pclk"; 2025 dmas = <&dmac1 13>, <&dmac1 14>; 2026 dma-names = "tx", "rx"; 2027 pinctrl-0 = <&uart6m1_xfer>; 2028 pinctrl-names = "default"; 2029 reg-io-width = <4>; 2030 reg-shift = <2>; 2031 status = "disabled"; 2032 }; 2033 2034 uart7: serial@feba0000 { 2035 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2036 reg = <0x0 0xfeba0000 0x0 0x100>; 2037 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; 2038 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2039 clock-names = "baudclk", "apb_pclk"; 2040 dmas = <&dmac2 7>, <&dmac2 8>; 2041 dma-names = "tx", "rx"; 2042 pinctrl-0 = <&uart7m1_xfer>; 2043 pinctrl-names = "default"; 2044 reg-io-width = <4>; 2045 reg-shift = <2>; 2046 status = "disabled"; 2047 }; 2048 2049 uart8: serial@febb0000 { 2050 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2051 reg = <0x0 0xfebb0000 0x0 0x100>; 2052 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; 2053 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2054 clock-names = "baudclk", "apb_pclk"; 2055 dmas = <&dmac2 9>, <&dmac2 10>; 2056 dma-names = "tx", "rx"; 2057 pinctrl-0 = <&uart8m1_xfer>; 2058 pinctrl-names = "default"; 2059 reg-io-width = <4>; 2060 reg-shift = <2>; 2061 status = "disabled"; 2062 }; 2063 2064 uart9: serial@febc0000 { 2065 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2066 reg = <0x0 0xfebc0000 0x0 0x100>; 2067 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; 2068 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2069 clock-names = "baudclk", "apb_pclk"; 2070 dmas = <&dmac2 11>, <&dmac2 12>; 2071 dma-names = "tx", "rx"; 2072 pinctrl-0 = <&uart9m1_xfer>; 2073 pinctrl-names = "default"; 2074 reg-io-width = <4>; 2075 reg-shift = <2>; 2076 status = "disabled"; 2077 }; 2078 2079 pwm4: pwm@febd0000 { 2080 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2081 reg = <0x0 0xfebd0000 0x0 0x10>; 2082 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2083 clock-names = "pwm", "pclk"; 2084 pinctrl-0 = <&pwm4m0_pins>; 2085 pinctrl-names = "default"; 2086 #pwm-cells = <3>; 2087 status = "disabled"; 2088 }; 2089 2090 pwm5: pwm@febd0010 { 2091 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2092 reg = <0x0 0xfebd0010 0x0 0x10>; 2093 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2094 clock-names = "pwm", "pclk"; 2095 pinctrl-0 = <&pwm5m0_pins>; 2096 pinctrl-names = "default"; 2097 #pwm-cells = <3>; 2098 status = "disabled"; 2099 }; 2100 2101 pwm6: pwm@febd0020 { 2102 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2103 reg = <0x0 0xfebd0020 0x0 0x10>; 2104 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2105 clock-names = "pwm", "pclk"; 2106 pinctrl-0 = <&pwm6m0_pins>; 2107 pinctrl-names = "default"; 2108 #pwm-cells = <3>; 2109 status = "disabled"; 2110 }; 2111 2112 pwm7: pwm@febd0030 { 2113 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2114 reg = <0x0 0xfebd0030 0x0 0x10>; 2115 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2116 clock-names = "pwm", "pclk"; 2117 pinctrl-0 = <&pwm7m0_pins>; 2118 pinctrl-names = "default"; 2119 #pwm-cells = <3>; 2120 status = "disabled"; 2121 }; 2122 2123 pwm8: pwm@febe0000 { 2124 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2125 reg = <0x0 0xfebe0000 0x0 0x10>; 2126 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2127 clock-names = "pwm", "pclk"; 2128 pinctrl-0 = <&pwm8m0_pins>; 2129 pinctrl-names = "default"; 2130 #pwm-cells = <3>; 2131 status = "disabled"; 2132 }; 2133 2134 pwm9: pwm@febe0010 { 2135 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2136 reg = <0x0 0xfebe0010 0x0 0x10>; 2137 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2138 clock-names = "pwm", "pclk"; 2139 pinctrl-0 = <&pwm9m0_pins>; 2140 pinctrl-names = "default"; 2141 #pwm-cells = <3>; 2142 status = "disabled"; 2143 }; 2144 2145 pwm10: pwm@febe0020 { 2146 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2147 reg = <0x0 0xfebe0020 0x0 0x10>; 2148 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2149 clock-names = "pwm", "pclk"; 2150 pinctrl-0 = <&pwm10m0_pins>; 2151 pinctrl-names = "default"; 2152 #pwm-cells = <3>; 2153 status = "disabled"; 2154 }; 2155 2156 pwm11: pwm@febe0030 { 2157 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2158 reg = <0x0 0xfebe0030 0x0 0x10>; 2159 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2160 clock-names = "pwm", "pclk"; 2161 pinctrl-0 = <&pwm11m0_pins>; 2162 pinctrl-names = "default"; 2163 #pwm-cells = <3>; 2164 status = "disabled"; 2165 }; 2166 2167 pwm12: pwm@febf0000 { 2168 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2169 reg = <0x0 0xfebf0000 0x0 0x10>; 2170 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2171 clock-names = "pwm", "pclk"; 2172 pinctrl-0 = <&pwm12m0_pins>; 2173 pinctrl-names = "default"; 2174 #pwm-cells = <3>; 2175 status = "disabled"; 2176 }; 2177 2178 pwm13: pwm@febf0010 { 2179 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2180 reg = <0x0 0xfebf0010 0x0 0x10>; 2181 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2182 clock-names = "pwm", "pclk"; 2183 pinctrl-0 = <&pwm13m0_pins>; 2184 pinctrl-names = "default"; 2185 #pwm-cells = <3>; 2186 status = "disabled"; 2187 }; 2188 2189 pwm14: pwm@febf0020 { 2190 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2191 reg = <0x0 0xfebf0020 0x0 0x10>; 2192 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2193 clock-names = "pwm", "pclk"; 2194 pinctrl-0 = <&pwm14m0_pins>; 2195 pinctrl-names = "default"; 2196 #pwm-cells = <3>; 2197 status = "disabled"; 2198 }; 2199 2200 pwm15: pwm@febf0030 { 2201 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2202 reg = <0x0 0xfebf0030 0x0 0x10>; 2203 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2204 clock-names = "pwm", "pclk"; 2205 pinctrl-0 = <&pwm15m0_pins>; 2206 pinctrl-names = "default"; 2207 #pwm-cells = <3>; 2208 status = "disabled"; 2209 }; 2210 2211 tsadc: tsadc@fec00000 { 2212 compatible = "rockchip,rk3588-tsadc"; 2213 reg = <0x0 0xfec00000 0x0 0x400>; 2214 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; 2215 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2216 clock-names = "tsadc", "apb_pclk"; 2217 assigned-clocks = <&cru CLK_TSADC>; 2218 assigned-clock-rates = <2000000>; 2219 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 2220 reset-names = "tsadc-apb", "tsadc"; 2221 rockchip,hw-tshut-temp = <120000>; 2222 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 2223 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2224 pinctrl-0 = <&tsadc_gpio_func>; 2225 pinctrl-1 = <&tsadc_shut>; 2226 pinctrl-names = "gpio", "otpout"; 2227 #thermal-sensor-cells = <1>; 2228 status = "disabled"; 2229 }; 2230 2231 saradc: adc@fec10000 { 2232 compatible = "rockchip,rk3588-saradc"; 2233 reg = <0x0 0xfec10000 0x0 0x10000>; 2234 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; 2235 #io-channel-cells = <1>; 2236 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2237 clock-names = "saradc", "apb_pclk"; 2238 resets = <&cru SRST_P_SARADC>; 2239 reset-names = "saradc-apb"; 2240 status = "disabled"; 2241 }; 2242 2243 i2c6: i2c@fec80000 { 2244 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2245 reg = <0x0 0xfec80000 0x0 0x1000>; 2246 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2247 clock-names = "i2c", "pclk"; 2248 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; 2249 pinctrl-0 = <&i2c6m0_xfer>; 2250 pinctrl-names = "default"; 2251 #address-cells = <1>; 2252 #size-cells = <0>; 2253 status = "disabled"; 2254 }; 2255 2256 i2c7: i2c@fec90000 { 2257 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2258 reg = <0x0 0xfec90000 0x0 0x1000>; 2259 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2260 clock-names = "i2c", "pclk"; 2261 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 2262 pinctrl-0 = <&i2c7m0_xfer>; 2263 pinctrl-names = "default"; 2264 #address-cells = <1>; 2265 #size-cells = <0>; 2266 status = "disabled"; 2267 }; 2268 2269 i2c8: i2c@feca0000 { 2270 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2271 reg = <0x0 0xfeca0000 0x0 0x1000>; 2272 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2273 clock-names = "i2c", "pclk"; 2274 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; 2275 pinctrl-0 = <&i2c8m0_xfer>; 2276 pinctrl-names = "default"; 2277 #address-cells = <1>; 2278 #size-cells = <0>; 2279 status = "disabled"; 2280 }; 2281 2282 spi4: spi@fecb0000 { 2283 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2284 reg = <0x0 0xfecb0000 0x0 0x1000>; 2285 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; 2286 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2287 clock-names = "spiclk", "apb_pclk"; 2288 dmas = <&dmac2 13>, <&dmac2 14>; 2289 dma-names = "tx", "rx"; 2290 num-cs = <2>; 2291 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 2292 pinctrl-names = "default"; 2293 #address-cells = <1>; 2294 #size-cells = <0>; 2295 status = "disabled"; 2296 }; 2297 2298 otp: efuse@fecc0000 { 2299 compatible = "rockchip,rk3588-otp"; 2300 reg = <0x0 0xfecc0000 0x0 0x400>; 2301 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 2302 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; 2303 clock-names = "otp", "apb_pclk", "phy", "arb"; 2304 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 2305 <&cru SRST_OTPC_ARB>; 2306 reset-names = "otp", "apb", "arb"; 2307 #address-cells = <1>; 2308 #size-cells = <1>; 2309 2310 cpu_code: cpu-code@2 { 2311 reg = <0x02 0x2>; 2312 }; 2313 2314 otp_id: id@7 { 2315 reg = <0x07 0x10>; 2316 }; 2317 2318 cpub0_leakage: cpu-leakage@17 { 2319 reg = <0x17 0x1>; 2320 }; 2321 2322 cpub1_leakage: cpu-leakage@18 { 2323 reg = <0x18 0x1>; 2324 }; 2325 2326 cpul_leakage: cpu-leakage@19 { 2327 reg = <0x19 0x1>; 2328 }; 2329 2330 log_leakage: log-leakage@1a { 2331 reg = <0x1a 0x1>; 2332 }; 2333 2334 gpu_leakage: gpu-leakage@1b { 2335 reg = <0x1b 0x1>; 2336 }; 2337 2338 otp_cpu_version: cpu-version@1c { 2339 reg = <0x1c 0x1>; 2340 bits = <3 3>; 2341 }; 2342 2343 npu_leakage: npu-leakage@28 { 2344 reg = <0x28 0x1>; 2345 }; 2346 2347 codec_leakage: codec-leakage@29 { 2348 reg = <0x29 0x1>; 2349 }; 2350 }; 2351 2352 dmac2: dma-controller@fed10000 { 2353 compatible = "arm,pl330", "arm,primecell"; 2354 reg = <0x0 0xfed10000 0x0 0x4000>; 2355 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, 2356 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; 2357 arm,pl330-periph-burst; 2358 clocks = <&cru ACLK_DMAC2>; 2359 clock-names = "apb_pclk"; 2360 #dma-cells = <1>; 2361 }; 2362 2363 combphy0_ps: phy@fee00000 { 2364 compatible = "rockchip,rk3588-naneng-combphy"; 2365 reg = <0x0 0xfee00000 0x0 0x100>; 2366 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, 2367 <&cru PCLK_PHP_ROOT>; 2368 clock-names = "ref", "apb", "pipe"; 2369 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 2370 assigned-clock-rates = <100000000>; 2371 #phy-cells = <1>; 2372 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; 2373 reset-names = "phy", "apb"; 2374 rockchip,pipe-grf = <&php_grf>; 2375 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 2376 status = "disabled"; 2377 }; 2378 2379 combphy2_psu: phy@fee20000 { 2380 compatible = "rockchip,rk3588-naneng-combphy"; 2381 reg = <0x0 0xfee20000 0x0 0x100>; 2382 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, 2383 <&cru PCLK_PHP_ROOT>; 2384 clock-names = "ref", "apb", "pipe"; 2385 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 2386 assigned-clock-rates = <100000000>; 2387 #phy-cells = <1>; 2388 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; 2389 reset-names = "phy", "apb"; 2390 rockchip,pipe-grf = <&php_grf>; 2391 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 2392 status = "disabled"; 2393 }; 2394 2395 system_sram2: sram@ff001000 { 2396 compatible = "mmio-sram"; 2397 reg = <0x0 0xff001000 0x0 0xef000>; 2398 ranges = <0x0 0x0 0xff001000 0xef000>; 2399 #address-cells = <1>; 2400 #size-cells = <1>; 2401 }; 2402 2403 pinctrl: pinctrl { 2404 compatible = "rockchip,rk3588-pinctrl"; 2405 ranges; 2406 rockchip,grf = <&ioc>; 2407 #address-cells = <2>; 2408 #size-cells = <2>; 2409 2410 gpio0: gpio@fd8a0000 { 2411 compatible = "rockchip,gpio-bank"; 2412 reg = <0x0 0xfd8a0000 0x0 0x100>; 2413 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 2414 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 2415 gpio-controller; 2416 gpio-ranges = <&pinctrl 0 0 32>; 2417 interrupt-controller; 2418 #gpio-cells = <2>; 2419 #interrupt-cells = <2>; 2420 }; 2421 2422 gpio1: gpio@fec20000 { 2423 compatible = "rockchip,gpio-bank"; 2424 reg = <0x0 0xfec20000 0x0 0x100>; 2425 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; 2426 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2427 gpio-controller; 2428 gpio-ranges = <&pinctrl 0 32 32>; 2429 interrupt-controller; 2430 #gpio-cells = <2>; 2431 #interrupt-cells = <2>; 2432 }; 2433 2434 gpio2: gpio@fec30000 { 2435 compatible = "rockchip,gpio-bank"; 2436 reg = <0x0 0xfec30000 0x0 0x100>; 2437 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; 2438 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2439 gpio-controller; 2440 gpio-ranges = <&pinctrl 0 64 32>; 2441 interrupt-controller; 2442 #gpio-cells = <2>; 2443 #interrupt-cells = <2>; 2444 }; 2445 2446 gpio3: gpio@fec40000 { 2447 compatible = "rockchip,gpio-bank"; 2448 reg = <0x0 0xfec40000 0x0 0x100>; 2449 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; 2450 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2451 gpio-controller; 2452 gpio-ranges = <&pinctrl 0 96 32>; 2453 interrupt-controller; 2454 #gpio-cells = <2>; 2455 #interrupt-cells = <2>; 2456 }; 2457 2458 gpio4: gpio@fec50000 { 2459 compatible = "rockchip,gpio-bank"; 2460 reg = <0x0 0xfec50000 0x0 0x100>; 2461 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; 2462 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2463 gpio-controller; 2464 gpio-ranges = <&pinctrl 0 128 32>; 2465 interrupt-controller; 2466 #gpio-cells = <2>; 2467 #interrupt-cells = <2>; 2468 }; 2469 }; 2470 2471 av1d: video-codec@fdc70000 { 2472 compatible = "rockchip,rk3588-av1-vpu"; 2473 reg = <0x0 0xfdc70000 0x0 0x800>; 2474 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 2475 interrupt-names = "vdpu"; 2476 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 2477 assigned-clock-rates = <400000000>, <400000000>; 2478 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 2479 clock-names = "aclk", "hclk"; 2480 power-domains = <&power RK3588_PD_AV1>; 2481 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; 2482 }; 2483}; 2484 2485#include "rk3588s-pinctrl.dtsi" 2486