1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/power/rk3588-power.h> 10#include <dt-bindings/reset/rockchip,rk3588-cru.h> 11 12/ { 13 compatible = "rockchip,rk3588"; 14 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu-map { 24 cluster0 { 25 core0 { 26 cpu = <&cpu_l0>; 27 }; 28 core1 { 29 cpu = <&cpu_l1>; 30 }; 31 core2 { 32 cpu = <&cpu_l2>; 33 }; 34 core3 { 35 cpu = <&cpu_l3>; 36 }; 37 }; 38 cluster1 { 39 core0 { 40 cpu = <&cpu_b0>; 41 }; 42 core1 { 43 cpu = <&cpu_b1>; 44 }; 45 }; 46 cluster2 { 47 core0 { 48 cpu = <&cpu_b2>; 49 }; 50 core1 { 51 cpu = <&cpu_b3>; 52 }; 53 }; 54 }; 55 56 cpu_l0: cpu@0 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a55"; 59 reg = <0x0>; 60 enable-method = "psci"; 61 capacity-dmips-mhz = <530>; 62 clocks = <&scmi_clk SCMI_CLK_CPUL>; 63 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; 64 assigned-clock-rates = <816000000>; 65 cpu-idle-states = <&CPU_SLEEP>; 66 i-cache-size = <32768>; 67 i-cache-line-size = <64>; 68 i-cache-sets = <128>; 69 d-cache-size = <32768>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 next-level-cache = <&l2_cache_l0>; 73 dynamic-power-coefficient = <228>; 74 #cooling-cells = <2>; 75 }; 76 77 cpu_l1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a55"; 80 reg = <0x100>; 81 enable-method = "psci"; 82 capacity-dmips-mhz = <530>; 83 clocks = <&scmi_clk SCMI_CLK_CPUL>; 84 cpu-idle-states = <&CPU_SLEEP>; 85 i-cache-size = <32768>; 86 i-cache-line-size = <64>; 87 i-cache-sets = <128>; 88 d-cache-size = <32768>; 89 d-cache-line-size = <64>; 90 d-cache-sets = <128>; 91 next-level-cache = <&l2_cache_l1>; 92 dynamic-power-coefficient = <228>; 93 #cooling-cells = <2>; 94 }; 95 96 cpu_l2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a55"; 99 reg = <0x200>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <530>; 102 clocks = <&scmi_clk SCMI_CLK_CPUL>; 103 cpu-idle-states = <&CPU_SLEEP>; 104 i-cache-size = <32768>; 105 i-cache-line-size = <64>; 106 i-cache-sets = <128>; 107 d-cache-size = <32768>; 108 d-cache-line-size = <64>; 109 d-cache-sets = <128>; 110 next-level-cache = <&l2_cache_l2>; 111 dynamic-power-coefficient = <228>; 112 #cooling-cells = <2>; 113 }; 114 115 cpu_l3: cpu@300 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a55"; 118 reg = <0x300>; 119 enable-method = "psci"; 120 capacity-dmips-mhz = <530>; 121 clocks = <&scmi_clk SCMI_CLK_CPUL>; 122 cpu-idle-states = <&CPU_SLEEP>; 123 i-cache-size = <32768>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <128>; 126 d-cache-size = <32768>; 127 d-cache-line-size = <64>; 128 d-cache-sets = <128>; 129 next-level-cache = <&l2_cache_l3>; 130 dynamic-power-coefficient = <228>; 131 #cooling-cells = <2>; 132 }; 133 134 cpu_b0: cpu@400 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a76"; 137 reg = <0x400>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <1024>; 140 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 141 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; 142 assigned-clock-rates = <816000000>; 143 cpu-idle-states = <&CPU_SLEEP>; 144 i-cache-size = <65536>; 145 i-cache-line-size = <64>; 146 i-cache-sets = <256>; 147 d-cache-size = <65536>; 148 d-cache-line-size = <64>; 149 d-cache-sets = <256>; 150 next-level-cache = <&l2_cache_b0>; 151 dynamic-power-coefficient = <416>; 152 #cooling-cells = <2>; 153 }; 154 155 cpu_b1: cpu@500 { 156 device_type = "cpu"; 157 compatible = "arm,cortex-a76"; 158 reg = <0x500>; 159 enable-method = "psci"; 160 capacity-dmips-mhz = <1024>; 161 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 162 cpu-idle-states = <&CPU_SLEEP>; 163 i-cache-size = <65536>; 164 i-cache-line-size = <64>; 165 i-cache-sets = <256>; 166 d-cache-size = <65536>; 167 d-cache-line-size = <64>; 168 d-cache-sets = <256>; 169 next-level-cache = <&l2_cache_b1>; 170 dynamic-power-coefficient = <416>; 171 #cooling-cells = <2>; 172 }; 173 174 cpu_b2: cpu@600 { 175 device_type = "cpu"; 176 compatible = "arm,cortex-a76"; 177 reg = <0x600>; 178 enable-method = "psci"; 179 capacity-dmips-mhz = <1024>; 180 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 181 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; 182 assigned-clock-rates = <816000000>; 183 cpu-idle-states = <&CPU_SLEEP>; 184 i-cache-size = <65536>; 185 i-cache-line-size = <64>; 186 i-cache-sets = <256>; 187 d-cache-size = <65536>; 188 d-cache-line-size = <64>; 189 d-cache-sets = <256>; 190 next-level-cache = <&l2_cache_b2>; 191 dynamic-power-coefficient = <416>; 192 #cooling-cells = <2>; 193 }; 194 195 cpu_b3: cpu@700 { 196 device_type = "cpu"; 197 compatible = "arm,cortex-a76"; 198 reg = <0x700>; 199 enable-method = "psci"; 200 capacity-dmips-mhz = <1024>; 201 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 202 cpu-idle-states = <&CPU_SLEEP>; 203 i-cache-size = <65536>; 204 i-cache-line-size = <64>; 205 i-cache-sets = <256>; 206 d-cache-size = <65536>; 207 d-cache-line-size = <64>; 208 d-cache-sets = <256>; 209 next-level-cache = <&l2_cache_b3>; 210 dynamic-power-coefficient = <416>; 211 #cooling-cells = <2>; 212 }; 213 214 idle-states { 215 entry-method = "psci"; 216 CPU_SLEEP: cpu-sleep { 217 compatible = "arm,idle-state"; 218 local-timer-stop; 219 arm,psci-suspend-param = <0x0010000>; 220 entry-latency-us = <100>; 221 exit-latency-us = <120>; 222 min-residency-us = <1000>; 223 }; 224 }; 225 226 l2_cache_l0: l2-cache-l0 { 227 compatible = "cache"; 228 cache-size = <131072>; 229 cache-line-size = <64>; 230 cache-sets = <512>; 231 cache-level = <2>; 232 next-level-cache = <&l3_cache>; 233 }; 234 235 l2_cache_l1: l2-cache-l1 { 236 compatible = "cache"; 237 cache-size = <131072>; 238 cache-line-size = <64>; 239 cache-sets = <512>; 240 cache-level = <2>; 241 next-level-cache = <&l3_cache>; 242 }; 243 244 l2_cache_l2: l2-cache-l2 { 245 compatible = "cache"; 246 cache-size = <131072>; 247 cache-line-size = <64>; 248 cache-sets = <512>; 249 cache-level = <2>; 250 next-level-cache = <&l3_cache>; 251 }; 252 253 l2_cache_l3: l2-cache-l3 { 254 compatible = "cache"; 255 cache-size = <131072>; 256 cache-line-size = <64>; 257 cache-sets = <512>; 258 cache-level = <2>; 259 next-level-cache = <&l3_cache>; 260 }; 261 262 l2_cache_b0: l2-cache-b0 { 263 compatible = "cache"; 264 cache-size = <524288>; 265 cache-line-size = <64>; 266 cache-sets = <1024>; 267 cache-level = <2>; 268 next-level-cache = <&l3_cache>; 269 }; 270 271 l2_cache_b1: l2-cache-b1 { 272 compatible = "cache"; 273 cache-size = <524288>; 274 cache-line-size = <64>; 275 cache-sets = <1024>; 276 cache-level = <2>; 277 next-level-cache = <&l3_cache>; 278 }; 279 280 l2_cache_b2: l2-cache-b2 { 281 compatible = "cache"; 282 cache-size = <524288>; 283 cache-line-size = <64>; 284 cache-sets = <1024>; 285 cache-level = <2>; 286 next-level-cache = <&l3_cache>; 287 }; 288 289 l2_cache_b3: l2-cache-b3 { 290 compatible = "cache"; 291 cache-size = <524288>; 292 cache-line-size = <64>; 293 cache-sets = <1024>; 294 cache-level = <2>; 295 next-level-cache = <&l3_cache>; 296 }; 297 298 l3_cache: l3-cache { 299 compatible = "cache"; 300 cache-size = <3145728>; 301 cache-line-size = <64>; 302 cache-sets = <4096>; 303 cache-level = <3>; 304 }; 305 }; 306 307 firmware { 308 optee: optee { 309 compatible = "linaro,optee-tz"; 310 method = "smc"; 311 }; 312 313 scmi: scmi { 314 compatible = "arm,scmi-smc"; 315 arm,smc-id = <0x82000010>; 316 shmem = <&scmi_shmem>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 320 scmi_clk: protocol@14 { 321 reg = <0x14>; 322 #clock-cells = <1>; 323 }; 324 325 scmi_reset: protocol@16 { 326 reg = <0x16>; 327 #reset-cells = <1>; 328 }; 329 }; 330 }; 331 332 pmu-a55 { 333 compatible = "arm,cortex-a55-pmu"; 334 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; 335 }; 336 337 pmu-a76 { 338 compatible = "arm,cortex-a76-pmu"; 339 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; 340 }; 341 342 psci { 343 compatible = "arm,psci-1.0"; 344 method = "smc"; 345 }; 346 347 spll: clock-0 { 348 compatible = "fixed-clock"; 349 clock-frequency = <702000000>; 350 clock-output-names = "spll"; 351 #clock-cells = <0>; 352 }; 353 354 timer { 355 compatible = "arm,armv8-timer"; 356 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 357 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 358 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 359 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, 360 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 361 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 362 }; 363 364 xin24m: clock-1 { 365 compatible = "fixed-clock"; 366 clock-frequency = <24000000>; 367 clock-output-names = "xin24m"; 368 #clock-cells = <0>; 369 }; 370 371 xin32k: clock-2 { 372 compatible = "fixed-clock"; 373 clock-frequency = <32768>; 374 clock-output-names = "xin32k"; 375 #clock-cells = <0>; 376 }; 377 378 pmu_sram: sram@10f000 { 379 compatible = "mmio-sram"; 380 reg = <0x0 0x0010f000 0x0 0x100>; 381 ranges = <0 0x0 0x0010f000 0x100>; 382 #address-cells = <1>; 383 #size-cells = <1>; 384 385 scmi_shmem: sram@0 { 386 compatible = "arm,scmi-shmem"; 387 reg = <0x0 0x100>; 388 }; 389 }; 390 391 sys_grf: syscon@fd58c000 { 392 compatible = "rockchip,rk3588-sys-grf", "syscon"; 393 reg = <0x0 0xfd58c000 0x0 0x1000>; 394 }; 395 396 php_grf: syscon@fd5b0000 { 397 compatible = "rockchip,rk3588-php-grf", "syscon"; 398 reg = <0x0 0xfd5b0000 0x0 0x1000>; 399 }; 400 401 ioc: syscon@fd5f0000 { 402 compatible = "rockchip,rk3588-ioc", "syscon"; 403 reg = <0x0 0xfd5f0000 0x0 0x10000>; 404 }; 405 406 system_sram1: sram@fd600000 { 407 compatible = "mmio-sram"; 408 reg = <0x0 0xfd600000 0x0 0x100000>; 409 ranges = <0x0 0x0 0xfd600000 0x100000>; 410 #address-cells = <1>; 411 #size-cells = <1>; 412 }; 413 414 cru: clock-controller@fd7c0000 { 415 compatible = "rockchip,rk3588-cru"; 416 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 417 assigned-clocks = 418 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 419 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 420 <&cru ACLK_CENTER_ROOT>, 421 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 422 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 423 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 424 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, 425 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 426 <&cru CLK_GPU>; 427 assigned-clock-rates = 428 <1100000000>, <786432000>, 429 <850000000>, <1188000000>, 430 <702000000>, 431 <400000000>, <500000000>, 432 <800000000>, <100000000>, 433 <400000000>, <100000000>, 434 <200000000>, <500000000>, 435 <375000000>, <150000000>, 436 <200000000>; 437 rockchip,grf = <&php_grf>; 438 #clock-cells = <1>; 439 #reset-cells = <1>; 440 }; 441 442 i2c0: i2c@fd880000 { 443 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 444 reg = <0x0 0xfd880000 0x0 0x1000>; 445 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; 446 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 447 clock-names = "i2c", "pclk"; 448 pinctrl-0 = <&i2c0m0_xfer>; 449 pinctrl-names = "default"; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 status = "disabled"; 453 }; 454 455 uart0: serial@fd890000 { 456 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 457 reg = <0x0 0xfd890000 0x0 0x100>; 458 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 459 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 460 clock-names = "baudclk", "apb_pclk"; 461 dmas = <&dmac0 6>, <&dmac0 7>; 462 dma-names = "tx", "rx"; 463 pinctrl-0 = <&uart0m1_xfer>; 464 pinctrl-names = "default"; 465 reg-shift = <2>; 466 reg-io-width = <4>; 467 status = "disabled"; 468 }; 469 470 pwm0: pwm@fd8b0000 { 471 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 472 reg = <0x0 0xfd8b0000 0x0 0x10>; 473 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 474 clock-names = "pwm", "pclk"; 475 pinctrl-0 = <&pwm0m0_pins>; 476 pinctrl-names = "default"; 477 #pwm-cells = <3>; 478 status = "disabled"; 479 }; 480 481 pwm1: pwm@fd8b0010 { 482 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 483 reg = <0x0 0xfd8b0010 0x0 0x10>; 484 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 485 clock-names = "pwm", "pclk"; 486 pinctrl-0 = <&pwm1m0_pins>; 487 pinctrl-names = "default"; 488 #pwm-cells = <3>; 489 status = "disabled"; 490 }; 491 492 pwm2: pwm@fd8b0020 { 493 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 494 reg = <0x0 0xfd8b0020 0x0 0x10>; 495 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 496 clock-names = "pwm", "pclk"; 497 pinctrl-0 = <&pwm2m0_pins>; 498 pinctrl-names = "default"; 499 #pwm-cells = <3>; 500 status = "disabled"; 501 }; 502 503 pwm3: pwm@fd8b0030 { 504 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 505 reg = <0x0 0xfd8b0030 0x0 0x10>; 506 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 507 clock-names = "pwm", "pclk"; 508 pinctrl-0 = <&pwm3m0_pins>; 509 pinctrl-names = "default"; 510 #pwm-cells = <3>; 511 status = "disabled"; 512 }; 513 514 pmu: power-management@fd8d8000 { 515 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 516 reg = <0x0 0xfd8d8000 0x0 0x400>; 517 518 power: power-controller { 519 compatible = "rockchip,rk3588-power-controller"; 520 #address-cells = <1>; 521 #power-domain-cells = <1>; 522 #size-cells = <0>; 523 status = "okay"; 524 525 /* These power domains are grouped by VD_NPU */ 526 power-domain@RK3588_PD_NPU { 527 reg = <RK3588_PD_NPU>; 528 #power-domain-cells = <0>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 532 power-domain@RK3588_PD_NPUTOP { 533 reg = <RK3588_PD_NPUTOP>; 534 clocks = <&cru HCLK_NPU_ROOT>, 535 <&cru PCLK_NPU_ROOT>, 536 <&cru CLK_NPU_DSU0>, 537 <&cru HCLK_NPU_CM0_ROOT>; 538 pm_qos = <&qos_npu0_mwr>, 539 <&qos_npu0_mro>, 540 <&qos_mcu_npu>; 541 #power-domain-cells = <0>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 545 power-domain@RK3588_PD_NPU1 { 546 reg = <RK3588_PD_NPU1>; 547 clocks = <&cru HCLK_NPU_ROOT>, 548 <&cru PCLK_NPU_ROOT>, 549 <&cru CLK_NPU_DSU0>; 550 pm_qos = <&qos_npu1>; 551 #power-domain-cells = <0>; 552 }; 553 power-domain@RK3588_PD_NPU2 { 554 reg = <RK3588_PD_NPU2>; 555 clocks = <&cru HCLK_NPU_ROOT>, 556 <&cru PCLK_NPU_ROOT>, 557 <&cru CLK_NPU_DSU0>; 558 pm_qos = <&qos_npu2>; 559 #power-domain-cells = <0>; 560 }; 561 }; 562 }; 563 /* These power domains are grouped by VD_GPU */ 564 power-domain@RK3588_PD_GPU { 565 reg = <RK3588_PD_GPU>; 566 clocks = <&cru CLK_GPU>, 567 <&cru CLK_GPU_COREGROUP>, 568 <&cru CLK_GPU_STACKS>; 569 pm_qos = <&qos_gpu_m0>, 570 <&qos_gpu_m1>, 571 <&qos_gpu_m2>, 572 <&qos_gpu_m3>; 573 #power-domain-cells = <0>; 574 }; 575 /* These power domains are grouped by VD_VCODEC */ 576 power-domain@RK3588_PD_VCODEC { 577 reg = <RK3588_PD_VCODEC>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 #power-domain-cells = <0>; 581 582 power-domain@RK3588_PD_RKVDEC0 { 583 reg = <RK3588_PD_RKVDEC0>; 584 clocks = <&cru HCLK_RKVDEC0>, 585 <&cru HCLK_VDPU_ROOT>, 586 <&cru ACLK_VDPU_ROOT>, 587 <&cru ACLK_RKVDEC0>, 588 <&cru ACLK_RKVDEC_CCU>; 589 pm_qos = <&qos_rkvdec0>; 590 #power-domain-cells = <0>; 591 }; 592 power-domain@RK3588_PD_RKVDEC1 { 593 reg = <RK3588_PD_RKVDEC1>; 594 clocks = <&cru HCLK_RKVDEC1>, 595 <&cru HCLK_VDPU_ROOT>, 596 <&cru ACLK_VDPU_ROOT>, 597 <&cru ACLK_RKVDEC1>; 598 pm_qos = <&qos_rkvdec1>; 599 #power-domain-cells = <0>; 600 }; 601 power-domain@RK3588_PD_VENC0 { 602 reg = <RK3588_PD_VENC0>; 603 clocks = <&cru HCLK_RKVENC0>, 604 <&cru ACLK_RKVENC0>; 605 pm_qos = <&qos_rkvenc0_m0ro>, 606 <&qos_rkvenc0_m1ro>, 607 <&qos_rkvenc0_m2wo>; 608 #address-cells = <1>; 609 #size-cells = <0>; 610 #power-domain-cells = <0>; 611 612 power-domain@RK3588_PD_VENC1 { 613 reg = <RK3588_PD_VENC1>; 614 clocks = <&cru HCLK_RKVENC1>, 615 <&cru HCLK_RKVENC0>, 616 <&cru ACLK_RKVENC0>, 617 <&cru ACLK_RKVENC1>; 618 pm_qos = <&qos_rkvenc1_m0ro>, 619 <&qos_rkvenc1_m1ro>, 620 <&qos_rkvenc1_m2wo>; 621 #power-domain-cells = <0>; 622 }; 623 }; 624 }; 625 /* These power domains are grouped by VD_LOGIC */ 626 power-domain@RK3588_PD_VDPU { 627 reg = <RK3588_PD_VDPU>; 628 clocks = <&cru HCLK_VDPU_ROOT>, 629 <&cru ACLK_VDPU_LOW_ROOT>, 630 <&cru ACLK_VDPU_ROOT>, 631 <&cru ACLK_JPEG_DECODER_ROOT>, 632 <&cru ACLK_IEP2P0>, 633 <&cru HCLK_IEP2P0>, 634 <&cru ACLK_JPEG_ENCODER0>, 635 <&cru HCLK_JPEG_ENCODER0>, 636 <&cru ACLK_JPEG_ENCODER1>, 637 <&cru HCLK_JPEG_ENCODER1>, 638 <&cru ACLK_JPEG_ENCODER2>, 639 <&cru HCLK_JPEG_ENCODER2>, 640 <&cru ACLK_JPEG_ENCODER3>, 641 <&cru HCLK_JPEG_ENCODER3>, 642 <&cru ACLK_JPEG_DECODER>, 643 <&cru HCLK_JPEG_DECODER>, 644 <&cru ACLK_RGA2>, 645 <&cru HCLK_RGA2>; 646 pm_qos = <&qos_iep>, 647 <&qos_jpeg_dec>, 648 <&qos_jpeg_enc0>, 649 <&qos_jpeg_enc1>, 650 <&qos_jpeg_enc2>, 651 <&qos_jpeg_enc3>, 652 <&qos_rga2_mro>, 653 <&qos_rga2_mwo>; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 #power-domain-cells = <0>; 657 658 659 power-domain@RK3588_PD_AV1 { 660 reg = <RK3588_PD_AV1>; 661 clocks = <&cru PCLK_AV1>, 662 <&cru ACLK_AV1>, 663 <&cru HCLK_VDPU_ROOT>; 664 pm_qos = <&qos_av1>; 665 #power-domain-cells = <0>; 666 }; 667 power-domain@RK3588_PD_RKVDEC0 { 668 reg = <RK3588_PD_RKVDEC0>; 669 clocks = <&cru HCLK_RKVDEC0>, 670 <&cru HCLK_VDPU_ROOT>, 671 <&cru ACLK_VDPU_ROOT>, 672 <&cru ACLK_RKVDEC0>; 673 pm_qos = <&qos_rkvdec0>; 674 #power-domain-cells = <0>; 675 }; 676 power-domain@RK3588_PD_RKVDEC1 { 677 reg = <RK3588_PD_RKVDEC1>; 678 clocks = <&cru HCLK_RKVDEC1>, 679 <&cru HCLK_VDPU_ROOT>, 680 <&cru ACLK_VDPU_ROOT>; 681 pm_qos = <&qos_rkvdec1>; 682 #power-domain-cells = <0>; 683 }; 684 power-domain@RK3588_PD_RGA30 { 685 reg = <RK3588_PD_RGA30>; 686 clocks = <&cru ACLK_RGA3_0>, 687 <&cru HCLK_RGA3_0>; 688 pm_qos = <&qos_rga3_0>; 689 #power-domain-cells = <0>; 690 }; 691 }; 692 power-domain@RK3588_PD_VOP { 693 reg = <RK3588_PD_VOP>; 694 clocks = <&cru PCLK_VOP_ROOT>, 695 <&cru HCLK_VOP_ROOT>, 696 <&cru ACLK_VOP>; 697 pm_qos = <&qos_vop_m0>, 698 <&qos_vop_m1>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 #power-domain-cells = <0>; 702 703 power-domain@RK3588_PD_VO0 { 704 reg = <RK3588_PD_VO0>; 705 clocks = <&cru PCLK_VO0_ROOT>, 706 <&cru PCLK_VO0_S_ROOT>, 707 <&cru HCLK_VO0_S_ROOT>, 708 <&cru ACLK_VO0_ROOT>, 709 <&cru HCLK_HDCP0>, 710 <&cru ACLK_HDCP0>, 711 <&cru HCLK_VOP_ROOT>; 712 pm_qos = <&qos_hdcp0>; 713 #power-domain-cells = <0>; 714 }; 715 }; 716 power-domain@RK3588_PD_VO1 { 717 reg = <RK3588_PD_VO1>; 718 clocks = <&cru PCLK_VO1_ROOT>, 719 <&cru PCLK_VO1_S_ROOT>, 720 <&cru HCLK_VO1_S_ROOT>, 721 <&cru HCLK_HDCP1>, 722 <&cru ACLK_HDCP1>, 723 <&cru ACLK_HDMIRX_ROOT>, 724 <&cru HCLK_VO1USB_TOP_ROOT>; 725 pm_qos = <&qos_hdcp1>, 726 <&qos_hdmirx>; 727 #power-domain-cells = <0>; 728 }; 729 power-domain@RK3588_PD_VI { 730 reg = <RK3588_PD_VI>; 731 clocks = <&cru HCLK_VI_ROOT>, 732 <&cru PCLK_VI_ROOT>, 733 <&cru HCLK_ISP0>, 734 <&cru ACLK_ISP0>, 735 <&cru HCLK_VICAP>, 736 <&cru ACLK_VICAP>; 737 pm_qos = <&qos_isp0_mro>, 738 <&qos_isp0_mwo>, 739 <&qos_vicap_m0>, 740 <&qos_vicap_m1>; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 #power-domain-cells = <0>; 744 745 power-domain@RK3588_PD_ISP1 { 746 reg = <RK3588_PD_ISP1>; 747 clocks = <&cru HCLK_ISP1>, 748 <&cru ACLK_ISP1>, 749 <&cru HCLK_VI_ROOT>, 750 <&cru PCLK_VI_ROOT>; 751 pm_qos = <&qos_isp1_mwo>, 752 <&qos_isp1_mro>; 753 #power-domain-cells = <0>; 754 }; 755 power-domain@RK3588_PD_FEC { 756 reg = <RK3588_PD_FEC>; 757 clocks = <&cru HCLK_FISHEYE0>, 758 <&cru ACLK_FISHEYE0>, 759 <&cru HCLK_FISHEYE1>, 760 <&cru ACLK_FISHEYE1>, 761 <&cru PCLK_VI_ROOT>; 762 pm_qos = <&qos_fisheye0>, 763 <&qos_fisheye1>; 764 #power-domain-cells = <0>; 765 }; 766 }; 767 power-domain@RK3588_PD_RGA31 { 768 reg = <RK3588_PD_RGA31>; 769 clocks = <&cru HCLK_RGA3_1>, 770 <&cru ACLK_RGA3_1>; 771 pm_qos = <&qos_rga3_1>; 772 #power-domain-cells = <0>; 773 }; 774 power-domain@RK3588_PD_USB { 775 reg = <RK3588_PD_USB>; 776 clocks = <&cru PCLK_PHP_ROOT>, 777 <&cru ACLK_USB_ROOT>, 778 <&cru HCLK_USB_ROOT>, 779 <&cru HCLK_HOST0>, 780 <&cru HCLK_HOST_ARB0>, 781 <&cru HCLK_HOST1>, 782 <&cru HCLK_HOST_ARB1>; 783 pm_qos = <&qos_usb3_0>, 784 <&qos_usb3_1>, 785 <&qos_usb2host_0>, 786 <&qos_usb2host_1>; 787 #power-domain-cells = <0>; 788 }; 789 power-domain@RK3588_PD_GMAC { 790 reg = <RK3588_PD_GMAC>; 791 clocks = <&cru PCLK_PHP_ROOT>, 792 <&cru ACLK_PCIE_ROOT>, 793 <&cru ACLK_PHP_ROOT>; 794 #power-domain-cells = <0>; 795 }; 796 power-domain@RK3588_PD_PCIE { 797 reg = <RK3588_PD_PCIE>; 798 clocks = <&cru PCLK_PHP_ROOT>, 799 <&cru ACLK_PCIE_ROOT>, 800 <&cru ACLK_PHP_ROOT>; 801 #power-domain-cells = <0>; 802 }; 803 power-domain@RK3588_PD_SDIO { 804 reg = <RK3588_PD_SDIO>; 805 clocks = <&cru HCLK_SDIO>, 806 <&cru HCLK_NVM_ROOT>; 807 pm_qos = <&qos_sdio>; 808 #power-domain-cells = <0>; 809 }; 810 power-domain@RK3588_PD_AUDIO { 811 reg = <RK3588_PD_AUDIO>; 812 clocks = <&cru HCLK_AUDIO_ROOT>, 813 <&cru PCLK_AUDIO_ROOT>; 814 #power-domain-cells = <0>; 815 }; 816 power-domain@RK3588_PD_SDMMC { 817 reg = <RK3588_PD_SDMMC>; 818 pm_qos = <&qos_sdmmc>; 819 #power-domain-cells = <0>; 820 }; 821 }; 822 }; 823 824 i2s4_8ch: i2s@fddc0000 { 825 compatible = "rockchip,rk3588-i2s-tdm"; 826 reg = <0x0 0xfddc0000 0x0 0x1000>; 827 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; 828 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 829 clock-names = "mclk_tx", "mclk_rx", "hclk"; 830 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 831 assigned-clock-parents = <&cru PLL_AUPLL>; 832 dmas = <&dmac2 0>; 833 dma-names = "tx"; 834 power-domains = <&power RK3588_PD_VO0>; 835 resets = <&cru SRST_M_I2S4_8CH_TX>; 836 reset-names = "tx-m"; 837 #sound-dai-cells = <0>; 838 status = "disabled"; 839 }; 840 841 i2s5_8ch: i2s@fddf0000 { 842 compatible = "rockchip,rk3588-i2s-tdm"; 843 reg = <0x0 0xfddf0000 0x0 0x1000>; 844 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; 845 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 846 clock-names = "mclk_tx", "mclk_rx", "hclk"; 847 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 848 assigned-clock-parents = <&cru PLL_AUPLL>; 849 dmas = <&dmac2 2>; 850 dma-names = "tx"; 851 power-domains = <&power RK3588_PD_VO1>; 852 resets = <&cru SRST_M_I2S5_8CH_TX>; 853 reset-names = "tx-m"; 854 #sound-dai-cells = <0>; 855 status = "disabled"; 856 }; 857 858 i2s9_8ch: i2s@fddfc000 { 859 compatible = "rockchip,rk3588-i2s-tdm"; 860 reg = <0x0 0xfddfc000 0x0 0x1000>; 861 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; 862 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 863 clock-names = "mclk_tx", "mclk_rx", "hclk"; 864 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 865 assigned-clock-parents = <&cru PLL_AUPLL>; 866 dmas = <&dmac2 23>; 867 dma-names = "rx"; 868 power-domains = <&power RK3588_PD_VO1>; 869 resets = <&cru SRST_M_I2S9_8CH_RX>; 870 reset-names = "rx-m"; 871 #sound-dai-cells = <0>; 872 status = "disabled"; 873 }; 874 875 qos_gpu_m0: qos@fdf35000 { 876 compatible = "rockchip,rk3588-qos", "syscon"; 877 reg = <0x0 0xfdf35000 0x0 0x20>; 878 }; 879 880 qos_gpu_m1: qos@fdf35200 { 881 compatible = "rockchip,rk3588-qos", "syscon"; 882 reg = <0x0 0xfdf35200 0x0 0x20>; 883 }; 884 885 qos_gpu_m2: qos@fdf35400 { 886 compatible = "rockchip,rk3588-qos", "syscon"; 887 reg = <0x0 0xfdf35400 0x0 0x20>; 888 }; 889 890 qos_gpu_m3: qos@fdf35600 { 891 compatible = "rockchip,rk3588-qos", "syscon"; 892 reg = <0x0 0xfdf35600 0x0 0x20>; 893 }; 894 895 qos_rga3_1: qos@fdf36000 { 896 compatible = "rockchip,rk3588-qos", "syscon"; 897 reg = <0x0 0xfdf36000 0x0 0x20>; 898 }; 899 900 qos_sdio: qos@fdf39000 { 901 compatible = "rockchip,rk3588-qos", "syscon"; 902 reg = <0x0 0xfdf39000 0x0 0x20>; 903 }; 904 905 qos_sdmmc: qos@fdf3d800 { 906 compatible = "rockchip,rk3588-qos", "syscon"; 907 reg = <0x0 0xfdf3d800 0x0 0x20>; 908 }; 909 910 qos_usb3_1: qos@fdf3e000 { 911 compatible = "rockchip,rk3588-qos", "syscon"; 912 reg = <0x0 0xfdf3e000 0x0 0x20>; 913 }; 914 915 qos_usb3_0: qos@fdf3e200 { 916 compatible = "rockchip,rk3588-qos", "syscon"; 917 reg = <0x0 0xfdf3e200 0x0 0x20>; 918 }; 919 920 qos_usb2host_0: qos@fdf3e400 { 921 compatible = "rockchip,rk3588-qos", "syscon"; 922 reg = <0x0 0xfdf3e400 0x0 0x20>; 923 }; 924 925 qos_usb2host_1: qos@fdf3e600 { 926 compatible = "rockchip,rk3588-qos", "syscon"; 927 reg = <0x0 0xfdf3e600 0x0 0x20>; 928 }; 929 930 qos_fisheye0: qos@fdf40000 { 931 compatible = "rockchip,rk3588-qos", "syscon"; 932 reg = <0x0 0xfdf40000 0x0 0x20>; 933 }; 934 935 qos_fisheye1: qos@fdf40200 { 936 compatible = "rockchip,rk3588-qos", "syscon"; 937 reg = <0x0 0xfdf40200 0x0 0x20>; 938 }; 939 940 qos_isp0_mro: qos@fdf40400 { 941 compatible = "rockchip,rk3588-qos", "syscon"; 942 reg = <0x0 0xfdf40400 0x0 0x20>; 943 }; 944 945 qos_isp0_mwo: qos@fdf40500 { 946 compatible = "rockchip,rk3588-qos", "syscon"; 947 reg = <0x0 0xfdf40500 0x0 0x20>; 948 }; 949 950 qos_vicap_m0: qos@fdf40600 { 951 compatible = "rockchip,rk3588-qos", "syscon"; 952 reg = <0x0 0xfdf40600 0x0 0x20>; 953 }; 954 955 qos_vicap_m1: qos@fdf40800 { 956 compatible = "rockchip,rk3588-qos", "syscon"; 957 reg = <0x0 0xfdf40800 0x0 0x20>; 958 }; 959 960 qos_isp1_mwo: qos@fdf41000 { 961 compatible = "rockchip,rk3588-qos", "syscon"; 962 reg = <0x0 0xfdf41000 0x0 0x20>; 963 }; 964 965 qos_isp1_mro: qos@fdf41100 { 966 compatible = "rockchip,rk3588-qos", "syscon"; 967 reg = <0x0 0xfdf41100 0x0 0x20>; 968 }; 969 970 qos_rkvenc0_m0ro: qos@fdf60000 { 971 compatible = "rockchip,rk3588-qos", "syscon"; 972 reg = <0x0 0xfdf60000 0x0 0x20>; 973 }; 974 975 qos_rkvenc0_m1ro: qos@fdf60200 { 976 compatible = "rockchip,rk3588-qos", "syscon"; 977 reg = <0x0 0xfdf60200 0x0 0x20>; 978 }; 979 980 qos_rkvenc0_m2wo: qos@fdf60400 { 981 compatible = "rockchip,rk3588-qos", "syscon"; 982 reg = <0x0 0xfdf60400 0x0 0x20>; 983 }; 984 985 qos_rkvenc1_m0ro: qos@fdf61000 { 986 compatible = "rockchip,rk3588-qos", "syscon"; 987 reg = <0x0 0xfdf61000 0x0 0x20>; 988 }; 989 990 qos_rkvenc1_m1ro: qos@fdf61200 { 991 compatible = "rockchip,rk3588-qos", "syscon"; 992 reg = <0x0 0xfdf61200 0x0 0x20>; 993 }; 994 995 qos_rkvenc1_m2wo: qos@fdf61400 { 996 compatible = "rockchip,rk3588-qos", "syscon"; 997 reg = <0x0 0xfdf61400 0x0 0x20>; 998 }; 999 1000 qos_rkvdec0: qos@fdf62000 { 1001 compatible = "rockchip,rk3588-qos", "syscon"; 1002 reg = <0x0 0xfdf62000 0x0 0x20>; 1003 }; 1004 1005 qos_rkvdec1: qos@fdf63000 { 1006 compatible = "rockchip,rk3588-qos", "syscon"; 1007 reg = <0x0 0xfdf63000 0x0 0x20>; 1008 }; 1009 1010 qos_av1: qos@fdf64000 { 1011 compatible = "rockchip,rk3588-qos", "syscon"; 1012 reg = <0x0 0xfdf64000 0x0 0x20>; 1013 }; 1014 1015 qos_iep: qos@fdf66000 { 1016 compatible = "rockchip,rk3588-qos", "syscon"; 1017 reg = <0x0 0xfdf66000 0x0 0x20>; 1018 }; 1019 1020 qos_jpeg_dec: qos@fdf66200 { 1021 compatible = "rockchip,rk3588-qos", "syscon"; 1022 reg = <0x0 0xfdf66200 0x0 0x20>; 1023 }; 1024 1025 qos_jpeg_enc0: qos@fdf66400 { 1026 compatible = "rockchip,rk3588-qos", "syscon"; 1027 reg = <0x0 0xfdf66400 0x0 0x20>; 1028 }; 1029 1030 qos_jpeg_enc1: qos@fdf66600 { 1031 compatible = "rockchip,rk3588-qos", "syscon"; 1032 reg = <0x0 0xfdf66600 0x0 0x20>; 1033 }; 1034 1035 qos_jpeg_enc2: qos@fdf66800 { 1036 compatible = "rockchip,rk3588-qos", "syscon"; 1037 reg = <0x0 0xfdf66800 0x0 0x20>; 1038 }; 1039 1040 qos_jpeg_enc3: qos@fdf66a00 { 1041 compatible = "rockchip,rk3588-qos", "syscon"; 1042 reg = <0x0 0xfdf66a00 0x0 0x20>; 1043 }; 1044 1045 qos_rga2_mro: qos@fdf66c00 { 1046 compatible = "rockchip,rk3588-qos", "syscon"; 1047 reg = <0x0 0xfdf66c00 0x0 0x20>; 1048 }; 1049 1050 qos_rga2_mwo: qos@fdf66e00 { 1051 compatible = "rockchip,rk3588-qos", "syscon"; 1052 reg = <0x0 0xfdf66e00 0x0 0x20>; 1053 }; 1054 1055 qos_rga3_0: qos@fdf67000 { 1056 compatible = "rockchip,rk3588-qos", "syscon"; 1057 reg = <0x0 0xfdf67000 0x0 0x20>; 1058 }; 1059 1060 qos_vdpu: qos@fdf67200 { 1061 compatible = "rockchip,rk3588-qos", "syscon"; 1062 reg = <0x0 0xfdf67200 0x0 0x20>; 1063 }; 1064 1065 qos_npu1: qos@fdf70000 { 1066 compatible = "rockchip,rk3588-qos", "syscon"; 1067 reg = <0x0 0xfdf70000 0x0 0x20>; 1068 }; 1069 1070 qos_npu2: qos@fdf71000 { 1071 compatible = "rockchip,rk3588-qos", "syscon"; 1072 reg = <0x0 0xfdf71000 0x0 0x20>; 1073 }; 1074 1075 qos_npu0_mwr: qos@fdf72000 { 1076 compatible = "rockchip,rk3588-qos", "syscon"; 1077 reg = <0x0 0xfdf72000 0x0 0x20>; 1078 }; 1079 1080 qos_npu0_mro: qos@fdf72200 { 1081 compatible = "rockchip,rk3588-qos", "syscon"; 1082 reg = <0x0 0xfdf72200 0x0 0x20>; 1083 }; 1084 1085 qos_mcu_npu: qos@fdf72400 { 1086 compatible = "rockchip,rk3588-qos", "syscon"; 1087 reg = <0x0 0xfdf72400 0x0 0x20>; 1088 }; 1089 1090 qos_hdcp0: qos@fdf80000 { 1091 compatible = "rockchip,rk3588-qos", "syscon"; 1092 reg = <0x0 0xfdf80000 0x0 0x20>; 1093 }; 1094 1095 qos_hdcp1: qos@fdf81000 { 1096 compatible = "rockchip,rk3588-qos", "syscon"; 1097 reg = <0x0 0xfdf81000 0x0 0x20>; 1098 }; 1099 1100 qos_hdmirx: qos@fdf81200 { 1101 compatible = "rockchip,rk3588-qos", "syscon"; 1102 reg = <0x0 0xfdf81200 0x0 0x20>; 1103 }; 1104 1105 qos_vop_m0: qos@fdf82000 { 1106 compatible = "rockchip,rk3588-qos", "syscon"; 1107 reg = <0x0 0xfdf82000 0x0 0x20>; 1108 }; 1109 1110 qos_vop_m1: qos@fdf82200 { 1111 compatible = "rockchip,rk3588-qos", "syscon"; 1112 reg = <0x0 0xfdf82200 0x0 0x20>; 1113 }; 1114 1115 gmac1: ethernet@fe1c0000 { 1116 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1117 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1118 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, 1119 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 1120 interrupt-names = "macirq", "eth_wake_irq"; 1121 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 1122 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1123 <&cru CLK_GMAC1_PTP_REF>; 1124 clock-names = "stmmaceth", "clk_mac_ref", 1125 "pclk_mac", "aclk_mac", 1126 "ptp_ref"; 1127 power-domains = <&power RK3588_PD_GMAC>; 1128 resets = <&cru SRST_A_GMAC1>; 1129 reset-names = "stmmaceth"; 1130 rockchip,grf = <&sys_grf>; 1131 rockchip,php-grf = <&php_grf>; 1132 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1133 snps,mixed-burst; 1134 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1135 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1136 snps,tso; 1137 status = "disabled"; 1138 1139 mdio1: mdio { 1140 compatible = "snps,dwmac-mdio"; 1141 #address-cells = <0x1>; 1142 #size-cells = <0x0>; 1143 }; 1144 1145 gmac1_stmmac_axi_setup: stmmac-axi-config { 1146 snps,blen = <0 0 0 0 16 8 4>; 1147 snps,wr_osr_lmt = <4>; 1148 snps,rd_osr_lmt = <8>; 1149 }; 1150 1151 gmac1_mtl_rx_setup: rx-queues-config { 1152 snps,rx-queues-to-use = <2>; 1153 queue0 {}; 1154 queue1 {}; 1155 }; 1156 1157 gmac1_mtl_tx_setup: tx-queues-config { 1158 snps,tx-queues-to-use = <2>; 1159 queue0 {}; 1160 queue1 {}; 1161 }; 1162 }; 1163 1164 sdmmc: mmc@fe2c0000 { 1165 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1166 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1167 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 1168 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 1169 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1170 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1171 fifo-depth = <0x100>; 1172 max-frequency = <200000000>; 1173 pinctrl-names = "default"; 1174 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1175 power-domains = <&power RK3588_PD_SDMMC>; 1176 status = "disabled"; 1177 }; 1178 1179 sdhci: mmc@fe2e0000 { 1180 compatible = "rockchip,rk3588-dwcmshc"; 1181 reg = <0x0 0xfe2e0000 0x0 0x10000>; 1182 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 1183 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 1184 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1185 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1186 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1187 <&cru TMCLK_EMMC>; 1188 clock-names = "core", "bus", "axi", "block", "timer"; 1189 max-frequency = <200000000>; 1190 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1191 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1192 <&cru SRST_T_EMMC>; 1193 reset-names = "core", "bus", "axi", "block", "timer"; 1194 status = "disabled"; 1195 }; 1196 1197 i2s0_8ch: i2s@fe470000 { 1198 compatible = "rockchip,rk3588-i2s-tdm"; 1199 reg = <0x0 0xfe470000 0x0 0x1000>; 1200 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; 1201 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1202 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1203 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1204 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 1205 dmas = <&dmac0 0>, <&dmac0 1>; 1206 dma-names = "tx", "rx"; 1207 power-domains = <&power RK3588_PD_AUDIO>; 1208 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1209 reset-names = "tx-m", "rx-m"; 1210 rockchip,trcm-sync-tx-only; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&i2s0_lrck 1213 &i2s0_sclk 1214 &i2s0_sdi0 1215 &i2s0_sdi1 1216 &i2s0_sdi2 1217 &i2s0_sdi3 1218 &i2s0_sdo0 1219 &i2s0_sdo1 1220 &i2s0_sdo2 1221 &i2s0_sdo3>; 1222 #sound-dai-cells = <0>; 1223 status = "disabled"; 1224 }; 1225 1226 i2s1_8ch: i2s@fe480000 { 1227 compatible = "rockchip,rk3588-i2s-tdm"; 1228 reg = <0x0 0xfe480000 0x0 0x1000>; 1229 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; 1230 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1231 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1232 dmas = <&dmac0 2>, <&dmac0 3>; 1233 dma-names = "tx", "rx"; 1234 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1235 reset-names = "tx-m", "rx-m"; 1236 rockchip,trcm-sync-tx-only; 1237 pinctrl-names = "default"; 1238 pinctrl-0 = <&i2s1m0_lrck 1239 &i2s1m0_sclk 1240 &i2s1m0_sdi0 1241 &i2s1m0_sdi1 1242 &i2s1m0_sdi2 1243 &i2s1m0_sdi3 1244 &i2s1m0_sdo0 1245 &i2s1m0_sdo1 1246 &i2s1m0_sdo2 1247 &i2s1m0_sdo3>; 1248 #sound-dai-cells = <0>; 1249 status = "disabled"; 1250 }; 1251 1252 i2s2_2ch: i2s@fe490000 { 1253 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1254 reg = <0x0 0xfe490000 0x0 0x1000>; 1255 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; 1256 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1257 clock-names = "i2s_clk", "i2s_hclk"; 1258 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1259 assigned-clock-parents = <&cru PLL_AUPLL>; 1260 dmas = <&dmac1 0>, <&dmac1 1>; 1261 dma-names = "tx", "rx"; 1262 power-domains = <&power RK3588_PD_AUDIO>; 1263 rockchip,trcm-sync-tx-only; 1264 pinctrl-names = "default"; 1265 pinctrl-0 = <&i2s2m1_lrck 1266 &i2s2m1_sclk 1267 &i2s2m1_sdi 1268 &i2s2m1_sdo>; 1269 #sound-dai-cells = <0>; 1270 status = "disabled"; 1271 }; 1272 1273 i2s3_2ch: i2s@fe4a0000 { 1274 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1275 reg = <0x0 0xfe4a0000 0x0 0x1000>; 1276 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; 1277 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 1278 clock-names = "i2s_clk", "i2s_hclk"; 1279 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 1280 assigned-clock-parents = <&cru PLL_AUPLL>; 1281 dmas = <&dmac1 2>, <&dmac1 3>; 1282 dma-names = "tx", "rx"; 1283 power-domains = <&power RK3588_PD_AUDIO>; 1284 rockchip,trcm-sync-tx-only; 1285 pinctrl-names = "default"; 1286 pinctrl-0 = <&i2s3_lrck 1287 &i2s3_sclk 1288 &i2s3_sdi 1289 &i2s3_sdo>; 1290 #sound-dai-cells = <0>; 1291 status = "disabled"; 1292 }; 1293 1294 gic: interrupt-controller@fe600000 { 1295 compatible = "arm,gic-v3"; 1296 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 1297 <0x0 0xfe680000 0 0x100000>; /* GICR */ 1298 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 1299 interrupt-controller; 1300 mbi-alias = <0x0 0xfe610000>; 1301 mbi-ranges = <424 56>; 1302 msi-controller; 1303 #interrupt-cells = <4>; 1304 1305 ppi-partitions { 1306 ppi_partition0: interrupt-partition-0 { 1307 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 1308 }; 1309 1310 ppi_partition1: interrupt-partition-1 { 1311 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; 1312 }; 1313 }; 1314 }; 1315 1316 dmac0: dma-controller@fea10000 { 1317 compatible = "arm,pl330", "arm,primecell"; 1318 reg = <0x0 0xfea10000 0x0 0x4000>; 1319 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, 1320 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; 1321 arm,pl330-periph-burst; 1322 clocks = <&cru ACLK_DMAC0>; 1323 clock-names = "apb_pclk"; 1324 #dma-cells = <1>; 1325 }; 1326 1327 dmac1: dma-controller@fea30000 { 1328 compatible = "arm,pl330", "arm,primecell"; 1329 reg = <0x0 0xfea30000 0x0 0x4000>; 1330 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, 1331 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; 1332 arm,pl330-periph-burst; 1333 clocks = <&cru ACLK_DMAC1>; 1334 clock-names = "apb_pclk"; 1335 #dma-cells = <1>; 1336 }; 1337 1338 i2c1: i2c@fea90000 { 1339 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1340 reg = <0x0 0xfea90000 0x0 0x1000>; 1341 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1342 clock-names = "i2c", "pclk"; 1343 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; 1344 pinctrl-0 = <&i2c1m0_xfer>; 1345 pinctrl-names = "default"; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 status = "disabled"; 1349 }; 1350 1351 i2c2: i2c@feaa0000 { 1352 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1353 reg = <0x0 0xfeaa0000 0x0 0x1000>; 1354 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1355 clock-names = "i2c", "pclk"; 1356 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; 1357 pinctrl-0 = <&i2c2m0_xfer>; 1358 pinctrl-names = "default"; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 status = "disabled"; 1362 }; 1363 1364 i2c3: i2c@feab0000 { 1365 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1366 reg = <0x0 0xfeab0000 0x0 0x1000>; 1367 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1368 clock-names = "i2c", "pclk"; 1369 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; 1370 pinctrl-0 = <&i2c3m0_xfer>; 1371 pinctrl-names = "default"; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 status = "disabled"; 1375 }; 1376 1377 i2c4: i2c@feac0000 { 1378 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1379 reg = <0x0 0xfeac0000 0x0 0x1000>; 1380 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1381 clock-names = "i2c", "pclk"; 1382 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; 1383 pinctrl-0 = <&i2c4m0_xfer>; 1384 pinctrl-names = "default"; 1385 #address-cells = <1>; 1386 #size-cells = <0>; 1387 status = "disabled"; 1388 }; 1389 1390 i2c5: i2c@fead0000 { 1391 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1392 reg = <0x0 0xfead0000 0x0 0x1000>; 1393 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1394 clock-names = "i2c", "pclk"; 1395 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; 1396 pinctrl-0 = <&i2c5m0_xfer>; 1397 pinctrl-names = "default"; 1398 #address-cells = <1>; 1399 #size-cells = <0>; 1400 status = "disabled"; 1401 }; 1402 1403 wdt: watchdog@feaf0000 { 1404 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; 1405 reg = <0x0 0xfeaf0000 0x0 0x100>; 1406 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 1407 clock-names = "tclk", "pclk"; 1408 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; 1409 }; 1410 1411 spi0: spi@feb00000 { 1412 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1413 reg = <0x0 0xfeb00000 0x0 0x1000>; 1414 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; 1415 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1416 clock-names = "spiclk", "apb_pclk"; 1417 dmas = <&dmac0 14>, <&dmac0 15>; 1418 dma-names = "tx", "rx"; 1419 num-cs = <2>; 1420 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1421 pinctrl-names = "default"; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 status = "disabled"; 1425 }; 1426 1427 spi1: spi@feb10000 { 1428 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1429 reg = <0x0 0xfeb10000 0x0 0x1000>; 1430 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; 1431 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1432 clock-names = "spiclk", "apb_pclk"; 1433 dmas = <&dmac0 16>, <&dmac0 17>; 1434 dma-names = "tx", "rx"; 1435 num-cs = <2>; 1436 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 1437 pinctrl-names = "default"; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 status = "disabled"; 1441 }; 1442 1443 spi2: spi@feb20000 { 1444 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1445 reg = <0x0 0xfeb20000 0x0 0x1000>; 1446 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; 1447 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1448 clock-names = "spiclk", "apb_pclk"; 1449 dmas = <&dmac1 15>, <&dmac1 16>; 1450 dma-names = "tx", "rx"; 1451 num-cs = <2>; 1452 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 1453 pinctrl-names = "default"; 1454 #address-cells = <1>; 1455 #size-cells = <0>; 1456 status = "disabled"; 1457 }; 1458 1459 spi3: spi@feb30000 { 1460 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1461 reg = <0x0 0xfeb30000 0x0 0x1000>; 1462 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; 1463 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1464 clock-names = "spiclk", "apb_pclk"; 1465 dmas = <&dmac1 17>, <&dmac1 18>; 1466 dma-names = "tx", "rx"; 1467 num-cs = <2>; 1468 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 1469 pinctrl-names = "default"; 1470 #address-cells = <1>; 1471 #size-cells = <0>; 1472 status = "disabled"; 1473 }; 1474 1475 uart1: serial@feb40000 { 1476 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1477 reg = <0x0 0xfeb40000 0x0 0x100>; 1478 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; 1479 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1480 clock-names = "baudclk", "apb_pclk"; 1481 dmas = <&dmac0 8>, <&dmac0 9>; 1482 dma-names = "tx", "rx"; 1483 pinctrl-0 = <&uart1m1_xfer>; 1484 pinctrl-names = "default"; 1485 reg-io-width = <4>; 1486 reg-shift = <2>; 1487 status = "disabled"; 1488 }; 1489 1490 uart2: serial@feb50000 { 1491 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1492 reg = <0x0 0xfeb50000 0x0 0x100>; 1493 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; 1494 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1495 clock-names = "baudclk", "apb_pclk"; 1496 dmas = <&dmac0 10>, <&dmac0 11>; 1497 dma-names = "tx", "rx"; 1498 pinctrl-0 = <&uart2m1_xfer>; 1499 pinctrl-names = "default"; 1500 reg-io-width = <4>; 1501 reg-shift = <2>; 1502 status = "disabled"; 1503 }; 1504 1505 uart3: serial@feb60000 { 1506 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1507 reg = <0x0 0xfeb60000 0x0 0x100>; 1508 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; 1509 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1510 clock-names = "baudclk", "apb_pclk"; 1511 dmas = <&dmac0 12>, <&dmac0 13>; 1512 dma-names = "tx", "rx"; 1513 pinctrl-0 = <&uart3m1_xfer>; 1514 pinctrl-names = "default"; 1515 reg-io-width = <4>; 1516 reg-shift = <2>; 1517 status = "disabled"; 1518 }; 1519 1520 uart4: serial@feb70000 { 1521 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1522 reg = <0x0 0xfeb70000 0x0 0x100>; 1523 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; 1524 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1525 clock-names = "baudclk", "apb_pclk"; 1526 dmas = <&dmac1 9>, <&dmac1 10>; 1527 dma-names = "tx", "rx"; 1528 pinctrl-0 = <&uart4m1_xfer>; 1529 pinctrl-names = "default"; 1530 reg-io-width = <4>; 1531 reg-shift = <2>; 1532 status = "disabled"; 1533 }; 1534 1535 uart5: serial@feb80000 { 1536 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1537 reg = <0x0 0xfeb80000 0x0 0x100>; 1538 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; 1539 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1540 clock-names = "baudclk", "apb_pclk"; 1541 dmas = <&dmac1 11>, <&dmac1 12>; 1542 dma-names = "tx", "rx"; 1543 pinctrl-0 = <&uart5m1_xfer>; 1544 pinctrl-names = "default"; 1545 reg-io-width = <4>; 1546 reg-shift = <2>; 1547 status = "disabled"; 1548 }; 1549 1550 uart6: serial@feb90000 { 1551 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1552 reg = <0x0 0xfeb90000 0x0 0x100>; 1553 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; 1554 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1555 clock-names = "baudclk", "apb_pclk"; 1556 dmas = <&dmac1 13>, <&dmac1 14>; 1557 dma-names = "tx", "rx"; 1558 pinctrl-0 = <&uart6m1_xfer>; 1559 pinctrl-names = "default"; 1560 reg-io-width = <4>; 1561 reg-shift = <2>; 1562 status = "disabled"; 1563 }; 1564 1565 uart7: serial@feba0000 { 1566 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1567 reg = <0x0 0xfeba0000 0x0 0x100>; 1568 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; 1569 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1570 clock-names = "baudclk", "apb_pclk"; 1571 dmas = <&dmac2 7>, <&dmac2 8>; 1572 dma-names = "tx", "rx"; 1573 pinctrl-0 = <&uart7m1_xfer>; 1574 pinctrl-names = "default"; 1575 reg-io-width = <4>; 1576 reg-shift = <2>; 1577 status = "disabled"; 1578 }; 1579 1580 uart8: serial@febb0000 { 1581 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1582 reg = <0x0 0xfebb0000 0x0 0x100>; 1583 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; 1584 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1585 clock-names = "baudclk", "apb_pclk"; 1586 dmas = <&dmac2 9>, <&dmac2 10>; 1587 dma-names = "tx", "rx"; 1588 pinctrl-0 = <&uart8m1_xfer>; 1589 pinctrl-names = "default"; 1590 reg-io-width = <4>; 1591 reg-shift = <2>; 1592 status = "disabled"; 1593 }; 1594 1595 uart9: serial@febc0000 { 1596 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1597 reg = <0x0 0xfebc0000 0x0 0x100>; 1598 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; 1599 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1600 clock-names = "baudclk", "apb_pclk"; 1601 dmas = <&dmac2 11>, <&dmac2 12>; 1602 dma-names = "tx", "rx"; 1603 pinctrl-0 = <&uart9m1_xfer>; 1604 pinctrl-names = "default"; 1605 reg-io-width = <4>; 1606 reg-shift = <2>; 1607 status = "disabled"; 1608 }; 1609 1610 pwm4: pwm@febd0000 { 1611 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1612 reg = <0x0 0xfebd0000 0x0 0x10>; 1613 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1614 clock-names = "pwm", "pclk"; 1615 pinctrl-0 = <&pwm4m0_pins>; 1616 pinctrl-names = "default"; 1617 #pwm-cells = <3>; 1618 status = "disabled"; 1619 }; 1620 1621 pwm5: pwm@febd0010 { 1622 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1623 reg = <0x0 0xfebd0010 0x0 0x10>; 1624 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1625 clock-names = "pwm", "pclk"; 1626 pinctrl-0 = <&pwm5m0_pins>; 1627 pinctrl-names = "default"; 1628 #pwm-cells = <3>; 1629 status = "disabled"; 1630 }; 1631 1632 pwm6: pwm@febd0020 { 1633 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1634 reg = <0x0 0xfebd0020 0x0 0x10>; 1635 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1636 clock-names = "pwm", "pclk"; 1637 pinctrl-0 = <&pwm6m0_pins>; 1638 pinctrl-names = "default"; 1639 #pwm-cells = <3>; 1640 status = "disabled"; 1641 }; 1642 1643 pwm7: pwm@febd0030 { 1644 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1645 reg = <0x0 0xfebd0030 0x0 0x10>; 1646 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1647 clock-names = "pwm", "pclk"; 1648 pinctrl-0 = <&pwm7m0_pins>; 1649 pinctrl-names = "default"; 1650 #pwm-cells = <3>; 1651 status = "disabled"; 1652 }; 1653 1654 pwm8: pwm@febe0000 { 1655 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1656 reg = <0x0 0xfebe0000 0x0 0x10>; 1657 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1658 clock-names = "pwm", "pclk"; 1659 pinctrl-0 = <&pwm8m0_pins>; 1660 pinctrl-names = "default"; 1661 #pwm-cells = <3>; 1662 status = "disabled"; 1663 }; 1664 1665 pwm9: pwm@febe0010 { 1666 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1667 reg = <0x0 0xfebe0010 0x0 0x10>; 1668 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1669 clock-names = "pwm", "pclk"; 1670 pinctrl-0 = <&pwm9m0_pins>; 1671 pinctrl-names = "default"; 1672 #pwm-cells = <3>; 1673 status = "disabled"; 1674 }; 1675 1676 pwm10: pwm@febe0020 { 1677 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1678 reg = <0x0 0xfebe0020 0x0 0x10>; 1679 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1680 clock-names = "pwm", "pclk"; 1681 pinctrl-0 = <&pwm10m0_pins>; 1682 pinctrl-names = "default"; 1683 #pwm-cells = <3>; 1684 status = "disabled"; 1685 }; 1686 1687 pwm11: pwm@febe0030 { 1688 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1689 reg = <0x0 0xfebe0030 0x0 0x10>; 1690 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1691 clock-names = "pwm", "pclk"; 1692 pinctrl-0 = <&pwm11m0_pins>; 1693 pinctrl-names = "default"; 1694 #pwm-cells = <3>; 1695 status = "disabled"; 1696 }; 1697 1698 pwm12: pwm@febf0000 { 1699 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1700 reg = <0x0 0xfebf0000 0x0 0x10>; 1701 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1702 clock-names = "pwm", "pclk"; 1703 pinctrl-0 = <&pwm12m0_pins>; 1704 pinctrl-names = "default"; 1705 #pwm-cells = <3>; 1706 status = "disabled"; 1707 }; 1708 1709 pwm13: pwm@febf0010 { 1710 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1711 reg = <0x0 0xfebf0010 0x0 0x10>; 1712 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1713 clock-names = "pwm", "pclk"; 1714 pinctrl-0 = <&pwm13m0_pins>; 1715 pinctrl-names = "default"; 1716 #pwm-cells = <3>; 1717 status = "disabled"; 1718 }; 1719 1720 pwm14: pwm@febf0020 { 1721 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1722 reg = <0x0 0xfebf0020 0x0 0x10>; 1723 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1724 clock-names = "pwm", "pclk"; 1725 pinctrl-0 = <&pwm14m0_pins>; 1726 pinctrl-names = "default"; 1727 #pwm-cells = <3>; 1728 status = "disabled"; 1729 }; 1730 1731 pwm15: pwm@febf0030 { 1732 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1733 reg = <0x0 0xfebf0030 0x0 0x10>; 1734 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1735 clock-names = "pwm", "pclk"; 1736 pinctrl-0 = <&pwm15m0_pins>; 1737 pinctrl-names = "default"; 1738 #pwm-cells = <3>; 1739 status = "disabled"; 1740 }; 1741 1742 tsadc: tsadc@fec00000 { 1743 compatible = "rockchip,rk3588-tsadc"; 1744 reg = <0x0 0xfec00000 0x0 0x400>; 1745 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; 1746 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 1747 clock-names = "tsadc", "apb_pclk"; 1748 assigned-clocks = <&cru CLK_TSADC>; 1749 assigned-clock-rates = <2000000>; 1750 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 1751 reset-names = "tsadc-apb", "tsadc"; 1752 rockchip,hw-tshut-temp = <120000>; 1753 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 1754 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 1755 pinctrl-0 = <&tsadc_gpio_func>; 1756 pinctrl-1 = <&tsadc_shut>; 1757 pinctrl-names = "gpio", "otpout"; 1758 #thermal-sensor-cells = <1>; 1759 status = "disabled"; 1760 }; 1761 1762 i2c6: i2c@fec80000 { 1763 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1764 reg = <0x0 0xfec80000 0x0 0x1000>; 1765 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 1766 clock-names = "i2c", "pclk"; 1767 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; 1768 pinctrl-0 = <&i2c6m0_xfer>; 1769 pinctrl-names = "default"; 1770 #address-cells = <1>; 1771 #size-cells = <0>; 1772 status = "disabled"; 1773 }; 1774 1775 i2c7: i2c@fec90000 { 1776 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1777 reg = <0x0 0xfec90000 0x0 0x1000>; 1778 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 1779 clock-names = "i2c", "pclk"; 1780 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 1781 pinctrl-0 = <&i2c7m0_xfer>; 1782 pinctrl-names = "default"; 1783 #address-cells = <1>; 1784 #size-cells = <0>; 1785 status = "disabled"; 1786 }; 1787 1788 i2c8: i2c@feca0000 { 1789 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1790 reg = <0x0 0xfeca0000 0x0 0x1000>; 1791 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 1792 clock-names = "i2c", "pclk"; 1793 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; 1794 pinctrl-0 = <&i2c8m0_xfer>; 1795 pinctrl-names = "default"; 1796 #address-cells = <1>; 1797 #size-cells = <0>; 1798 status = "disabled"; 1799 }; 1800 1801 spi4: spi@fecb0000 { 1802 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1803 reg = <0x0 0xfecb0000 0x0 0x1000>; 1804 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; 1805 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 1806 clock-names = "spiclk", "apb_pclk"; 1807 dmas = <&dmac2 13>, <&dmac2 14>; 1808 dma-names = "tx", "rx"; 1809 num-cs = <2>; 1810 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 1811 pinctrl-names = "default"; 1812 #address-cells = <1>; 1813 #size-cells = <0>; 1814 status = "disabled"; 1815 }; 1816 1817 dmac2: dma-controller@fed10000 { 1818 compatible = "arm,pl330", "arm,primecell"; 1819 reg = <0x0 0xfed10000 0x0 0x4000>; 1820 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, 1821 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; 1822 arm,pl330-periph-burst; 1823 clocks = <&cru ACLK_DMAC2>; 1824 clock-names = "apb_pclk"; 1825 #dma-cells = <1>; 1826 }; 1827 1828 system_sram2: sram@ff001000 { 1829 compatible = "mmio-sram"; 1830 reg = <0x0 0xff001000 0x0 0xef000>; 1831 ranges = <0x0 0x0 0xff001000 0xef000>; 1832 #address-cells = <1>; 1833 #size-cells = <1>; 1834 }; 1835 1836 pinctrl: pinctrl { 1837 compatible = "rockchip,rk3588-pinctrl"; 1838 ranges; 1839 rockchip,grf = <&ioc>; 1840 #address-cells = <2>; 1841 #size-cells = <2>; 1842 1843 gpio0: gpio@fd8a0000 { 1844 compatible = "rockchip,gpio-bank"; 1845 reg = <0x0 0xfd8a0000 0x0 0x100>; 1846 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 1847 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 1848 gpio-controller; 1849 gpio-ranges = <&pinctrl 0 0 32>; 1850 interrupt-controller; 1851 #gpio-cells = <2>; 1852 #interrupt-cells = <2>; 1853 }; 1854 1855 gpio1: gpio@fec20000 { 1856 compatible = "rockchip,gpio-bank"; 1857 reg = <0x0 0xfec20000 0x0 0x100>; 1858 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; 1859 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1860 gpio-controller; 1861 gpio-ranges = <&pinctrl 0 32 32>; 1862 interrupt-controller; 1863 #gpio-cells = <2>; 1864 #interrupt-cells = <2>; 1865 }; 1866 1867 gpio2: gpio@fec30000 { 1868 compatible = "rockchip,gpio-bank"; 1869 reg = <0x0 0xfec30000 0x0 0x100>; 1870 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; 1871 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1872 gpio-controller; 1873 gpio-ranges = <&pinctrl 0 64 32>; 1874 interrupt-controller; 1875 #gpio-cells = <2>; 1876 #interrupt-cells = <2>; 1877 }; 1878 1879 gpio3: gpio@fec40000 { 1880 compatible = "rockchip,gpio-bank"; 1881 reg = <0x0 0xfec40000 0x0 0x100>; 1882 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; 1883 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1884 gpio-controller; 1885 gpio-ranges = <&pinctrl 0 96 32>; 1886 interrupt-controller; 1887 #gpio-cells = <2>; 1888 #interrupt-cells = <2>; 1889 }; 1890 1891 gpio4: gpio@fec50000 { 1892 compatible = "rockchip,gpio-bank"; 1893 reg = <0x0 0xfec50000 0x0 0x100>; 1894 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; 1895 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1896 gpio-controller; 1897 gpio-ranges = <&pinctrl 0 128 32>; 1898 interrupt-controller; 1899 #gpio-cells = <2>; 1900 #interrupt-cells = <2>; 1901 }; 1902 }; 1903}; 1904 1905#include "rk3588s-pinctrl.dtsi" 1906