1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/power/rk3588-power.h> 10#include <dt-bindings/reset/rockchip,rk3588-cru.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/ata/ahci.h> 13 14/ { 15 compatible = "rockchip,rk3588"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 gpio2 = &gpio2; 25 gpio3 = &gpio3; 26 gpio4 = &gpio4; 27 i2c0 = &i2c0; 28 i2c1 = &i2c1; 29 i2c2 = &i2c2; 30 i2c3 = &i2c3; 31 i2c4 = &i2c4; 32 i2c5 = &i2c5; 33 i2c6 = &i2c6; 34 i2c7 = &i2c7; 35 i2c8 = &i2c8; 36 serial0 = &uart0; 37 serial1 = &uart1; 38 serial2 = &uart2; 39 serial3 = &uart3; 40 serial4 = &uart4; 41 serial5 = &uart5; 42 serial6 = &uart6; 43 serial7 = &uart7; 44 serial8 = &uart8; 45 serial9 = &uart9; 46 spi0 = &spi0; 47 spi1 = &spi1; 48 spi2 = &spi2; 49 spi3 = &spi3; 50 spi4 = &spi4; 51 }; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 57 cpu-map { 58 cluster0 { 59 core0 { 60 cpu = <&cpu_l0>; 61 }; 62 core1 { 63 cpu = <&cpu_l1>; 64 }; 65 core2 { 66 cpu = <&cpu_l2>; 67 }; 68 core3 { 69 cpu = <&cpu_l3>; 70 }; 71 }; 72 cluster1 { 73 core0 { 74 cpu = <&cpu_b0>; 75 }; 76 core1 { 77 cpu = <&cpu_b1>; 78 }; 79 }; 80 cluster2 { 81 core0 { 82 cpu = <&cpu_b2>; 83 }; 84 core1 { 85 cpu = <&cpu_b3>; 86 }; 87 }; 88 }; 89 90 cpu_l0: cpu@0 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a55"; 93 reg = <0x0>; 94 enable-method = "psci"; 95 capacity-dmips-mhz = <530>; 96 clocks = <&scmi_clk SCMI_CLK_CPUL>; 97 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; 98 assigned-clock-rates = <816000000>; 99 cpu-idle-states = <&CPU_SLEEP>; 100 i-cache-size = <32768>; 101 i-cache-line-size = <64>; 102 i-cache-sets = <128>; 103 d-cache-size = <32768>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 next-level-cache = <&l2_cache_l0>; 107 dynamic-power-coefficient = <228>; 108 #cooling-cells = <2>; 109 }; 110 111 cpu_l1: cpu@100 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a55"; 114 reg = <0x100>; 115 enable-method = "psci"; 116 capacity-dmips-mhz = <530>; 117 clocks = <&scmi_clk SCMI_CLK_CPUL>; 118 cpu-idle-states = <&CPU_SLEEP>; 119 i-cache-size = <32768>; 120 i-cache-line-size = <64>; 121 i-cache-sets = <128>; 122 d-cache-size = <32768>; 123 d-cache-line-size = <64>; 124 d-cache-sets = <128>; 125 next-level-cache = <&l2_cache_l1>; 126 dynamic-power-coefficient = <228>; 127 #cooling-cells = <2>; 128 }; 129 130 cpu_l2: cpu@200 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a55"; 133 reg = <0x200>; 134 enable-method = "psci"; 135 capacity-dmips-mhz = <530>; 136 clocks = <&scmi_clk SCMI_CLK_CPUL>; 137 cpu-idle-states = <&CPU_SLEEP>; 138 i-cache-size = <32768>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <128>; 141 d-cache-size = <32768>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <128>; 144 next-level-cache = <&l2_cache_l2>; 145 dynamic-power-coefficient = <228>; 146 #cooling-cells = <2>; 147 }; 148 149 cpu_l3: cpu@300 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a55"; 152 reg = <0x300>; 153 enable-method = "psci"; 154 capacity-dmips-mhz = <530>; 155 clocks = <&scmi_clk SCMI_CLK_CPUL>; 156 cpu-idle-states = <&CPU_SLEEP>; 157 i-cache-size = <32768>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <128>; 160 d-cache-size = <32768>; 161 d-cache-line-size = <64>; 162 d-cache-sets = <128>; 163 next-level-cache = <&l2_cache_l3>; 164 dynamic-power-coefficient = <228>; 165 #cooling-cells = <2>; 166 }; 167 168 cpu_b0: cpu@400 { 169 device_type = "cpu"; 170 compatible = "arm,cortex-a76"; 171 reg = <0x400>; 172 enable-method = "psci"; 173 capacity-dmips-mhz = <1024>; 174 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 175 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; 176 assigned-clock-rates = <816000000>; 177 cpu-idle-states = <&CPU_SLEEP>; 178 i-cache-size = <65536>; 179 i-cache-line-size = <64>; 180 i-cache-sets = <256>; 181 d-cache-size = <65536>; 182 d-cache-line-size = <64>; 183 d-cache-sets = <256>; 184 next-level-cache = <&l2_cache_b0>; 185 dynamic-power-coefficient = <416>; 186 #cooling-cells = <2>; 187 }; 188 189 cpu_b1: cpu@500 { 190 device_type = "cpu"; 191 compatible = "arm,cortex-a76"; 192 reg = <0x500>; 193 enable-method = "psci"; 194 capacity-dmips-mhz = <1024>; 195 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 196 cpu-idle-states = <&CPU_SLEEP>; 197 i-cache-size = <65536>; 198 i-cache-line-size = <64>; 199 i-cache-sets = <256>; 200 d-cache-size = <65536>; 201 d-cache-line-size = <64>; 202 d-cache-sets = <256>; 203 next-level-cache = <&l2_cache_b1>; 204 dynamic-power-coefficient = <416>; 205 #cooling-cells = <2>; 206 }; 207 208 cpu_b2: cpu@600 { 209 device_type = "cpu"; 210 compatible = "arm,cortex-a76"; 211 reg = <0x600>; 212 enable-method = "psci"; 213 capacity-dmips-mhz = <1024>; 214 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 215 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; 216 assigned-clock-rates = <816000000>; 217 cpu-idle-states = <&CPU_SLEEP>; 218 i-cache-size = <65536>; 219 i-cache-line-size = <64>; 220 i-cache-sets = <256>; 221 d-cache-size = <65536>; 222 d-cache-line-size = <64>; 223 d-cache-sets = <256>; 224 next-level-cache = <&l2_cache_b2>; 225 dynamic-power-coefficient = <416>; 226 #cooling-cells = <2>; 227 }; 228 229 cpu_b3: cpu@700 { 230 device_type = "cpu"; 231 compatible = "arm,cortex-a76"; 232 reg = <0x700>; 233 enable-method = "psci"; 234 capacity-dmips-mhz = <1024>; 235 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 236 cpu-idle-states = <&CPU_SLEEP>; 237 i-cache-size = <65536>; 238 i-cache-line-size = <64>; 239 i-cache-sets = <256>; 240 d-cache-size = <65536>; 241 d-cache-line-size = <64>; 242 d-cache-sets = <256>; 243 next-level-cache = <&l2_cache_b3>; 244 dynamic-power-coefficient = <416>; 245 #cooling-cells = <2>; 246 }; 247 248 idle-states { 249 entry-method = "psci"; 250 CPU_SLEEP: cpu-sleep { 251 compatible = "arm,idle-state"; 252 local-timer-stop; 253 arm,psci-suspend-param = <0x0010000>; 254 entry-latency-us = <100>; 255 exit-latency-us = <120>; 256 min-residency-us = <1000>; 257 }; 258 }; 259 260 l2_cache_l0: l2-cache-l0 { 261 compatible = "cache"; 262 cache-size = <131072>; 263 cache-line-size = <64>; 264 cache-sets = <512>; 265 cache-level = <2>; 266 cache-unified; 267 next-level-cache = <&l3_cache>; 268 }; 269 270 l2_cache_l1: l2-cache-l1 { 271 compatible = "cache"; 272 cache-size = <131072>; 273 cache-line-size = <64>; 274 cache-sets = <512>; 275 cache-level = <2>; 276 cache-unified; 277 next-level-cache = <&l3_cache>; 278 }; 279 280 l2_cache_l2: l2-cache-l2 { 281 compatible = "cache"; 282 cache-size = <131072>; 283 cache-line-size = <64>; 284 cache-sets = <512>; 285 cache-level = <2>; 286 cache-unified; 287 next-level-cache = <&l3_cache>; 288 }; 289 290 l2_cache_l3: l2-cache-l3 { 291 compatible = "cache"; 292 cache-size = <131072>; 293 cache-line-size = <64>; 294 cache-sets = <512>; 295 cache-level = <2>; 296 cache-unified; 297 next-level-cache = <&l3_cache>; 298 }; 299 300 l2_cache_b0: l2-cache-b0 { 301 compatible = "cache"; 302 cache-size = <524288>; 303 cache-line-size = <64>; 304 cache-sets = <1024>; 305 cache-level = <2>; 306 cache-unified; 307 next-level-cache = <&l3_cache>; 308 }; 309 310 l2_cache_b1: l2-cache-b1 { 311 compatible = "cache"; 312 cache-size = <524288>; 313 cache-line-size = <64>; 314 cache-sets = <1024>; 315 cache-level = <2>; 316 cache-unified; 317 next-level-cache = <&l3_cache>; 318 }; 319 320 l2_cache_b2: l2-cache-b2 { 321 compatible = "cache"; 322 cache-size = <524288>; 323 cache-line-size = <64>; 324 cache-sets = <1024>; 325 cache-level = <2>; 326 cache-unified; 327 next-level-cache = <&l3_cache>; 328 }; 329 330 l2_cache_b3: l2-cache-b3 { 331 compatible = "cache"; 332 cache-size = <524288>; 333 cache-line-size = <64>; 334 cache-sets = <1024>; 335 cache-level = <2>; 336 cache-unified; 337 next-level-cache = <&l3_cache>; 338 }; 339 340 l3_cache: l3-cache { 341 compatible = "cache"; 342 cache-size = <3145728>; 343 cache-line-size = <64>; 344 cache-sets = <4096>; 345 cache-level = <3>; 346 cache-unified; 347 }; 348 }; 349 350 display_subsystem: display-subsystem { 351 compatible = "rockchip,display-subsystem"; 352 ports = <&vop_out>; 353 }; 354 355 firmware { 356 optee: optee { 357 compatible = "linaro,optee-tz"; 358 method = "smc"; 359 }; 360 361 scmi: scmi { 362 compatible = "arm,scmi-smc"; 363 arm,smc-id = <0x82000010>; 364 shmem = <&scmi_shmem>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 368 scmi_clk: protocol@14 { 369 reg = <0x14>; 370 #clock-cells = <1>; 371 }; 372 373 scmi_reset: protocol@16 { 374 reg = <0x16>; 375 #reset-cells = <1>; 376 }; 377 }; 378 }; 379 380 pmu-a55 { 381 compatible = "arm,cortex-a55-pmu"; 382 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; 383 }; 384 385 pmu-a76 { 386 compatible = "arm,cortex-a76-pmu"; 387 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; 388 }; 389 390 psci { 391 compatible = "arm,psci-1.0"; 392 method = "smc"; 393 }; 394 395 spll: clock-0 { 396 compatible = "fixed-clock"; 397 clock-frequency = <702000000>; 398 clock-output-names = "spll"; 399 #clock-cells = <0>; 400 }; 401 402 timer { 403 compatible = "arm,armv8-timer"; 404 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 405 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 406 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 407 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, 408 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 409 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 410 }; 411 412 xin24m: clock-1 { 413 compatible = "fixed-clock"; 414 clock-frequency = <24000000>; 415 clock-output-names = "xin24m"; 416 #clock-cells = <0>; 417 }; 418 419 xin32k: clock-2 { 420 compatible = "fixed-clock"; 421 clock-frequency = <32768>; 422 clock-output-names = "xin32k"; 423 #clock-cells = <0>; 424 }; 425 426 pmu_sram: sram@10f000 { 427 compatible = "mmio-sram"; 428 reg = <0x0 0x0010f000 0x0 0x100>; 429 ranges = <0 0x0 0x0010f000 0x100>; 430 #address-cells = <1>; 431 #size-cells = <1>; 432 433 scmi_shmem: sram@0 { 434 compatible = "arm,scmi-shmem"; 435 reg = <0x0 0x100>; 436 }; 437 }; 438 439 gpu: gpu@fb000000 { 440 compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; 441 reg = <0x0 0xfb000000 0x0 0x200000>; 442 #cooling-cells = <2>; 443 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 444 assigned-clock-rates = <200000000>; 445 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, 446 <&cru CLK_GPU_STACKS>; 447 clock-names = "core", "coregroup", "stacks"; 448 dynamic-power-coefficient = <2982>; 449 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, 450 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, 451 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>; 452 interrupt-names = "job", "mmu", "gpu"; 453 operating-points-v2 = <&gpu_opp_table>; 454 power-domains = <&power RK3588_PD_GPU>; 455 status = "disabled"; 456 457 gpu_opp_table: opp-table { 458 compatible = "operating-points-v2"; 459 460 opp-300000000 { 461 opp-hz = /bits/ 64 <300000000>; 462 opp-microvolt = <675000 675000 850000>; 463 }; 464 opp-400000000 { 465 opp-hz = /bits/ 64 <400000000>; 466 opp-microvolt = <675000 675000 850000>; 467 }; 468 opp-500000000 { 469 opp-hz = /bits/ 64 <500000000>; 470 opp-microvolt = <675000 675000 850000>; 471 }; 472 opp-600000000 { 473 opp-hz = /bits/ 64 <600000000>; 474 opp-microvolt = <675000 675000 850000>; 475 }; 476 opp-700000000 { 477 opp-hz = /bits/ 64 <700000000>; 478 opp-microvolt = <700000 700000 850000>; 479 }; 480 opp-800000000 { 481 opp-hz = /bits/ 64 <800000000>; 482 opp-microvolt = <750000 750000 850000>; 483 }; 484 opp-900000000 { 485 opp-hz = /bits/ 64 <900000000>; 486 opp-microvolt = <800000 800000 850000>; 487 }; 488 opp-1000000000 { 489 opp-hz = /bits/ 64 <1000000000>; 490 opp-microvolt = <850000 850000 850000>; 491 }; 492 }; 493 }; 494 495 usb_host0_xhci: usb@fc000000 { 496 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 497 reg = <0x0 0xfc000000 0x0 0x400000>; 498 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 499 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, 500 <&cru ACLK_USB3OTG0>; 501 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 502 dr_mode = "otg"; 503 phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; 504 phy-names = "usb2-phy", "usb3-phy"; 505 phy_type = "utmi_wide"; 506 power-domains = <&power RK3588_PD_USB>; 507 resets = <&cru SRST_A_USB3OTG0>; 508 snps,dis_enblslpm_quirk; 509 snps,dis-u1-entry-quirk; 510 snps,dis-u2-entry-quirk; 511 snps,dis-u2-freeclk-exists-quirk; 512 snps,dis-del-phy-power-chg-quirk; 513 snps,dis-tx-ipgap-linecheck-quirk; 514 status = "disabled"; 515 }; 516 517 usb_host0_ehci: usb@fc800000 { 518 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 519 reg = <0x0 0xfc800000 0x0 0x40000>; 520 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; 521 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 522 phys = <&u2phy2_host>; 523 phy-names = "usb"; 524 power-domains = <&power RK3588_PD_USB>; 525 status = "disabled"; 526 }; 527 528 usb_host0_ohci: usb@fc840000 { 529 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 530 reg = <0x0 0xfc840000 0x0 0x40000>; 531 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; 532 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 533 phys = <&u2phy2_host>; 534 phy-names = "usb"; 535 power-domains = <&power RK3588_PD_USB>; 536 status = "disabled"; 537 }; 538 539 usb_host1_ehci: usb@fc880000 { 540 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 541 reg = <0x0 0xfc880000 0x0 0x40000>; 542 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; 543 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 544 phys = <&u2phy3_host>; 545 phy-names = "usb"; 546 power-domains = <&power RK3588_PD_USB>; 547 status = "disabled"; 548 }; 549 550 usb_host1_ohci: usb@fc8c0000 { 551 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 552 reg = <0x0 0xfc8c0000 0x0 0x40000>; 553 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; 554 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 555 phys = <&u2phy3_host>; 556 phy-names = "usb"; 557 power-domains = <&power RK3588_PD_USB>; 558 status = "disabled"; 559 }; 560 561 usb_host2_xhci: usb@fcd00000 { 562 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 563 reg = <0x0 0xfcd00000 0x0 0x400000>; 564 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; 565 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, 566 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, 567 <&cru CLK_PIPEPHY2_PIPE_U3_G>; 568 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; 569 dr_mode = "host"; 570 phys = <&combphy2_psu PHY_TYPE_USB3>; 571 phy-names = "usb3-phy"; 572 phy_type = "utmi_wide"; 573 resets = <&cru SRST_A_USB3OTG2>; 574 snps,dis_enblslpm_quirk; 575 snps,dis-u2-freeclk-exists-quirk; 576 snps,dis-del-phy-power-chg-quirk; 577 snps,dis-tx-ipgap-linecheck-quirk; 578 snps,dis_rxdet_inp3_quirk; 579 status = "disabled"; 580 }; 581 582 mmu600_pcie: iommu@fc900000 { 583 compatible = "arm,smmu-v3"; 584 reg = <0x0 0xfc900000 0x0 0x200000>; 585 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>, 586 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>, 587 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, 588 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>; 589 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 590 #iommu-cells = <1>; 591 status = "disabled"; 592 }; 593 594 mmu600_php: iommu@fcb00000 { 595 compatible = "arm,smmu-v3"; 596 reg = <0x0 0xfcb00000 0x0 0x200000>; 597 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>, 598 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, 599 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>, 600 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; 601 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 602 #iommu-cells = <1>; 603 status = "disabled"; 604 }; 605 606 pmu1grf: syscon@fd58a000 { 607 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; 608 reg = <0x0 0xfd58a000 0x0 0x10000>; 609 }; 610 611 sys_grf: syscon@fd58c000 { 612 compatible = "rockchip,rk3588-sys-grf", "syscon"; 613 reg = <0x0 0xfd58c000 0x0 0x1000>; 614 }; 615 616 vop_grf: syscon@fd5a4000 { 617 compatible = "rockchip,rk3588-vop-grf", "syscon"; 618 reg = <0x0 0xfd5a4000 0x0 0x2000>; 619 }; 620 621 vo0_grf: syscon@fd5a6000 { 622 compatible = "rockchip,rk3588-vo-grf", "syscon"; 623 reg = <0x0 0xfd5a6000 0x0 0x2000>; 624 clocks = <&cru PCLK_VO0GRF>; 625 }; 626 627 vo1_grf: syscon@fd5a8000 { 628 compatible = "rockchip,rk3588-vo-grf", "syscon"; 629 reg = <0x0 0xfd5a8000 0x0 0x100>; 630 clocks = <&cru PCLK_VO1GRF>; 631 }; 632 633 usb_grf: syscon@fd5ac000 { 634 compatible = "rockchip,rk3588-usb-grf", "syscon"; 635 reg = <0x0 0xfd5ac000 0x0 0x4000>; 636 }; 637 638 php_grf: syscon@fd5b0000 { 639 compatible = "rockchip,rk3588-php-grf", "syscon"; 640 reg = <0x0 0xfd5b0000 0x0 0x1000>; 641 }; 642 643 pipe_phy0_grf: syscon@fd5bc000 { 644 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 645 reg = <0x0 0xfd5bc000 0x0 0x100>; 646 }; 647 648 pipe_phy2_grf: syscon@fd5c4000 { 649 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 650 reg = <0x0 0xfd5c4000 0x0 0x100>; 651 }; 652 653 usbdpphy0_grf: syscon@fd5c8000 { 654 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 655 reg = <0x0 0xfd5c8000 0x0 0x4000>; 656 }; 657 658 usb2phy0_grf: syscon@fd5d0000 { 659 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 660 reg = <0x0 0xfd5d0000 0x0 0x4000>; 661 #address-cells = <1>; 662 #size-cells = <1>; 663 664 u2phy0: usb2phy@0 { 665 compatible = "rockchip,rk3588-usb2phy"; 666 reg = <0x0 0x10>; 667 #clock-cells = <0>; 668 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 669 clock-names = "phyclk"; 670 clock-output-names = "usb480m_phy0"; 671 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; 672 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; 673 reset-names = "phy", "apb"; 674 status = "disabled"; 675 676 u2phy0_otg: otg-port { 677 #phy-cells = <0>; 678 status = "disabled"; 679 }; 680 }; 681 }; 682 683 usb2phy2_grf: syscon@fd5d8000 { 684 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 685 reg = <0x0 0xfd5d8000 0x0 0x4000>; 686 #address-cells = <1>; 687 #size-cells = <1>; 688 689 u2phy2: usb2phy@8000 { 690 compatible = "rockchip,rk3588-usb2phy"; 691 reg = <0x8000 0x10>; 692 #clock-cells = <0>; 693 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 694 clock-names = "phyclk"; 695 clock-output-names = "usb480m_phy2"; 696 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 697 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 698 reset-names = "phy", "apb"; 699 status = "disabled"; 700 701 u2phy2_host: host-port { 702 #phy-cells = <0>; 703 status = "disabled"; 704 }; 705 }; 706 }; 707 708 usb2phy3_grf: syscon@fd5dc000 { 709 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 710 reg = <0x0 0xfd5dc000 0x0 0x4000>; 711 #address-cells = <1>; 712 #size-cells = <1>; 713 714 u2phy3: usb2phy@c000 { 715 compatible = "rockchip,rk3588-usb2phy"; 716 reg = <0xc000 0x10>; 717 #clock-cells = <0>; 718 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 719 clock-names = "phyclk"; 720 clock-output-names = "usb480m_phy3"; 721 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 722 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 723 reset-names = "phy", "apb"; 724 status = "disabled"; 725 726 u2phy3_host: host-port { 727 #phy-cells = <0>; 728 status = "disabled"; 729 }; 730 }; 731 }; 732 733 hdptxphy0_grf: syscon@fd5e0000 { 734 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 735 reg = <0x0 0xfd5e0000 0x0 0x100>; 736 }; 737 738 ioc: syscon@fd5f0000 { 739 compatible = "rockchip,rk3588-ioc", "syscon"; 740 reg = <0x0 0xfd5f0000 0x0 0x10000>; 741 }; 742 743 system_sram1: sram@fd600000 { 744 compatible = "mmio-sram"; 745 reg = <0x0 0xfd600000 0x0 0x100000>; 746 ranges = <0x0 0x0 0xfd600000 0x100000>; 747 #address-cells = <1>; 748 #size-cells = <1>; 749 }; 750 751 cru: clock-controller@fd7c0000 { 752 compatible = "rockchip,rk3588-cru"; 753 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 754 assigned-clocks = 755 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 756 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 757 <&cru ACLK_CENTER_ROOT>, 758 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 759 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 760 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 761 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, 762 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 763 <&cru CLK_GPU>; 764 assigned-clock-rates = 765 <1100000000>, <786432000>, 766 <850000000>, <1188000000>, 767 <702000000>, 768 <400000000>, <500000000>, 769 <800000000>, <100000000>, 770 <400000000>, <100000000>, 771 <200000000>, <500000000>, 772 <375000000>, <150000000>, 773 <200000000>; 774 rockchip,grf = <&php_grf>; 775 #clock-cells = <1>; 776 #reset-cells = <1>; 777 }; 778 779 i2c0: i2c@fd880000 { 780 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 781 reg = <0x0 0xfd880000 0x0 0x1000>; 782 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; 783 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 784 clock-names = "i2c", "pclk"; 785 pinctrl-0 = <&i2c0m0_xfer>; 786 pinctrl-names = "default"; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 status = "disabled"; 790 }; 791 792 uart0: serial@fd890000 { 793 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 794 reg = <0x0 0xfd890000 0x0 0x100>; 795 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 796 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 797 clock-names = "baudclk", "apb_pclk"; 798 dmas = <&dmac0 6>, <&dmac0 7>; 799 dma-names = "tx", "rx"; 800 pinctrl-0 = <&uart0m1_xfer>; 801 pinctrl-names = "default"; 802 reg-shift = <2>; 803 reg-io-width = <4>; 804 status = "disabled"; 805 }; 806 807 pwm0: pwm@fd8b0000 { 808 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 809 reg = <0x0 0xfd8b0000 0x0 0x10>; 810 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 811 clock-names = "pwm", "pclk"; 812 pinctrl-0 = <&pwm0m0_pins>; 813 pinctrl-names = "default"; 814 #pwm-cells = <3>; 815 status = "disabled"; 816 }; 817 818 pwm1: pwm@fd8b0010 { 819 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 820 reg = <0x0 0xfd8b0010 0x0 0x10>; 821 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 822 clock-names = "pwm", "pclk"; 823 pinctrl-0 = <&pwm1m0_pins>; 824 pinctrl-names = "default"; 825 #pwm-cells = <3>; 826 status = "disabled"; 827 }; 828 829 pwm2: pwm@fd8b0020 { 830 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 831 reg = <0x0 0xfd8b0020 0x0 0x10>; 832 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 833 clock-names = "pwm", "pclk"; 834 pinctrl-0 = <&pwm2m0_pins>; 835 pinctrl-names = "default"; 836 #pwm-cells = <3>; 837 status = "disabled"; 838 }; 839 840 pwm3: pwm@fd8b0030 { 841 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 842 reg = <0x0 0xfd8b0030 0x0 0x10>; 843 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 844 clock-names = "pwm", "pclk"; 845 pinctrl-0 = <&pwm3m0_pins>; 846 pinctrl-names = "default"; 847 #pwm-cells = <3>; 848 status = "disabled"; 849 }; 850 851 pmu: power-management@fd8d8000 { 852 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 853 reg = <0x0 0xfd8d8000 0x0 0x400>; 854 855 power: power-controller { 856 compatible = "rockchip,rk3588-power-controller"; 857 #address-cells = <1>; 858 #power-domain-cells = <1>; 859 #size-cells = <0>; 860 status = "okay"; 861 862 /* These power domains are grouped by VD_NPU */ 863 power-domain@RK3588_PD_NPU { 864 reg = <RK3588_PD_NPU>; 865 #power-domain-cells = <0>; 866 #address-cells = <1>; 867 #size-cells = <0>; 868 869 power-domain@RK3588_PD_NPUTOP { 870 reg = <RK3588_PD_NPUTOP>; 871 clocks = <&cru HCLK_NPU_ROOT>, 872 <&cru PCLK_NPU_ROOT>, 873 <&cru CLK_NPU_DSU0>, 874 <&cru HCLK_NPU_CM0_ROOT>; 875 pm_qos = <&qos_npu0_mwr>, 876 <&qos_npu0_mro>, 877 <&qos_mcu_npu>; 878 #power-domain-cells = <0>; 879 #address-cells = <1>; 880 #size-cells = <0>; 881 882 power-domain@RK3588_PD_NPU1 { 883 reg = <RK3588_PD_NPU1>; 884 clocks = <&cru HCLK_NPU_ROOT>, 885 <&cru PCLK_NPU_ROOT>, 886 <&cru CLK_NPU_DSU0>; 887 pm_qos = <&qos_npu1>; 888 #power-domain-cells = <0>; 889 }; 890 power-domain@RK3588_PD_NPU2 { 891 reg = <RK3588_PD_NPU2>; 892 clocks = <&cru HCLK_NPU_ROOT>, 893 <&cru PCLK_NPU_ROOT>, 894 <&cru CLK_NPU_DSU0>; 895 pm_qos = <&qos_npu2>; 896 #power-domain-cells = <0>; 897 }; 898 }; 899 }; 900 /* These power domains are grouped by VD_GPU */ 901 power-domain@RK3588_PD_GPU { 902 reg = <RK3588_PD_GPU>; 903 clocks = <&cru CLK_GPU>, 904 <&cru CLK_GPU_COREGROUP>, 905 <&cru CLK_GPU_STACKS>; 906 pm_qos = <&qos_gpu_m0>, 907 <&qos_gpu_m1>, 908 <&qos_gpu_m2>, 909 <&qos_gpu_m3>; 910 #power-domain-cells = <0>; 911 }; 912 /* These power domains are grouped by VD_VCODEC */ 913 power-domain@RK3588_PD_VCODEC { 914 reg = <RK3588_PD_VCODEC>; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 #power-domain-cells = <0>; 918 919 power-domain@RK3588_PD_RKVDEC0 { 920 reg = <RK3588_PD_RKVDEC0>; 921 clocks = <&cru HCLK_RKVDEC0>, 922 <&cru HCLK_VDPU_ROOT>, 923 <&cru ACLK_VDPU_ROOT>, 924 <&cru ACLK_RKVDEC0>, 925 <&cru ACLK_RKVDEC_CCU>; 926 pm_qos = <&qos_rkvdec0>; 927 #power-domain-cells = <0>; 928 }; 929 power-domain@RK3588_PD_RKVDEC1 { 930 reg = <RK3588_PD_RKVDEC1>; 931 clocks = <&cru HCLK_RKVDEC1>, 932 <&cru HCLK_VDPU_ROOT>, 933 <&cru ACLK_VDPU_ROOT>, 934 <&cru ACLK_RKVDEC1>; 935 pm_qos = <&qos_rkvdec1>; 936 #power-domain-cells = <0>; 937 }; 938 power-domain@RK3588_PD_VENC0 { 939 reg = <RK3588_PD_VENC0>; 940 clocks = <&cru HCLK_RKVENC0>, 941 <&cru ACLK_RKVENC0>; 942 pm_qos = <&qos_rkvenc0_m0ro>, 943 <&qos_rkvenc0_m1ro>, 944 <&qos_rkvenc0_m2wo>; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 #power-domain-cells = <0>; 948 949 power-domain@RK3588_PD_VENC1 { 950 reg = <RK3588_PD_VENC1>; 951 clocks = <&cru HCLK_RKVENC1>, 952 <&cru HCLK_RKVENC0>, 953 <&cru ACLK_RKVENC0>, 954 <&cru ACLK_RKVENC1>; 955 pm_qos = <&qos_rkvenc1_m0ro>, 956 <&qos_rkvenc1_m1ro>, 957 <&qos_rkvenc1_m2wo>; 958 #power-domain-cells = <0>; 959 }; 960 }; 961 }; 962 /* These power domains are grouped by VD_LOGIC */ 963 power-domain@RK3588_PD_VDPU { 964 reg = <RK3588_PD_VDPU>; 965 clocks = <&cru HCLK_VDPU_ROOT>, 966 <&cru ACLK_VDPU_LOW_ROOT>, 967 <&cru ACLK_VDPU_ROOT>, 968 <&cru ACLK_JPEG_DECODER_ROOT>, 969 <&cru ACLK_IEP2P0>, 970 <&cru HCLK_IEP2P0>, 971 <&cru ACLK_JPEG_ENCODER0>, 972 <&cru HCLK_JPEG_ENCODER0>, 973 <&cru ACLK_JPEG_ENCODER1>, 974 <&cru HCLK_JPEG_ENCODER1>, 975 <&cru ACLK_JPEG_ENCODER2>, 976 <&cru HCLK_JPEG_ENCODER2>, 977 <&cru ACLK_JPEG_ENCODER3>, 978 <&cru HCLK_JPEG_ENCODER3>, 979 <&cru ACLK_JPEG_DECODER>, 980 <&cru HCLK_JPEG_DECODER>, 981 <&cru ACLK_RGA2>, 982 <&cru HCLK_RGA2>; 983 pm_qos = <&qos_iep>, 984 <&qos_jpeg_dec>, 985 <&qos_jpeg_enc0>, 986 <&qos_jpeg_enc1>, 987 <&qos_jpeg_enc2>, 988 <&qos_jpeg_enc3>, 989 <&qos_rga2_mro>, 990 <&qos_rga2_mwo>; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 #power-domain-cells = <0>; 994 995 996 power-domain@RK3588_PD_AV1 { 997 reg = <RK3588_PD_AV1>; 998 clocks = <&cru PCLK_AV1>, 999 <&cru ACLK_AV1>, 1000 <&cru HCLK_VDPU_ROOT>; 1001 pm_qos = <&qos_av1>; 1002 #power-domain-cells = <0>; 1003 }; 1004 power-domain@RK3588_PD_RKVDEC0 { 1005 reg = <RK3588_PD_RKVDEC0>; 1006 clocks = <&cru HCLK_RKVDEC0>, 1007 <&cru HCLK_VDPU_ROOT>, 1008 <&cru ACLK_VDPU_ROOT>, 1009 <&cru ACLK_RKVDEC0>; 1010 pm_qos = <&qos_rkvdec0>; 1011 #power-domain-cells = <0>; 1012 }; 1013 power-domain@RK3588_PD_RKVDEC1 { 1014 reg = <RK3588_PD_RKVDEC1>; 1015 clocks = <&cru HCLK_RKVDEC1>, 1016 <&cru HCLK_VDPU_ROOT>, 1017 <&cru ACLK_VDPU_ROOT>; 1018 pm_qos = <&qos_rkvdec1>; 1019 #power-domain-cells = <0>; 1020 }; 1021 power-domain@RK3588_PD_RGA30 { 1022 reg = <RK3588_PD_RGA30>; 1023 clocks = <&cru ACLK_RGA3_0>, 1024 <&cru HCLK_RGA3_0>; 1025 pm_qos = <&qos_rga3_0>; 1026 #power-domain-cells = <0>; 1027 }; 1028 }; 1029 power-domain@RK3588_PD_VOP { 1030 reg = <RK3588_PD_VOP>; 1031 clocks = <&cru PCLK_VOP_ROOT>, 1032 <&cru HCLK_VOP_ROOT>, 1033 <&cru ACLK_VOP>; 1034 pm_qos = <&qos_vop_m0>, 1035 <&qos_vop_m1>; 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 #power-domain-cells = <0>; 1039 1040 power-domain@RK3588_PD_VO0 { 1041 reg = <RK3588_PD_VO0>; 1042 clocks = <&cru PCLK_VO0_ROOT>, 1043 <&cru PCLK_VO0_S_ROOT>, 1044 <&cru HCLK_VO0_S_ROOT>, 1045 <&cru ACLK_VO0_ROOT>, 1046 <&cru HCLK_HDCP0>, 1047 <&cru ACLK_HDCP0>, 1048 <&cru HCLK_VOP_ROOT>; 1049 pm_qos = <&qos_hdcp0>; 1050 #power-domain-cells = <0>; 1051 }; 1052 }; 1053 power-domain@RK3588_PD_VO1 { 1054 reg = <RK3588_PD_VO1>; 1055 clocks = <&cru PCLK_VO1_ROOT>, 1056 <&cru PCLK_VO1_S_ROOT>, 1057 <&cru HCLK_VO1_S_ROOT>, 1058 <&cru HCLK_HDCP1>, 1059 <&cru ACLK_HDCP1>, 1060 <&cru ACLK_HDMIRX_ROOT>, 1061 <&cru HCLK_VO1USB_TOP_ROOT>; 1062 pm_qos = <&qos_hdcp1>, 1063 <&qos_hdmirx>; 1064 #power-domain-cells = <0>; 1065 }; 1066 power-domain@RK3588_PD_VI { 1067 reg = <RK3588_PD_VI>; 1068 clocks = <&cru HCLK_VI_ROOT>, 1069 <&cru PCLK_VI_ROOT>, 1070 <&cru HCLK_ISP0>, 1071 <&cru ACLK_ISP0>, 1072 <&cru HCLK_VICAP>, 1073 <&cru ACLK_VICAP>; 1074 pm_qos = <&qos_isp0_mro>, 1075 <&qos_isp0_mwo>, 1076 <&qos_vicap_m0>, 1077 <&qos_vicap_m1>; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 #power-domain-cells = <0>; 1081 1082 power-domain@RK3588_PD_ISP1 { 1083 reg = <RK3588_PD_ISP1>; 1084 clocks = <&cru HCLK_ISP1>, 1085 <&cru ACLK_ISP1>, 1086 <&cru HCLK_VI_ROOT>, 1087 <&cru PCLK_VI_ROOT>; 1088 pm_qos = <&qos_isp1_mwo>, 1089 <&qos_isp1_mro>; 1090 #power-domain-cells = <0>; 1091 }; 1092 power-domain@RK3588_PD_FEC { 1093 reg = <RK3588_PD_FEC>; 1094 clocks = <&cru HCLK_FISHEYE0>, 1095 <&cru ACLK_FISHEYE0>, 1096 <&cru HCLK_FISHEYE1>, 1097 <&cru ACLK_FISHEYE1>, 1098 <&cru PCLK_VI_ROOT>; 1099 pm_qos = <&qos_fisheye0>, 1100 <&qos_fisheye1>; 1101 #power-domain-cells = <0>; 1102 }; 1103 }; 1104 power-domain@RK3588_PD_RGA31 { 1105 reg = <RK3588_PD_RGA31>; 1106 clocks = <&cru HCLK_RGA3_1>, 1107 <&cru ACLK_RGA3_1>; 1108 pm_qos = <&qos_rga3_1>; 1109 #power-domain-cells = <0>; 1110 }; 1111 power-domain@RK3588_PD_USB { 1112 reg = <RK3588_PD_USB>; 1113 clocks = <&cru PCLK_PHP_ROOT>, 1114 <&cru ACLK_USB_ROOT>, 1115 <&cru ACLK_USB>, 1116 <&cru HCLK_USB_ROOT>, 1117 <&cru HCLK_HOST0>, 1118 <&cru HCLK_HOST_ARB0>, 1119 <&cru HCLK_HOST1>, 1120 <&cru HCLK_HOST_ARB1>; 1121 pm_qos = <&qos_usb3_0>, 1122 <&qos_usb3_1>, 1123 <&qos_usb2host_0>, 1124 <&qos_usb2host_1>; 1125 #power-domain-cells = <0>; 1126 }; 1127 power-domain@RK3588_PD_GMAC { 1128 reg = <RK3588_PD_GMAC>; 1129 clocks = <&cru PCLK_PHP_ROOT>, 1130 <&cru ACLK_PCIE_ROOT>, 1131 <&cru ACLK_PHP_ROOT>; 1132 #power-domain-cells = <0>; 1133 }; 1134 power-domain@RK3588_PD_PCIE { 1135 reg = <RK3588_PD_PCIE>; 1136 clocks = <&cru PCLK_PHP_ROOT>, 1137 <&cru ACLK_PCIE_ROOT>, 1138 <&cru ACLK_PHP_ROOT>; 1139 #power-domain-cells = <0>; 1140 }; 1141 power-domain@RK3588_PD_SDIO { 1142 reg = <RK3588_PD_SDIO>; 1143 clocks = <&cru HCLK_SDIO>, 1144 <&cru HCLK_NVM_ROOT>; 1145 pm_qos = <&qos_sdio>; 1146 #power-domain-cells = <0>; 1147 }; 1148 power-domain@RK3588_PD_AUDIO { 1149 reg = <RK3588_PD_AUDIO>; 1150 clocks = <&cru HCLK_AUDIO_ROOT>, 1151 <&cru PCLK_AUDIO_ROOT>; 1152 #power-domain-cells = <0>; 1153 }; 1154 power-domain@RK3588_PD_SDMMC { 1155 reg = <RK3588_PD_SDMMC>; 1156 pm_qos = <&qos_sdmmc>; 1157 #power-domain-cells = <0>; 1158 }; 1159 }; 1160 }; 1161 1162 av1d: video-codec@fdc70000 { 1163 compatible = "rockchip,rk3588-av1-vpu"; 1164 reg = <0x0 0xfdc70000 0x0 0x800>; 1165 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 1166 interrupt-names = "vdpu"; 1167 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1168 assigned-clock-rates = <400000000>, <400000000>; 1169 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1170 clock-names = "aclk", "hclk"; 1171 power-domains = <&power RK3588_PD_AV1>; 1172 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; 1173 }; 1174 1175 vop: vop@fdd90000 { 1176 compatible = "rockchip,rk3588-vop"; 1177 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; 1178 reg-names = "vop", "gamma-lut"; 1179 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1180 clocks = <&cru ACLK_VOP>, 1181 <&cru HCLK_VOP>, 1182 <&cru DCLK_VOP0>, 1183 <&cru DCLK_VOP1>, 1184 <&cru DCLK_VOP2>, 1185 <&cru DCLK_VOP3>, 1186 <&cru PCLK_VOP_ROOT>; 1187 clock-names = "aclk", 1188 "hclk", 1189 "dclk_vp0", 1190 "dclk_vp1", 1191 "dclk_vp2", 1192 "dclk_vp3", 1193 "pclk_vop"; 1194 iommus = <&vop_mmu>; 1195 power-domains = <&power RK3588_PD_VOP>; 1196 rockchip,grf = <&sys_grf>; 1197 rockchip,vop-grf = <&vop_grf>; 1198 rockchip,vo1-grf = <&vo1_grf>; 1199 rockchip,pmu = <&pmu>; 1200 status = "disabled"; 1201 1202 vop_out: ports { 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 1206 vp0: port@0 { 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 reg = <0>; 1210 }; 1211 1212 vp1: port@1 { 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 reg = <1>; 1216 }; 1217 1218 vp2: port@2 { 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 reg = <2>; 1222 }; 1223 1224 vp3: port@3 { 1225 #address-cells = <1>; 1226 #size-cells = <0>; 1227 reg = <3>; 1228 }; 1229 }; 1230 }; 1231 1232 vop_mmu: iommu@fdd97e00 { 1233 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1234 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 1235 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1236 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1237 clock-names = "aclk", "iface"; 1238 #iommu-cells = <0>; 1239 power-domains = <&power RK3588_PD_VOP>; 1240 status = "disabled"; 1241 }; 1242 1243 i2s4_8ch: i2s@fddc0000 { 1244 compatible = "rockchip,rk3588-i2s-tdm"; 1245 reg = <0x0 0xfddc0000 0x0 0x1000>; 1246 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; 1247 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 1248 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1249 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 1250 assigned-clock-parents = <&cru PLL_AUPLL>; 1251 dmas = <&dmac2 0>; 1252 dma-names = "tx"; 1253 power-domains = <&power RK3588_PD_VO0>; 1254 resets = <&cru SRST_M_I2S4_8CH_TX>; 1255 reset-names = "tx-m"; 1256 #sound-dai-cells = <0>; 1257 status = "disabled"; 1258 }; 1259 1260 i2s5_8ch: i2s@fddf0000 { 1261 compatible = "rockchip,rk3588-i2s-tdm"; 1262 reg = <0x0 0xfddf0000 0x0 0x1000>; 1263 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; 1264 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 1265 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1266 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 1267 assigned-clock-parents = <&cru PLL_AUPLL>; 1268 dmas = <&dmac2 2>; 1269 dma-names = "tx"; 1270 power-domains = <&power RK3588_PD_VO1>; 1271 resets = <&cru SRST_M_I2S5_8CH_TX>; 1272 reset-names = "tx-m"; 1273 #sound-dai-cells = <0>; 1274 status = "disabled"; 1275 }; 1276 1277 i2s9_8ch: i2s@fddfc000 { 1278 compatible = "rockchip,rk3588-i2s-tdm"; 1279 reg = <0x0 0xfddfc000 0x0 0x1000>; 1280 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; 1281 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 1282 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1283 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 1284 assigned-clock-parents = <&cru PLL_AUPLL>; 1285 dmas = <&dmac2 23>; 1286 dma-names = "rx"; 1287 power-domains = <&power RK3588_PD_VO1>; 1288 resets = <&cru SRST_M_I2S9_8CH_RX>; 1289 reset-names = "rx-m"; 1290 #sound-dai-cells = <0>; 1291 status = "disabled"; 1292 }; 1293 1294 qos_gpu_m0: qos@fdf35000 { 1295 compatible = "rockchip,rk3588-qos", "syscon"; 1296 reg = <0x0 0xfdf35000 0x0 0x20>; 1297 }; 1298 1299 qos_gpu_m1: qos@fdf35200 { 1300 compatible = "rockchip,rk3588-qos", "syscon"; 1301 reg = <0x0 0xfdf35200 0x0 0x20>; 1302 }; 1303 1304 qos_gpu_m2: qos@fdf35400 { 1305 compatible = "rockchip,rk3588-qos", "syscon"; 1306 reg = <0x0 0xfdf35400 0x0 0x20>; 1307 }; 1308 1309 qos_gpu_m3: qos@fdf35600 { 1310 compatible = "rockchip,rk3588-qos", "syscon"; 1311 reg = <0x0 0xfdf35600 0x0 0x20>; 1312 }; 1313 1314 qos_rga3_1: qos@fdf36000 { 1315 compatible = "rockchip,rk3588-qos", "syscon"; 1316 reg = <0x0 0xfdf36000 0x0 0x20>; 1317 }; 1318 1319 qos_sdio: qos@fdf39000 { 1320 compatible = "rockchip,rk3588-qos", "syscon"; 1321 reg = <0x0 0xfdf39000 0x0 0x20>; 1322 }; 1323 1324 qos_sdmmc: qos@fdf3d800 { 1325 compatible = "rockchip,rk3588-qos", "syscon"; 1326 reg = <0x0 0xfdf3d800 0x0 0x20>; 1327 }; 1328 1329 qos_usb3_1: qos@fdf3e000 { 1330 compatible = "rockchip,rk3588-qos", "syscon"; 1331 reg = <0x0 0xfdf3e000 0x0 0x20>; 1332 }; 1333 1334 qos_usb3_0: qos@fdf3e200 { 1335 compatible = "rockchip,rk3588-qos", "syscon"; 1336 reg = <0x0 0xfdf3e200 0x0 0x20>; 1337 }; 1338 1339 qos_usb2host_0: qos@fdf3e400 { 1340 compatible = "rockchip,rk3588-qos", "syscon"; 1341 reg = <0x0 0xfdf3e400 0x0 0x20>; 1342 }; 1343 1344 qos_usb2host_1: qos@fdf3e600 { 1345 compatible = "rockchip,rk3588-qos", "syscon"; 1346 reg = <0x0 0xfdf3e600 0x0 0x20>; 1347 }; 1348 1349 qos_fisheye0: qos@fdf40000 { 1350 compatible = "rockchip,rk3588-qos", "syscon"; 1351 reg = <0x0 0xfdf40000 0x0 0x20>; 1352 }; 1353 1354 qos_fisheye1: qos@fdf40200 { 1355 compatible = "rockchip,rk3588-qos", "syscon"; 1356 reg = <0x0 0xfdf40200 0x0 0x20>; 1357 }; 1358 1359 qos_isp0_mro: qos@fdf40400 { 1360 compatible = "rockchip,rk3588-qos", "syscon"; 1361 reg = <0x0 0xfdf40400 0x0 0x20>; 1362 }; 1363 1364 qos_isp0_mwo: qos@fdf40500 { 1365 compatible = "rockchip,rk3588-qos", "syscon"; 1366 reg = <0x0 0xfdf40500 0x0 0x20>; 1367 }; 1368 1369 qos_vicap_m0: qos@fdf40600 { 1370 compatible = "rockchip,rk3588-qos", "syscon"; 1371 reg = <0x0 0xfdf40600 0x0 0x20>; 1372 }; 1373 1374 qos_vicap_m1: qos@fdf40800 { 1375 compatible = "rockchip,rk3588-qos", "syscon"; 1376 reg = <0x0 0xfdf40800 0x0 0x20>; 1377 }; 1378 1379 qos_isp1_mwo: qos@fdf41000 { 1380 compatible = "rockchip,rk3588-qos", "syscon"; 1381 reg = <0x0 0xfdf41000 0x0 0x20>; 1382 }; 1383 1384 qos_isp1_mro: qos@fdf41100 { 1385 compatible = "rockchip,rk3588-qos", "syscon"; 1386 reg = <0x0 0xfdf41100 0x0 0x20>; 1387 }; 1388 1389 qos_rkvenc0_m0ro: qos@fdf60000 { 1390 compatible = "rockchip,rk3588-qos", "syscon"; 1391 reg = <0x0 0xfdf60000 0x0 0x20>; 1392 }; 1393 1394 qos_rkvenc0_m1ro: qos@fdf60200 { 1395 compatible = "rockchip,rk3588-qos", "syscon"; 1396 reg = <0x0 0xfdf60200 0x0 0x20>; 1397 }; 1398 1399 qos_rkvenc0_m2wo: qos@fdf60400 { 1400 compatible = "rockchip,rk3588-qos", "syscon"; 1401 reg = <0x0 0xfdf60400 0x0 0x20>; 1402 }; 1403 1404 qos_rkvenc1_m0ro: qos@fdf61000 { 1405 compatible = "rockchip,rk3588-qos", "syscon"; 1406 reg = <0x0 0xfdf61000 0x0 0x20>; 1407 }; 1408 1409 qos_rkvenc1_m1ro: qos@fdf61200 { 1410 compatible = "rockchip,rk3588-qos", "syscon"; 1411 reg = <0x0 0xfdf61200 0x0 0x20>; 1412 }; 1413 1414 qos_rkvenc1_m2wo: qos@fdf61400 { 1415 compatible = "rockchip,rk3588-qos", "syscon"; 1416 reg = <0x0 0xfdf61400 0x0 0x20>; 1417 }; 1418 1419 qos_rkvdec0: qos@fdf62000 { 1420 compatible = "rockchip,rk3588-qos", "syscon"; 1421 reg = <0x0 0xfdf62000 0x0 0x20>; 1422 }; 1423 1424 qos_rkvdec1: qos@fdf63000 { 1425 compatible = "rockchip,rk3588-qos", "syscon"; 1426 reg = <0x0 0xfdf63000 0x0 0x20>; 1427 }; 1428 1429 qos_av1: qos@fdf64000 { 1430 compatible = "rockchip,rk3588-qos", "syscon"; 1431 reg = <0x0 0xfdf64000 0x0 0x20>; 1432 }; 1433 1434 qos_iep: qos@fdf66000 { 1435 compatible = "rockchip,rk3588-qos", "syscon"; 1436 reg = <0x0 0xfdf66000 0x0 0x20>; 1437 }; 1438 1439 qos_jpeg_dec: qos@fdf66200 { 1440 compatible = "rockchip,rk3588-qos", "syscon"; 1441 reg = <0x0 0xfdf66200 0x0 0x20>; 1442 }; 1443 1444 qos_jpeg_enc0: qos@fdf66400 { 1445 compatible = "rockchip,rk3588-qos", "syscon"; 1446 reg = <0x0 0xfdf66400 0x0 0x20>; 1447 }; 1448 1449 qos_jpeg_enc1: qos@fdf66600 { 1450 compatible = "rockchip,rk3588-qos", "syscon"; 1451 reg = <0x0 0xfdf66600 0x0 0x20>; 1452 }; 1453 1454 qos_jpeg_enc2: qos@fdf66800 { 1455 compatible = "rockchip,rk3588-qos", "syscon"; 1456 reg = <0x0 0xfdf66800 0x0 0x20>; 1457 }; 1458 1459 qos_jpeg_enc3: qos@fdf66a00 { 1460 compatible = "rockchip,rk3588-qos", "syscon"; 1461 reg = <0x0 0xfdf66a00 0x0 0x20>; 1462 }; 1463 1464 qos_rga2_mro: qos@fdf66c00 { 1465 compatible = "rockchip,rk3588-qos", "syscon"; 1466 reg = <0x0 0xfdf66c00 0x0 0x20>; 1467 }; 1468 1469 qos_rga2_mwo: qos@fdf66e00 { 1470 compatible = "rockchip,rk3588-qos", "syscon"; 1471 reg = <0x0 0xfdf66e00 0x0 0x20>; 1472 }; 1473 1474 qos_rga3_0: qos@fdf67000 { 1475 compatible = "rockchip,rk3588-qos", "syscon"; 1476 reg = <0x0 0xfdf67000 0x0 0x20>; 1477 }; 1478 1479 qos_vdpu: qos@fdf67200 { 1480 compatible = "rockchip,rk3588-qos", "syscon"; 1481 reg = <0x0 0xfdf67200 0x0 0x20>; 1482 }; 1483 1484 qos_npu1: qos@fdf70000 { 1485 compatible = "rockchip,rk3588-qos", "syscon"; 1486 reg = <0x0 0xfdf70000 0x0 0x20>; 1487 }; 1488 1489 qos_npu2: qos@fdf71000 { 1490 compatible = "rockchip,rk3588-qos", "syscon"; 1491 reg = <0x0 0xfdf71000 0x0 0x20>; 1492 }; 1493 1494 qos_npu0_mwr: qos@fdf72000 { 1495 compatible = "rockchip,rk3588-qos", "syscon"; 1496 reg = <0x0 0xfdf72000 0x0 0x20>; 1497 }; 1498 1499 qos_npu0_mro: qos@fdf72200 { 1500 compatible = "rockchip,rk3588-qos", "syscon"; 1501 reg = <0x0 0xfdf72200 0x0 0x20>; 1502 }; 1503 1504 qos_mcu_npu: qos@fdf72400 { 1505 compatible = "rockchip,rk3588-qos", "syscon"; 1506 reg = <0x0 0xfdf72400 0x0 0x20>; 1507 }; 1508 1509 qos_hdcp0: qos@fdf80000 { 1510 compatible = "rockchip,rk3588-qos", "syscon"; 1511 reg = <0x0 0xfdf80000 0x0 0x20>; 1512 }; 1513 1514 qos_hdcp1: qos@fdf81000 { 1515 compatible = "rockchip,rk3588-qos", "syscon"; 1516 reg = <0x0 0xfdf81000 0x0 0x20>; 1517 }; 1518 1519 qos_hdmirx: qos@fdf81200 { 1520 compatible = "rockchip,rk3588-qos", "syscon"; 1521 reg = <0x0 0xfdf81200 0x0 0x20>; 1522 }; 1523 1524 qos_vop_m0: qos@fdf82000 { 1525 compatible = "rockchip,rk3588-qos", "syscon"; 1526 reg = <0x0 0xfdf82000 0x0 0x20>; 1527 }; 1528 1529 qos_vop_m1: qos@fdf82200 { 1530 compatible = "rockchip,rk3588-qos", "syscon"; 1531 reg = <0x0 0xfdf82200 0x0 0x20>; 1532 }; 1533 1534 dfi: dfi@fe060000 { 1535 reg = <0x00 0xfe060000 0x00 0x10000>; 1536 compatible = "rockchip,rk3588-dfi"; 1537 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, 1538 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, 1539 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, 1540 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1541 rockchip,pmu = <&pmu1grf>; 1542 }; 1543 1544 pcie2x1l1: pcie@fe180000 { 1545 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1546 bus-range = <0x30 0x3f>; 1547 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 1548 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 1549 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; 1550 clock-names = "aclk_mst", "aclk_slv", 1551 "aclk_dbi", "pclk", 1552 "aux", "pipe"; 1553 device_type = "pci"; 1554 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, 1555 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, 1556 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, 1557 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, 1558 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; 1559 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1560 #interrupt-cells = <1>; 1561 interrupt-map-mask = <0 0 0 7>; 1562 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 1563 <0 0 0 2 &pcie2x1l1_intc 1>, 1564 <0 0 0 3 &pcie2x1l1_intc 2>, 1565 <0 0 0 4 &pcie2x1l1_intc 3>; 1566 linux,pci-domain = <3>; 1567 max-link-speed = <2>; 1568 msi-map = <0x3000 &its0 0x3000 0x1000>; 1569 num-lanes = <1>; 1570 phys = <&combphy2_psu PHY_TYPE_PCIE>; 1571 phy-names = "pcie-phy"; 1572 power-domains = <&power RK3588_PD_PCIE>; 1573 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, 1574 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, 1575 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; 1576 reg = <0xa 0x40c00000 0x0 0x00400000>, 1577 <0x0 0xfe180000 0x0 0x00010000>, 1578 <0x0 0xf3000000 0x0 0x00100000>; 1579 reg-names = "dbi", "apb", "config"; 1580 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; 1581 reset-names = "pwr", "pipe"; 1582 #address-cells = <3>; 1583 #size-cells = <2>; 1584 status = "disabled"; 1585 1586 pcie2x1l1_intc: legacy-interrupt-controller { 1587 interrupt-controller; 1588 #address-cells = <0>; 1589 #interrupt-cells = <1>; 1590 interrupt-parent = <&gic>; 1591 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; 1592 }; 1593 }; 1594 1595 pcie2x1l2: pcie@fe190000 { 1596 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1597 bus-range = <0x40 0x4f>; 1598 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 1599 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 1600 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; 1601 clock-names = "aclk_mst", "aclk_slv", 1602 "aclk_dbi", "pclk", 1603 "aux", "pipe"; 1604 device_type = "pci"; 1605 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, 1606 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, 1607 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, 1608 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, 1609 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; 1610 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1611 #interrupt-cells = <1>; 1612 interrupt-map-mask = <0 0 0 7>; 1613 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 1614 <0 0 0 2 &pcie2x1l2_intc 1>, 1615 <0 0 0 3 &pcie2x1l2_intc 2>, 1616 <0 0 0 4 &pcie2x1l2_intc 3>; 1617 linux,pci-domain = <4>; 1618 max-link-speed = <2>; 1619 msi-map = <0x4000 &its0 0x4000 0x1000>; 1620 num-lanes = <1>; 1621 phys = <&combphy0_ps PHY_TYPE_PCIE>; 1622 phy-names = "pcie-phy"; 1623 power-domains = <&power RK3588_PD_PCIE>; 1624 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 1625 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, 1626 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; 1627 reg = <0xa 0x41000000 0x0 0x00400000>, 1628 <0x0 0xfe190000 0x0 0x00010000>, 1629 <0x0 0xf4000000 0x0 0x00100000>; 1630 reg-names = "dbi", "apb", "config"; 1631 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; 1632 reset-names = "pwr", "pipe"; 1633 #address-cells = <3>; 1634 #size-cells = <2>; 1635 status = "disabled"; 1636 1637 pcie2x1l2_intc: legacy-interrupt-controller { 1638 interrupt-controller; 1639 #address-cells = <0>; 1640 #interrupt-cells = <1>; 1641 interrupt-parent = <&gic>; 1642 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; 1643 }; 1644 }; 1645 1646 gmac1: ethernet@fe1c0000 { 1647 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1648 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1649 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, 1650 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 1651 interrupt-names = "macirq", "eth_wake_irq"; 1652 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 1653 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1654 <&cru CLK_GMAC1_PTP_REF>; 1655 clock-names = "stmmaceth", "clk_mac_ref", 1656 "pclk_mac", "aclk_mac", 1657 "ptp_ref"; 1658 power-domains = <&power RK3588_PD_GMAC>; 1659 resets = <&cru SRST_A_GMAC1>; 1660 reset-names = "stmmaceth"; 1661 rockchip,grf = <&sys_grf>; 1662 rockchip,php-grf = <&php_grf>; 1663 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1664 snps,mixed-burst; 1665 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1666 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1667 snps,tso; 1668 status = "disabled"; 1669 1670 mdio1: mdio { 1671 compatible = "snps,dwmac-mdio"; 1672 #address-cells = <0x1>; 1673 #size-cells = <0x0>; 1674 }; 1675 1676 gmac1_stmmac_axi_setup: stmmac-axi-config { 1677 snps,blen = <0 0 0 0 16 8 4>; 1678 snps,wr_osr_lmt = <4>; 1679 snps,rd_osr_lmt = <8>; 1680 }; 1681 1682 gmac1_mtl_rx_setup: rx-queues-config { 1683 snps,rx-queues-to-use = <2>; 1684 queue0 {}; 1685 queue1 {}; 1686 }; 1687 1688 gmac1_mtl_tx_setup: tx-queues-config { 1689 snps,tx-queues-to-use = <2>; 1690 queue0 {}; 1691 queue1 {}; 1692 }; 1693 }; 1694 1695 sata0: sata@fe210000 { 1696 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1697 reg = <0 0xfe210000 0 0x1000>; 1698 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; 1699 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1700 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, 1701 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; 1702 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1703 ports-implemented = <0x1>; 1704 #address-cells = <1>; 1705 #size-cells = <0>; 1706 status = "disabled"; 1707 1708 sata-port@0 { 1709 reg = <0>; 1710 hba-port-cap = <HBA_PORT_FBSCP>; 1711 phys = <&combphy0_ps PHY_TYPE_SATA>; 1712 phy-names = "sata-phy"; 1713 snps,rx-ts-max = <32>; 1714 snps,tx-ts-max = <32>; 1715 }; 1716 }; 1717 1718 sata2: sata@fe230000 { 1719 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1720 reg = <0 0xfe230000 0 0x1000>; 1721 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; 1722 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 1723 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, 1724 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; 1725 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1726 ports-implemented = <0x1>; 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 status = "disabled"; 1730 1731 sata-port@0 { 1732 reg = <0>; 1733 hba-port-cap = <HBA_PORT_FBSCP>; 1734 phys = <&combphy2_psu PHY_TYPE_SATA>; 1735 phy-names = "sata-phy"; 1736 snps,rx-ts-max = <32>; 1737 snps,tx-ts-max = <32>; 1738 }; 1739 }; 1740 1741 sfc: spi@fe2b0000 { 1742 compatible = "rockchip,sfc"; 1743 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1744 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; 1745 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1746 clock-names = "clk_sfc", "hclk_sfc"; 1747 #address-cells = <1>; 1748 #size-cells = <0>; 1749 status = "disabled"; 1750 }; 1751 1752 sdmmc: mmc@fe2c0000 { 1753 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1754 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1755 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 1756 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 1757 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1758 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1759 fifo-depth = <0x100>; 1760 max-frequency = <200000000>; 1761 pinctrl-names = "default"; 1762 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1763 power-domains = <&power RK3588_PD_SDMMC>; 1764 status = "disabled"; 1765 }; 1766 1767 sdio: mmc@fe2d0000 { 1768 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1769 reg = <0x00 0xfe2d0000 0x00 0x4000>; 1770 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; 1771 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 1772 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1773 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1774 fifo-depth = <0x100>; 1775 max-frequency = <200000000>; 1776 pinctrl-names = "default"; 1777 pinctrl-0 = <&sdiom1_pins>; 1778 power-domains = <&power RK3588_PD_SDIO>; 1779 status = "disabled"; 1780 }; 1781 1782 sdhci: mmc@fe2e0000 { 1783 compatible = "rockchip,rk3588-dwcmshc"; 1784 reg = <0x0 0xfe2e0000 0x0 0x10000>; 1785 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 1786 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 1787 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1788 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1789 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1790 <&cru TMCLK_EMMC>; 1791 clock-names = "core", "bus", "axi", "block", "timer"; 1792 max-frequency = <200000000>; 1793 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 1794 <&emmc_cmd>, <&emmc_data_strobe>; 1795 pinctrl-names = "default"; 1796 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1797 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1798 <&cru SRST_T_EMMC>; 1799 reset-names = "core", "bus", "axi", "block", "timer"; 1800 status = "disabled"; 1801 }; 1802 1803 i2s0_8ch: i2s@fe470000 { 1804 compatible = "rockchip,rk3588-i2s-tdm"; 1805 reg = <0x0 0xfe470000 0x0 0x1000>; 1806 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; 1807 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1808 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1809 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1810 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 1811 dmas = <&dmac0 0>, <&dmac0 1>; 1812 dma-names = "tx", "rx"; 1813 power-domains = <&power RK3588_PD_AUDIO>; 1814 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1815 reset-names = "tx-m", "rx-m"; 1816 rockchip,trcm-sync-tx-only; 1817 pinctrl-names = "default"; 1818 pinctrl-0 = <&i2s0_lrck 1819 &i2s0_sclk 1820 &i2s0_sdi0 1821 &i2s0_sdi1 1822 &i2s0_sdi2 1823 &i2s0_sdi3 1824 &i2s0_sdo0 1825 &i2s0_sdo1 1826 &i2s0_sdo2 1827 &i2s0_sdo3>; 1828 #sound-dai-cells = <0>; 1829 status = "disabled"; 1830 }; 1831 1832 i2s1_8ch: i2s@fe480000 { 1833 compatible = "rockchip,rk3588-i2s-tdm"; 1834 reg = <0x0 0xfe480000 0x0 0x1000>; 1835 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; 1836 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1837 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1838 dmas = <&dmac0 2>, <&dmac0 3>; 1839 dma-names = "tx", "rx"; 1840 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1841 reset-names = "tx-m", "rx-m"; 1842 rockchip,trcm-sync-tx-only; 1843 pinctrl-names = "default"; 1844 pinctrl-0 = <&i2s1m0_lrck 1845 &i2s1m0_sclk 1846 &i2s1m0_sdi0 1847 &i2s1m0_sdi1 1848 &i2s1m0_sdi2 1849 &i2s1m0_sdi3 1850 &i2s1m0_sdo0 1851 &i2s1m0_sdo1 1852 &i2s1m0_sdo2 1853 &i2s1m0_sdo3>; 1854 #sound-dai-cells = <0>; 1855 status = "disabled"; 1856 }; 1857 1858 i2s2_2ch: i2s@fe490000 { 1859 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1860 reg = <0x0 0xfe490000 0x0 0x1000>; 1861 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; 1862 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1863 clock-names = "i2s_clk", "i2s_hclk"; 1864 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1865 assigned-clock-parents = <&cru PLL_AUPLL>; 1866 dmas = <&dmac1 0>, <&dmac1 1>; 1867 dma-names = "tx", "rx"; 1868 power-domains = <&power RK3588_PD_AUDIO>; 1869 pinctrl-names = "default"; 1870 pinctrl-0 = <&i2s2m1_lrck 1871 &i2s2m1_sclk 1872 &i2s2m1_sdi 1873 &i2s2m1_sdo>; 1874 #sound-dai-cells = <0>; 1875 status = "disabled"; 1876 }; 1877 1878 i2s3_2ch: i2s@fe4a0000 { 1879 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1880 reg = <0x0 0xfe4a0000 0x0 0x1000>; 1881 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; 1882 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 1883 clock-names = "i2s_clk", "i2s_hclk"; 1884 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 1885 assigned-clock-parents = <&cru PLL_AUPLL>; 1886 dmas = <&dmac1 2>, <&dmac1 3>; 1887 dma-names = "tx", "rx"; 1888 power-domains = <&power RK3588_PD_AUDIO>; 1889 pinctrl-names = "default"; 1890 pinctrl-0 = <&i2s3_lrck 1891 &i2s3_sclk 1892 &i2s3_sdi 1893 &i2s3_sdo>; 1894 #sound-dai-cells = <0>; 1895 status = "disabled"; 1896 }; 1897 1898 gic: interrupt-controller@fe600000 { 1899 compatible = "arm,gic-v3"; 1900 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 1901 <0x0 0xfe680000 0 0x100000>; /* GICR */ 1902 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 1903 interrupt-controller; 1904 mbi-alias = <0x0 0xfe610000>; 1905 mbi-ranges = <424 56>; 1906 msi-controller; 1907 ranges; 1908 #address-cells = <2>; 1909 #interrupt-cells = <4>; 1910 #size-cells = <2>; 1911 1912 its0: msi-controller@fe640000 { 1913 compatible = "arm,gic-v3-its"; 1914 reg = <0x0 0xfe640000 0x0 0x20000>; 1915 msi-controller; 1916 #msi-cells = <1>; 1917 }; 1918 1919 its1: msi-controller@fe660000 { 1920 compatible = "arm,gic-v3-its"; 1921 reg = <0x0 0xfe660000 0x0 0x20000>; 1922 msi-controller; 1923 #msi-cells = <1>; 1924 }; 1925 1926 ppi-partitions { 1927 ppi_partition0: interrupt-partition-0 { 1928 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 1929 }; 1930 1931 ppi_partition1: interrupt-partition-1 { 1932 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; 1933 }; 1934 }; 1935 }; 1936 1937 dmac0: dma-controller@fea10000 { 1938 compatible = "arm,pl330", "arm,primecell"; 1939 reg = <0x0 0xfea10000 0x0 0x4000>; 1940 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, 1941 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; 1942 arm,pl330-periph-burst; 1943 clocks = <&cru ACLK_DMAC0>; 1944 clock-names = "apb_pclk"; 1945 #dma-cells = <1>; 1946 }; 1947 1948 dmac1: dma-controller@fea30000 { 1949 compatible = "arm,pl330", "arm,primecell"; 1950 reg = <0x0 0xfea30000 0x0 0x4000>; 1951 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, 1952 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; 1953 arm,pl330-periph-burst; 1954 clocks = <&cru ACLK_DMAC1>; 1955 clock-names = "apb_pclk"; 1956 #dma-cells = <1>; 1957 }; 1958 1959 i2c1: i2c@fea90000 { 1960 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1961 reg = <0x0 0xfea90000 0x0 0x1000>; 1962 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1963 clock-names = "i2c", "pclk"; 1964 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; 1965 pinctrl-0 = <&i2c1m0_xfer>; 1966 pinctrl-names = "default"; 1967 #address-cells = <1>; 1968 #size-cells = <0>; 1969 status = "disabled"; 1970 }; 1971 1972 i2c2: i2c@feaa0000 { 1973 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1974 reg = <0x0 0xfeaa0000 0x0 0x1000>; 1975 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1976 clock-names = "i2c", "pclk"; 1977 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; 1978 pinctrl-0 = <&i2c2m0_xfer>; 1979 pinctrl-names = "default"; 1980 #address-cells = <1>; 1981 #size-cells = <0>; 1982 status = "disabled"; 1983 }; 1984 1985 i2c3: i2c@feab0000 { 1986 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1987 reg = <0x0 0xfeab0000 0x0 0x1000>; 1988 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1989 clock-names = "i2c", "pclk"; 1990 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; 1991 pinctrl-0 = <&i2c3m0_xfer>; 1992 pinctrl-names = "default"; 1993 #address-cells = <1>; 1994 #size-cells = <0>; 1995 status = "disabled"; 1996 }; 1997 1998 i2c4: i2c@feac0000 { 1999 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2000 reg = <0x0 0xfeac0000 0x0 0x1000>; 2001 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2002 clock-names = "i2c", "pclk"; 2003 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; 2004 pinctrl-0 = <&i2c4m0_xfer>; 2005 pinctrl-names = "default"; 2006 #address-cells = <1>; 2007 #size-cells = <0>; 2008 status = "disabled"; 2009 }; 2010 2011 i2c5: i2c@fead0000 { 2012 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2013 reg = <0x0 0xfead0000 0x0 0x1000>; 2014 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2015 clock-names = "i2c", "pclk"; 2016 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; 2017 pinctrl-0 = <&i2c5m0_xfer>; 2018 pinctrl-names = "default"; 2019 #address-cells = <1>; 2020 #size-cells = <0>; 2021 status = "disabled"; 2022 }; 2023 2024 timer0: timer@feae0000 { 2025 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 2026 reg = <0x0 0xfeae0000 0x0 0x20>; 2027 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; 2028 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 2029 clock-names = "pclk", "timer"; 2030 }; 2031 2032 wdt: watchdog@feaf0000 { 2033 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; 2034 reg = <0x0 0xfeaf0000 0x0 0x100>; 2035 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 2036 clock-names = "tclk", "pclk"; 2037 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; 2038 }; 2039 2040 spi0: spi@feb00000 { 2041 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2042 reg = <0x0 0xfeb00000 0x0 0x1000>; 2043 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; 2044 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 2045 clock-names = "spiclk", "apb_pclk"; 2046 dmas = <&dmac0 14>, <&dmac0 15>; 2047 dma-names = "tx", "rx"; 2048 num-cs = <2>; 2049 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 2050 pinctrl-names = "default"; 2051 #address-cells = <1>; 2052 #size-cells = <0>; 2053 status = "disabled"; 2054 }; 2055 2056 spi1: spi@feb10000 { 2057 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2058 reg = <0x0 0xfeb10000 0x0 0x1000>; 2059 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; 2060 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 2061 clock-names = "spiclk", "apb_pclk"; 2062 dmas = <&dmac0 16>, <&dmac0 17>; 2063 dma-names = "tx", "rx"; 2064 num-cs = <2>; 2065 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 2066 pinctrl-names = "default"; 2067 #address-cells = <1>; 2068 #size-cells = <0>; 2069 status = "disabled"; 2070 }; 2071 2072 spi2: spi@feb20000 { 2073 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2074 reg = <0x0 0xfeb20000 0x0 0x1000>; 2075 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; 2076 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 2077 clock-names = "spiclk", "apb_pclk"; 2078 dmas = <&dmac1 15>, <&dmac1 16>; 2079 dma-names = "tx", "rx"; 2080 num-cs = <2>; 2081 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 2082 pinctrl-names = "default"; 2083 #address-cells = <1>; 2084 #size-cells = <0>; 2085 status = "disabled"; 2086 }; 2087 2088 spi3: spi@feb30000 { 2089 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2090 reg = <0x0 0xfeb30000 0x0 0x1000>; 2091 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; 2092 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 2093 clock-names = "spiclk", "apb_pclk"; 2094 dmas = <&dmac1 17>, <&dmac1 18>; 2095 dma-names = "tx", "rx"; 2096 num-cs = <2>; 2097 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 2098 pinctrl-names = "default"; 2099 #address-cells = <1>; 2100 #size-cells = <0>; 2101 status = "disabled"; 2102 }; 2103 2104 uart1: serial@feb40000 { 2105 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2106 reg = <0x0 0xfeb40000 0x0 0x100>; 2107 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; 2108 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 2109 clock-names = "baudclk", "apb_pclk"; 2110 dmas = <&dmac0 8>, <&dmac0 9>; 2111 dma-names = "tx", "rx"; 2112 pinctrl-0 = <&uart1m1_xfer>; 2113 pinctrl-names = "default"; 2114 reg-io-width = <4>; 2115 reg-shift = <2>; 2116 status = "disabled"; 2117 }; 2118 2119 uart2: serial@feb50000 { 2120 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2121 reg = <0x0 0xfeb50000 0x0 0x100>; 2122 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; 2123 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 2124 clock-names = "baudclk", "apb_pclk"; 2125 dmas = <&dmac0 10>, <&dmac0 11>; 2126 dma-names = "tx", "rx"; 2127 pinctrl-0 = <&uart2m1_xfer>; 2128 pinctrl-names = "default"; 2129 reg-io-width = <4>; 2130 reg-shift = <2>; 2131 status = "disabled"; 2132 }; 2133 2134 uart3: serial@feb60000 { 2135 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2136 reg = <0x0 0xfeb60000 0x0 0x100>; 2137 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; 2138 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 2139 clock-names = "baudclk", "apb_pclk"; 2140 dmas = <&dmac0 12>, <&dmac0 13>; 2141 dma-names = "tx", "rx"; 2142 pinctrl-0 = <&uart3m1_xfer>; 2143 pinctrl-names = "default"; 2144 reg-io-width = <4>; 2145 reg-shift = <2>; 2146 status = "disabled"; 2147 }; 2148 2149 uart4: serial@feb70000 { 2150 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2151 reg = <0x0 0xfeb70000 0x0 0x100>; 2152 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; 2153 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 2154 clock-names = "baudclk", "apb_pclk"; 2155 dmas = <&dmac1 9>, <&dmac1 10>; 2156 dma-names = "tx", "rx"; 2157 pinctrl-0 = <&uart4m1_xfer>; 2158 pinctrl-names = "default"; 2159 reg-io-width = <4>; 2160 reg-shift = <2>; 2161 status = "disabled"; 2162 }; 2163 2164 uart5: serial@feb80000 { 2165 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2166 reg = <0x0 0xfeb80000 0x0 0x100>; 2167 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; 2168 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2169 clock-names = "baudclk", "apb_pclk"; 2170 dmas = <&dmac1 11>, <&dmac1 12>; 2171 dma-names = "tx", "rx"; 2172 pinctrl-0 = <&uart5m1_xfer>; 2173 pinctrl-names = "default"; 2174 reg-io-width = <4>; 2175 reg-shift = <2>; 2176 status = "disabled"; 2177 }; 2178 2179 uart6: serial@feb90000 { 2180 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2181 reg = <0x0 0xfeb90000 0x0 0x100>; 2182 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; 2183 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2184 clock-names = "baudclk", "apb_pclk"; 2185 dmas = <&dmac1 13>, <&dmac1 14>; 2186 dma-names = "tx", "rx"; 2187 pinctrl-0 = <&uart6m1_xfer>; 2188 pinctrl-names = "default"; 2189 reg-io-width = <4>; 2190 reg-shift = <2>; 2191 status = "disabled"; 2192 }; 2193 2194 uart7: serial@feba0000 { 2195 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2196 reg = <0x0 0xfeba0000 0x0 0x100>; 2197 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; 2198 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2199 clock-names = "baudclk", "apb_pclk"; 2200 dmas = <&dmac2 7>, <&dmac2 8>; 2201 dma-names = "tx", "rx"; 2202 pinctrl-0 = <&uart7m1_xfer>; 2203 pinctrl-names = "default"; 2204 reg-io-width = <4>; 2205 reg-shift = <2>; 2206 status = "disabled"; 2207 }; 2208 2209 uart8: serial@febb0000 { 2210 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2211 reg = <0x0 0xfebb0000 0x0 0x100>; 2212 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; 2213 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2214 clock-names = "baudclk", "apb_pclk"; 2215 dmas = <&dmac2 9>, <&dmac2 10>; 2216 dma-names = "tx", "rx"; 2217 pinctrl-0 = <&uart8m1_xfer>; 2218 pinctrl-names = "default"; 2219 reg-io-width = <4>; 2220 reg-shift = <2>; 2221 status = "disabled"; 2222 }; 2223 2224 uart9: serial@febc0000 { 2225 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2226 reg = <0x0 0xfebc0000 0x0 0x100>; 2227 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; 2228 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2229 clock-names = "baudclk", "apb_pclk"; 2230 dmas = <&dmac2 11>, <&dmac2 12>; 2231 dma-names = "tx", "rx"; 2232 pinctrl-0 = <&uart9m1_xfer>; 2233 pinctrl-names = "default"; 2234 reg-io-width = <4>; 2235 reg-shift = <2>; 2236 status = "disabled"; 2237 }; 2238 2239 pwm4: pwm@febd0000 { 2240 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2241 reg = <0x0 0xfebd0000 0x0 0x10>; 2242 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2243 clock-names = "pwm", "pclk"; 2244 pinctrl-0 = <&pwm4m0_pins>; 2245 pinctrl-names = "default"; 2246 #pwm-cells = <3>; 2247 status = "disabled"; 2248 }; 2249 2250 pwm5: pwm@febd0010 { 2251 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2252 reg = <0x0 0xfebd0010 0x0 0x10>; 2253 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2254 clock-names = "pwm", "pclk"; 2255 pinctrl-0 = <&pwm5m0_pins>; 2256 pinctrl-names = "default"; 2257 #pwm-cells = <3>; 2258 status = "disabled"; 2259 }; 2260 2261 pwm6: pwm@febd0020 { 2262 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2263 reg = <0x0 0xfebd0020 0x0 0x10>; 2264 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2265 clock-names = "pwm", "pclk"; 2266 pinctrl-0 = <&pwm6m0_pins>; 2267 pinctrl-names = "default"; 2268 #pwm-cells = <3>; 2269 status = "disabled"; 2270 }; 2271 2272 pwm7: pwm@febd0030 { 2273 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2274 reg = <0x0 0xfebd0030 0x0 0x10>; 2275 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2276 clock-names = "pwm", "pclk"; 2277 pinctrl-0 = <&pwm7m0_pins>; 2278 pinctrl-names = "default"; 2279 #pwm-cells = <3>; 2280 status = "disabled"; 2281 }; 2282 2283 pwm8: pwm@febe0000 { 2284 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2285 reg = <0x0 0xfebe0000 0x0 0x10>; 2286 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2287 clock-names = "pwm", "pclk"; 2288 pinctrl-0 = <&pwm8m0_pins>; 2289 pinctrl-names = "default"; 2290 #pwm-cells = <3>; 2291 status = "disabled"; 2292 }; 2293 2294 pwm9: pwm@febe0010 { 2295 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2296 reg = <0x0 0xfebe0010 0x0 0x10>; 2297 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2298 clock-names = "pwm", "pclk"; 2299 pinctrl-0 = <&pwm9m0_pins>; 2300 pinctrl-names = "default"; 2301 #pwm-cells = <3>; 2302 status = "disabled"; 2303 }; 2304 2305 pwm10: pwm@febe0020 { 2306 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2307 reg = <0x0 0xfebe0020 0x0 0x10>; 2308 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2309 clock-names = "pwm", "pclk"; 2310 pinctrl-0 = <&pwm10m0_pins>; 2311 pinctrl-names = "default"; 2312 #pwm-cells = <3>; 2313 status = "disabled"; 2314 }; 2315 2316 pwm11: pwm@febe0030 { 2317 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2318 reg = <0x0 0xfebe0030 0x0 0x10>; 2319 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2320 clock-names = "pwm", "pclk"; 2321 pinctrl-0 = <&pwm11m0_pins>; 2322 pinctrl-names = "default"; 2323 #pwm-cells = <3>; 2324 status = "disabled"; 2325 }; 2326 2327 pwm12: pwm@febf0000 { 2328 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2329 reg = <0x0 0xfebf0000 0x0 0x10>; 2330 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2331 clock-names = "pwm", "pclk"; 2332 pinctrl-0 = <&pwm12m0_pins>; 2333 pinctrl-names = "default"; 2334 #pwm-cells = <3>; 2335 status = "disabled"; 2336 }; 2337 2338 pwm13: pwm@febf0010 { 2339 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2340 reg = <0x0 0xfebf0010 0x0 0x10>; 2341 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2342 clock-names = "pwm", "pclk"; 2343 pinctrl-0 = <&pwm13m0_pins>; 2344 pinctrl-names = "default"; 2345 #pwm-cells = <3>; 2346 status = "disabled"; 2347 }; 2348 2349 pwm14: pwm@febf0020 { 2350 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2351 reg = <0x0 0xfebf0020 0x0 0x10>; 2352 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2353 clock-names = "pwm", "pclk"; 2354 pinctrl-0 = <&pwm14m0_pins>; 2355 pinctrl-names = "default"; 2356 #pwm-cells = <3>; 2357 status = "disabled"; 2358 }; 2359 2360 pwm15: pwm@febf0030 { 2361 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2362 reg = <0x0 0xfebf0030 0x0 0x10>; 2363 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2364 clock-names = "pwm", "pclk"; 2365 pinctrl-0 = <&pwm15m0_pins>; 2366 pinctrl-names = "default"; 2367 #pwm-cells = <3>; 2368 status = "disabled"; 2369 }; 2370 2371 tsadc: tsadc@fec00000 { 2372 compatible = "rockchip,rk3588-tsadc"; 2373 reg = <0x0 0xfec00000 0x0 0x400>; 2374 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; 2375 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2376 clock-names = "tsadc", "apb_pclk"; 2377 assigned-clocks = <&cru CLK_TSADC>; 2378 assigned-clock-rates = <2000000>; 2379 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 2380 reset-names = "tsadc-apb", "tsadc"; 2381 rockchip,hw-tshut-temp = <120000>; 2382 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 2383 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2384 pinctrl-0 = <&tsadc_gpio_func>; 2385 pinctrl-1 = <&tsadc_shut>; 2386 pinctrl-names = "gpio", "otpout"; 2387 #thermal-sensor-cells = <1>; 2388 status = "disabled"; 2389 }; 2390 2391 saradc: adc@fec10000 { 2392 compatible = "rockchip,rk3588-saradc"; 2393 reg = <0x0 0xfec10000 0x0 0x10000>; 2394 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; 2395 #io-channel-cells = <1>; 2396 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2397 clock-names = "saradc", "apb_pclk"; 2398 resets = <&cru SRST_P_SARADC>; 2399 reset-names = "saradc-apb"; 2400 status = "disabled"; 2401 }; 2402 2403 i2c6: i2c@fec80000 { 2404 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2405 reg = <0x0 0xfec80000 0x0 0x1000>; 2406 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2407 clock-names = "i2c", "pclk"; 2408 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; 2409 pinctrl-0 = <&i2c6m0_xfer>; 2410 pinctrl-names = "default"; 2411 #address-cells = <1>; 2412 #size-cells = <0>; 2413 status = "disabled"; 2414 }; 2415 2416 i2c7: i2c@fec90000 { 2417 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2418 reg = <0x0 0xfec90000 0x0 0x1000>; 2419 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2420 clock-names = "i2c", "pclk"; 2421 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 2422 pinctrl-0 = <&i2c7m0_xfer>; 2423 pinctrl-names = "default"; 2424 #address-cells = <1>; 2425 #size-cells = <0>; 2426 status = "disabled"; 2427 }; 2428 2429 i2c8: i2c@feca0000 { 2430 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2431 reg = <0x0 0xfeca0000 0x0 0x1000>; 2432 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2433 clock-names = "i2c", "pclk"; 2434 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; 2435 pinctrl-0 = <&i2c8m0_xfer>; 2436 pinctrl-names = "default"; 2437 #address-cells = <1>; 2438 #size-cells = <0>; 2439 status = "disabled"; 2440 }; 2441 2442 spi4: spi@fecb0000 { 2443 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2444 reg = <0x0 0xfecb0000 0x0 0x1000>; 2445 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; 2446 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2447 clock-names = "spiclk", "apb_pclk"; 2448 dmas = <&dmac2 13>, <&dmac2 14>; 2449 dma-names = "tx", "rx"; 2450 num-cs = <2>; 2451 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 2452 pinctrl-names = "default"; 2453 #address-cells = <1>; 2454 #size-cells = <0>; 2455 status = "disabled"; 2456 }; 2457 2458 otp: efuse@fecc0000 { 2459 compatible = "rockchip,rk3588-otp"; 2460 reg = <0x0 0xfecc0000 0x0 0x400>; 2461 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 2462 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; 2463 clock-names = "otp", "apb_pclk", "phy", "arb"; 2464 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 2465 <&cru SRST_OTPC_ARB>; 2466 reset-names = "otp", "apb", "arb"; 2467 #address-cells = <1>; 2468 #size-cells = <1>; 2469 2470 cpu_code: cpu-code@2 { 2471 reg = <0x02 0x2>; 2472 }; 2473 2474 otp_id: id@7 { 2475 reg = <0x07 0x10>; 2476 }; 2477 2478 cpub0_leakage: cpu-leakage@17 { 2479 reg = <0x17 0x1>; 2480 }; 2481 2482 cpub1_leakage: cpu-leakage@18 { 2483 reg = <0x18 0x1>; 2484 }; 2485 2486 cpul_leakage: cpu-leakage@19 { 2487 reg = <0x19 0x1>; 2488 }; 2489 2490 log_leakage: log-leakage@1a { 2491 reg = <0x1a 0x1>; 2492 }; 2493 2494 gpu_leakage: gpu-leakage@1b { 2495 reg = <0x1b 0x1>; 2496 }; 2497 2498 otp_cpu_version: cpu-version@1c { 2499 reg = <0x1c 0x1>; 2500 bits = <3 3>; 2501 }; 2502 2503 npu_leakage: npu-leakage@28 { 2504 reg = <0x28 0x1>; 2505 }; 2506 2507 codec_leakage: codec-leakage@29 { 2508 reg = <0x29 0x1>; 2509 }; 2510 }; 2511 2512 dmac2: dma-controller@fed10000 { 2513 compatible = "arm,pl330", "arm,primecell"; 2514 reg = <0x0 0xfed10000 0x0 0x4000>; 2515 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, 2516 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; 2517 arm,pl330-periph-burst; 2518 clocks = <&cru ACLK_DMAC2>; 2519 clock-names = "apb_pclk"; 2520 #dma-cells = <1>; 2521 }; 2522 2523 hdptxphy_hdmi0: phy@fed60000 { 2524 compatible = "rockchip,rk3588-hdptx-phy"; 2525 reg = <0x0 0xfed60000 0x0 0x2000>; 2526 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 2527 clock-names = "ref", "apb"; 2528 #phy-cells = <0>; 2529 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, 2530 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, 2531 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, 2532 <&cru SRST_HDPTX0_LCPLL>; 2533 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 2534 "lcpll"; 2535 rockchip,grf = <&hdptxphy0_grf>; 2536 status = "disabled"; 2537 }; 2538 2539 usbdp_phy0: phy@fed80000 { 2540 compatible = "rockchip,rk3588-usbdp-phy"; 2541 reg = <0x0 0xfed80000 0x0 0x10000>; 2542 #phy-cells = <1>; 2543 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 2544 <&cru CLK_USBDP_PHY0_IMMORTAL>, 2545 <&cru PCLK_USBDPPHY0>, 2546 <&u2phy0>; 2547 clock-names = "refclk", "immortal", "pclk", "utmi"; 2548 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 2549 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 2550 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 2551 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 2552 <&cru SRST_P_USBDPPHY0>; 2553 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 2554 rockchip,u2phy-grf = <&usb2phy0_grf>; 2555 rockchip,usb-grf = <&usb_grf>; 2556 rockchip,usbdpphy-grf = <&usbdpphy0_grf>; 2557 rockchip,vo-grf = <&vo0_grf>; 2558 status = "disabled"; 2559 }; 2560 2561 combphy0_ps: phy@fee00000 { 2562 compatible = "rockchip,rk3588-naneng-combphy"; 2563 reg = <0x0 0xfee00000 0x0 0x100>; 2564 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, 2565 <&cru PCLK_PHP_ROOT>; 2566 clock-names = "ref", "apb", "pipe"; 2567 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 2568 assigned-clock-rates = <100000000>; 2569 #phy-cells = <1>; 2570 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; 2571 reset-names = "phy", "apb"; 2572 rockchip,pipe-grf = <&php_grf>; 2573 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 2574 status = "disabled"; 2575 }; 2576 2577 combphy2_psu: phy@fee20000 { 2578 compatible = "rockchip,rk3588-naneng-combphy"; 2579 reg = <0x0 0xfee20000 0x0 0x100>; 2580 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, 2581 <&cru PCLK_PHP_ROOT>; 2582 clock-names = "ref", "apb", "pipe"; 2583 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 2584 assigned-clock-rates = <100000000>; 2585 #phy-cells = <1>; 2586 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; 2587 reset-names = "phy", "apb"; 2588 rockchip,pipe-grf = <&php_grf>; 2589 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 2590 status = "disabled"; 2591 }; 2592 2593 system_sram2: sram@ff001000 { 2594 compatible = "mmio-sram"; 2595 reg = <0x0 0xff001000 0x0 0xef000>; 2596 ranges = <0x0 0x0 0xff001000 0xef000>; 2597 #address-cells = <1>; 2598 #size-cells = <1>; 2599 }; 2600 2601 pinctrl: pinctrl { 2602 compatible = "rockchip,rk3588-pinctrl"; 2603 ranges; 2604 rockchip,grf = <&ioc>; 2605 #address-cells = <2>; 2606 #size-cells = <2>; 2607 2608 gpio0: gpio@fd8a0000 { 2609 compatible = "rockchip,gpio-bank"; 2610 reg = <0x0 0xfd8a0000 0x0 0x100>; 2611 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 2612 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 2613 gpio-controller; 2614 gpio-ranges = <&pinctrl 0 0 32>; 2615 interrupt-controller; 2616 #gpio-cells = <2>; 2617 #interrupt-cells = <2>; 2618 }; 2619 2620 gpio1: gpio@fec20000 { 2621 compatible = "rockchip,gpio-bank"; 2622 reg = <0x0 0xfec20000 0x0 0x100>; 2623 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; 2624 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2625 gpio-controller; 2626 gpio-ranges = <&pinctrl 0 32 32>; 2627 interrupt-controller; 2628 #gpio-cells = <2>; 2629 #interrupt-cells = <2>; 2630 }; 2631 2632 gpio2: gpio@fec30000 { 2633 compatible = "rockchip,gpio-bank"; 2634 reg = <0x0 0xfec30000 0x0 0x100>; 2635 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; 2636 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2637 gpio-controller; 2638 gpio-ranges = <&pinctrl 0 64 32>; 2639 interrupt-controller; 2640 #gpio-cells = <2>; 2641 #interrupt-cells = <2>; 2642 }; 2643 2644 gpio3: gpio@fec40000 { 2645 compatible = "rockchip,gpio-bank"; 2646 reg = <0x0 0xfec40000 0x0 0x100>; 2647 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; 2648 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2649 gpio-controller; 2650 gpio-ranges = <&pinctrl 0 96 32>; 2651 interrupt-controller; 2652 #gpio-cells = <2>; 2653 #interrupt-cells = <2>; 2654 }; 2655 2656 gpio4: gpio@fec50000 { 2657 compatible = "rockchip,gpio-bank"; 2658 reg = <0x0 0xfec50000 0x0 0x100>; 2659 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; 2660 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2661 gpio-controller; 2662 gpio-ranges = <&pinctrl 0 128 32>; 2663 interrupt-controller; 2664 #gpio-cells = <2>; 2665 #interrupt-cells = <2>; 2666 }; 2667 }; 2668}; 2669 2670#include "rk3588s-pinctrl.dtsi" 2671