1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include "rk3588s.dtsi" 7#include "rk3588-pinctrl.dtsi" 8 9/ { 10 usb_host1_xhci: usb@fc400000 { 11 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 12 reg = <0x0 0xfc400000 0x0 0x400000>; 13 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; 14 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, 15 <&cru ACLK_USB3OTG1>; 16 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 17 dr_mode = "otg"; 18 phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; 19 phy-names = "usb2-phy", "usb3-phy"; 20 phy_type = "utmi_wide"; 21 power-domains = <&power RK3588_PD_USB>; 22 resets = <&cru SRST_A_USB3OTG1>; 23 snps,dis_enblslpm_quirk; 24 snps,dis-u2-freeclk-exists-quirk; 25 snps,dis-del-phy-power-chg-quirk; 26 snps,dis-tx-ipgap-linecheck-quirk; 27 status = "disabled"; 28 }; 29 30 pcie30_phy_grf: syscon@fd5b8000 { 31 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; 32 reg = <0x0 0xfd5b8000 0x0 0x10000>; 33 }; 34 35 pipe_phy1_grf: syscon@fd5c0000 { 36 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 37 reg = <0x0 0xfd5c0000 0x0 0x100>; 38 }; 39 40 usbdpphy1_grf: syscon@fd5cc000 { 41 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 42 reg = <0x0 0xfd5cc000 0x0 0x4000>; 43 }; 44 45 usb2phy1_grf: syscon@fd5d4000 { 46 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 47 reg = <0x0 0xfd5d4000 0x0 0x4000>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 51 u2phy1: usb2phy@4000 { 52 compatible = "rockchip,rk3588-usb2phy"; 53 reg = <0x4000 0x10>; 54 #clock-cells = <0>; 55 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 56 clock-names = "phyclk"; 57 clock-output-names = "usb480m_phy1"; 58 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>; 59 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; 60 reset-names = "phy", "apb"; 61 status = "disabled"; 62 63 u2phy1_otg: otg-port { 64 #phy-cells = <0>; 65 status = "disabled"; 66 }; 67 }; 68 }; 69 70 i2s8_8ch: i2s@fddc8000 { 71 compatible = "rockchip,rk3588-i2s-tdm"; 72 reg = <0x0 0xfddc8000 0x0 0x1000>; 73 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>; 74 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; 75 clock-names = "mclk_tx", "mclk_rx", "hclk"; 76 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; 77 assigned-clock-parents = <&cru PLL_AUPLL>; 78 dmas = <&dmac2 22>; 79 dma-names = "tx"; 80 power-domains = <&power RK3588_PD_VO0>; 81 resets = <&cru SRST_M_I2S8_8CH_TX>; 82 reset-names = "tx-m"; 83 #sound-dai-cells = <0>; 84 status = "disabled"; 85 }; 86 87 i2s6_8ch: i2s@fddf4000 { 88 compatible = "rockchip,rk3588-i2s-tdm"; 89 reg = <0x0 0xfddf4000 0x0 0x1000>; 90 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 91 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; 92 clock-names = "mclk_tx", "mclk_rx", "hclk"; 93 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; 94 assigned-clock-parents = <&cru PLL_AUPLL>; 95 dmas = <&dmac2 4>; 96 dma-names = "tx"; 97 power-domains = <&power RK3588_PD_VO1>; 98 resets = <&cru SRST_M_I2S6_8CH_TX>; 99 reset-names = "tx-m"; 100 #sound-dai-cells = <0>; 101 status = "disabled"; 102 }; 103 104 i2s7_8ch: i2s@fddf8000 { 105 compatible = "rockchip,rk3588-i2s-tdm"; 106 reg = <0x0 0xfddf8000 0x0 0x1000>; 107 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>; 108 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; 109 clock-names = "mclk_tx", "mclk_rx", "hclk"; 110 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; 111 assigned-clock-parents = <&cru PLL_AUPLL>; 112 dmas = <&dmac2 21>; 113 dma-names = "rx"; 114 power-domains = <&power RK3588_PD_VO1>; 115 resets = <&cru SRST_M_I2S7_8CH_RX>; 116 reset-names = "rx-m"; 117 #sound-dai-cells = <0>; 118 status = "disabled"; 119 }; 120 121 i2s10_8ch: i2s@fde00000 { 122 compatible = "rockchip,rk3588-i2s-tdm"; 123 reg = <0x0 0xfde00000 0x0 0x1000>; 124 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>; 125 clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; 126 clock-names = "mclk_tx", "mclk_rx", "hclk"; 127 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; 128 assigned-clock-parents = <&cru PLL_AUPLL>; 129 dmas = <&dmac2 24>; 130 dma-names = "rx"; 131 power-domains = <&power RK3588_PD_VO1>; 132 resets = <&cru SRST_M_I2S10_8CH_RX>; 133 reset-names = "rx-m"; 134 #sound-dai-cells = <0>; 135 status = "disabled"; 136 }; 137 138 pcie3x4: pcie@fe150000 { 139 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 140 #address-cells = <3>; 141 #size-cells = <2>; 142 bus-range = <0x00 0x0f>; 143 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 144 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 145 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; 146 clock-names = "aclk_mst", "aclk_slv", 147 "aclk_dbi", "pclk", 148 "aux", "pipe"; 149 device_type = "pci"; 150 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, 151 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, 152 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, 153 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, 154 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 155 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 156 #interrupt-cells = <1>; 157 interrupt-map-mask = <0 0 0 7>; 158 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, 159 <0 0 0 2 &pcie3x4_intc 1>, 160 <0 0 0 3 &pcie3x4_intc 2>, 161 <0 0 0 4 &pcie3x4_intc 3>; 162 linux,pci-domain = <0>; 163 max-link-speed = <3>; 164 msi-map = <0x0000 &its1 0x0000 0x1000>; 165 num-lanes = <4>; 166 phys = <&pcie30phy>; 167 phy-names = "pcie-phy"; 168 power-domains = <&power RK3588_PD_PCIE>; 169 ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, 170 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, 171 <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; 172 reg = <0xa 0x40000000 0x0 0x00400000>, 173 <0x0 0xfe150000 0x0 0x00010000>, 174 <0x0 0xf0000000 0x0 0x00100000>; 175 reg-names = "dbi", "apb", "config"; 176 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; 177 reset-names = "pwr", "pipe"; 178 status = "disabled"; 179 180 pcie3x4_intc: legacy-interrupt-controller { 181 interrupt-controller; 182 #address-cells = <0>; 183 #interrupt-cells = <1>; 184 interrupt-parent = <&gic>; 185 interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; 186 }; 187 }; 188 189 pcie3x2: pcie@fe160000 { 190 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 191 #address-cells = <3>; 192 #size-cells = <2>; 193 bus-range = <0x10 0x1f>; 194 clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, 195 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, 196 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; 197 clock-names = "aclk_mst", "aclk_slv", 198 "aclk_dbi", "pclk", 199 "aux", "pipe"; 200 device_type = "pci"; 201 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, 202 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, 203 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, 204 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, 205 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 206 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 207 #interrupt-cells = <1>; 208 interrupt-map-mask = <0 0 0 7>; 209 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, 210 <0 0 0 2 &pcie3x2_intc 1>, 211 <0 0 0 3 &pcie3x2_intc 2>, 212 <0 0 0 4 &pcie3x2_intc 3>; 213 linux,pci-domain = <1>; 214 max-link-speed = <3>; 215 msi-map = <0x1000 &its1 0x1000 0x1000>; 216 num-lanes = <2>; 217 phys = <&pcie30phy>; 218 phy-names = "pcie-phy"; 219 power-domains = <&power RK3588_PD_PCIE>; 220 ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, 221 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, 222 <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; 223 reg = <0xa 0x40400000 0x0 0x00400000>, 224 <0x0 0xfe160000 0x0 0x00010000>, 225 <0x0 0xf1000000 0x0 0x00100000>; 226 reg-names = "dbi", "apb", "config"; 227 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; 228 reset-names = "pwr", "pipe"; 229 status = "disabled"; 230 231 pcie3x2_intc: legacy-interrupt-controller { 232 interrupt-controller; 233 #address-cells = <0>; 234 #interrupt-cells = <1>; 235 interrupt-parent = <&gic>; 236 interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; 237 }; 238 }; 239 240 pcie2x1l0: pcie@fe170000 { 241 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 242 bus-range = <0x20 0x2f>; 243 clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, 244 <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, 245 <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; 246 clock-names = "aclk_mst", "aclk_slv", 247 "aclk_dbi", "pclk", 248 "aux", "pipe"; 249 device_type = "pci"; 250 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, 251 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, 252 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, 253 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, 254 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; 255 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 256 #interrupt-cells = <1>; 257 interrupt-map-mask = <0 0 0 7>; 258 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, 259 <0 0 0 2 &pcie2x1l0_intc 1>, 260 <0 0 0 3 &pcie2x1l0_intc 2>, 261 <0 0 0 4 &pcie2x1l0_intc 3>; 262 linux,pci-domain = <2>; 263 max-link-speed = <2>; 264 msi-map = <0x2000 &its0 0x2000 0x1000>; 265 num-lanes = <1>; 266 phys = <&combphy1_ps PHY_TYPE_PCIE>; 267 phy-names = "pcie-phy"; 268 power-domains = <&power RK3588_PD_PCIE>; 269 ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, 270 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, 271 <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; 272 reg = <0xa 0x40800000 0x0 0x00400000>, 273 <0x0 0xfe170000 0x0 0x00010000>, 274 <0x0 0xf2000000 0x0 0x00100000>; 275 reg-names = "dbi", "apb", "config"; 276 resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; 277 reset-names = "pwr", "pipe"; 278 #address-cells = <3>; 279 #size-cells = <2>; 280 status = "disabled"; 281 282 pcie2x1l0_intc: legacy-interrupt-controller { 283 interrupt-controller; 284 #address-cells = <0>; 285 #interrupt-cells = <1>; 286 interrupt-parent = <&gic>; 287 interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; 288 }; 289 }; 290 291 gmac0: ethernet@fe1b0000 { 292 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 293 reg = <0x0 0xfe1b0000 0x0 0x10000>; 294 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>, 295 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 296 interrupt-names = "macirq", "eth_wake_irq"; 297 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 298 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 299 <&cru CLK_GMAC0_PTP_REF>; 300 clock-names = "stmmaceth", "clk_mac_ref", 301 "pclk_mac", "aclk_mac", 302 "ptp_ref"; 303 power-domains = <&power RK3588_PD_GMAC>; 304 resets = <&cru SRST_A_GMAC0>; 305 reset-names = "stmmaceth"; 306 rockchip,grf = <&sys_grf>; 307 rockchip,php-grf = <&php_grf>; 308 snps,axi-config = <&gmac0_stmmac_axi_setup>; 309 snps,mixed-burst; 310 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 311 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 312 snps,tso; 313 status = "disabled"; 314 315 mdio0: mdio { 316 compatible = "snps,dwmac-mdio"; 317 #address-cells = <0x1>; 318 #size-cells = <0x0>; 319 }; 320 321 gmac0_stmmac_axi_setup: stmmac-axi-config { 322 snps,blen = <0 0 0 0 16 8 4>; 323 snps,wr_osr_lmt = <4>; 324 snps,rd_osr_lmt = <8>; 325 }; 326 327 gmac0_mtl_rx_setup: rx-queues-config { 328 snps,rx-queues-to-use = <2>; 329 queue0 {}; 330 queue1 {}; 331 }; 332 333 gmac0_mtl_tx_setup: tx-queues-config { 334 snps,tx-queues-to-use = <2>; 335 queue0 {}; 336 queue1 {}; 337 }; 338 }; 339 340 sata1: sata@fe220000 { 341 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 342 reg = <0 0xfe220000 0 0x1000>; 343 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 344 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, 345 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, 346 <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; 347 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 348 ports-implemented = <0x1>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 status = "disabled"; 352 353 sata-port@0 { 354 reg = <0>; 355 hba-port-cap = <HBA_PORT_FBSCP>; 356 phys = <&combphy1_ps PHY_TYPE_SATA>; 357 phy-names = "sata-phy"; 358 snps,rx-ts-max = <32>; 359 snps,tx-ts-max = <32>; 360 }; 361 }; 362 363 usbdp_phy1: phy@fed90000 { 364 compatible = "rockchip,rk3588-usbdp-phy"; 365 reg = <0x0 0xfed90000 0x0 0x10000>; 366 #phy-cells = <1>; 367 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 368 <&cru CLK_USBDP_PHY1_IMMORTAL>, 369 <&cru PCLK_USBDPPHY1>, 370 <&u2phy1>; 371 clock-names = "refclk", "immortal", "pclk", "utmi"; 372 resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, 373 <&cru SRST_USBDP_COMBO_PHY1_CMN>, 374 <&cru SRST_USBDP_COMBO_PHY1_LANE>, 375 <&cru SRST_USBDP_COMBO_PHY1_PCS>, 376 <&cru SRST_P_USBDPPHY1>; 377 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 378 rockchip,u2phy-grf = <&usb2phy1_grf>; 379 rockchip,usb-grf = <&usb_grf>; 380 rockchip,usbdpphy-grf = <&usbdpphy1_grf>; 381 rockchip,vo-grf = <&vo0_grf>; 382 status = "disabled"; 383 }; 384 385 combphy1_ps: phy@fee10000 { 386 compatible = "rockchip,rk3588-naneng-combphy"; 387 reg = <0x0 0xfee10000 0x0 0x100>; 388 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, 389 <&cru PCLK_PHP_ROOT>; 390 clock-names = "ref", "apb", "pipe"; 391 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; 392 assigned-clock-rates = <100000000>; 393 #phy-cells = <1>; 394 resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; 395 reset-names = "phy", "apb"; 396 rockchip,pipe-grf = <&php_grf>; 397 rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 398 status = "disabled"; 399 }; 400 401 pcie30phy: phy@fee80000 { 402 compatible = "rockchip,rk3588-pcie3-phy"; 403 reg = <0x0 0xfee80000 0x0 0x20000>; 404 #phy-cells = <0>; 405 clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; 406 clock-names = "pclk"; 407 resets = <&cru SRST_PCIE30_PHY>; 408 reset-names = "phy"; 409 rockchip,pipe-grf = <&php_grf>; 410 rockchip,phy-grf = <&pcie30_phy_grf>; 411 status = "disabled"; 412 }; 413}; 414