1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/leds/common.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include "rk3588.dtsi" 10 11/ { 12 compatible = "tsd,rk3588-tiger", "rockchip,rk3588"; 13 14 aliases { 15 mmc0 = &sdhci; 16 rtc0 = &rtc_twi; 17 }; 18 19 emmc_pwrseq: emmc-pwrseq { 20 compatible = "mmc-pwrseq-emmc"; 21 pinctrl-0 = <&emmc_reset>; 22 pinctrl-names = "default"; 23 reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; 24 }; 25 26 leds { 27 compatible = "gpio-leds"; 28 pinctrl-names = "default"; 29 pinctrl-0 = <&module_led_pin>; 30 31 /* Named LED1 on the board */ 32 led-1 { 33 gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; 34 function = LED_FUNCTION_HEARTBEAT; 35 linux,default-trigger = "heartbeat"; 36 color = <LED_COLOR_ID_AMBER>; 37 }; 38 }; 39 40 /* 41 * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE 42 * clock generator. 43 * The clock output is gated via the OE pin on the clock generator. 44 * This is modeled as a fixed-clock plus a gpio-gate-clock. 45 */ 46 pcie_refclk_gen: pcie-refclk-gen-clock { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <1000000000>; 50 }; 51 52 pcie_refclk: pcie-refclk-clock { 53 compatible = "gpio-gate-clock"; 54 clocks = <&pcie_refclk_gen>; 55 #clock-cells = <0>; 56 enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M1_L */ 57 }; 58 59 vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { 60 compatible = "regulator-fixed"; 61 regulator-name = "vcc_1v1_nldo_s3"; 62 regulator-always-on; 63 regulator-boot-on; 64 regulator-min-microvolt = <1100000>; 65 regulator-max-microvolt = <1100000>; 66 vin-supply = <&vcc5v0_sys>; 67 }; 68 69 vcc_1v2_s3: vcc-1v2-s3-regulator { 70 compatible = "regulator-fixed"; 71 regulator-name = "vcc_1v2_s3"; 72 regulator-always-on; 73 regulator-boot-on; 74 regulator-min-microvolt = <1200000>; 75 regulator-max-microvolt = <1200000>; 76 vin-supply = <&vcc5v0_sys>; 77 }; 78 79 vcc5v0_sys: vcc5v0-sys-regulator { 80 compatible = "regulator-fixed"; 81 regulator-name = "vcc5v0_sys"; 82 regulator-always-on; 83 regulator-boot-on; 84 regulator-min-microvolt = <5000000>; 85 regulator-max-microvolt = <5000000>; 86 vin-supply = <&vcc5v0_baseboard>; 87 }; 88}; 89 90&cpu_b0 { 91 cpu-supply = <&vdd_cpu_big0_s0>; 92}; 93 94&cpu_b1 { 95 cpu-supply = <&vdd_cpu_big0_s0>; 96}; 97 98&cpu_b2 { 99 cpu-supply = <&vdd_cpu_big1_s0>; 100}; 101 102&cpu_b3 { 103 cpu-supply = <&vdd_cpu_big1_s0>; 104}; 105 106&cpu_l0 { 107 cpu-supply = <&vdd_cpu_lit_s0>; 108}; 109 110&cpu_l1 { 111 cpu-supply = <&vdd_cpu_lit_s0>; 112}; 113 114&cpu_l2 { 115 cpu-supply = <&vdd_cpu_lit_s0>; 116}; 117 118&cpu_l3 { 119 cpu-supply = <&vdd_cpu_lit_s0>; 120}; 121 122&gmac0 { 123 clock_in_out = "output"; 124 phy-handle = <&rgmii_phy>; 125 phy-mode = "rgmii"; 126 phy-supply = <&vcc_1v2_s3>; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&gmac0_miim 129 &gmac0_rx_bus2 130 &gmac0_tx_bus2 131 &gmac0_rgmii_clk 132 &gmac0_rgmii_bus 133 ð0_pins 134 ð_reset>; 135 tx_delay = <0x10>; 136 rx_delay = <0x10>; 137 snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; 138 snps,reset-active-low; 139 snps,reset-delays-us = <0 10000 100000>; 140}; 141 142&i2c1 { 143 pinctrl-0 = <&i2c1m0_xfer>; 144}; 145 146&i2c1m0_xfer { 147 rockchip,pins = 148 /* i2c1_scl_m0 */ 149 <0 RK_PB5 9 &pcfg_pull_none_drv_level_0>, 150 /* i2c1_sda_m0 */ 151 <0 RK_PB6 9 &pcfg_pull_none_drv_level_0>; 152}; 153 154&i2c2 { 155 pinctrl-0 = <&i2c2m3_xfer>; 156 status = "okay"; 157}; 158 159&i2c2m3_xfer { 160 rockchip,pins = 161 /* i2c2_scl_m3 */ 162 <1 RK_PC5 9 &pcfg_pull_none_drv_level_0>, 163 /* i2c2_sda_m3 */ 164 <1 RK_PC4 9 &pcfg_pull_none_drv_level_0>; 165}; 166 167&i2c3 { 168 pinctrl-0 = <&i2c3m0_xfer>; 169}; 170 171&i2c4 { 172 pinctrl-0 = <&i2c4m4_xfer>; 173 status = "okay"; 174 175 vdd_npu_s0: regulator@42 { 176 compatible = "rockchip,rk8602"; 177 reg = <0x42>; 178 fcs,suspend-voltage-selector = <1>; 179 regulator-name = "vdd_npu_s0"; 180 regulator-always-on; 181 regulator-boot-on; 182 regulator-min-microvolt = <550000>; 183 regulator-max-microvolt = <950000>; 184 regulator-ramp-delay = <2300>; 185 vin-supply = <&vcc5v0_sys>; 186 187 regulator-state-mem { 188 regulator-off-in-suspend; 189 }; 190 }; 191}; 192 193&i2c5 { 194 pinctrl-0 = <&i2c5m1_xfer>; 195}; 196 197&i2c5m1_xfer { 198 rockchip,pins = 199 /* i2c5_scl_m1 */ 200 <4 RK_PB6 9 &pcfg_pull_none_drv_level_0>, 201 /* i2c5_sda_m1 */ 202 <4 RK_PB7 9 &pcfg_pull_none_drv_level_0>; 203}; 204 205&i2c6 { 206 /* 207 * Mule-ATtiny can handle up to Fast mode Plus (1MHz) on I2C bus, 208 * but SOC can handle only up to (400kHz). 209 */ 210 clock-frequency = <400000>; 211 status = "okay"; 212 213 fan@18 { 214 compatible = "ti,amc6821"; 215 reg = <0x18>; 216 }; 217 218 rtc_twi: rtc@6f { 219 compatible = "isil,isl1208"; 220 reg = <0x6f>; 221 }; 222}; 223 224&i2c6m0_xfer { 225 rockchip,pins = 226 /* i2c6_scl_m0 */ 227 <0 RK_PD0 9 &pcfg_pull_none_drv_level_0>, 228 /* i2c6_sda_m0 */ 229 <0 RK_PC7 9 &pcfg_pull_none_drv_level_0>; 230}; 231 232&i2c7 { 233 status = "okay"; 234 235 vdd_cpu_big0_s0: regulator@42 { 236 compatible = "rockchip,rk8602"; 237 reg = <0x42>; 238 fcs,suspend-voltage-selector = <1>; 239 regulator-name = "vdd_cpu_big0_s0"; 240 regulator-always-on; 241 regulator-boot-on; 242 regulator-min-microvolt = <550000>; 243 regulator-max-microvolt = <1050000>; 244 regulator-ramp-delay = <2300>; 245 vin-supply = <&vcc5v0_sys>; 246 247 regulator-state-mem { 248 regulator-off-in-suspend; 249 }; 250 }; 251 252 vdd_cpu_big1_s0: regulator@43 { 253 compatible = "rockchip,rk8603", "rockchip,rk8602"; 254 reg = <0x43>; 255 fcs,suspend-voltage-selector = <1>; 256 regulator-name = "vdd_cpu_big1_s0"; 257 regulator-always-on; 258 regulator-boot-on; 259 regulator-min-microvolt = <550000>; 260 regulator-max-microvolt = <1050000>; 261 regulator-ramp-delay = <2300>; 262 vin-supply = <&vcc5v0_sys>; 263 264 regulator-state-mem { 265 regulator-off-in-suspend; 266 }; 267 }; 268}; 269 270&i2c7m0_xfer { 271 rockchip,pins = 272 /* i2c7_scl_m0 */ 273 <1 RK_PD0 9 &pcfg_pull_none_drv_level_0>, 274 /* i2c7_sda_m0 */ 275 <1 RK_PD1 9 &pcfg_pull_none_drv_level_0>; 276}; 277 278&i2c8 { 279 pinctrl-0 = <&i2c8m2_xfer>; 280}; 281 282&mdio0 { 283 rgmii_phy: ethernet-phy@6 { 284 /* KSZ9031 or KSZ9131 */ 285 compatible = "ethernet-phy-ieee802.3-c22"; 286 reg = <0x6>; 287 clocks = <&cru REFCLKO25M_ETH0_OUT>; 288 }; 289}; 290 291&pcie3x4 { 292 /* 293 * The board has a gpio-controlled "pcie_refclk" generator, 294 * so add it to the list of clocks. 295 */ 296 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 297 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 298 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, 299 <&pcie_refclk>; 300 clock-names = "aclk_mst", "aclk_slv", 301 "aclk_dbi", "pclk", 302 "aux", "pipe", 303 "ref"; 304 reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; 305}; 306 307&pinctrl { 308 emmc { 309 emmc_reset: emmc-reset { 310 rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 311 }; 312 }; 313 314 ethernet { 315 eth_reset: eth-reset { 316 rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 317 }; 318 }; 319 320 leds { 321 module_led_pin: module-led-pin { 322 rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 323 }; 324 }; 325}; 326 327&saradc { 328 vref-supply = <&vcc_1v8_s0>; 329 status = "okay"; 330}; 331 332&sdhci { 333 bus-width = <8>; 334 cap-mmc-highspeed; 335 mmc-ddr-1_8v; 336 mmc-hs200-1_8v; 337 mmc-hs400-1_8v; 338 mmc-hs400-enhanced-strobe; 339 mmc-pwrseq = <&emmc_pwrseq>; 340 no-sdio; 341 no-sd; 342 non-removable; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>; 345 supports-cqe; 346 vmmc-supply = <&vcc_3v3_s3>; 347 vqmmc-supply = <&vcc_1v8_s3>; 348 status = "okay"; 349}; 350 351&sdmmc { 352 bus-width = <4>; 353 cap-sd-highspeed; 354 max-frequency = <150000000>; 355 vqmmc-supply = <&vccio_sd_s0>; 356}; 357 358&spi0 { 359 pinctrl-0 = <&spi0m1_cs0 &spi0m1_cs1 &spi0m3_pins>; 360}; 361 362&spi2 { 363 assigned-clocks = <&cru CLK_SPI2>; 364 assigned-clock-rates = <200000000>; 365 num-cs = <1>; 366 pinctrl-names = "default"; 367 pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; 368 status = "okay"; 369 370 pmic@0 { 371 compatible = "rockchip,rk806"; 372 reg = <0x0>; 373 interrupt-parent = <&gpio0>; 374 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 375 gpio-controller; 376 #gpio-cells = <2>; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, 379 <&rk806_dvs2_null>, <&rk806_dvs3_null>; 380 spi-max-frequency = <1000000>; 381 system-power-controller; 382 vcc1-supply = <&vcc5v0_sys>; 383 vcc2-supply = <&vcc5v0_sys>; 384 vcc3-supply = <&vcc5v0_sys>; 385 vcc4-supply = <&vcc5v0_sys>; 386 vcc5-supply = <&vcc5v0_sys>; 387 vcc6-supply = <&vcc5v0_sys>; 388 vcc7-supply = <&vcc5v0_sys>; 389 vcc8-supply = <&vcc5v0_sys>; 390 vcc9-supply = <&vcc5v0_sys>; 391 vcc10-supply = <&vcc5v0_sys>; 392 vcc11-supply = <&vcc_2v0_pldo_s3>; 393 vcc12-supply = <&vcc5v0_sys>; 394 vcc13-supply = <&vcc_1v1_nldo_s3>; 395 vcc14-supply = <&vcc_1v1_nldo_s3>; 396 vcca-supply = <&vcc5v0_sys>; 397 398 rk806_dvs1_null: dvs1-null-pins { 399 pins = "gpio_pwrctrl2"; 400 function = "pin_fun0"; 401 }; 402 403 rk806_dvs2_null: dvs2-null-pins { 404 pins = "gpio_pwrctrl2"; 405 function = "pin_fun0"; 406 }; 407 408 rk806_dvs3_null: dvs3-null-pins { 409 pins = "gpio_pwrctrl3"; 410 function = "pin_fun0"; 411 }; 412 413 regulators { 414 vdd_gpu_s0: dcdc-reg1 { 415 regulator-boot-on; 416 regulator-min-microvolt = <550000>; 417 regulator-max-microvolt = <950000>; 418 regulator-ramp-delay = <12500>; 419 regulator-name = "vdd_gpu_s0"; 420 regulator-enable-ramp-delay = <400>; 421 422 regulator-state-mem { 423 regulator-off-in-suspend; 424 }; 425 }; 426 427 vdd_cpu_lit_s0: dcdc-reg2 { 428 regulator-name = "vdd_cpu_lit_s0"; 429 regulator-always-on; 430 regulator-boot-on; 431 regulator-min-microvolt = <550000>; 432 regulator-max-microvolt = <950000>; 433 regulator-ramp-delay = <12500>; 434 435 regulator-state-mem { 436 regulator-off-in-suspend; 437 }; 438 }; 439 440 vdd_log_s0: dcdc-reg3 { 441 regulator-name = "vdd_log_s0"; 442 regulator-always-on; 443 regulator-boot-on; 444 regulator-min-microvolt = <675000>; 445 regulator-max-microvolt = <750000>; 446 regulator-ramp-delay = <12500>; 447 448 regulator-state-mem { 449 regulator-off-in-suspend; 450 regulator-suspend-microvolt = <750000>; 451 }; 452 }; 453 454 vdd_vdenc_s0: dcdc-reg4 { 455 regulator-name = "vdd_vdenc_s0"; 456 regulator-always-on; 457 regulator-boot-on; 458 regulator-min-microvolt = <550000>; 459 regulator-max-microvolt = <950000>; 460 regulator-ramp-delay = <12500>; 461 462 regulator-state-mem { 463 regulator-off-in-suspend; 464 }; 465 }; 466 467 vdd_ddr_s0: dcdc-reg5 { 468 regulator-name = "vdd_ddr_s0"; 469 regulator-always-on; 470 regulator-boot-on; 471 regulator-min-microvolt = <675000>; 472 regulator-max-microvolt = <900000>; 473 regulator-ramp-delay = <12500>; 474 475 regulator-state-mem { 476 regulator-off-in-suspend; 477 regulator-suspend-microvolt = <850000>; 478 }; 479 }; 480 481 vdd2_ddr_s3: dcdc-reg6 { 482 regulator-name = "vdd2_ddr_s3"; 483 regulator-always-on; 484 regulator-boot-on; 485 486 regulator-state-mem { 487 regulator-on-in-suspend; 488 }; 489 }; 490 491 vcc_2v0_pldo_s3: dcdc-reg7 { 492 regulator-name = "vcc_2v0_pldo_s3"; 493 regulator-always-on; 494 regulator-boot-on; 495 regulator-min-microvolt = <2000000>; 496 regulator-max-microvolt = <2000000>; 497 regulator-ramp-delay = <12500>; 498 499 regulator-state-mem { 500 regulator-on-in-suspend; 501 regulator-suspend-microvolt = <2000000>; 502 }; 503 }; 504 505 vcc_3v3_s3: dcdc-reg8 { 506 regulator-name = "vcc_3v3_s3"; 507 regulator-always-on; 508 regulator-boot-on; 509 regulator-min-microvolt = <3300000>; 510 regulator-max-microvolt = <3300000>; 511 512 regulator-state-mem { 513 regulator-on-in-suspend; 514 regulator-suspend-microvolt = <3300000>; 515 }; 516 }; 517 518 vddq_ddr_s0: dcdc-reg9 { 519 regulator-name = "vddq_ddr_s0"; 520 regulator-always-on; 521 regulator-boot-on; 522 523 regulator-state-mem { 524 regulator-off-in-suspend; 525 }; 526 }; 527 528 vcc_1v8_s3: dcdc-reg10 { 529 regulator-name = "vcc_1v8_s3"; 530 regulator-always-on; 531 regulator-boot-on; 532 regulator-min-microvolt = <1800000>; 533 regulator-max-microvolt = <1800000>; 534 535 regulator-state-mem { 536 regulator-on-in-suspend; 537 regulator-suspend-microvolt = <1800000>; 538 }; 539 }; 540 541 vcca_1v8_s0: pldo-reg1 { 542 regulator-name = "vcca_1v8_s0"; 543 regulator-always-on; 544 regulator-boot-on; 545 regulator-min-microvolt = <1800000>; 546 regulator-max-microvolt = <1800000>; 547 548 regulator-state-mem { 549 regulator-off-in-suspend; 550 }; 551 }; 552 553 vcc_1v8_s0: pldo-reg2 { 554 regulator-name = "vcc_1v8_s0"; 555 regulator-always-on; 556 regulator-boot-on; 557 regulator-min-microvolt = <1800000>; 558 regulator-max-microvolt = <1800000>; 559 560 regulator-state-mem { 561 regulator-off-in-suspend; 562 regulator-suspend-microvolt = <1800000>; 563 }; 564 }; 565 566 vdda_1v2_s0: pldo-reg3 { 567 regulator-name = "vdda_1v2_s0"; 568 regulator-always-on; 569 regulator-boot-on; 570 regulator-min-microvolt = <1200000>; 571 regulator-max-microvolt = <1200000>; 572 573 regulator-state-mem { 574 regulator-off-in-suspend; 575 }; 576 }; 577 578 vcca_3v3_s0: pldo-reg4 { 579 regulator-name = "vcca_3v3_s0"; 580 regulator-always-on; 581 regulator-boot-on; 582 regulator-min-microvolt = <3300000>; 583 regulator-max-microvolt = <3300000>; 584 regulator-ramp-delay = <12500>; 585 586 regulator-state-mem { 587 regulator-off-in-suspend; 588 }; 589 }; 590 591 vccio_sd_s0: pldo-reg5 { 592 regulator-name = "vccio_sd_s0"; 593 regulator-always-on; 594 regulator-boot-on; 595 regulator-min-microvolt = <1800000>; 596 regulator-max-microvolt = <3300000>; 597 regulator-ramp-delay = <12500>; 598 599 regulator-state-mem { 600 regulator-off-in-suspend; 601 }; 602 }; 603 604 pldo6_s3: pldo-reg6 { 605 regulator-name = "pldo6_s3"; 606 regulator-always-on; 607 regulator-boot-on; 608 regulator-min-microvolt = <1800000>; 609 regulator-max-microvolt = <1800000>; 610 611 regulator-state-mem { 612 regulator-on-in-suspend; 613 regulator-suspend-microvolt = <1800000>; 614 }; 615 }; 616 617 vdd_0v75_s3: nldo-reg1 { 618 regulator-name = "vdd_0v75_s3"; 619 regulator-always-on; 620 regulator-boot-on; 621 regulator-min-microvolt = <750000>; 622 regulator-max-microvolt = <750000>; 623 624 regulator-state-mem { 625 regulator-on-in-suspend; 626 regulator-suspend-microvolt = <750000>; 627 }; 628 }; 629 630 vdda_ddr_pll_s0: nldo-reg2 { 631 regulator-name = "vdda_ddr_pll_s0"; 632 regulator-always-on; 633 regulator-boot-on; 634 regulator-min-microvolt = <850000>; 635 regulator-max-microvolt = <850000>; 636 637 regulator-state-mem { 638 regulator-off-in-suspend; 639 regulator-suspend-microvolt = <850000>; 640 }; 641 }; 642 643 vdda_0v75_s0: nldo-reg3 { 644 regulator-name = "vdda_0v75_s0"; 645 regulator-always-on; 646 regulator-boot-on; 647 regulator-min-microvolt = <750000>; 648 regulator-max-microvolt = <750000>; 649 650 regulator-state-mem { 651 regulator-off-in-suspend; 652 }; 653 }; 654 655 vdda_0v85_s0: nldo-reg4 { 656 regulator-name = "vdda_0v85_s0"; 657 regulator-always-on; 658 regulator-boot-on; 659 regulator-min-microvolt = <850000>; 660 regulator-max-microvolt = <850000>; 661 662 regulator-state-mem { 663 regulator-off-in-suspend; 664 }; 665 }; 666 667 vdd_0v75_s0: nldo-reg5 { 668 regulator-name = "vdd_0v75_s0"; 669 regulator-always-on; 670 regulator-boot-on; 671 regulator-min-microvolt = <750000>; 672 regulator-max-microvolt = <750000>; 673 674 regulator-state-mem { 675 regulator-off-in-suspend; 676 }; 677 }; 678 }; 679 }; 680}; 681 682&tsadc { 683 status = "okay"; 684}; 685 686/* Mule-ATtiny UPDI */ 687&uart4 { 688 pinctrl-0 = <&uart4m2_xfer>; 689 status = "okay"; 690}; 691