1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/leds/common.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include "rk3588.dtsi" 10 11/ { 12 compatible = "tsd,rk3588-tiger", "rockchip,rk3588"; 13 14 aliases { 15 mmc0 = &sdhci; 16 rtc0 = &rtc_twi; 17 }; 18 19 emmc_pwrseq: emmc-pwrseq { 20 compatible = "mmc-pwrseq-emmc"; 21 pinctrl-0 = <&emmc_reset>; 22 pinctrl-names = "default"; 23 reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; 24 }; 25 26 extcon_usb3: extcon-usb3 { 27 compatible = "linux,extcon-usb-gpio"; 28 id-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; 29 pinctrl-names = "default"; 30 pinctrl-0 = <&usb3_id>; 31 status = "disabled"; 32 }; 33 34 leds { 35 compatible = "gpio-leds"; 36 pinctrl-names = "default"; 37 pinctrl-0 = <&module_led_pin>; 38 39 /* Named LED1 on the board */ 40 led-1 { 41 gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; 42 function = LED_FUNCTION_HEARTBEAT; 43 linux,default-trigger = "heartbeat"; 44 color = <LED_COLOR_ID_AMBER>; 45 }; 46 }; 47 48 /* 49 * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE 50 * clock generator. 51 * The clock output is gated via the OE pin on the clock generator. 52 * This is modeled as a fixed-clock plus a gpio-gate-clock. 53 */ 54 pcie_refclk_gen: pcie-refclk-gen-clock { 55 compatible = "fixed-clock"; 56 #clock-cells = <0>; 57 clock-frequency = <100000000>; 58 }; 59 60 pcie_refclk: pcie-refclk-clock { 61 compatible = "gpio-gate-clock"; 62 clocks = <&pcie_refclk_gen>; 63 #clock-cells = <0>; 64 enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M1_L */ 65 }; 66 67 vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { 68 compatible = "regulator-fixed"; 69 regulator-name = "vcc_1v1_nldo_s3"; 70 regulator-always-on; 71 regulator-boot-on; 72 regulator-min-microvolt = <1100000>; 73 regulator-max-microvolt = <1100000>; 74 vin-supply = <&vcc5v0_sys>; 75 }; 76 77 vcc_1v2_s3: vcc-1v2-s3-regulator { 78 compatible = "regulator-fixed"; 79 regulator-name = "vcc_1v2_s3"; 80 regulator-always-on; 81 regulator-boot-on; 82 regulator-min-microvolt = <1200000>; 83 regulator-max-microvolt = <1200000>; 84 vin-supply = <&vcc5v0_sys>; 85 }; 86 87 vcc5v0_sys: vcc5v0-sys-regulator { 88 compatible = "regulator-fixed"; 89 regulator-name = "vcc5v0_sys"; 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <5000000>; 93 regulator-max-microvolt = <5000000>; 94 vin-supply = <&vcc5v0_baseboard>; 95 }; 96}; 97 98&cpu_b0 { 99 cpu-supply = <&vdd_cpu_big0_s0>; 100}; 101 102&cpu_b1 { 103 cpu-supply = <&vdd_cpu_big0_s0>; 104}; 105 106&cpu_b2 { 107 cpu-supply = <&vdd_cpu_big1_s0>; 108}; 109 110&cpu_b3 { 111 cpu-supply = <&vdd_cpu_big1_s0>; 112}; 113 114&cpu_l0 { 115 cpu-supply = <&vdd_cpu_lit_s0>; 116}; 117 118&cpu_l1 { 119 cpu-supply = <&vdd_cpu_lit_s0>; 120}; 121 122&cpu_l2 { 123 cpu-supply = <&vdd_cpu_lit_s0>; 124}; 125 126&cpu_l3 { 127 cpu-supply = <&vdd_cpu_lit_s0>; 128}; 129 130&gmac0 { 131 clock_in_out = "output"; 132 phy-handle = <&rgmii_phy>; 133 phy-mode = "rgmii"; 134 phy-supply = <&vcc_1v2_s3>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&gmac0_miim 137 &gmac0_rx_bus2 138 &gmac0_tx_bus2 139 &gmac0_rgmii_clk 140 &gmac0_rgmii_bus 141 ð0_pins 142 ð_reset>; 143 tx_delay = <0x10>; 144 rx_delay = <0x10>; 145 snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; 146 snps,reset-active-low; 147 snps,reset-delays-us = <0 10000 100000>; 148}; 149 150&gpu { 151 mali-supply = <&vdd_gpu_s0>; 152 status = "okay"; 153}; 154 155&i2c1 { 156 pinctrl-0 = <&i2c1m0_xfer>; 157}; 158 159&i2c1m0_xfer { 160 rockchip,pins = 161 /* i2c1_scl_m0 */ 162 <0 RK_PB5 9 &pcfg_pull_none_drv_level_0>, 163 /* i2c1_sda_m0 */ 164 <0 RK_PB6 9 &pcfg_pull_none_drv_level_0>; 165}; 166 167&i2c2 { 168 pinctrl-0 = <&i2c2m3_xfer>; 169 status = "okay"; 170}; 171 172&i2c2m3_xfer { 173 rockchip,pins = 174 /* i2c2_scl_m3 */ 175 <1 RK_PC5 9 &pcfg_pull_none_drv_level_0>, 176 /* i2c2_sda_m3 */ 177 <1 RK_PC4 9 &pcfg_pull_none_drv_level_0>; 178}; 179 180&i2c3 { 181 pinctrl-0 = <&i2c3m0_xfer>; 182}; 183 184&i2c4 { 185 pinctrl-0 = <&i2c4m4_xfer>; 186 status = "okay"; 187 188 vdd_npu_s0: regulator@42 { 189 compatible = "rockchip,rk8602"; 190 reg = <0x42>; 191 fcs,suspend-voltage-selector = <1>; 192 regulator-name = "vdd_npu_s0"; 193 regulator-always-on; 194 regulator-boot-on; 195 regulator-min-microvolt = <550000>; 196 regulator-max-microvolt = <950000>; 197 regulator-ramp-delay = <2300>; 198 vin-supply = <&vcc5v0_sys>; 199 200 regulator-state-mem { 201 regulator-off-in-suspend; 202 }; 203 }; 204}; 205 206&i2c5 { 207 pinctrl-0 = <&i2c5m1_xfer>; 208}; 209 210&i2c5m1_xfer { 211 rockchip,pins = 212 /* i2c5_scl_m1 */ 213 <4 RK_PB6 9 &pcfg_pull_none_drv_level_0>, 214 /* i2c5_sda_m1 */ 215 <4 RK_PB7 9 &pcfg_pull_none_drv_level_0>; 216}; 217 218&i2c6 { 219 /* 220 * Mule-ATtiny can handle up to Fast mode Plus (1MHz) on I2C bus, 221 * but SOC can handle only up to (400kHz). 222 */ 223 clock-frequency = <400000>; 224 status = "okay"; 225 226 fan@18 { 227 compatible = "ti,amc6821"; 228 reg = <0x18>; 229 }; 230 231 rtc_twi: rtc@6f { 232 compatible = "isil,isl1208"; 233 reg = <0x6f>; 234 }; 235}; 236 237&i2c6m0_xfer { 238 rockchip,pins = 239 /* i2c6_scl_m0 */ 240 <0 RK_PD0 9 &pcfg_pull_none_drv_level_0>, 241 /* i2c6_sda_m0 */ 242 <0 RK_PC7 9 &pcfg_pull_none_drv_level_0>; 243}; 244 245&i2c7 { 246 status = "okay"; 247 248 vdd_cpu_big0_s0: regulator@42 { 249 compatible = "rockchip,rk8602"; 250 reg = <0x42>; 251 fcs,suspend-voltage-selector = <1>; 252 regulator-name = "vdd_cpu_big0_s0"; 253 regulator-always-on; 254 regulator-boot-on; 255 regulator-min-microvolt = <550000>; 256 regulator-max-microvolt = <1050000>; 257 regulator-ramp-delay = <2300>; 258 vin-supply = <&vcc5v0_sys>; 259 260 regulator-state-mem { 261 regulator-off-in-suspend; 262 }; 263 }; 264 265 vdd_cpu_big1_s0: regulator@43 { 266 compatible = "rockchip,rk8603", "rockchip,rk8602"; 267 reg = <0x43>; 268 fcs,suspend-voltage-selector = <1>; 269 regulator-name = "vdd_cpu_big1_s0"; 270 regulator-always-on; 271 regulator-boot-on; 272 regulator-min-microvolt = <550000>; 273 regulator-max-microvolt = <1050000>; 274 regulator-ramp-delay = <2300>; 275 vin-supply = <&vcc5v0_sys>; 276 277 regulator-state-mem { 278 regulator-off-in-suspend; 279 }; 280 }; 281}; 282 283&i2c7m0_xfer { 284 rockchip,pins = 285 /* i2c7_scl_m0 */ 286 <1 RK_PD0 9 &pcfg_pull_none_drv_level_0>, 287 /* i2c7_sda_m0 */ 288 <1 RK_PD1 9 &pcfg_pull_none_drv_level_0>; 289}; 290 291&i2c8 { 292 pinctrl-0 = <&i2c8m2_xfer>; 293}; 294 295&mdio0 { 296 rgmii_phy: ethernet-phy@6 { 297 /* KSZ9031 or KSZ9131 */ 298 compatible = "ethernet-phy-ieee802.3-c22"; 299 reg = <0x6>; 300 clocks = <&cru REFCLKO25M_ETH0_OUT>; 301 }; 302}; 303 304&pcie3x4 { 305 /* 306 * The board has a gpio-controlled "pcie_refclk" generator, 307 * so add it to the list of clocks. 308 */ 309 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 310 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 311 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, 312 <&pcie_refclk>; 313 clock-names = "aclk_mst", "aclk_slv", 314 "aclk_dbi", "pclk", 315 "aux", "pipe", 316 "ref"; 317 reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; 318}; 319 320&pinctrl { 321 emmc { 322 emmc_reset: emmc-reset { 323 rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 324 }; 325 }; 326 327 ethernet { 328 eth_reset: eth-reset { 329 rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 330 }; 331 }; 332 333 leds { 334 module_led_pin: module-led-pin { 335 rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 336 }; 337 }; 338 339 usb3 { 340 usb3_id: usb3-id { 341 rockchip,pins = 342 <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; 343 }; 344 }; 345}; 346 347&saradc { 348 vref-supply = <&vcc_1v8_s0>; 349 status = "okay"; 350}; 351 352&sdhci { 353 bus-width = <8>; 354 cap-mmc-highspeed; 355 mmc-ddr-1_8v; 356 mmc-hs200-1_8v; 357 mmc-hs400-1_8v; 358 mmc-hs400-enhanced-strobe; 359 mmc-pwrseq = <&emmc_pwrseq>; 360 no-sdio; 361 no-sd; 362 non-removable; 363 pinctrl-names = "default"; 364 pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>; 365 supports-cqe; 366 vmmc-supply = <&vcc_3v3_s3>; 367 vqmmc-supply = <&vcc_1v8_s3>; 368 status = "okay"; 369}; 370 371&sdmmc { 372 bus-width = <4>; 373 cap-sd-highspeed; 374 max-frequency = <150000000>; 375 vqmmc-supply = <&vccio_sd_s0>; 376}; 377 378&spi0 { 379 pinctrl-0 = <&spi0m1_cs0 &spi0m1_cs1 &spi0m3_pins>; 380}; 381 382&spi2 { 383 assigned-clocks = <&cru CLK_SPI2>; 384 assigned-clock-rates = <200000000>; 385 num-cs = <1>; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; 388 status = "okay"; 389 390 pmic@0 { 391 compatible = "rockchip,rk806"; 392 reg = <0x0>; 393 interrupt-parent = <&gpio0>; 394 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 395 gpio-controller; 396 #gpio-cells = <2>; 397 pinctrl-names = "default"; 398 pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, 399 <&rk806_dvs2_null>, <&rk806_dvs3_null>; 400 spi-max-frequency = <1000000>; 401 system-power-controller; 402 vcc1-supply = <&vcc5v0_sys>; 403 vcc2-supply = <&vcc5v0_sys>; 404 vcc3-supply = <&vcc5v0_sys>; 405 vcc4-supply = <&vcc5v0_sys>; 406 vcc5-supply = <&vcc5v0_sys>; 407 vcc6-supply = <&vcc5v0_sys>; 408 vcc7-supply = <&vcc5v0_sys>; 409 vcc8-supply = <&vcc5v0_sys>; 410 vcc9-supply = <&vcc5v0_sys>; 411 vcc10-supply = <&vcc5v0_sys>; 412 vcc11-supply = <&vcc_2v0_pldo_s3>; 413 vcc12-supply = <&vcc5v0_sys>; 414 vcc13-supply = <&vcc_1v1_nldo_s3>; 415 vcc14-supply = <&vcc_1v1_nldo_s3>; 416 vcca-supply = <&vcc5v0_sys>; 417 418 rk806_dvs1_null: dvs1-null-pins { 419 pins = "gpio_pwrctrl1"; 420 function = "pin_fun0"; 421 }; 422 423 rk806_dvs2_null: dvs2-null-pins { 424 pins = "gpio_pwrctrl2"; 425 function = "pin_fun0"; 426 }; 427 428 rk806_dvs3_null: dvs3-null-pins { 429 pins = "gpio_pwrctrl3"; 430 function = "pin_fun0"; 431 }; 432 433 regulators { 434 vdd_gpu_s0: dcdc-reg1 { 435 regulator-boot-on; 436 regulator-min-microvolt = <550000>; 437 regulator-max-microvolt = <950000>; 438 regulator-ramp-delay = <12500>; 439 regulator-name = "vdd_gpu_s0"; 440 regulator-enable-ramp-delay = <400>; 441 442 regulator-state-mem { 443 regulator-off-in-suspend; 444 }; 445 }; 446 447 vdd_cpu_lit_s0: dcdc-reg2 { 448 regulator-name = "vdd_cpu_lit_s0"; 449 regulator-always-on; 450 regulator-boot-on; 451 regulator-min-microvolt = <550000>; 452 regulator-max-microvolt = <950000>; 453 regulator-ramp-delay = <12500>; 454 455 regulator-state-mem { 456 regulator-off-in-suspend; 457 }; 458 }; 459 460 vdd_log_s0: dcdc-reg3 { 461 regulator-name = "vdd_log_s0"; 462 regulator-always-on; 463 regulator-boot-on; 464 regulator-min-microvolt = <675000>; 465 regulator-max-microvolt = <750000>; 466 regulator-ramp-delay = <12500>; 467 468 regulator-state-mem { 469 regulator-off-in-suspend; 470 regulator-suspend-microvolt = <750000>; 471 }; 472 }; 473 474 vdd_vdenc_s0: dcdc-reg4 { 475 regulator-name = "vdd_vdenc_s0"; 476 regulator-always-on; 477 regulator-boot-on; 478 regulator-min-microvolt = <550000>; 479 regulator-max-microvolt = <950000>; 480 regulator-ramp-delay = <12500>; 481 482 regulator-state-mem { 483 regulator-off-in-suspend; 484 }; 485 }; 486 487 vdd_ddr_s0: dcdc-reg5 { 488 regulator-name = "vdd_ddr_s0"; 489 regulator-always-on; 490 regulator-boot-on; 491 regulator-min-microvolt = <675000>; 492 regulator-max-microvolt = <900000>; 493 regulator-ramp-delay = <12500>; 494 495 regulator-state-mem { 496 regulator-off-in-suspend; 497 regulator-suspend-microvolt = <850000>; 498 }; 499 }; 500 501 vdd2_ddr_s3: dcdc-reg6 { 502 regulator-name = "vdd2_ddr_s3"; 503 regulator-always-on; 504 regulator-boot-on; 505 506 regulator-state-mem { 507 regulator-on-in-suspend; 508 }; 509 }; 510 511 vcc_2v0_pldo_s3: dcdc-reg7 { 512 regulator-name = "vcc_2v0_pldo_s3"; 513 regulator-always-on; 514 regulator-boot-on; 515 regulator-min-microvolt = <2000000>; 516 regulator-max-microvolt = <2000000>; 517 regulator-ramp-delay = <12500>; 518 519 regulator-state-mem { 520 regulator-on-in-suspend; 521 regulator-suspend-microvolt = <2000000>; 522 }; 523 }; 524 525 vcc_3v3_s3: dcdc-reg8 { 526 regulator-name = "vcc_3v3_s3"; 527 regulator-always-on; 528 regulator-boot-on; 529 regulator-min-microvolt = <3300000>; 530 regulator-max-microvolt = <3300000>; 531 532 regulator-state-mem { 533 regulator-on-in-suspend; 534 regulator-suspend-microvolt = <3300000>; 535 }; 536 }; 537 538 vddq_ddr_s0: dcdc-reg9 { 539 regulator-name = "vddq_ddr_s0"; 540 regulator-always-on; 541 regulator-boot-on; 542 543 regulator-state-mem { 544 regulator-off-in-suspend; 545 }; 546 }; 547 548 vcc_1v8_s3: dcdc-reg10 { 549 regulator-name = "vcc_1v8_s3"; 550 regulator-always-on; 551 regulator-boot-on; 552 regulator-min-microvolt = <1800000>; 553 regulator-max-microvolt = <1800000>; 554 555 regulator-state-mem { 556 regulator-on-in-suspend; 557 regulator-suspend-microvolt = <1800000>; 558 }; 559 }; 560 561 vcca_1v8_s0: pldo-reg1 { 562 regulator-name = "vcca_1v8_s0"; 563 regulator-always-on; 564 regulator-boot-on; 565 regulator-min-microvolt = <1800000>; 566 regulator-max-microvolt = <1800000>; 567 568 regulator-state-mem { 569 regulator-off-in-suspend; 570 }; 571 }; 572 573 vcc_1v8_s0: pldo-reg2 { 574 regulator-name = "vcc_1v8_s0"; 575 regulator-always-on; 576 regulator-boot-on; 577 regulator-min-microvolt = <1800000>; 578 regulator-max-microvolt = <1800000>; 579 580 regulator-state-mem { 581 regulator-off-in-suspend; 582 regulator-suspend-microvolt = <1800000>; 583 }; 584 }; 585 586 vdda_1v2_s0: pldo-reg3 { 587 regulator-name = "vdda_1v2_s0"; 588 regulator-always-on; 589 regulator-boot-on; 590 regulator-min-microvolt = <1200000>; 591 regulator-max-microvolt = <1200000>; 592 593 regulator-state-mem { 594 regulator-off-in-suspend; 595 }; 596 }; 597 598 vcca_3v3_s0: pldo-reg4 { 599 regulator-name = "vcca_3v3_s0"; 600 regulator-always-on; 601 regulator-boot-on; 602 regulator-min-microvolt = <3300000>; 603 regulator-max-microvolt = <3300000>; 604 regulator-ramp-delay = <12500>; 605 606 regulator-state-mem { 607 regulator-off-in-suspend; 608 }; 609 }; 610 611 vccio_sd_s0: pldo-reg5 { 612 regulator-name = "vccio_sd_s0"; 613 regulator-always-on; 614 regulator-boot-on; 615 regulator-min-microvolt = <1800000>; 616 regulator-max-microvolt = <3300000>; 617 regulator-ramp-delay = <12500>; 618 619 regulator-state-mem { 620 regulator-off-in-suspend; 621 }; 622 }; 623 624 pldo6_s3: pldo-reg6 { 625 regulator-name = "pldo6_s3"; 626 regulator-always-on; 627 regulator-boot-on; 628 regulator-min-microvolt = <1800000>; 629 regulator-max-microvolt = <1800000>; 630 631 regulator-state-mem { 632 regulator-on-in-suspend; 633 regulator-suspend-microvolt = <1800000>; 634 }; 635 }; 636 637 vdd_0v75_s3: nldo-reg1 { 638 regulator-name = "vdd_0v75_s3"; 639 regulator-always-on; 640 regulator-boot-on; 641 regulator-min-microvolt = <750000>; 642 regulator-max-microvolt = <750000>; 643 644 regulator-state-mem { 645 regulator-on-in-suspend; 646 regulator-suspend-microvolt = <750000>; 647 }; 648 }; 649 650 vdda_ddr_pll_s0: nldo-reg2 { 651 regulator-name = "vdda_ddr_pll_s0"; 652 regulator-always-on; 653 regulator-boot-on; 654 regulator-min-microvolt = <850000>; 655 regulator-max-microvolt = <850000>; 656 657 regulator-state-mem { 658 regulator-off-in-suspend; 659 regulator-suspend-microvolt = <850000>; 660 }; 661 }; 662 663 vdda_0v75_s0: nldo-reg3 { 664 regulator-name = "vdda_0v75_s0"; 665 regulator-always-on; 666 regulator-boot-on; 667 regulator-min-microvolt = <750000>; 668 regulator-max-microvolt = <750000>; 669 670 regulator-state-mem { 671 regulator-off-in-suspend; 672 }; 673 }; 674 675 vdda_0v85_s0: nldo-reg4 { 676 regulator-name = "vdda_0v85_s0"; 677 regulator-always-on; 678 regulator-boot-on; 679 regulator-min-microvolt = <850000>; 680 regulator-max-microvolt = <850000>; 681 682 regulator-state-mem { 683 regulator-off-in-suspend; 684 }; 685 }; 686 687 vdd_0v75_s0: nldo-reg5 { 688 regulator-name = "vdd_0v75_s0"; 689 regulator-always-on; 690 regulator-boot-on; 691 regulator-min-microvolt = <750000>; 692 regulator-max-microvolt = <750000>; 693 694 regulator-state-mem { 695 regulator-off-in-suspend; 696 }; 697 }; 698 }; 699 }; 700}; 701 702&tsadc { 703 status = "okay"; 704}; 705 706/* Routed to UART0 on the Q7 connector */ 707&uart2 { 708 pinctrl-0 = <&uart2m2_xfer>; 709}; 710 711/* Mule-ATtiny UPDI */ 712&uart4 { 713 pinctrl-0 = <&uart4m2_xfer>; 714 status = "okay"; 715}; 716