1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include "rk3588-base.dtsi" 7#include "rk3588-extra-pinctrl.dtsi" 8 9/ { 10 hdmi1_sound: hdmi1-sound { 11 compatible = "simple-audio-card"; 12 simple-audio-card,format = "i2s"; 13 simple-audio-card,mclk-fs = <128>; 14 simple-audio-card,name = "hdmi1"; 15 status = "disabled"; 16 17 simple-audio-card,codec { 18 sound-dai = <&hdmi1>; 19 }; 20 21 simple-audio-card,cpu { 22 sound-dai = <&i2s6_8ch>; 23 }; 24 }; 25 26 reserved-memory { 27 #address-cells = <2>; 28 #size-cells = <2>; 29 ranges; 30 31 /* 32 * The 4k HDMI capture controller works only with 32bit 33 * phys addresses and doesn't support IOMMU. HDMI RX CMA 34 * must be reserved below 4GB. 35 * The size of 160MB was determined as follows: 36 * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB 37 * To ensure sufficient support for practical use-cases, 38 * we doubled the 66MB value. 39 */ 40 hdmi_receiver_cma: hdmi-receiver-cma { 41 compatible = "shared-dma-pool"; 42 alloc-ranges = <0x0 0x0 0x0 0xffffffff>; 43 size = <0x0 (160 * 0x100000)>; /* 160MiB */ 44 alignment = <0x0 0x40000>; /* 64K */ 45 no-map; 46 status = "disabled"; 47 }; 48 }; 49 50 usb_host1_xhci: usb@fc400000 { 51 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 52 reg = <0x0 0xfc400000 0x0 0x400000>; 53 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; 54 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, 55 <&cru ACLK_USB3OTG1>; 56 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 57 dr_mode = "otg"; 58 phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; 59 phy-names = "usb2-phy", "usb3-phy"; 60 phy_type = "utmi_wide"; 61 power-domains = <&power RK3588_PD_USB>; 62 resets = <&cru SRST_A_USB3OTG1>; 63 snps,dis_enblslpm_quirk; 64 snps,dis-u2-freeclk-exists-quirk; 65 snps,dis-del-phy-power-chg-quirk; 66 snps,dis-tx-ipgap-linecheck-quirk; 67 status = "disabled"; 68 }; 69 70 pcie30_phy_grf: syscon@fd5b8000 { 71 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; 72 reg = <0x0 0xfd5b8000 0x0 0x10000>; 73 }; 74 75 pipe_phy1_grf: syscon@fd5c0000 { 76 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 77 reg = <0x0 0xfd5c0000 0x0 0x100>; 78 }; 79 80 usbdpphy1_grf: syscon@fd5cc000 { 81 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 82 reg = <0x0 0xfd5cc000 0x0 0x4000>; 83 }; 84 85 usb2phy1_grf: syscon@fd5d4000 { 86 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 87 reg = <0x0 0xfd5d4000 0x0 0x4000>; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 91 u2phy1: usb2phy@4000 { 92 compatible = "rockchip,rk3588-usb2phy"; 93 reg = <0x4000 0x10>; 94 #clock-cells = <0>; 95 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 96 clock-names = "phyclk"; 97 clock-output-names = "usb480m_phy1"; 98 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>; 99 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; 100 reset-names = "phy", "apb"; 101 status = "disabled"; 102 103 u2phy1_otg: otg-port { 104 #phy-cells = <0>; 105 status = "disabled"; 106 }; 107 }; 108 }; 109 110 hdptxphy1_grf: syscon@fd5e4000 { 111 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 112 reg = <0x0 0xfd5e4000 0x0 0x100>; 113 }; 114 115 spdif_tx5: spdif-tx@fddb8000 { 116 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 117 reg = <0x0 0xfddb8000 0x0 0x1000>; 118 assigned-clock-parents = <&cru PLL_AUPLL>; 119 assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>; 120 clock-names = "mclk", "hclk"; 121 clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>; 122 dma-names = "tx"; 123 dmas = <&dmac1 22>; 124 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 125 power-domains = <&power RK3588_PD_VO0>; 126 #sound-dai-cells = <0>; 127 status = "disabled"; 128 }; 129 130 i2s8_8ch: i2s@fddc8000 { 131 compatible = "rockchip,rk3588-i2s-tdm"; 132 reg = <0x0 0xfddc8000 0x0 0x1000>; 133 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>; 134 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; 135 clock-names = "mclk_tx", "mclk_rx", "hclk"; 136 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; 137 assigned-clock-parents = <&cru PLL_AUPLL>; 138 dmas = <&dmac2 22>; 139 dma-names = "tx"; 140 power-domains = <&power RK3588_PD_VO0>; 141 resets = <&cru SRST_M_I2S8_8CH_TX>; 142 reset-names = "tx-m"; 143 #sound-dai-cells = <0>; 144 status = "disabled"; 145 }; 146 147 spdif_tx4: spdif-tx@fdde8000 { 148 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 149 reg = <0x0 0xfdde8000 0x0 0x1000>; 150 assigned-clock-parents = <&cru PLL_AUPLL>; 151 assigned-clocks = <&cru CLK_SPDIF4_SRC>; 152 clock-names = "mclk", "hclk"; 153 clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; 154 dma-names = "tx"; 155 dmas = <&dmac1 8>; 156 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 157 power-domains = <&power RK3588_PD_VO1>; 158 #sound-dai-cells = <0>; 159 status = "disabled"; 160 }; 161 162 i2s6_8ch: i2s@fddf4000 { 163 compatible = "rockchip,rk3588-i2s-tdm"; 164 reg = <0x0 0xfddf4000 0x0 0x1000>; 165 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 166 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; 167 clock-names = "mclk_tx", "mclk_rx", "hclk"; 168 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; 169 assigned-clock-parents = <&cru PLL_AUPLL>; 170 dmas = <&dmac2 4>; 171 dma-names = "tx"; 172 power-domains = <&power RK3588_PD_VO1>; 173 resets = <&cru SRST_M_I2S6_8CH_TX>; 174 reset-names = "tx-m"; 175 #sound-dai-cells = <0>; 176 status = "disabled"; 177 }; 178 179 i2s7_8ch: i2s@fddf8000 { 180 compatible = "rockchip,rk3588-i2s-tdm"; 181 reg = <0x0 0xfddf8000 0x0 0x1000>; 182 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>; 183 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; 184 clock-names = "mclk_tx", "mclk_rx", "hclk"; 185 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; 186 assigned-clock-parents = <&cru PLL_AUPLL>; 187 dmas = <&dmac2 21>; 188 dma-names = "rx"; 189 power-domains = <&power RK3588_PD_VO1>; 190 resets = <&cru SRST_M_I2S7_8CH_RX>; 191 reset-names = "rx-m"; 192 #sound-dai-cells = <0>; 193 status = "disabled"; 194 }; 195 196 i2s10_8ch: i2s@fde00000 { 197 compatible = "rockchip,rk3588-i2s-tdm"; 198 reg = <0x0 0xfde00000 0x0 0x1000>; 199 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>; 200 clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; 201 clock-names = "mclk_tx", "mclk_rx", "hclk"; 202 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; 203 assigned-clock-parents = <&cru PLL_AUPLL>; 204 dmas = <&dmac2 24>; 205 dma-names = "rx"; 206 power-domains = <&power RK3588_PD_VO1>; 207 resets = <&cru SRST_M_I2S10_8CH_RX>; 208 reset-names = "rx-m"; 209 #sound-dai-cells = <0>; 210 status = "disabled"; 211 }; 212 213 hdmi1: hdmi@fdea0000 { 214 compatible = "rockchip,rk3588-dw-hdmi-qp"; 215 reg = <0x0 0xfdea0000 0x0 0x20000>; 216 clocks = <&cru PCLK_HDMITX1>, 217 <&cru CLK_HDMITX1_EARC>, 218 <&cru CLK_HDMITX1_REF>, 219 <&cru MCLK_I2S6_8CH_TX>, 220 <&cru CLK_HDMIHDP1>, 221 <&cru HCLK_VO1>; 222 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; 223 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>, 224 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>, 225 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>, 226 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>, 227 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; 228 interrupt-names = "avp", "cec", "earc", "main", "hpd"; 229 phys = <&hdptxphy1>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd 232 &hdmim1_tx1_scl &hdmim1_tx1_sda>; 233 power-domains = <&power RK3588_PD_VO1>; 234 resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; 235 reset-names = "ref", "hdp"; 236 rockchip,grf = <&sys_grf>; 237 rockchip,vo-grf = <&vo1_grf>; 238 #sound-dai-cells = <0>; 239 status = "disabled"; 240 241 ports { 242 #address-cells = <1>; 243 #size-cells = <0>; 244 245 hdmi1_in: port@0 { 246 reg = <0>; 247 }; 248 249 hdmi1_out: port@1 { 250 reg = <1>; 251 }; 252 }; 253 }; 254 255 hdmi_receiver: hdmi_receiver@fdee0000 { 256 compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; 257 reg = <0x0 0xfdee0000 0x0 0x6000>; 258 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>, 259 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>, 260 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>; 261 interrupt-names = "cec", "hdmi", "dma"; 262 clocks = <&cru ACLK_HDMIRX>, 263 <&cru CLK_HDMIRX_AUD>, 264 <&cru CLK_CR_PARA>, 265 <&cru PCLK_HDMIRX>, 266 <&cru CLK_HDMIRX_REF>, 267 <&cru PCLK_S_HDMIRX>, 268 <&cru HCLK_VO1>; 269 clock-names = "aclk", 270 "audio", 271 "cr_para", 272 "pclk", 273 "ref", 274 "hclk_s_hdmirx", 275 "hclk_vo1"; 276 memory-region = <&hdmi_receiver_cma>; 277 power-domains = <&power RK3588_PD_VO1>; 278 resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, 279 <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; 280 reset-names = "axi", "apb", "ref", "biu"; 281 rockchip,grf = <&sys_grf>; 282 rockchip,vo1-grf = <&vo1_grf>; 283 status = "disabled"; 284 }; 285 286 pcie3x4: pcie@fe150000 { 287 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 288 #address-cells = <3>; 289 #size-cells = <2>; 290 bus-range = <0x00 0x0f>; 291 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 292 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 293 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; 294 clock-names = "aclk_mst", "aclk_slv", 295 "aclk_dbi", "pclk", 296 "aux", "pipe"; 297 device_type = "pci"; 298 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, 299 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, 300 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, 301 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, 302 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 303 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 304 #interrupt-cells = <1>; 305 interrupt-map-mask = <0 0 0 7>; 306 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, 307 <0 0 0 2 &pcie3x4_intc 1>, 308 <0 0 0 3 &pcie3x4_intc 2>, 309 <0 0 0 4 &pcie3x4_intc 3>; 310 linux,pci-domain = <0>; 311 max-link-speed = <3>; 312 msi-map = <0x0000 &its1 0x0000 0x1000>; 313 iommu-map = <0x0000 &mmu600_pcie 0x0000 0x1000>; 314 num-lanes = <4>; 315 phys = <&pcie30phy>; 316 phy-names = "pcie-phy"; 317 power-domains = <&power RK3588_PD_PCIE>; 318 ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, 319 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, 320 <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; 321 reg = <0xa 0x40000000 0x0 0x00400000>, 322 <0x0 0xfe150000 0x0 0x00010000>, 323 <0x0 0xf0000000 0x0 0x00100000>; 324 reg-names = "dbi", "apb", "config"; 325 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; 326 reset-names = "pwr", "pipe"; 327 status = "disabled"; 328 329 pcie3x4_intc: legacy-interrupt-controller { 330 interrupt-controller; 331 #address-cells = <0>; 332 #interrupt-cells = <1>; 333 interrupt-parent = <&gic>; 334 interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; 335 }; 336 }; 337 338 pcie3x4_ep: pcie-ep@fe150000 { 339 compatible = "rockchip,rk3588-pcie-ep"; 340 reg = <0xa 0x40000000 0x0 0x00100000>, 341 <0xa 0x40100000 0x0 0x00100000>, 342 <0x0 0xfe150000 0x0 0x00010000>, 343 <0x9 0x00000000 0x0 0x40000000>, 344 <0xa 0x40300000 0x0 0x00100000>; 345 reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; 346 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 347 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 348 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; 349 clock-names = "aclk_mst", "aclk_slv", 350 "aclk_dbi", "pclk", 351 "aux", "pipe"; 352 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, 353 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, 354 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, 355 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, 356 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>, 357 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>, 358 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>, 359 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>, 360 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 361 interrupt-names = "sys", "pmc", "msg", "legacy", "err", 362 "dma0", "dma1", "dma2", "dma3"; 363 max-link-speed = <3>; 364 num-lanes = <4>; 365 phys = <&pcie30phy>; 366 phy-names = "pcie-phy"; 367 power-domains = <&power RK3588_PD_PCIE>; 368 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; 369 reset-names = "pwr", "pipe"; 370 status = "disabled"; 371 }; 372 373 pcie3x2: pcie@fe160000 { 374 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 375 #address-cells = <3>; 376 #size-cells = <2>; 377 bus-range = <0x10 0x1f>; 378 clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, 379 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, 380 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; 381 clock-names = "aclk_mst", "aclk_slv", 382 "aclk_dbi", "pclk", 383 "aux", "pipe"; 384 device_type = "pci"; 385 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, 386 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, 387 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, 388 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, 389 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 390 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 391 #interrupt-cells = <1>; 392 interrupt-map-mask = <0 0 0 7>; 393 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, 394 <0 0 0 2 &pcie3x2_intc 1>, 395 <0 0 0 3 &pcie3x2_intc 2>, 396 <0 0 0 4 &pcie3x2_intc 3>; 397 linux,pci-domain = <1>; 398 max-link-speed = <3>; 399 msi-map = <0x1000 &its1 0x1000 0x1000>; 400 iommu-map = <0x1000 &mmu600_pcie 0x1000 0x1000>; 401 num-lanes = <2>; 402 phys = <&pcie30phy>; 403 phy-names = "pcie-phy"; 404 power-domains = <&power RK3588_PD_PCIE>; 405 ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, 406 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, 407 <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; 408 reg = <0xa 0x40400000 0x0 0x00400000>, 409 <0x0 0xfe160000 0x0 0x00010000>, 410 <0x0 0xf1000000 0x0 0x00100000>; 411 reg-names = "dbi", "apb", "config"; 412 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; 413 reset-names = "pwr", "pipe"; 414 status = "disabled"; 415 416 pcie3x2_intc: legacy-interrupt-controller { 417 interrupt-controller; 418 #address-cells = <0>; 419 #interrupt-cells = <1>; 420 interrupt-parent = <&gic>; 421 interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; 422 }; 423 }; 424 425 pcie2x1l0: pcie@fe170000 { 426 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 427 bus-range = <0x20 0x2f>; 428 clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, 429 <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, 430 <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; 431 clock-names = "aclk_mst", "aclk_slv", 432 "aclk_dbi", "pclk", 433 "aux", "pipe"; 434 device_type = "pci"; 435 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, 436 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, 437 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, 438 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, 439 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; 440 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 441 #interrupt-cells = <1>; 442 interrupt-map-mask = <0 0 0 7>; 443 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, 444 <0 0 0 2 &pcie2x1l0_intc 1>, 445 <0 0 0 3 &pcie2x1l0_intc 2>, 446 <0 0 0 4 &pcie2x1l0_intc 3>; 447 linux,pci-domain = <2>; 448 max-link-speed = <2>; 449 msi-map = <0x2000 &its0 0x2000 0x1000>; 450 iommu-map = <0x2000 &mmu600_pcie 0x2000 0x1000>; 451 num-lanes = <1>; 452 phys = <&combphy1_ps PHY_TYPE_PCIE>; 453 phy-names = "pcie-phy"; 454 power-domains = <&power RK3588_PD_PCIE>; 455 ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, 456 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, 457 <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; 458 reg = <0xa 0x40800000 0x0 0x00400000>, 459 <0x0 0xfe170000 0x0 0x00010000>, 460 <0x0 0xf2000000 0x0 0x00100000>; 461 reg-names = "dbi", "apb", "config"; 462 resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; 463 reset-names = "pwr", "pipe"; 464 #address-cells = <3>; 465 #size-cells = <2>; 466 status = "disabled"; 467 468 pcie2x1l0_intc: legacy-interrupt-controller { 469 interrupt-controller; 470 #address-cells = <0>; 471 #interrupt-cells = <1>; 472 interrupt-parent = <&gic>; 473 interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; 474 }; 475 }; 476 477 gmac0: ethernet@fe1b0000 { 478 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 479 reg = <0x0 0xfe1b0000 0x0 0x10000>; 480 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>, 481 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 482 interrupt-names = "macirq", "eth_wake_irq"; 483 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 484 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 485 <&cru CLK_GMAC0_PTP_REF>; 486 clock-names = "stmmaceth", "clk_mac_ref", 487 "pclk_mac", "aclk_mac", 488 "ptp_ref"; 489 power-domains = <&power RK3588_PD_GMAC>; 490 resets = <&cru SRST_A_GMAC0>; 491 reset-names = "stmmaceth"; 492 rockchip,grf = <&sys_grf>; 493 rockchip,php-grf = <&php_grf>; 494 snps,axi-config = <&gmac0_stmmac_axi_setup>; 495 snps,mixed-burst; 496 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 497 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 498 snps,tso; 499 status = "disabled"; 500 501 mdio0: mdio { 502 compatible = "snps,dwmac-mdio"; 503 #address-cells = <0x1>; 504 #size-cells = <0x0>; 505 }; 506 507 gmac0_stmmac_axi_setup: stmmac-axi-config { 508 snps,blen = <0 0 0 0 16 8 4>; 509 snps,wr_osr_lmt = <4>; 510 snps,rd_osr_lmt = <8>; 511 }; 512 513 gmac0_mtl_rx_setup: rx-queues-config { 514 snps,rx-queues-to-use = <2>; 515 queue0 {}; 516 queue1 {}; 517 }; 518 519 gmac0_mtl_tx_setup: tx-queues-config { 520 snps,tx-queues-to-use = <2>; 521 queue0 {}; 522 queue1 {}; 523 }; 524 }; 525 526 sata1: sata@fe220000 { 527 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 528 reg = <0 0xfe220000 0 0x1000>; 529 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 530 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, 531 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, 532 <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; 533 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 534 ports-implemented = <0x1>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 status = "disabled"; 538 539 sata-port@0 { 540 reg = <0>; 541 hba-port-cap = <HBA_PORT_FBSCP>; 542 phys = <&combphy1_ps PHY_TYPE_SATA>; 543 phy-names = "sata-phy"; 544 snps,rx-ts-max = <32>; 545 snps,tx-ts-max = <32>; 546 }; 547 }; 548 549 hdptxphy1: phy@fed70000 { 550 compatible = "rockchip,rk3588-hdptx-phy"; 551 reg = <0x0 0xfed70000 0x0 0x2000>; 552 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; 553 clock-names = "ref", "apb"; 554 #clock-cells = <0>; 555 #phy-cells = <0>; 556 resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, 557 <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, 558 <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, 559 <&cru SRST_HDPTX1_LCPLL>; 560 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 561 "lcpll"; 562 rockchip,grf = <&hdptxphy1_grf>; 563 status = "disabled"; 564 }; 565 566 usbdp_phy1: phy@fed90000 { 567 compatible = "rockchip,rk3588-usbdp-phy"; 568 reg = <0x0 0xfed90000 0x0 0x10000>; 569 #phy-cells = <1>; 570 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 571 <&cru CLK_USBDP_PHY1_IMMORTAL>, 572 <&cru PCLK_USBDPPHY1>, 573 <&u2phy1>; 574 clock-names = "refclk", "immortal", "pclk", "utmi"; 575 resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, 576 <&cru SRST_USBDP_COMBO_PHY1_CMN>, 577 <&cru SRST_USBDP_COMBO_PHY1_LANE>, 578 <&cru SRST_USBDP_COMBO_PHY1_PCS>, 579 <&cru SRST_P_USBDPPHY1>; 580 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 581 rockchip,u2phy-grf = <&usb2phy1_grf>; 582 rockchip,usb-grf = <&usb_grf>; 583 rockchip,usbdpphy-grf = <&usbdpphy1_grf>; 584 rockchip,vo-grf = <&vo0_grf>; 585 status = "disabled"; 586 }; 587 588 combphy1_ps: phy@fee10000 { 589 compatible = "rockchip,rk3588-naneng-combphy"; 590 reg = <0x0 0xfee10000 0x0 0x100>; 591 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, 592 <&cru PCLK_PHP_ROOT>; 593 clock-names = "ref", "apb", "pipe"; 594 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; 595 assigned-clock-rates = <100000000>; 596 #phy-cells = <1>; 597 resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; 598 reset-names = "phy", "apb"; 599 rockchip,pipe-grf = <&php_grf>; 600 rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 601 status = "disabled"; 602 }; 603 604 pcie30phy: phy@fee80000 { 605 compatible = "rockchip,rk3588-pcie3-phy"; 606 reg = <0x0 0xfee80000 0x0 0x20000>; 607 #phy-cells = <0>; 608 clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; 609 clock-names = "pclk"; 610 resets = <&cru SRST_PCIE30_PHY>; 611 reset-names = "phy"; 612 rockchip,pipe-grf = <&php_grf>; 613 rockchip,phy-grf = <&pcie30_phy_grf>; 614 status = "disabled"; 615 }; 616}; 617 618&vop { 619 clocks = <&cru ACLK_VOP>, 620 <&cru HCLK_VOP>, 621 <&cru DCLK_VOP0>, 622 <&cru DCLK_VOP1>, 623 <&cru DCLK_VOP2>, 624 <&cru DCLK_VOP3>, 625 <&cru PCLK_VOP_ROOT>, 626 <&hdptxphy0>, 627 <&hdptxphy1>; 628 clock-names = "aclk", 629 "hclk", 630 "dclk_vp0", 631 "dclk_vp1", 632 "dclk_vp2", 633 "dclk_vp3", 634 "pclk_vop", 635 "pll_hdmiphy0", 636 "pll_hdmiphy1"; 637}; 638