xref: /linux/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi (revision d53b8e36925256097a08d7cb749198d85cbf9b2b)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7
8/ {
9	chosen {
10		stdout-path = "serial2:1500000n8";
11	};
12
13	vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
14		compatible = "regulator-fixed";
15		regulator-name = "vcc3v3_pcie2x1l0";
16		regulator-min-microvolt = <3300000>;
17		regulator-max-microvolt = <3300000>;
18		startup-delay-us = <5000>;
19		vin-supply = <&vcc_3v3_s3>;
20	};
21
22	vcc3v3_pcie3x2: vcc3v3-pcie3x2-regulator {
23		compatible = "regulator-fixed";
24		enable-active-high;
25		gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; /* PCIE_4G_PWEN */
26		pinctrl-names = "default";
27		pinctrl-0 = <&pcie3x2_vcc3v3_en>;
28		regulator-name = "vcc3v3_pcie3x2";
29		regulator-min-microvolt = <3300000>;
30		regulator-max-microvolt = <3300000>;
31		startup-delay-us = <5000>;
32		vin-supply = <&vcc5v0_sys>;
33	};
34
35	vcc3v3_pcie3x4: vcc3v3-pcie3x4-regulator {
36		compatible = "regulator-fixed";
37		enable-active-high;
38		gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; /* PCIE30x4_PWREN_H */
39		pinctrl-names = "default";
40		pinctrl-0 = <&pcie3x4_vcc3v3_en>;
41		regulator-name = "vcc3v3_pcie3x4";
42		regulator-min-microvolt = <3300000>;
43		regulator-max-microvolt = <3300000>;
44		startup-delay-us = <5000>;
45		vin-supply = <&vcc5v0_sys>;
46	};
47
48	vcc5v0_host: vcc5v0-host-regulator {
49		compatible = "regulator-fixed";
50		enable-active-high;
51		gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>;
52		pinctrl-names = "default";
53		pinctrl-0 = <&vcc5v0_host_en>;
54		regulator-name = "vcc5v0_host";
55		regulator-min-microvolt = <5000000>;
56		regulator-max-microvolt = <5000000>;
57		regulator-boot-on;
58		regulator-always-on;
59		vin-supply = <&vcc5v0_sys>;
60	};
61};
62
63&combphy0_ps {
64	status = "okay";
65};
66
67&combphy1_ps {
68	status = "okay";
69};
70
71&combphy2_psu {
72	status = "okay";
73};
74
75&i2c6 {
76	status = "okay";
77
78	hym8563: rtc@51 {
79		compatible = "haoyu,hym8563";
80		reg = <0x51>;
81		interrupt-parent = <&gpio0>;
82		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
83		#clock-cells = <0>;
84		clock-output-names = "hym8563";
85		pinctrl-names = "default";
86		pinctrl-0 = <&hym8563_int>;
87		wakeup-source;
88	};
89};
90
91/* ETH */
92&pcie2x1l0 {
93	pinctrl-names = "default";
94	pinctrl-0 = <&pcie2_0_rst>;
95	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; /* PCIE20_1_PERST_L */
96	vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
97	status = "okay";
98};
99
100&pcie30phy {
101	status = "okay";
102};
103
104/* B-Key and E-Key */
105&pcie3x2 {
106	pinctrl-names = "default";
107	pinctrl-0 = <&pcie3x2_rst>;
108	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */
109	vpcie3v3-supply = <&vcc3v3_pcie3x2>;
110	status = "okay";
111};
112
113/* M-Key */
114&pcie3x4 {
115	pinctrl-names = "default";
116	pinctrl-0 = <&pcie3x4_rst>;
117	reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */
118	vpcie3v3-supply = <&vcc3v3_pcie3x4>;
119	status = "okay";
120};
121
122&pinctrl {
123	pcie2 {
124		pcie2_0_rst: pcie2-0-rst {
125			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
126		};
127	};
128
129	pcie3 {
130		pcie3x2_rst: pcie3x2-rst {
131			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
132		};
133
134		pcie3x2_vcc3v3_en: pcie3x2-vcc3v3-en {
135			rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
136		};
137
138		pcie3x4_rst: pcie3x4-rst {
139			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
140		};
141
142		pcie3x4_vcc3v3_en: pcie3x4-vcc3v3-en {
143			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
144		};
145	};
146
147	hym8563 {
148		hym8563_int: hym8563-int {
149			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
150		};
151	};
152
153	usb {
154		vcc5v0_host_en: vcc5v0-host-en {
155			rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
156		};
157	};
158};
159
160/* FAN */
161&pwm2 {
162	pinctrl-0 = <&pwm2m1_pins>;
163	pinctrl-names = "default";
164	status = "okay";
165};
166
167&sata0 {
168	status = "okay";
169};
170
171&sdmmc {
172	bus-width = <4>;
173	cap-mmc-highspeed;
174	cap-sd-highspeed;
175	disable-wp;
176	no-sdio;
177	no-mmc;
178	sd-uhs-sdr104;
179	vmmc-supply = <&vcc_3v3_s3>;
180	vqmmc-supply = <&vccio_sd_s0>;
181	status = "okay";
182};
183
184&uart2 {
185	pinctrl-0 = <&uart2m0_xfer>;
186	status = "okay";
187};
188
189/* RS232 */
190&uart6 {
191	pinctrl-0 = <&uart6m0_xfer>;
192	pinctrl-names = "default";
193	status = "okay";
194};
195
196/* RS485 */
197&uart7 {
198	pinctrl-0 = <&uart7m2_xfer>;
199	pinctrl-names = "default";
200	status = "okay";
201};
202
203&u2phy2 {
204	status = "okay";
205};
206
207&u2phy2_host {
208	/* connected to USB hub, which is powered by vcc5v0_sys */
209	phy-supply = <&vcc5v0_sys>;
210	status = "okay";
211};
212
213&u2phy3 {
214	status = "okay";
215};
216
217&u2phy3_host {
218	phy-supply = <&vcc5v0_host>;
219	status = "okay";
220};
221
222&usb_host0_ehci {
223	status = "okay";
224};
225
226&usb_host0_ohci {
227	status = "okay";
228};
229
230&usb_host1_ehci {
231	status = "okay";
232};
233
234&usb_host1_ohci {
235	status = "okay";
236};
237
238&usb_host2_xhci {
239	status = "okay";
240};
241