1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/power/rk3588-power.h> 10#include <dt-bindings/reset/rockchip,rk3588-cru.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/ata/ahci.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3588"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 gpio4 = &gpio4; 28 i2c0 = &i2c0; 29 i2c1 = &i2c1; 30 i2c2 = &i2c2; 31 i2c3 = &i2c3; 32 i2c4 = &i2c4; 33 i2c5 = &i2c5; 34 i2c6 = &i2c6; 35 i2c7 = &i2c7; 36 i2c8 = &i2c8; 37 serial0 = &uart0; 38 serial1 = &uart1; 39 serial2 = &uart2; 40 serial3 = &uart3; 41 serial4 = &uart4; 42 serial5 = &uart5; 43 serial6 = &uart6; 44 serial7 = &uart7; 45 serial8 = &uart8; 46 serial9 = &uart9; 47 spi0 = &spi0; 48 spi1 = &spi1; 49 spi2 = &spi2; 50 spi3 = &spi3; 51 spi4 = &spi4; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu_l0>; 62 }; 63 core1 { 64 cpu = <&cpu_l1>; 65 }; 66 core2 { 67 cpu = <&cpu_l2>; 68 }; 69 core3 { 70 cpu = <&cpu_l3>; 71 }; 72 }; 73 cluster1 { 74 core0 { 75 cpu = <&cpu_b0>; 76 }; 77 core1 { 78 cpu = <&cpu_b1>; 79 }; 80 }; 81 cluster2 { 82 core0 { 83 cpu = <&cpu_b2>; 84 }; 85 core1 { 86 cpu = <&cpu_b3>; 87 }; 88 }; 89 }; 90 91 cpu_l0: cpu@0 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0>; 95 enable-method = "psci"; 96 capacity-dmips-mhz = <530>; 97 clocks = <&scmi_clk SCMI_CLK_CPUL>; 98 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; 99 assigned-clock-rates = <816000000>; 100 cpu-idle-states = <&CPU_SLEEP>; 101 i-cache-size = <32768>; 102 i-cache-line-size = <64>; 103 i-cache-sets = <128>; 104 d-cache-size = <32768>; 105 d-cache-line-size = <64>; 106 d-cache-sets = <128>; 107 next-level-cache = <&l2_cache_l0>; 108 dynamic-power-coefficient = <228>; 109 #cooling-cells = <2>; 110 }; 111 112 cpu_l1: cpu@100 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a55"; 115 reg = <0x100>; 116 enable-method = "psci"; 117 capacity-dmips-mhz = <530>; 118 clocks = <&scmi_clk SCMI_CLK_CPUL>; 119 cpu-idle-states = <&CPU_SLEEP>; 120 i-cache-size = <32768>; 121 i-cache-line-size = <64>; 122 i-cache-sets = <128>; 123 d-cache-size = <32768>; 124 d-cache-line-size = <64>; 125 d-cache-sets = <128>; 126 next-level-cache = <&l2_cache_l1>; 127 dynamic-power-coefficient = <228>; 128 #cooling-cells = <2>; 129 }; 130 131 cpu_l2: cpu@200 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a55"; 134 reg = <0x200>; 135 enable-method = "psci"; 136 capacity-dmips-mhz = <530>; 137 clocks = <&scmi_clk SCMI_CLK_CPUL>; 138 cpu-idle-states = <&CPU_SLEEP>; 139 i-cache-size = <32768>; 140 i-cache-line-size = <64>; 141 i-cache-sets = <128>; 142 d-cache-size = <32768>; 143 d-cache-line-size = <64>; 144 d-cache-sets = <128>; 145 next-level-cache = <&l2_cache_l2>; 146 dynamic-power-coefficient = <228>; 147 #cooling-cells = <2>; 148 }; 149 150 cpu_l3: cpu@300 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a55"; 153 reg = <0x300>; 154 enable-method = "psci"; 155 capacity-dmips-mhz = <530>; 156 clocks = <&scmi_clk SCMI_CLK_CPUL>; 157 cpu-idle-states = <&CPU_SLEEP>; 158 i-cache-size = <32768>; 159 i-cache-line-size = <64>; 160 i-cache-sets = <128>; 161 d-cache-size = <32768>; 162 d-cache-line-size = <64>; 163 d-cache-sets = <128>; 164 next-level-cache = <&l2_cache_l3>; 165 dynamic-power-coefficient = <228>; 166 #cooling-cells = <2>; 167 }; 168 169 cpu_b0: cpu@400 { 170 device_type = "cpu"; 171 compatible = "arm,cortex-a76"; 172 reg = <0x400>; 173 enable-method = "psci"; 174 capacity-dmips-mhz = <1024>; 175 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 176 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; 177 assigned-clock-rates = <816000000>; 178 cpu-idle-states = <&CPU_SLEEP>; 179 i-cache-size = <65536>; 180 i-cache-line-size = <64>; 181 i-cache-sets = <256>; 182 d-cache-size = <65536>; 183 d-cache-line-size = <64>; 184 d-cache-sets = <256>; 185 next-level-cache = <&l2_cache_b0>; 186 dynamic-power-coefficient = <416>; 187 #cooling-cells = <2>; 188 }; 189 190 cpu_b1: cpu@500 { 191 device_type = "cpu"; 192 compatible = "arm,cortex-a76"; 193 reg = <0x500>; 194 enable-method = "psci"; 195 capacity-dmips-mhz = <1024>; 196 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 197 cpu-idle-states = <&CPU_SLEEP>; 198 i-cache-size = <65536>; 199 i-cache-line-size = <64>; 200 i-cache-sets = <256>; 201 d-cache-size = <65536>; 202 d-cache-line-size = <64>; 203 d-cache-sets = <256>; 204 next-level-cache = <&l2_cache_b1>; 205 dynamic-power-coefficient = <416>; 206 #cooling-cells = <2>; 207 }; 208 209 cpu_b2: cpu@600 { 210 device_type = "cpu"; 211 compatible = "arm,cortex-a76"; 212 reg = <0x600>; 213 enable-method = "psci"; 214 capacity-dmips-mhz = <1024>; 215 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 216 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; 217 assigned-clock-rates = <816000000>; 218 cpu-idle-states = <&CPU_SLEEP>; 219 i-cache-size = <65536>; 220 i-cache-line-size = <64>; 221 i-cache-sets = <256>; 222 d-cache-size = <65536>; 223 d-cache-line-size = <64>; 224 d-cache-sets = <256>; 225 next-level-cache = <&l2_cache_b2>; 226 dynamic-power-coefficient = <416>; 227 #cooling-cells = <2>; 228 }; 229 230 cpu_b3: cpu@700 { 231 device_type = "cpu"; 232 compatible = "arm,cortex-a76"; 233 reg = <0x700>; 234 enable-method = "psci"; 235 capacity-dmips-mhz = <1024>; 236 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 237 cpu-idle-states = <&CPU_SLEEP>; 238 i-cache-size = <65536>; 239 i-cache-line-size = <64>; 240 i-cache-sets = <256>; 241 d-cache-size = <65536>; 242 d-cache-line-size = <64>; 243 d-cache-sets = <256>; 244 next-level-cache = <&l2_cache_b3>; 245 dynamic-power-coefficient = <416>; 246 #cooling-cells = <2>; 247 }; 248 249 idle-states { 250 entry-method = "psci"; 251 CPU_SLEEP: cpu-sleep { 252 compatible = "arm,idle-state"; 253 local-timer-stop; 254 arm,psci-suspend-param = <0x0010000>; 255 entry-latency-us = <100>; 256 exit-latency-us = <120>; 257 min-residency-us = <1000>; 258 }; 259 }; 260 261 l2_cache_l0: l2-cache-l0 { 262 compatible = "cache"; 263 cache-size = <131072>; 264 cache-line-size = <64>; 265 cache-sets = <512>; 266 cache-level = <2>; 267 cache-unified; 268 next-level-cache = <&l3_cache>; 269 }; 270 271 l2_cache_l1: l2-cache-l1 { 272 compatible = "cache"; 273 cache-size = <131072>; 274 cache-line-size = <64>; 275 cache-sets = <512>; 276 cache-level = <2>; 277 cache-unified; 278 next-level-cache = <&l3_cache>; 279 }; 280 281 l2_cache_l2: l2-cache-l2 { 282 compatible = "cache"; 283 cache-size = <131072>; 284 cache-line-size = <64>; 285 cache-sets = <512>; 286 cache-level = <2>; 287 cache-unified; 288 next-level-cache = <&l3_cache>; 289 }; 290 291 l2_cache_l3: l2-cache-l3 { 292 compatible = "cache"; 293 cache-size = <131072>; 294 cache-line-size = <64>; 295 cache-sets = <512>; 296 cache-level = <2>; 297 cache-unified; 298 next-level-cache = <&l3_cache>; 299 }; 300 301 l2_cache_b0: l2-cache-b0 { 302 compatible = "cache"; 303 cache-size = <524288>; 304 cache-line-size = <64>; 305 cache-sets = <1024>; 306 cache-level = <2>; 307 cache-unified; 308 next-level-cache = <&l3_cache>; 309 }; 310 311 l2_cache_b1: l2-cache-b1 { 312 compatible = "cache"; 313 cache-size = <524288>; 314 cache-line-size = <64>; 315 cache-sets = <1024>; 316 cache-level = <2>; 317 cache-unified; 318 next-level-cache = <&l3_cache>; 319 }; 320 321 l2_cache_b2: l2-cache-b2 { 322 compatible = "cache"; 323 cache-size = <524288>; 324 cache-line-size = <64>; 325 cache-sets = <1024>; 326 cache-level = <2>; 327 cache-unified; 328 next-level-cache = <&l3_cache>; 329 }; 330 331 l2_cache_b3: l2-cache-b3 { 332 compatible = "cache"; 333 cache-size = <524288>; 334 cache-line-size = <64>; 335 cache-sets = <1024>; 336 cache-level = <2>; 337 cache-unified; 338 next-level-cache = <&l3_cache>; 339 }; 340 341 l3_cache: l3-cache { 342 compatible = "cache"; 343 cache-size = <3145728>; 344 cache-line-size = <64>; 345 cache-sets = <4096>; 346 cache-level = <3>; 347 cache-unified; 348 }; 349 }; 350 351 display_subsystem: display-subsystem { 352 compatible = "rockchip,display-subsystem"; 353 ports = <&vop_out>; 354 }; 355 356 firmware { 357 optee: optee { 358 compatible = "linaro,optee-tz"; 359 method = "smc"; 360 }; 361 362 scmi: scmi { 363 compatible = "arm,scmi-smc"; 364 arm,smc-id = <0x82000010>; 365 shmem = <&scmi_shmem>; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 369 scmi_clk: protocol@14 { 370 reg = <0x14>; 371 #clock-cells = <1>; 372 }; 373 374 scmi_reset: protocol@16 { 375 reg = <0x16>; 376 #reset-cells = <1>; 377 }; 378 }; 379 }; 380 381 pmu-a55 { 382 compatible = "arm,cortex-a55-pmu"; 383 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; 384 }; 385 386 pmu-a76 { 387 compatible = "arm,cortex-a76-pmu"; 388 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; 389 }; 390 391 psci { 392 compatible = "arm,psci-1.0"; 393 method = "smc"; 394 }; 395 396 spll: clock-0 { 397 compatible = "fixed-clock"; 398 clock-frequency = <702000000>; 399 clock-output-names = "spll"; 400 #clock-cells = <0>; 401 }; 402 403 timer { 404 compatible = "arm,armv8-timer"; 405 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 406 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 407 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 408 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, 409 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 410 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 411 }; 412 413 xin24m: clock-1 { 414 compatible = "fixed-clock"; 415 clock-frequency = <24000000>; 416 clock-output-names = "xin24m"; 417 #clock-cells = <0>; 418 }; 419 420 xin32k: clock-2 { 421 compatible = "fixed-clock"; 422 clock-frequency = <32768>; 423 clock-output-names = "xin32k"; 424 #clock-cells = <0>; 425 }; 426 427 pmu_sram: sram@10f000 { 428 compatible = "mmio-sram"; 429 reg = <0x0 0x0010f000 0x0 0x100>; 430 ranges = <0 0x0 0x0010f000 0x100>; 431 #address-cells = <1>; 432 #size-cells = <1>; 433 434 scmi_shmem: sram@0 { 435 compatible = "arm,scmi-shmem"; 436 reg = <0x0 0x100>; 437 }; 438 }; 439 440 gpu: gpu@fb000000 { 441 compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; 442 reg = <0x0 0xfb000000 0x0 0x200000>; 443 #cooling-cells = <2>; 444 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 445 assigned-clock-rates = <200000000>; 446 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, 447 <&cru CLK_GPU_STACKS>; 448 clock-names = "core", "coregroup", "stacks"; 449 dynamic-power-coefficient = <2982>; 450 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, 451 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, 452 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>; 453 interrupt-names = "job", "mmu", "gpu"; 454 power-domains = <&power RK3588_PD_GPU>; 455 status = "disabled"; 456 }; 457 458 usb_host0_xhci: usb@fc000000 { 459 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 460 reg = <0x0 0xfc000000 0x0 0x400000>; 461 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 462 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, 463 <&cru ACLK_USB3OTG0>; 464 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 465 dr_mode = "otg"; 466 phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; 467 phy-names = "usb2-phy", "usb3-phy"; 468 phy_type = "utmi_wide"; 469 power-domains = <&power RK3588_PD_USB>; 470 resets = <&cru SRST_A_USB3OTG0>; 471 snps,dis_enblslpm_quirk; 472 snps,dis-u1-entry-quirk; 473 snps,dis-u2-entry-quirk; 474 snps,dis-u2-freeclk-exists-quirk; 475 snps,dis-del-phy-power-chg-quirk; 476 snps,dis-tx-ipgap-linecheck-quirk; 477 status = "disabled"; 478 }; 479 480 usb_host0_ehci: usb@fc800000 { 481 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 482 reg = <0x0 0xfc800000 0x0 0x40000>; 483 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; 484 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 485 phys = <&u2phy2_host>; 486 phy-names = "usb"; 487 power-domains = <&power RK3588_PD_USB>; 488 status = "disabled"; 489 }; 490 491 usb_host0_ohci: usb@fc840000 { 492 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 493 reg = <0x0 0xfc840000 0x0 0x40000>; 494 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; 495 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 496 phys = <&u2phy2_host>; 497 phy-names = "usb"; 498 power-domains = <&power RK3588_PD_USB>; 499 status = "disabled"; 500 }; 501 502 usb_host1_ehci: usb@fc880000 { 503 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 504 reg = <0x0 0xfc880000 0x0 0x40000>; 505 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; 506 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 507 phys = <&u2phy3_host>; 508 phy-names = "usb"; 509 power-domains = <&power RK3588_PD_USB>; 510 status = "disabled"; 511 }; 512 513 usb_host1_ohci: usb@fc8c0000 { 514 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 515 reg = <0x0 0xfc8c0000 0x0 0x40000>; 516 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; 517 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 518 phys = <&u2phy3_host>; 519 phy-names = "usb"; 520 power-domains = <&power RK3588_PD_USB>; 521 status = "disabled"; 522 }; 523 524 usb_host2_xhci: usb@fcd00000 { 525 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 526 reg = <0x0 0xfcd00000 0x0 0x400000>; 527 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; 528 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, 529 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, 530 <&cru CLK_PIPEPHY2_PIPE_U3_G>; 531 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; 532 dr_mode = "host"; 533 phys = <&combphy2_psu PHY_TYPE_USB3>; 534 phy-names = "usb3-phy"; 535 phy_type = "utmi_wide"; 536 resets = <&cru SRST_A_USB3OTG2>; 537 snps,dis_enblslpm_quirk; 538 snps,dis-u2-freeclk-exists-quirk; 539 snps,dis-del-phy-power-chg-quirk; 540 snps,dis-tx-ipgap-linecheck-quirk; 541 snps,dis_rxdet_inp3_quirk; 542 status = "disabled"; 543 }; 544 545 mmu600_pcie: iommu@fc900000 { 546 compatible = "arm,smmu-v3"; 547 reg = <0x0 0xfc900000 0x0 0x200000>; 548 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>, 549 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>, 550 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, 551 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>; 552 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 553 #iommu-cells = <1>; 554 status = "disabled"; 555 }; 556 557 mmu600_php: iommu@fcb00000 { 558 compatible = "arm,smmu-v3"; 559 reg = <0x0 0xfcb00000 0x0 0x200000>; 560 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>, 561 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, 562 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>, 563 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; 564 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 565 #iommu-cells = <1>; 566 status = "disabled"; 567 }; 568 569 pmu1grf: syscon@fd58a000 { 570 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; 571 reg = <0x0 0xfd58a000 0x0 0x10000>; 572 }; 573 574 sys_grf: syscon@fd58c000 { 575 compatible = "rockchip,rk3588-sys-grf", "syscon"; 576 reg = <0x0 0xfd58c000 0x0 0x1000>; 577 }; 578 579 vop_grf: syscon@fd5a4000 { 580 compatible = "rockchip,rk3588-vop-grf", "syscon"; 581 reg = <0x0 0xfd5a4000 0x0 0x2000>; 582 }; 583 584 vo0_grf: syscon@fd5a6000 { 585 compatible = "rockchip,rk3588-vo-grf", "syscon"; 586 reg = <0x0 0xfd5a6000 0x0 0x2000>; 587 clocks = <&cru PCLK_VO0GRF>; 588 }; 589 590 vo1_grf: syscon@fd5a8000 { 591 compatible = "rockchip,rk3588-vo-grf", "syscon"; 592 reg = <0x0 0xfd5a8000 0x0 0x100>; 593 clocks = <&cru PCLK_VO1GRF>; 594 }; 595 596 usb_grf: syscon@fd5ac000 { 597 compatible = "rockchip,rk3588-usb-grf", "syscon"; 598 reg = <0x0 0xfd5ac000 0x0 0x4000>; 599 }; 600 601 php_grf: syscon@fd5b0000 { 602 compatible = "rockchip,rk3588-php-grf", "syscon"; 603 reg = <0x0 0xfd5b0000 0x0 0x1000>; 604 }; 605 606 pipe_phy0_grf: syscon@fd5bc000 { 607 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 608 reg = <0x0 0xfd5bc000 0x0 0x100>; 609 }; 610 611 pipe_phy2_grf: syscon@fd5c4000 { 612 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 613 reg = <0x0 0xfd5c4000 0x0 0x100>; 614 }; 615 616 usbdpphy0_grf: syscon@fd5c8000 { 617 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 618 reg = <0x0 0xfd5c8000 0x0 0x4000>; 619 }; 620 621 usb2phy0_grf: syscon@fd5d0000 { 622 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 623 reg = <0x0 0xfd5d0000 0x0 0x4000>; 624 #address-cells = <1>; 625 #size-cells = <1>; 626 627 u2phy0: usb2phy@0 { 628 compatible = "rockchip,rk3588-usb2phy"; 629 reg = <0x0 0x10>; 630 #clock-cells = <0>; 631 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 632 clock-names = "phyclk"; 633 clock-output-names = "usb480m_phy0"; 634 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; 635 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; 636 reset-names = "phy", "apb"; 637 status = "disabled"; 638 639 u2phy0_otg: otg-port { 640 #phy-cells = <0>; 641 status = "disabled"; 642 }; 643 }; 644 }; 645 646 usb2phy2_grf: syscon@fd5d8000 { 647 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 648 reg = <0x0 0xfd5d8000 0x0 0x4000>; 649 #address-cells = <1>; 650 #size-cells = <1>; 651 652 u2phy2: usb2phy@8000 { 653 compatible = "rockchip,rk3588-usb2phy"; 654 reg = <0x8000 0x10>; 655 #clock-cells = <0>; 656 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 657 clock-names = "phyclk"; 658 clock-output-names = "usb480m_phy2"; 659 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 660 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 661 reset-names = "phy", "apb"; 662 status = "disabled"; 663 664 u2phy2_host: host-port { 665 #phy-cells = <0>; 666 status = "disabled"; 667 }; 668 }; 669 }; 670 671 usb2phy3_grf: syscon@fd5dc000 { 672 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 673 reg = <0x0 0xfd5dc000 0x0 0x4000>; 674 #address-cells = <1>; 675 #size-cells = <1>; 676 677 u2phy3: usb2phy@c000 { 678 compatible = "rockchip,rk3588-usb2phy"; 679 reg = <0xc000 0x10>; 680 #clock-cells = <0>; 681 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 682 clock-names = "phyclk"; 683 clock-output-names = "usb480m_phy3"; 684 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 685 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 686 reset-names = "phy", "apb"; 687 status = "disabled"; 688 689 u2phy3_host: host-port { 690 #phy-cells = <0>; 691 status = "disabled"; 692 }; 693 }; 694 }; 695 696 hdptxphy0_grf: syscon@fd5e0000 { 697 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 698 reg = <0x0 0xfd5e0000 0x0 0x100>; 699 }; 700 701 ioc: syscon@fd5f0000 { 702 compatible = "rockchip,rk3588-ioc", "syscon"; 703 reg = <0x0 0xfd5f0000 0x0 0x10000>; 704 }; 705 706 system_sram1: sram@fd600000 { 707 compatible = "mmio-sram"; 708 reg = <0x0 0xfd600000 0x0 0x100000>; 709 ranges = <0x0 0x0 0xfd600000 0x100000>; 710 #address-cells = <1>; 711 #size-cells = <1>; 712 }; 713 714 cru: clock-controller@fd7c0000 { 715 compatible = "rockchip,rk3588-cru"; 716 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 717 assigned-clocks = 718 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 719 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 720 <&cru ACLK_CENTER_ROOT>, 721 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 722 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 723 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 724 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, 725 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 726 <&cru CLK_GPU>; 727 assigned-clock-rates = 728 <1100000000>, <786432000>, 729 <850000000>, <1188000000>, 730 <702000000>, 731 <400000000>, <500000000>, 732 <800000000>, <100000000>, 733 <400000000>, <100000000>, 734 <200000000>, <500000000>, 735 <375000000>, <150000000>, 736 <200000000>; 737 rockchip,grf = <&php_grf>; 738 #clock-cells = <1>; 739 #reset-cells = <1>; 740 }; 741 742 i2c0: i2c@fd880000 { 743 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 744 reg = <0x0 0xfd880000 0x0 0x1000>; 745 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; 746 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 747 clock-names = "i2c", "pclk"; 748 pinctrl-0 = <&i2c0m0_xfer>; 749 pinctrl-names = "default"; 750 #address-cells = <1>; 751 #size-cells = <0>; 752 status = "disabled"; 753 }; 754 755 uart0: serial@fd890000 { 756 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 757 reg = <0x0 0xfd890000 0x0 0x100>; 758 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 759 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 760 clock-names = "baudclk", "apb_pclk"; 761 dmas = <&dmac0 6>, <&dmac0 7>; 762 dma-names = "tx", "rx"; 763 pinctrl-0 = <&uart0m1_xfer>; 764 pinctrl-names = "default"; 765 reg-shift = <2>; 766 reg-io-width = <4>; 767 status = "disabled"; 768 }; 769 770 pwm0: pwm@fd8b0000 { 771 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 772 reg = <0x0 0xfd8b0000 0x0 0x10>; 773 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 774 clock-names = "pwm", "pclk"; 775 pinctrl-0 = <&pwm0m0_pins>; 776 pinctrl-names = "default"; 777 #pwm-cells = <3>; 778 status = "disabled"; 779 }; 780 781 pwm1: pwm@fd8b0010 { 782 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 783 reg = <0x0 0xfd8b0010 0x0 0x10>; 784 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 785 clock-names = "pwm", "pclk"; 786 pinctrl-0 = <&pwm1m0_pins>; 787 pinctrl-names = "default"; 788 #pwm-cells = <3>; 789 status = "disabled"; 790 }; 791 792 pwm2: pwm@fd8b0020 { 793 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 794 reg = <0x0 0xfd8b0020 0x0 0x10>; 795 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 796 clock-names = "pwm", "pclk"; 797 pinctrl-0 = <&pwm2m0_pins>; 798 pinctrl-names = "default"; 799 #pwm-cells = <3>; 800 status = "disabled"; 801 }; 802 803 pwm3: pwm@fd8b0030 { 804 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 805 reg = <0x0 0xfd8b0030 0x0 0x10>; 806 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 807 clock-names = "pwm", "pclk"; 808 pinctrl-0 = <&pwm3m0_pins>; 809 pinctrl-names = "default"; 810 #pwm-cells = <3>; 811 status = "disabled"; 812 }; 813 814 pmu: power-management@fd8d8000 { 815 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 816 reg = <0x0 0xfd8d8000 0x0 0x400>; 817 818 power: power-controller { 819 compatible = "rockchip,rk3588-power-controller"; 820 #address-cells = <1>; 821 #power-domain-cells = <1>; 822 #size-cells = <0>; 823 status = "okay"; 824 825 /* These power domains are grouped by VD_NPU */ 826 power-domain@RK3588_PD_NPU { 827 reg = <RK3588_PD_NPU>; 828 #power-domain-cells = <0>; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 832 power-domain@RK3588_PD_NPUTOP { 833 reg = <RK3588_PD_NPUTOP>; 834 clocks = <&cru HCLK_NPU_ROOT>, 835 <&cru PCLK_NPU_ROOT>, 836 <&cru CLK_NPU_DSU0>, 837 <&cru HCLK_NPU_CM0_ROOT>; 838 pm_qos = <&qos_npu0_mwr>, 839 <&qos_npu0_mro>, 840 <&qos_mcu_npu>; 841 #power-domain-cells = <0>; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 845 power-domain@RK3588_PD_NPU1 { 846 reg = <RK3588_PD_NPU1>; 847 clocks = <&cru HCLK_NPU_ROOT>, 848 <&cru PCLK_NPU_ROOT>, 849 <&cru CLK_NPU_DSU0>; 850 pm_qos = <&qos_npu1>; 851 #power-domain-cells = <0>; 852 }; 853 power-domain@RK3588_PD_NPU2 { 854 reg = <RK3588_PD_NPU2>; 855 clocks = <&cru HCLK_NPU_ROOT>, 856 <&cru PCLK_NPU_ROOT>, 857 <&cru CLK_NPU_DSU0>; 858 pm_qos = <&qos_npu2>; 859 #power-domain-cells = <0>; 860 }; 861 }; 862 }; 863 /* These power domains are grouped by VD_GPU */ 864 power-domain@RK3588_PD_GPU { 865 reg = <RK3588_PD_GPU>; 866 clocks = <&cru CLK_GPU>, 867 <&cru CLK_GPU_COREGROUP>, 868 <&cru CLK_GPU_STACKS>; 869 pm_qos = <&qos_gpu_m0>, 870 <&qos_gpu_m1>, 871 <&qos_gpu_m2>, 872 <&qos_gpu_m3>; 873 #power-domain-cells = <0>; 874 }; 875 /* These power domains are grouped by VD_VCODEC */ 876 power-domain@RK3588_PD_VCODEC { 877 reg = <RK3588_PD_VCODEC>; 878 #address-cells = <1>; 879 #size-cells = <0>; 880 #power-domain-cells = <0>; 881 882 power-domain@RK3588_PD_RKVDEC0 { 883 reg = <RK3588_PD_RKVDEC0>; 884 clocks = <&cru HCLK_RKVDEC0>, 885 <&cru HCLK_VDPU_ROOT>, 886 <&cru ACLK_VDPU_ROOT>, 887 <&cru ACLK_RKVDEC0>, 888 <&cru ACLK_RKVDEC_CCU>; 889 pm_qos = <&qos_rkvdec0>; 890 #power-domain-cells = <0>; 891 }; 892 power-domain@RK3588_PD_RKVDEC1 { 893 reg = <RK3588_PD_RKVDEC1>; 894 clocks = <&cru HCLK_RKVDEC1>, 895 <&cru HCLK_VDPU_ROOT>, 896 <&cru ACLK_VDPU_ROOT>, 897 <&cru ACLK_RKVDEC1>; 898 pm_qos = <&qos_rkvdec1>; 899 #power-domain-cells = <0>; 900 }; 901 power-domain@RK3588_PD_VENC0 { 902 reg = <RK3588_PD_VENC0>; 903 clocks = <&cru HCLK_RKVENC0>, 904 <&cru ACLK_RKVENC0>; 905 pm_qos = <&qos_rkvenc0_m0ro>, 906 <&qos_rkvenc0_m1ro>, 907 <&qos_rkvenc0_m2wo>; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 #power-domain-cells = <0>; 911 912 power-domain@RK3588_PD_VENC1 { 913 reg = <RK3588_PD_VENC1>; 914 clocks = <&cru HCLK_RKVENC1>, 915 <&cru HCLK_RKVENC0>, 916 <&cru ACLK_RKVENC0>, 917 <&cru ACLK_RKVENC1>; 918 pm_qos = <&qos_rkvenc1_m0ro>, 919 <&qos_rkvenc1_m1ro>, 920 <&qos_rkvenc1_m2wo>; 921 #power-domain-cells = <0>; 922 }; 923 }; 924 }; 925 /* These power domains are grouped by VD_LOGIC */ 926 power-domain@RK3588_PD_VDPU { 927 reg = <RK3588_PD_VDPU>; 928 clocks = <&cru HCLK_VDPU_ROOT>, 929 <&cru ACLK_VDPU_LOW_ROOT>, 930 <&cru ACLK_VDPU_ROOT>, 931 <&cru ACLK_JPEG_DECODER_ROOT>, 932 <&cru ACLK_IEP2P0>, 933 <&cru HCLK_IEP2P0>, 934 <&cru ACLK_JPEG_ENCODER0>, 935 <&cru HCLK_JPEG_ENCODER0>, 936 <&cru ACLK_JPEG_ENCODER1>, 937 <&cru HCLK_JPEG_ENCODER1>, 938 <&cru ACLK_JPEG_ENCODER2>, 939 <&cru HCLK_JPEG_ENCODER2>, 940 <&cru ACLK_JPEG_ENCODER3>, 941 <&cru HCLK_JPEG_ENCODER3>, 942 <&cru ACLK_JPEG_DECODER>, 943 <&cru HCLK_JPEG_DECODER>, 944 <&cru ACLK_RGA2>, 945 <&cru HCLK_RGA2>; 946 pm_qos = <&qos_iep>, 947 <&qos_jpeg_dec>, 948 <&qos_jpeg_enc0>, 949 <&qos_jpeg_enc1>, 950 <&qos_jpeg_enc2>, 951 <&qos_jpeg_enc3>, 952 <&qos_rga2_mro>, 953 <&qos_rga2_mwo>; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 #power-domain-cells = <0>; 957 958 959 power-domain@RK3588_PD_AV1 { 960 reg = <RK3588_PD_AV1>; 961 clocks = <&cru PCLK_AV1>, 962 <&cru ACLK_AV1>, 963 <&cru HCLK_VDPU_ROOT>; 964 pm_qos = <&qos_av1>; 965 #power-domain-cells = <0>; 966 }; 967 power-domain@RK3588_PD_RKVDEC0 { 968 reg = <RK3588_PD_RKVDEC0>; 969 clocks = <&cru HCLK_RKVDEC0>, 970 <&cru HCLK_VDPU_ROOT>, 971 <&cru ACLK_VDPU_ROOT>, 972 <&cru ACLK_RKVDEC0>; 973 pm_qos = <&qos_rkvdec0>; 974 #power-domain-cells = <0>; 975 }; 976 power-domain@RK3588_PD_RKVDEC1 { 977 reg = <RK3588_PD_RKVDEC1>; 978 clocks = <&cru HCLK_RKVDEC1>, 979 <&cru HCLK_VDPU_ROOT>, 980 <&cru ACLK_VDPU_ROOT>; 981 pm_qos = <&qos_rkvdec1>; 982 #power-domain-cells = <0>; 983 }; 984 power-domain@RK3588_PD_RGA30 { 985 reg = <RK3588_PD_RGA30>; 986 clocks = <&cru ACLK_RGA3_0>, 987 <&cru HCLK_RGA3_0>; 988 pm_qos = <&qos_rga3_0>; 989 #power-domain-cells = <0>; 990 }; 991 }; 992 power-domain@RK3588_PD_VOP { 993 reg = <RK3588_PD_VOP>; 994 clocks = <&cru PCLK_VOP_ROOT>, 995 <&cru HCLK_VOP_ROOT>, 996 <&cru ACLK_VOP>; 997 pm_qos = <&qos_vop_m0>, 998 <&qos_vop_m1>; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 #power-domain-cells = <0>; 1002 1003 power-domain@RK3588_PD_VO0 { 1004 reg = <RK3588_PD_VO0>; 1005 clocks = <&cru PCLK_VO0_ROOT>, 1006 <&cru PCLK_VO0_S_ROOT>, 1007 <&cru HCLK_VO0_S_ROOT>, 1008 <&cru ACLK_VO0_ROOT>, 1009 <&cru HCLK_HDCP0>, 1010 <&cru ACLK_HDCP0>, 1011 <&cru HCLK_VOP_ROOT>; 1012 pm_qos = <&qos_hdcp0>; 1013 #power-domain-cells = <0>; 1014 }; 1015 }; 1016 power-domain@RK3588_PD_VO1 { 1017 reg = <RK3588_PD_VO1>; 1018 clocks = <&cru PCLK_VO1_ROOT>, 1019 <&cru PCLK_VO1_S_ROOT>, 1020 <&cru HCLK_VO1_S_ROOT>, 1021 <&cru HCLK_HDCP1>, 1022 <&cru ACLK_HDCP1>, 1023 <&cru ACLK_HDMIRX_ROOT>, 1024 <&cru HCLK_VO1USB_TOP_ROOT>; 1025 pm_qos = <&qos_hdcp1>, 1026 <&qos_hdmirx>; 1027 #power-domain-cells = <0>; 1028 }; 1029 power-domain@RK3588_PD_VI { 1030 reg = <RK3588_PD_VI>; 1031 clocks = <&cru HCLK_VI_ROOT>, 1032 <&cru PCLK_VI_ROOT>, 1033 <&cru HCLK_ISP0>, 1034 <&cru ACLK_ISP0>, 1035 <&cru HCLK_VICAP>, 1036 <&cru ACLK_VICAP>; 1037 pm_qos = <&qos_isp0_mro>, 1038 <&qos_isp0_mwo>, 1039 <&qos_vicap_m0>, 1040 <&qos_vicap_m1>; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 #power-domain-cells = <0>; 1044 1045 power-domain@RK3588_PD_ISP1 { 1046 reg = <RK3588_PD_ISP1>; 1047 clocks = <&cru HCLK_ISP1>, 1048 <&cru ACLK_ISP1>, 1049 <&cru HCLK_VI_ROOT>, 1050 <&cru PCLK_VI_ROOT>; 1051 pm_qos = <&qos_isp1_mwo>, 1052 <&qos_isp1_mro>; 1053 #power-domain-cells = <0>; 1054 }; 1055 power-domain@RK3588_PD_FEC { 1056 reg = <RK3588_PD_FEC>; 1057 clocks = <&cru HCLK_FISHEYE0>, 1058 <&cru ACLK_FISHEYE0>, 1059 <&cru HCLK_FISHEYE1>, 1060 <&cru ACLK_FISHEYE1>, 1061 <&cru PCLK_VI_ROOT>; 1062 pm_qos = <&qos_fisheye0>, 1063 <&qos_fisheye1>; 1064 #power-domain-cells = <0>; 1065 }; 1066 }; 1067 power-domain@RK3588_PD_RGA31 { 1068 reg = <RK3588_PD_RGA31>; 1069 clocks = <&cru HCLK_RGA3_1>, 1070 <&cru ACLK_RGA3_1>; 1071 pm_qos = <&qos_rga3_1>; 1072 #power-domain-cells = <0>; 1073 }; 1074 power-domain@RK3588_PD_USB { 1075 reg = <RK3588_PD_USB>; 1076 clocks = <&cru PCLK_PHP_ROOT>, 1077 <&cru ACLK_USB_ROOT>, 1078 <&cru ACLK_USB>, 1079 <&cru HCLK_USB_ROOT>, 1080 <&cru HCLK_HOST0>, 1081 <&cru HCLK_HOST_ARB0>, 1082 <&cru HCLK_HOST1>, 1083 <&cru HCLK_HOST_ARB1>; 1084 pm_qos = <&qos_usb3_0>, 1085 <&qos_usb3_1>, 1086 <&qos_usb2host_0>, 1087 <&qos_usb2host_1>; 1088 #power-domain-cells = <0>; 1089 }; 1090 power-domain@RK3588_PD_GMAC { 1091 reg = <RK3588_PD_GMAC>; 1092 clocks = <&cru PCLK_PHP_ROOT>, 1093 <&cru ACLK_PCIE_ROOT>, 1094 <&cru ACLK_PHP_ROOT>; 1095 #power-domain-cells = <0>; 1096 }; 1097 power-domain@RK3588_PD_PCIE { 1098 reg = <RK3588_PD_PCIE>; 1099 clocks = <&cru PCLK_PHP_ROOT>, 1100 <&cru ACLK_PCIE_ROOT>, 1101 <&cru ACLK_PHP_ROOT>; 1102 #power-domain-cells = <0>; 1103 }; 1104 power-domain@RK3588_PD_SDIO { 1105 reg = <RK3588_PD_SDIO>; 1106 clocks = <&cru HCLK_SDIO>, 1107 <&cru HCLK_NVM_ROOT>; 1108 pm_qos = <&qos_sdio>; 1109 #power-domain-cells = <0>; 1110 }; 1111 power-domain@RK3588_PD_AUDIO { 1112 reg = <RK3588_PD_AUDIO>; 1113 clocks = <&cru HCLK_AUDIO_ROOT>, 1114 <&cru PCLK_AUDIO_ROOT>; 1115 #power-domain-cells = <0>; 1116 }; 1117 power-domain@RK3588_PD_SDMMC { 1118 reg = <RK3588_PD_SDMMC>; 1119 pm_qos = <&qos_sdmmc>; 1120 #power-domain-cells = <0>; 1121 }; 1122 }; 1123 }; 1124 1125 av1d: video-codec@fdc70000 { 1126 compatible = "rockchip,rk3588-av1-vpu"; 1127 reg = <0x0 0xfdc70000 0x0 0x800>; 1128 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 1129 interrupt-names = "vdpu"; 1130 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1131 assigned-clock-rates = <400000000>, <400000000>; 1132 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1133 clock-names = "aclk", "hclk"; 1134 power-domains = <&power RK3588_PD_AV1>; 1135 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; 1136 }; 1137 1138 vop: vop@fdd90000 { 1139 compatible = "rockchip,rk3588-vop"; 1140 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; 1141 reg-names = "vop", "gamma-lut"; 1142 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1143 clocks = <&cru ACLK_VOP>, 1144 <&cru HCLK_VOP>, 1145 <&cru DCLK_VOP0>, 1146 <&cru DCLK_VOP1>, 1147 <&cru DCLK_VOP2>, 1148 <&cru DCLK_VOP3>, 1149 <&cru PCLK_VOP_ROOT>; 1150 clock-names = "aclk", 1151 "hclk", 1152 "dclk_vp0", 1153 "dclk_vp1", 1154 "dclk_vp2", 1155 "dclk_vp3", 1156 "pclk_vop"; 1157 iommus = <&vop_mmu>; 1158 power-domains = <&power RK3588_PD_VOP>; 1159 rockchip,grf = <&sys_grf>; 1160 rockchip,vop-grf = <&vop_grf>; 1161 rockchip,vo1-grf = <&vo1_grf>; 1162 rockchip,pmu = <&pmu>; 1163 status = "disabled"; 1164 1165 vop_out: ports { 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 1169 vp0: port@0 { 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 reg = <0>; 1173 }; 1174 1175 vp1: port@1 { 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 reg = <1>; 1179 }; 1180 1181 vp2: port@2 { 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 reg = <2>; 1185 }; 1186 1187 vp3: port@3 { 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 reg = <3>; 1191 }; 1192 }; 1193 }; 1194 1195 vop_mmu: iommu@fdd97e00 { 1196 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1197 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 1198 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1199 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1200 clock-names = "aclk", "iface"; 1201 #iommu-cells = <0>; 1202 power-domains = <&power RK3588_PD_VOP>; 1203 status = "disabled"; 1204 }; 1205 1206 i2s4_8ch: i2s@fddc0000 { 1207 compatible = "rockchip,rk3588-i2s-tdm"; 1208 reg = <0x0 0xfddc0000 0x0 0x1000>; 1209 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; 1210 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 1211 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1212 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 1213 assigned-clock-parents = <&cru PLL_AUPLL>; 1214 dmas = <&dmac2 0>; 1215 dma-names = "tx"; 1216 power-domains = <&power RK3588_PD_VO0>; 1217 resets = <&cru SRST_M_I2S4_8CH_TX>; 1218 reset-names = "tx-m"; 1219 #sound-dai-cells = <0>; 1220 status = "disabled"; 1221 }; 1222 1223 i2s5_8ch: i2s@fddf0000 { 1224 compatible = "rockchip,rk3588-i2s-tdm"; 1225 reg = <0x0 0xfddf0000 0x0 0x1000>; 1226 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; 1227 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 1228 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1229 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 1230 assigned-clock-parents = <&cru PLL_AUPLL>; 1231 dmas = <&dmac2 2>; 1232 dma-names = "tx"; 1233 power-domains = <&power RK3588_PD_VO1>; 1234 resets = <&cru SRST_M_I2S5_8CH_TX>; 1235 reset-names = "tx-m"; 1236 #sound-dai-cells = <0>; 1237 status = "disabled"; 1238 }; 1239 1240 i2s9_8ch: i2s@fddfc000 { 1241 compatible = "rockchip,rk3588-i2s-tdm"; 1242 reg = <0x0 0xfddfc000 0x0 0x1000>; 1243 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; 1244 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 1245 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1246 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 1247 assigned-clock-parents = <&cru PLL_AUPLL>; 1248 dmas = <&dmac2 23>; 1249 dma-names = "rx"; 1250 power-domains = <&power RK3588_PD_VO1>; 1251 resets = <&cru SRST_M_I2S9_8CH_RX>; 1252 reset-names = "rx-m"; 1253 #sound-dai-cells = <0>; 1254 status = "disabled"; 1255 }; 1256 1257 qos_gpu_m0: qos@fdf35000 { 1258 compatible = "rockchip,rk3588-qos", "syscon"; 1259 reg = <0x0 0xfdf35000 0x0 0x20>; 1260 }; 1261 1262 qos_gpu_m1: qos@fdf35200 { 1263 compatible = "rockchip,rk3588-qos", "syscon"; 1264 reg = <0x0 0xfdf35200 0x0 0x20>; 1265 }; 1266 1267 qos_gpu_m2: qos@fdf35400 { 1268 compatible = "rockchip,rk3588-qos", "syscon"; 1269 reg = <0x0 0xfdf35400 0x0 0x20>; 1270 }; 1271 1272 qos_gpu_m3: qos@fdf35600 { 1273 compatible = "rockchip,rk3588-qos", "syscon"; 1274 reg = <0x0 0xfdf35600 0x0 0x20>; 1275 }; 1276 1277 qos_rga3_1: qos@fdf36000 { 1278 compatible = "rockchip,rk3588-qos", "syscon"; 1279 reg = <0x0 0xfdf36000 0x0 0x20>; 1280 }; 1281 1282 qos_sdio: qos@fdf39000 { 1283 compatible = "rockchip,rk3588-qos", "syscon"; 1284 reg = <0x0 0xfdf39000 0x0 0x20>; 1285 }; 1286 1287 qos_sdmmc: qos@fdf3d800 { 1288 compatible = "rockchip,rk3588-qos", "syscon"; 1289 reg = <0x0 0xfdf3d800 0x0 0x20>; 1290 }; 1291 1292 qos_usb3_1: qos@fdf3e000 { 1293 compatible = "rockchip,rk3588-qos", "syscon"; 1294 reg = <0x0 0xfdf3e000 0x0 0x20>; 1295 }; 1296 1297 qos_usb3_0: qos@fdf3e200 { 1298 compatible = "rockchip,rk3588-qos", "syscon"; 1299 reg = <0x0 0xfdf3e200 0x0 0x20>; 1300 }; 1301 1302 qos_usb2host_0: qos@fdf3e400 { 1303 compatible = "rockchip,rk3588-qos", "syscon"; 1304 reg = <0x0 0xfdf3e400 0x0 0x20>; 1305 }; 1306 1307 qos_usb2host_1: qos@fdf3e600 { 1308 compatible = "rockchip,rk3588-qos", "syscon"; 1309 reg = <0x0 0xfdf3e600 0x0 0x20>; 1310 }; 1311 1312 qos_fisheye0: qos@fdf40000 { 1313 compatible = "rockchip,rk3588-qos", "syscon"; 1314 reg = <0x0 0xfdf40000 0x0 0x20>; 1315 }; 1316 1317 qos_fisheye1: qos@fdf40200 { 1318 compatible = "rockchip,rk3588-qos", "syscon"; 1319 reg = <0x0 0xfdf40200 0x0 0x20>; 1320 }; 1321 1322 qos_isp0_mro: qos@fdf40400 { 1323 compatible = "rockchip,rk3588-qos", "syscon"; 1324 reg = <0x0 0xfdf40400 0x0 0x20>; 1325 }; 1326 1327 qos_isp0_mwo: qos@fdf40500 { 1328 compatible = "rockchip,rk3588-qos", "syscon"; 1329 reg = <0x0 0xfdf40500 0x0 0x20>; 1330 }; 1331 1332 qos_vicap_m0: qos@fdf40600 { 1333 compatible = "rockchip,rk3588-qos", "syscon"; 1334 reg = <0x0 0xfdf40600 0x0 0x20>; 1335 }; 1336 1337 qos_vicap_m1: qos@fdf40800 { 1338 compatible = "rockchip,rk3588-qos", "syscon"; 1339 reg = <0x0 0xfdf40800 0x0 0x20>; 1340 }; 1341 1342 qos_isp1_mwo: qos@fdf41000 { 1343 compatible = "rockchip,rk3588-qos", "syscon"; 1344 reg = <0x0 0xfdf41000 0x0 0x20>; 1345 }; 1346 1347 qos_isp1_mro: qos@fdf41100 { 1348 compatible = "rockchip,rk3588-qos", "syscon"; 1349 reg = <0x0 0xfdf41100 0x0 0x20>; 1350 }; 1351 1352 qos_rkvenc0_m0ro: qos@fdf60000 { 1353 compatible = "rockchip,rk3588-qos", "syscon"; 1354 reg = <0x0 0xfdf60000 0x0 0x20>; 1355 }; 1356 1357 qos_rkvenc0_m1ro: qos@fdf60200 { 1358 compatible = "rockchip,rk3588-qos", "syscon"; 1359 reg = <0x0 0xfdf60200 0x0 0x20>; 1360 }; 1361 1362 qos_rkvenc0_m2wo: qos@fdf60400 { 1363 compatible = "rockchip,rk3588-qos", "syscon"; 1364 reg = <0x0 0xfdf60400 0x0 0x20>; 1365 }; 1366 1367 qos_rkvenc1_m0ro: qos@fdf61000 { 1368 compatible = "rockchip,rk3588-qos", "syscon"; 1369 reg = <0x0 0xfdf61000 0x0 0x20>; 1370 }; 1371 1372 qos_rkvenc1_m1ro: qos@fdf61200 { 1373 compatible = "rockchip,rk3588-qos", "syscon"; 1374 reg = <0x0 0xfdf61200 0x0 0x20>; 1375 }; 1376 1377 qos_rkvenc1_m2wo: qos@fdf61400 { 1378 compatible = "rockchip,rk3588-qos", "syscon"; 1379 reg = <0x0 0xfdf61400 0x0 0x20>; 1380 }; 1381 1382 qos_rkvdec0: qos@fdf62000 { 1383 compatible = "rockchip,rk3588-qos", "syscon"; 1384 reg = <0x0 0xfdf62000 0x0 0x20>; 1385 }; 1386 1387 qos_rkvdec1: qos@fdf63000 { 1388 compatible = "rockchip,rk3588-qos", "syscon"; 1389 reg = <0x0 0xfdf63000 0x0 0x20>; 1390 }; 1391 1392 qos_av1: qos@fdf64000 { 1393 compatible = "rockchip,rk3588-qos", "syscon"; 1394 reg = <0x0 0xfdf64000 0x0 0x20>; 1395 }; 1396 1397 qos_iep: qos@fdf66000 { 1398 compatible = "rockchip,rk3588-qos", "syscon"; 1399 reg = <0x0 0xfdf66000 0x0 0x20>; 1400 }; 1401 1402 qos_jpeg_dec: qos@fdf66200 { 1403 compatible = "rockchip,rk3588-qos", "syscon"; 1404 reg = <0x0 0xfdf66200 0x0 0x20>; 1405 }; 1406 1407 qos_jpeg_enc0: qos@fdf66400 { 1408 compatible = "rockchip,rk3588-qos", "syscon"; 1409 reg = <0x0 0xfdf66400 0x0 0x20>; 1410 }; 1411 1412 qos_jpeg_enc1: qos@fdf66600 { 1413 compatible = "rockchip,rk3588-qos", "syscon"; 1414 reg = <0x0 0xfdf66600 0x0 0x20>; 1415 }; 1416 1417 qos_jpeg_enc2: qos@fdf66800 { 1418 compatible = "rockchip,rk3588-qos", "syscon"; 1419 reg = <0x0 0xfdf66800 0x0 0x20>; 1420 }; 1421 1422 qos_jpeg_enc3: qos@fdf66a00 { 1423 compatible = "rockchip,rk3588-qos", "syscon"; 1424 reg = <0x0 0xfdf66a00 0x0 0x20>; 1425 }; 1426 1427 qos_rga2_mro: qos@fdf66c00 { 1428 compatible = "rockchip,rk3588-qos", "syscon"; 1429 reg = <0x0 0xfdf66c00 0x0 0x20>; 1430 }; 1431 1432 qos_rga2_mwo: qos@fdf66e00 { 1433 compatible = "rockchip,rk3588-qos", "syscon"; 1434 reg = <0x0 0xfdf66e00 0x0 0x20>; 1435 }; 1436 1437 qos_rga3_0: qos@fdf67000 { 1438 compatible = "rockchip,rk3588-qos", "syscon"; 1439 reg = <0x0 0xfdf67000 0x0 0x20>; 1440 }; 1441 1442 qos_vdpu: qos@fdf67200 { 1443 compatible = "rockchip,rk3588-qos", "syscon"; 1444 reg = <0x0 0xfdf67200 0x0 0x20>; 1445 }; 1446 1447 qos_npu1: qos@fdf70000 { 1448 compatible = "rockchip,rk3588-qos", "syscon"; 1449 reg = <0x0 0xfdf70000 0x0 0x20>; 1450 }; 1451 1452 qos_npu2: qos@fdf71000 { 1453 compatible = "rockchip,rk3588-qos", "syscon"; 1454 reg = <0x0 0xfdf71000 0x0 0x20>; 1455 }; 1456 1457 qos_npu0_mwr: qos@fdf72000 { 1458 compatible = "rockchip,rk3588-qos", "syscon"; 1459 reg = <0x0 0xfdf72000 0x0 0x20>; 1460 }; 1461 1462 qos_npu0_mro: qos@fdf72200 { 1463 compatible = "rockchip,rk3588-qos", "syscon"; 1464 reg = <0x0 0xfdf72200 0x0 0x20>; 1465 }; 1466 1467 qos_mcu_npu: qos@fdf72400 { 1468 compatible = "rockchip,rk3588-qos", "syscon"; 1469 reg = <0x0 0xfdf72400 0x0 0x20>; 1470 }; 1471 1472 qos_hdcp0: qos@fdf80000 { 1473 compatible = "rockchip,rk3588-qos", "syscon"; 1474 reg = <0x0 0xfdf80000 0x0 0x20>; 1475 }; 1476 1477 qos_hdcp1: qos@fdf81000 { 1478 compatible = "rockchip,rk3588-qos", "syscon"; 1479 reg = <0x0 0xfdf81000 0x0 0x20>; 1480 }; 1481 1482 qos_hdmirx: qos@fdf81200 { 1483 compatible = "rockchip,rk3588-qos", "syscon"; 1484 reg = <0x0 0xfdf81200 0x0 0x20>; 1485 }; 1486 1487 qos_vop_m0: qos@fdf82000 { 1488 compatible = "rockchip,rk3588-qos", "syscon"; 1489 reg = <0x0 0xfdf82000 0x0 0x20>; 1490 }; 1491 1492 qos_vop_m1: qos@fdf82200 { 1493 compatible = "rockchip,rk3588-qos", "syscon"; 1494 reg = <0x0 0xfdf82200 0x0 0x20>; 1495 }; 1496 1497 dfi: dfi@fe060000 { 1498 reg = <0x00 0xfe060000 0x00 0x10000>; 1499 compatible = "rockchip,rk3588-dfi"; 1500 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, 1501 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, 1502 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, 1503 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1504 rockchip,pmu = <&pmu1grf>; 1505 }; 1506 1507 pcie2x1l1: pcie@fe180000 { 1508 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1509 bus-range = <0x30 0x3f>; 1510 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 1511 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 1512 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; 1513 clock-names = "aclk_mst", "aclk_slv", 1514 "aclk_dbi", "pclk", 1515 "aux", "pipe"; 1516 device_type = "pci"; 1517 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, 1518 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, 1519 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, 1520 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, 1521 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; 1522 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1523 #interrupt-cells = <1>; 1524 interrupt-map-mask = <0 0 0 7>; 1525 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 1526 <0 0 0 2 &pcie2x1l1_intc 1>, 1527 <0 0 0 3 &pcie2x1l1_intc 2>, 1528 <0 0 0 4 &pcie2x1l1_intc 3>; 1529 linux,pci-domain = <3>; 1530 max-link-speed = <2>; 1531 msi-map = <0x3000 &its0 0x3000 0x1000>; 1532 num-lanes = <1>; 1533 phys = <&combphy2_psu PHY_TYPE_PCIE>; 1534 phy-names = "pcie-phy"; 1535 power-domains = <&power RK3588_PD_PCIE>; 1536 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, 1537 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, 1538 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; 1539 reg = <0xa 0x40c00000 0x0 0x00400000>, 1540 <0x0 0xfe180000 0x0 0x00010000>, 1541 <0x0 0xf3000000 0x0 0x00100000>; 1542 reg-names = "dbi", "apb", "config"; 1543 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; 1544 reset-names = "pwr", "pipe"; 1545 #address-cells = <3>; 1546 #size-cells = <2>; 1547 status = "disabled"; 1548 1549 pcie2x1l1_intc: legacy-interrupt-controller { 1550 interrupt-controller; 1551 #address-cells = <0>; 1552 #interrupt-cells = <1>; 1553 interrupt-parent = <&gic>; 1554 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; 1555 }; 1556 }; 1557 1558 pcie2x1l2: pcie@fe190000 { 1559 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1560 bus-range = <0x40 0x4f>; 1561 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 1562 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 1563 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; 1564 clock-names = "aclk_mst", "aclk_slv", 1565 "aclk_dbi", "pclk", 1566 "aux", "pipe"; 1567 device_type = "pci"; 1568 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, 1569 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, 1570 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, 1571 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, 1572 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; 1573 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1574 #interrupt-cells = <1>; 1575 interrupt-map-mask = <0 0 0 7>; 1576 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 1577 <0 0 0 2 &pcie2x1l2_intc 1>, 1578 <0 0 0 3 &pcie2x1l2_intc 2>, 1579 <0 0 0 4 &pcie2x1l2_intc 3>; 1580 linux,pci-domain = <4>; 1581 max-link-speed = <2>; 1582 msi-map = <0x4000 &its0 0x4000 0x1000>; 1583 num-lanes = <1>; 1584 phys = <&combphy0_ps PHY_TYPE_PCIE>; 1585 phy-names = "pcie-phy"; 1586 power-domains = <&power RK3588_PD_PCIE>; 1587 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 1588 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, 1589 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; 1590 reg = <0xa 0x41000000 0x0 0x00400000>, 1591 <0x0 0xfe190000 0x0 0x00010000>, 1592 <0x0 0xf4000000 0x0 0x00100000>; 1593 reg-names = "dbi", "apb", "config"; 1594 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; 1595 reset-names = "pwr", "pipe"; 1596 #address-cells = <3>; 1597 #size-cells = <2>; 1598 status = "disabled"; 1599 1600 pcie2x1l2_intc: legacy-interrupt-controller { 1601 interrupt-controller; 1602 #address-cells = <0>; 1603 #interrupt-cells = <1>; 1604 interrupt-parent = <&gic>; 1605 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; 1606 }; 1607 }; 1608 1609 gmac1: ethernet@fe1c0000 { 1610 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1611 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1612 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, 1613 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 1614 interrupt-names = "macirq", "eth_wake_irq"; 1615 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 1616 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1617 <&cru CLK_GMAC1_PTP_REF>; 1618 clock-names = "stmmaceth", "clk_mac_ref", 1619 "pclk_mac", "aclk_mac", 1620 "ptp_ref"; 1621 power-domains = <&power RK3588_PD_GMAC>; 1622 resets = <&cru SRST_A_GMAC1>; 1623 reset-names = "stmmaceth"; 1624 rockchip,grf = <&sys_grf>; 1625 rockchip,php-grf = <&php_grf>; 1626 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1627 snps,mixed-burst; 1628 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1629 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1630 snps,tso; 1631 status = "disabled"; 1632 1633 mdio1: mdio { 1634 compatible = "snps,dwmac-mdio"; 1635 #address-cells = <0x1>; 1636 #size-cells = <0x0>; 1637 }; 1638 1639 gmac1_stmmac_axi_setup: stmmac-axi-config { 1640 snps,blen = <0 0 0 0 16 8 4>; 1641 snps,wr_osr_lmt = <4>; 1642 snps,rd_osr_lmt = <8>; 1643 }; 1644 1645 gmac1_mtl_rx_setup: rx-queues-config { 1646 snps,rx-queues-to-use = <2>; 1647 queue0 {}; 1648 queue1 {}; 1649 }; 1650 1651 gmac1_mtl_tx_setup: tx-queues-config { 1652 snps,tx-queues-to-use = <2>; 1653 queue0 {}; 1654 queue1 {}; 1655 }; 1656 }; 1657 1658 sata0: sata@fe210000 { 1659 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1660 reg = <0 0xfe210000 0 0x1000>; 1661 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; 1662 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1663 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, 1664 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; 1665 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1666 ports-implemented = <0x1>; 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 status = "disabled"; 1670 1671 sata-port@0 { 1672 reg = <0>; 1673 hba-port-cap = <HBA_PORT_FBSCP>; 1674 phys = <&combphy0_ps PHY_TYPE_SATA>; 1675 phy-names = "sata-phy"; 1676 snps,rx-ts-max = <32>; 1677 snps,tx-ts-max = <32>; 1678 }; 1679 }; 1680 1681 sata2: sata@fe230000 { 1682 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1683 reg = <0 0xfe230000 0 0x1000>; 1684 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; 1685 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 1686 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, 1687 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; 1688 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1689 ports-implemented = <0x1>; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 status = "disabled"; 1693 1694 sata-port@0 { 1695 reg = <0>; 1696 hba-port-cap = <HBA_PORT_FBSCP>; 1697 phys = <&combphy2_psu PHY_TYPE_SATA>; 1698 phy-names = "sata-phy"; 1699 snps,rx-ts-max = <32>; 1700 snps,tx-ts-max = <32>; 1701 }; 1702 }; 1703 1704 sfc: spi@fe2b0000 { 1705 compatible = "rockchip,sfc"; 1706 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1707 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; 1708 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1709 clock-names = "clk_sfc", "hclk_sfc"; 1710 #address-cells = <1>; 1711 #size-cells = <0>; 1712 status = "disabled"; 1713 }; 1714 1715 sdmmc: mmc@fe2c0000 { 1716 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1717 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1718 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 1719 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 1720 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1721 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1722 fifo-depth = <0x100>; 1723 max-frequency = <200000000>; 1724 pinctrl-names = "default"; 1725 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1726 power-domains = <&power RK3588_PD_SDMMC>; 1727 status = "disabled"; 1728 }; 1729 1730 sdio: mmc@fe2d0000 { 1731 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1732 reg = <0x00 0xfe2d0000 0x00 0x4000>; 1733 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; 1734 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 1735 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1736 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1737 fifo-depth = <0x100>; 1738 max-frequency = <200000000>; 1739 pinctrl-names = "default"; 1740 pinctrl-0 = <&sdiom1_pins>; 1741 power-domains = <&power RK3588_PD_SDIO>; 1742 status = "disabled"; 1743 }; 1744 1745 sdhci: mmc@fe2e0000 { 1746 compatible = "rockchip,rk3588-dwcmshc"; 1747 reg = <0x0 0xfe2e0000 0x0 0x10000>; 1748 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 1749 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 1750 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1751 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1752 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1753 <&cru TMCLK_EMMC>; 1754 clock-names = "core", "bus", "axi", "block", "timer"; 1755 max-frequency = <200000000>; 1756 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 1757 <&emmc_cmd>, <&emmc_data_strobe>; 1758 pinctrl-names = "default"; 1759 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1760 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1761 <&cru SRST_T_EMMC>; 1762 reset-names = "core", "bus", "axi", "block", "timer"; 1763 status = "disabled"; 1764 }; 1765 1766 i2s0_8ch: i2s@fe470000 { 1767 compatible = "rockchip,rk3588-i2s-tdm"; 1768 reg = <0x0 0xfe470000 0x0 0x1000>; 1769 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; 1770 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1771 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1772 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1773 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 1774 dmas = <&dmac0 0>, <&dmac0 1>; 1775 dma-names = "tx", "rx"; 1776 power-domains = <&power RK3588_PD_AUDIO>; 1777 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1778 reset-names = "tx-m", "rx-m"; 1779 rockchip,trcm-sync-tx-only; 1780 pinctrl-names = "default"; 1781 pinctrl-0 = <&i2s0_lrck 1782 &i2s0_sclk 1783 &i2s0_sdi0 1784 &i2s0_sdi1 1785 &i2s0_sdi2 1786 &i2s0_sdi3 1787 &i2s0_sdo0 1788 &i2s0_sdo1 1789 &i2s0_sdo2 1790 &i2s0_sdo3>; 1791 #sound-dai-cells = <0>; 1792 status = "disabled"; 1793 }; 1794 1795 i2s1_8ch: i2s@fe480000 { 1796 compatible = "rockchip,rk3588-i2s-tdm"; 1797 reg = <0x0 0xfe480000 0x0 0x1000>; 1798 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; 1799 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1800 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1801 dmas = <&dmac0 2>, <&dmac0 3>; 1802 dma-names = "tx", "rx"; 1803 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1804 reset-names = "tx-m", "rx-m"; 1805 rockchip,trcm-sync-tx-only; 1806 pinctrl-names = "default"; 1807 pinctrl-0 = <&i2s1m0_lrck 1808 &i2s1m0_sclk 1809 &i2s1m0_sdi0 1810 &i2s1m0_sdi1 1811 &i2s1m0_sdi2 1812 &i2s1m0_sdi3 1813 &i2s1m0_sdo0 1814 &i2s1m0_sdo1 1815 &i2s1m0_sdo2 1816 &i2s1m0_sdo3>; 1817 #sound-dai-cells = <0>; 1818 status = "disabled"; 1819 }; 1820 1821 i2s2_2ch: i2s@fe490000 { 1822 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1823 reg = <0x0 0xfe490000 0x0 0x1000>; 1824 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; 1825 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1826 clock-names = "i2s_clk", "i2s_hclk"; 1827 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1828 assigned-clock-parents = <&cru PLL_AUPLL>; 1829 dmas = <&dmac1 0>, <&dmac1 1>; 1830 dma-names = "tx", "rx"; 1831 power-domains = <&power RK3588_PD_AUDIO>; 1832 pinctrl-names = "default"; 1833 pinctrl-0 = <&i2s2m1_lrck 1834 &i2s2m1_sclk 1835 &i2s2m1_sdi 1836 &i2s2m1_sdo>; 1837 #sound-dai-cells = <0>; 1838 status = "disabled"; 1839 }; 1840 1841 i2s3_2ch: i2s@fe4a0000 { 1842 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1843 reg = <0x0 0xfe4a0000 0x0 0x1000>; 1844 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; 1845 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 1846 clock-names = "i2s_clk", "i2s_hclk"; 1847 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 1848 assigned-clock-parents = <&cru PLL_AUPLL>; 1849 dmas = <&dmac1 2>, <&dmac1 3>; 1850 dma-names = "tx", "rx"; 1851 power-domains = <&power RK3588_PD_AUDIO>; 1852 pinctrl-names = "default"; 1853 pinctrl-0 = <&i2s3_lrck 1854 &i2s3_sclk 1855 &i2s3_sdi 1856 &i2s3_sdo>; 1857 #sound-dai-cells = <0>; 1858 status = "disabled"; 1859 }; 1860 1861 gic: interrupt-controller@fe600000 { 1862 compatible = "arm,gic-v3"; 1863 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 1864 <0x0 0xfe680000 0 0x100000>; /* GICR */ 1865 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 1866 interrupt-controller; 1867 mbi-alias = <0x0 0xfe610000>; 1868 mbi-ranges = <424 56>; 1869 msi-controller; 1870 ranges; 1871 #address-cells = <2>; 1872 #interrupt-cells = <4>; 1873 #size-cells = <2>; 1874 1875 its0: msi-controller@fe640000 { 1876 compatible = "arm,gic-v3-its"; 1877 reg = <0x0 0xfe640000 0x0 0x20000>; 1878 msi-controller; 1879 #msi-cells = <1>; 1880 }; 1881 1882 its1: msi-controller@fe660000 { 1883 compatible = "arm,gic-v3-its"; 1884 reg = <0x0 0xfe660000 0x0 0x20000>; 1885 msi-controller; 1886 #msi-cells = <1>; 1887 }; 1888 1889 ppi-partitions { 1890 ppi_partition0: interrupt-partition-0 { 1891 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 1892 }; 1893 1894 ppi_partition1: interrupt-partition-1 { 1895 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; 1896 }; 1897 }; 1898 }; 1899 1900 dmac0: dma-controller@fea10000 { 1901 compatible = "arm,pl330", "arm,primecell"; 1902 reg = <0x0 0xfea10000 0x0 0x4000>; 1903 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, 1904 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; 1905 arm,pl330-periph-burst; 1906 clocks = <&cru ACLK_DMAC0>; 1907 clock-names = "apb_pclk"; 1908 #dma-cells = <1>; 1909 }; 1910 1911 dmac1: dma-controller@fea30000 { 1912 compatible = "arm,pl330", "arm,primecell"; 1913 reg = <0x0 0xfea30000 0x0 0x4000>; 1914 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, 1915 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; 1916 arm,pl330-periph-burst; 1917 clocks = <&cru ACLK_DMAC1>; 1918 clock-names = "apb_pclk"; 1919 #dma-cells = <1>; 1920 }; 1921 1922 i2c1: i2c@fea90000 { 1923 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1924 reg = <0x0 0xfea90000 0x0 0x1000>; 1925 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1926 clock-names = "i2c", "pclk"; 1927 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; 1928 pinctrl-0 = <&i2c1m0_xfer>; 1929 pinctrl-names = "default"; 1930 #address-cells = <1>; 1931 #size-cells = <0>; 1932 status = "disabled"; 1933 }; 1934 1935 i2c2: i2c@feaa0000 { 1936 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1937 reg = <0x0 0xfeaa0000 0x0 0x1000>; 1938 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1939 clock-names = "i2c", "pclk"; 1940 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; 1941 pinctrl-0 = <&i2c2m0_xfer>; 1942 pinctrl-names = "default"; 1943 #address-cells = <1>; 1944 #size-cells = <0>; 1945 status = "disabled"; 1946 }; 1947 1948 i2c3: i2c@feab0000 { 1949 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1950 reg = <0x0 0xfeab0000 0x0 0x1000>; 1951 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1952 clock-names = "i2c", "pclk"; 1953 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; 1954 pinctrl-0 = <&i2c3m0_xfer>; 1955 pinctrl-names = "default"; 1956 #address-cells = <1>; 1957 #size-cells = <0>; 1958 status = "disabled"; 1959 }; 1960 1961 i2c4: i2c@feac0000 { 1962 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1963 reg = <0x0 0xfeac0000 0x0 0x1000>; 1964 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1965 clock-names = "i2c", "pclk"; 1966 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; 1967 pinctrl-0 = <&i2c4m0_xfer>; 1968 pinctrl-names = "default"; 1969 #address-cells = <1>; 1970 #size-cells = <0>; 1971 status = "disabled"; 1972 }; 1973 1974 i2c5: i2c@fead0000 { 1975 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1976 reg = <0x0 0xfead0000 0x0 0x1000>; 1977 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1978 clock-names = "i2c", "pclk"; 1979 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; 1980 pinctrl-0 = <&i2c5m0_xfer>; 1981 pinctrl-names = "default"; 1982 #address-cells = <1>; 1983 #size-cells = <0>; 1984 status = "disabled"; 1985 }; 1986 1987 timer0: timer@feae0000 { 1988 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 1989 reg = <0x0 0xfeae0000 0x0 0x20>; 1990 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; 1991 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 1992 clock-names = "pclk", "timer"; 1993 }; 1994 1995 wdt: watchdog@feaf0000 { 1996 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; 1997 reg = <0x0 0xfeaf0000 0x0 0x100>; 1998 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 1999 clock-names = "tclk", "pclk"; 2000 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; 2001 }; 2002 2003 spi0: spi@feb00000 { 2004 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2005 reg = <0x0 0xfeb00000 0x0 0x1000>; 2006 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; 2007 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 2008 clock-names = "spiclk", "apb_pclk"; 2009 dmas = <&dmac0 14>, <&dmac0 15>; 2010 dma-names = "tx", "rx"; 2011 num-cs = <2>; 2012 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 2013 pinctrl-names = "default"; 2014 #address-cells = <1>; 2015 #size-cells = <0>; 2016 status = "disabled"; 2017 }; 2018 2019 spi1: spi@feb10000 { 2020 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2021 reg = <0x0 0xfeb10000 0x0 0x1000>; 2022 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; 2023 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 2024 clock-names = "spiclk", "apb_pclk"; 2025 dmas = <&dmac0 16>, <&dmac0 17>; 2026 dma-names = "tx", "rx"; 2027 num-cs = <2>; 2028 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 2029 pinctrl-names = "default"; 2030 #address-cells = <1>; 2031 #size-cells = <0>; 2032 status = "disabled"; 2033 }; 2034 2035 spi2: spi@feb20000 { 2036 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2037 reg = <0x0 0xfeb20000 0x0 0x1000>; 2038 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; 2039 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 2040 clock-names = "spiclk", "apb_pclk"; 2041 dmas = <&dmac1 15>, <&dmac1 16>; 2042 dma-names = "tx", "rx"; 2043 num-cs = <2>; 2044 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 2045 pinctrl-names = "default"; 2046 #address-cells = <1>; 2047 #size-cells = <0>; 2048 status = "disabled"; 2049 }; 2050 2051 spi3: spi@feb30000 { 2052 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2053 reg = <0x0 0xfeb30000 0x0 0x1000>; 2054 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; 2055 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 2056 clock-names = "spiclk", "apb_pclk"; 2057 dmas = <&dmac1 17>, <&dmac1 18>; 2058 dma-names = "tx", "rx"; 2059 num-cs = <2>; 2060 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 2061 pinctrl-names = "default"; 2062 #address-cells = <1>; 2063 #size-cells = <0>; 2064 status = "disabled"; 2065 }; 2066 2067 uart1: serial@feb40000 { 2068 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2069 reg = <0x0 0xfeb40000 0x0 0x100>; 2070 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; 2071 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 2072 clock-names = "baudclk", "apb_pclk"; 2073 dmas = <&dmac0 8>, <&dmac0 9>; 2074 dma-names = "tx", "rx"; 2075 pinctrl-0 = <&uart1m1_xfer>; 2076 pinctrl-names = "default"; 2077 reg-io-width = <4>; 2078 reg-shift = <2>; 2079 status = "disabled"; 2080 }; 2081 2082 uart2: serial@feb50000 { 2083 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2084 reg = <0x0 0xfeb50000 0x0 0x100>; 2085 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; 2086 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 2087 clock-names = "baudclk", "apb_pclk"; 2088 dmas = <&dmac0 10>, <&dmac0 11>; 2089 dma-names = "tx", "rx"; 2090 pinctrl-0 = <&uart2m1_xfer>; 2091 pinctrl-names = "default"; 2092 reg-io-width = <4>; 2093 reg-shift = <2>; 2094 status = "disabled"; 2095 }; 2096 2097 uart3: serial@feb60000 { 2098 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2099 reg = <0x0 0xfeb60000 0x0 0x100>; 2100 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; 2101 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 2102 clock-names = "baudclk", "apb_pclk"; 2103 dmas = <&dmac0 12>, <&dmac0 13>; 2104 dma-names = "tx", "rx"; 2105 pinctrl-0 = <&uart3m1_xfer>; 2106 pinctrl-names = "default"; 2107 reg-io-width = <4>; 2108 reg-shift = <2>; 2109 status = "disabled"; 2110 }; 2111 2112 uart4: serial@feb70000 { 2113 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2114 reg = <0x0 0xfeb70000 0x0 0x100>; 2115 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; 2116 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 2117 clock-names = "baudclk", "apb_pclk"; 2118 dmas = <&dmac1 9>, <&dmac1 10>; 2119 dma-names = "tx", "rx"; 2120 pinctrl-0 = <&uart4m1_xfer>; 2121 pinctrl-names = "default"; 2122 reg-io-width = <4>; 2123 reg-shift = <2>; 2124 status = "disabled"; 2125 }; 2126 2127 uart5: serial@feb80000 { 2128 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2129 reg = <0x0 0xfeb80000 0x0 0x100>; 2130 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; 2131 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2132 clock-names = "baudclk", "apb_pclk"; 2133 dmas = <&dmac1 11>, <&dmac1 12>; 2134 dma-names = "tx", "rx"; 2135 pinctrl-0 = <&uart5m1_xfer>; 2136 pinctrl-names = "default"; 2137 reg-io-width = <4>; 2138 reg-shift = <2>; 2139 status = "disabled"; 2140 }; 2141 2142 uart6: serial@feb90000 { 2143 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2144 reg = <0x0 0xfeb90000 0x0 0x100>; 2145 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; 2146 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2147 clock-names = "baudclk", "apb_pclk"; 2148 dmas = <&dmac1 13>, <&dmac1 14>; 2149 dma-names = "tx", "rx"; 2150 pinctrl-0 = <&uart6m1_xfer>; 2151 pinctrl-names = "default"; 2152 reg-io-width = <4>; 2153 reg-shift = <2>; 2154 status = "disabled"; 2155 }; 2156 2157 uart7: serial@feba0000 { 2158 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2159 reg = <0x0 0xfeba0000 0x0 0x100>; 2160 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; 2161 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2162 clock-names = "baudclk", "apb_pclk"; 2163 dmas = <&dmac2 7>, <&dmac2 8>; 2164 dma-names = "tx", "rx"; 2165 pinctrl-0 = <&uart7m1_xfer>; 2166 pinctrl-names = "default"; 2167 reg-io-width = <4>; 2168 reg-shift = <2>; 2169 status = "disabled"; 2170 }; 2171 2172 uart8: serial@febb0000 { 2173 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2174 reg = <0x0 0xfebb0000 0x0 0x100>; 2175 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; 2176 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2177 clock-names = "baudclk", "apb_pclk"; 2178 dmas = <&dmac2 9>, <&dmac2 10>; 2179 dma-names = "tx", "rx"; 2180 pinctrl-0 = <&uart8m1_xfer>; 2181 pinctrl-names = "default"; 2182 reg-io-width = <4>; 2183 reg-shift = <2>; 2184 status = "disabled"; 2185 }; 2186 2187 uart9: serial@febc0000 { 2188 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2189 reg = <0x0 0xfebc0000 0x0 0x100>; 2190 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; 2191 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2192 clock-names = "baudclk", "apb_pclk"; 2193 dmas = <&dmac2 11>, <&dmac2 12>; 2194 dma-names = "tx", "rx"; 2195 pinctrl-0 = <&uart9m1_xfer>; 2196 pinctrl-names = "default"; 2197 reg-io-width = <4>; 2198 reg-shift = <2>; 2199 status = "disabled"; 2200 }; 2201 2202 pwm4: pwm@febd0000 { 2203 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2204 reg = <0x0 0xfebd0000 0x0 0x10>; 2205 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2206 clock-names = "pwm", "pclk"; 2207 pinctrl-0 = <&pwm4m0_pins>; 2208 pinctrl-names = "default"; 2209 #pwm-cells = <3>; 2210 status = "disabled"; 2211 }; 2212 2213 pwm5: pwm@febd0010 { 2214 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2215 reg = <0x0 0xfebd0010 0x0 0x10>; 2216 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2217 clock-names = "pwm", "pclk"; 2218 pinctrl-0 = <&pwm5m0_pins>; 2219 pinctrl-names = "default"; 2220 #pwm-cells = <3>; 2221 status = "disabled"; 2222 }; 2223 2224 pwm6: pwm@febd0020 { 2225 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2226 reg = <0x0 0xfebd0020 0x0 0x10>; 2227 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2228 clock-names = "pwm", "pclk"; 2229 pinctrl-0 = <&pwm6m0_pins>; 2230 pinctrl-names = "default"; 2231 #pwm-cells = <3>; 2232 status = "disabled"; 2233 }; 2234 2235 pwm7: pwm@febd0030 { 2236 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2237 reg = <0x0 0xfebd0030 0x0 0x10>; 2238 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2239 clock-names = "pwm", "pclk"; 2240 pinctrl-0 = <&pwm7m0_pins>; 2241 pinctrl-names = "default"; 2242 #pwm-cells = <3>; 2243 status = "disabled"; 2244 }; 2245 2246 pwm8: pwm@febe0000 { 2247 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2248 reg = <0x0 0xfebe0000 0x0 0x10>; 2249 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2250 clock-names = "pwm", "pclk"; 2251 pinctrl-0 = <&pwm8m0_pins>; 2252 pinctrl-names = "default"; 2253 #pwm-cells = <3>; 2254 status = "disabled"; 2255 }; 2256 2257 pwm9: pwm@febe0010 { 2258 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2259 reg = <0x0 0xfebe0010 0x0 0x10>; 2260 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2261 clock-names = "pwm", "pclk"; 2262 pinctrl-0 = <&pwm9m0_pins>; 2263 pinctrl-names = "default"; 2264 #pwm-cells = <3>; 2265 status = "disabled"; 2266 }; 2267 2268 pwm10: pwm@febe0020 { 2269 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2270 reg = <0x0 0xfebe0020 0x0 0x10>; 2271 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2272 clock-names = "pwm", "pclk"; 2273 pinctrl-0 = <&pwm10m0_pins>; 2274 pinctrl-names = "default"; 2275 #pwm-cells = <3>; 2276 status = "disabled"; 2277 }; 2278 2279 pwm11: pwm@febe0030 { 2280 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2281 reg = <0x0 0xfebe0030 0x0 0x10>; 2282 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2283 clock-names = "pwm", "pclk"; 2284 pinctrl-0 = <&pwm11m0_pins>; 2285 pinctrl-names = "default"; 2286 #pwm-cells = <3>; 2287 status = "disabled"; 2288 }; 2289 2290 pwm12: pwm@febf0000 { 2291 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2292 reg = <0x0 0xfebf0000 0x0 0x10>; 2293 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2294 clock-names = "pwm", "pclk"; 2295 pinctrl-0 = <&pwm12m0_pins>; 2296 pinctrl-names = "default"; 2297 #pwm-cells = <3>; 2298 status = "disabled"; 2299 }; 2300 2301 pwm13: pwm@febf0010 { 2302 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2303 reg = <0x0 0xfebf0010 0x0 0x10>; 2304 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2305 clock-names = "pwm", "pclk"; 2306 pinctrl-0 = <&pwm13m0_pins>; 2307 pinctrl-names = "default"; 2308 #pwm-cells = <3>; 2309 status = "disabled"; 2310 }; 2311 2312 pwm14: pwm@febf0020 { 2313 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2314 reg = <0x0 0xfebf0020 0x0 0x10>; 2315 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2316 clock-names = "pwm", "pclk"; 2317 pinctrl-0 = <&pwm14m0_pins>; 2318 pinctrl-names = "default"; 2319 #pwm-cells = <3>; 2320 status = "disabled"; 2321 }; 2322 2323 pwm15: pwm@febf0030 { 2324 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2325 reg = <0x0 0xfebf0030 0x0 0x10>; 2326 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2327 clock-names = "pwm", "pclk"; 2328 pinctrl-0 = <&pwm15m0_pins>; 2329 pinctrl-names = "default"; 2330 #pwm-cells = <3>; 2331 status = "disabled"; 2332 }; 2333 2334 thermal_zones: thermal-zones { 2335 /* sensor near the center of the SoC */ 2336 package_thermal: package-thermal { 2337 polling-delay-passive = <0>; 2338 polling-delay = <0>; 2339 thermal-sensors = <&tsadc 0>; 2340 2341 trips { 2342 package_crit: package-crit { 2343 temperature = <115000>; 2344 hysteresis = <0>; 2345 type = "critical"; 2346 }; 2347 }; 2348 }; 2349 2350 /* sensor between A76 cores 0 and 1 */ 2351 bigcore0_thermal: bigcore0-thermal { 2352 polling-delay-passive = <100>; 2353 polling-delay = <0>; 2354 thermal-sensors = <&tsadc 1>; 2355 2356 trips { 2357 bigcore0_alert: bigcore0-alert { 2358 temperature = <85000>; 2359 hysteresis = <2000>; 2360 type = "passive"; 2361 }; 2362 2363 bigcore0_crit: bigcore0-crit { 2364 temperature = <115000>; 2365 hysteresis = <0>; 2366 type = "critical"; 2367 }; 2368 }; 2369 2370 cooling-maps { 2371 map0 { 2372 trip = <&bigcore0_alert>; 2373 cooling-device = 2374 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2375 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2376 }; 2377 }; 2378 }; 2379 2380 /* sensor between A76 cores 2 and 3 */ 2381 bigcore2_thermal: bigcore2-thermal { 2382 polling-delay-passive = <100>; 2383 polling-delay = <0>; 2384 thermal-sensors = <&tsadc 2>; 2385 2386 trips { 2387 bigcore2_alert: bigcore2-alert { 2388 temperature = <85000>; 2389 hysteresis = <2000>; 2390 type = "passive"; 2391 }; 2392 2393 bigcore2_crit: bigcore2-crit { 2394 temperature = <115000>; 2395 hysteresis = <0>; 2396 type = "critical"; 2397 }; 2398 }; 2399 2400 cooling-maps { 2401 map0 { 2402 trip = <&bigcore2_alert>; 2403 cooling-device = 2404 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2405 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2406 }; 2407 }; 2408 }; 2409 2410 /* sensor between the four A55 cores */ 2411 little_core_thermal: littlecore-thermal { 2412 polling-delay-passive = <100>; 2413 polling-delay = <0>; 2414 thermal-sensors = <&tsadc 3>; 2415 2416 trips { 2417 littlecore_alert: littlecore-alert { 2418 temperature = <85000>; 2419 hysteresis = <2000>; 2420 type = "passive"; 2421 }; 2422 2423 littlecore_crit: littlecore-crit { 2424 temperature = <115000>; 2425 hysteresis = <0>; 2426 type = "critical"; 2427 }; 2428 }; 2429 2430 cooling-maps { 2431 map0 { 2432 trip = <&littlecore_alert>; 2433 cooling-device = 2434 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2435 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2436 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2437 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2438 }; 2439 }; 2440 }; 2441 2442 /* sensor near the PD_CENTER power domain */ 2443 center_thermal: center-thermal { 2444 polling-delay-passive = <0>; 2445 polling-delay = <0>; 2446 thermal-sensors = <&tsadc 4>; 2447 2448 trips { 2449 center_crit: center-crit { 2450 temperature = <115000>; 2451 hysteresis = <0>; 2452 type = "critical"; 2453 }; 2454 }; 2455 }; 2456 2457 gpu_thermal: gpu-thermal { 2458 polling-delay-passive = <100>; 2459 polling-delay = <0>; 2460 thermal-sensors = <&tsadc 5>; 2461 2462 trips { 2463 gpu_alert: gpu-alert { 2464 temperature = <85000>; 2465 hysteresis = <2000>; 2466 type = "passive"; 2467 }; 2468 2469 gpu_crit: gpu-crit { 2470 temperature = <115000>; 2471 hysteresis = <0>; 2472 type = "critical"; 2473 }; 2474 }; 2475 2476 cooling-maps { 2477 map0 { 2478 trip = <&gpu_alert>; 2479 cooling-device = 2480 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2481 }; 2482 }; 2483 }; 2484 2485 npu_thermal: npu-thermal { 2486 polling-delay-passive = <0>; 2487 polling-delay = <0>; 2488 thermal-sensors = <&tsadc 6>; 2489 2490 trips { 2491 npu_crit: npu-crit { 2492 temperature = <115000>; 2493 hysteresis = <0>; 2494 type = "critical"; 2495 }; 2496 }; 2497 }; 2498 }; 2499 2500 tsadc: tsadc@fec00000 { 2501 compatible = "rockchip,rk3588-tsadc"; 2502 reg = <0x0 0xfec00000 0x0 0x400>; 2503 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; 2504 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2505 clock-names = "tsadc", "apb_pclk"; 2506 assigned-clocks = <&cru CLK_TSADC>; 2507 assigned-clock-rates = <2000000>; 2508 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 2509 reset-names = "tsadc-apb", "tsadc"; 2510 rockchip,hw-tshut-temp = <120000>; 2511 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 2512 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2513 pinctrl-0 = <&tsadc_gpio_func>; 2514 pinctrl-1 = <&tsadc_shut>; 2515 pinctrl-names = "gpio", "otpout"; 2516 #thermal-sensor-cells = <1>; 2517 status = "disabled"; 2518 }; 2519 2520 saradc: adc@fec10000 { 2521 compatible = "rockchip,rk3588-saradc"; 2522 reg = <0x0 0xfec10000 0x0 0x10000>; 2523 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; 2524 #io-channel-cells = <1>; 2525 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2526 clock-names = "saradc", "apb_pclk"; 2527 resets = <&cru SRST_P_SARADC>; 2528 reset-names = "saradc-apb"; 2529 status = "disabled"; 2530 }; 2531 2532 i2c6: i2c@fec80000 { 2533 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2534 reg = <0x0 0xfec80000 0x0 0x1000>; 2535 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2536 clock-names = "i2c", "pclk"; 2537 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; 2538 pinctrl-0 = <&i2c6m0_xfer>; 2539 pinctrl-names = "default"; 2540 #address-cells = <1>; 2541 #size-cells = <0>; 2542 status = "disabled"; 2543 }; 2544 2545 i2c7: i2c@fec90000 { 2546 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2547 reg = <0x0 0xfec90000 0x0 0x1000>; 2548 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2549 clock-names = "i2c", "pclk"; 2550 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 2551 pinctrl-0 = <&i2c7m0_xfer>; 2552 pinctrl-names = "default"; 2553 #address-cells = <1>; 2554 #size-cells = <0>; 2555 status = "disabled"; 2556 }; 2557 2558 i2c8: i2c@feca0000 { 2559 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2560 reg = <0x0 0xfeca0000 0x0 0x1000>; 2561 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2562 clock-names = "i2c", "pclk"; 2563 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; 2564 pinctrl-0 = <&i2c8m0_xfer>; 2565 pinctrl-names = "default"; 2566 #address-cells = <1>; 2567 #size-cells = <0>; 2568 status = "disabled"; 2569 }; 2570 2571 spi4: spi@fecb0000 { 2572 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2573 reg = <0x0 0xfecb0000 0x0 0x1000>; 2574 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; 2575 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2576 clock-names = "spiclk", "apb_pclk"; 2577 dmas = <&dmac2 13>, <&dmac2 14>; 2578 dma-names = "tx", "rx"; 2579 num-cs = <2>; 2580 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 2581 pinctrl-names = "default"; 2582 #address-cells = <1>; 2583 #size-cells = <0>; 2584 status = "disabled"; 2585 }; 2586 2587 otp: efuse@fecc0000 { 2588 compatible = "rockchip,rk3588-otp"; 2589 reg = <0x0 0xfecc0000 0x0 0x400>; 2590 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 2591 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; 2592 clock-names = "otp", "apb_pclk", "phy", "arb"; 2593 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 2594 <&cru SRST_OTPC_ARB>; 2595 reset-names = "otp", "apb", "arb"; 2596 #address-cells = <1>; 2597 #size-cells = <1>; 2598 2599 cpu_code: cpu-code@2 { 2600 reg = <0x02 0x2>; 2601 }; 2602 2603 otp_id: id@7 { 2604 reg = <0x07 0x10>; 2605 }; 2606 2607 cpub0_leakage: cpu-leakage@17 { 2608 reg = <0x17 0x1>; 2609 }; 2610 2611 cpub1_leakage: cpu-leakage@18 { 2612 reg = <0x18 0x1>; 2613 }; 2614 2615 cpul_leakage: cpu-leakage@19 { 2616 reg = <0x19 0x1>; 2617 }; 2618 2619 log_leakage: log-leakage@1a { 2620 reg = <0x1a 0x1>; 2621 }; 2622 2623 gpu_leakage: gpu-leakage@1b { 2624 reg = <0x1b 0x1>; 2625 }; 2626 2627 otp_cpu_version: cpu-version@1c { 2628 reg = <0x1c 0x1>; 2629 bits = <3 3>; 2630 }; 2631 2632 npu_leakage: npu-leakage@28 { 2633 reg = <0x28 0x1>; 2634 }; 2635 2636 codec_leakage: codec-leakage@29 { 2637 reg = <0x29 0x1>; 2638 }; 2639 }; 2640 2641 dmac2: dma-controller@fed10000 { 2642 compatible = "arm,pl330", "arm,primecell"; 2643 reg = <0x0 0xfed10000 0x0 0x4000>; 2644 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, 2645 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; 2646 arm,pl330-periph-burst; 2647 clocks = <&cru ACLK_DMAC2>; 2648 clock-names = "apb_pclk"; 2649 #dma-cells = <1>; 2650 }; 2651 2652 hdptxphy_hdmi0: phy@fed60000 { 2653 compatible = "rockchip,rk3588-hdptx-phy"; 2654 reg = <0x0 0xfed60000 0x0 0x2000>; 2655 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 2656 clock-names = "ref", "apb"; 2657 #phy-cells = <0>; 2658 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, 2659 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, 2660 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, 2661 <&cru SRST_HDPTX0_LCPLL>; 2662 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 2663 "lcpll"; 2664 rockchip,grf = <&hdptxphy0_grf>; 2665 status = "disabled"; 2666 }; 2667 2668 usbdp_phy0: phy@fed80000 { 2669 compatible = "rockchip,rk3588-usbdp-phy"; 2670 reg = <0x0 0xfed80000 0x0 0x10000>; 2671 #phy-cells = <1>; 2672 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 2673 <&cru CLK_USBDP_PHY0_IMMORTAL>, 2674 <&cru PCLK_USBDPPHY0>, 2675 <&u2phy0>; 2676 clock-names = "refclk", "immortal", "pclk", "utmi"; 2677 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 2678 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 2679 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 2680 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 2681 <&cru SRST_P_USBDPPHY0>; 2682 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 2683 rockchip,u2phy-grf = <&usb2phy0_grf>; 2684 rockchip,usb-grf = <&usb_grf>; 2685 rockchip,usbdpphy-grf = <&usbdpphy0_grf>; 2686 rockchip,vo-grf = <&vo0_grf>; 2687 status = "disabled"; 2688 }; 2689 2690 combphy0_ps: phy@fee00000 { 2691 compatible = "rockchip,rk3588-naneng-combphy"; 2692 reg = <0x0 0xfee00000 0x0 0x100>; 2693 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, 2694 <&cru PCLK_PHP_ROOT>; 2695 clock-names = "ref", "apb", "pipe"; 2696 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 2697 assigned-clock-rates = <100000000>; 2698 #phy-cells = <1>; 2699 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; 2700 reset-names = "phy", "apb"; 2701 rockchip,pipe-grf = <&php_grf>; 2702 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 2703 status = "disabled"; 2704 }; 2705 2706 combphy2_psu: phy@fee20000 { 2707 compatible = "rockchip,rk3588-naneng-combphy"; 2708 reg = <0x0 0xfee20000 0x0 0x100>; 2709 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, 2710 <&cru PCLK_PHP_ROOT>; 2711 clock-names = "ref", "apb", "pipe"; 2712 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 2713 assigned-clock-rates = <100000000>; 2714 #phy-cells = <1>; 2715 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; 2716 reset-names = "phy", "apb"; 2717 rockchip,pipe-grf = <&php_grf>; 2718 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 2719 status = "disabled"; 2720 }; 2721 2722 system_sram2: sram@ff001000 { 2723 compatible = "mmio-sram"; 2724 reg = <0x0 0xff001000 0x0 0xef000>; 2725 ranges = <0x0 0x0 0xff001000 0xef000>; 2726 #address-cells = <1>; 2727 #size-cells = <1>; 2728 }; 2729 2730 pinctrl: pinctrl { 2731 compatible = "rockchip,rk3588-pinctrl"; 2732 ranges; 2733 rockchip,grf = <&ioc>; 2734 #address-cells = <2>; 2735 #size-cells = <2>; 2736 2737 gpio0: gpio@fd8a0000 { 2738 compatible = "rockchip,gpio-bank"; 2739 reg = <0x0 0xfd8a0000 0x0 0x100>; 2740 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 2741 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 2742 gpio-controller; 2743 gpio-ranges = <&pinctrl 0 0 32>; 2744 interrupt-controller; 2745 #gpio-cells = <2>; 2746 #interrupt-cells = <2>; 2747 }; 2748 2749 gpio1: gpio@fec20000 { 2750 compatible = "rockchip,gpio-bank"; 2751 reg = <0x0 0xfec20000 0x0 0x100>; 2752 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; 2753 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2754 gpio-controller; 2755 gpio-ranges = <&pinctrl 0 32 32>; 2756 interrupt-controller; 2757 #gpio-cells = <2>; 2758 #interrupt-cells = <2>; 2759 }; 2760 2761 gpio2: gpio@fec30000 { 2762 compatible = "rockchip,gpio-bank"; 2763 reg = <0x0 0xfec30000 0x0 0x100>; 2764 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; 2765 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2766 gpio-controller; 2767 gpio-ranges = <&pinctrl 0 64 32>; 2768 interrupt-controller; 2769 #gpio-cells = <2>; 2770 #interrupt-cells = <2>; 2771 }; 2772 2773 gpio3: gpio@fec40000 { 2774 compatible = "rockchip,gpio-bank"; 2775 reg = <0x0 0xfec40000 0x0 0x100>; 2776 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; 2777 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2778 gpio-controller; 2779 gpio-ranges = <&pinctrl 0 96 32>; 2780 interrupt-controller; 2781 #gpio-cells = <2>; 2782 #interrupt-cells = <2>; 2783 }; 2784 2785 gpio4: gpio@fec50000 { 2786 compatible = "rockchip,gpio-bank"; 2787 reg = <0x0 0xfec50000 0x0 0x100>; 2788 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; 2789 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2790 gpio-controller; 2791 gpio-ranges = <&pinctrl 0 128 32>; 2792 interrupt-controller; 2793 #gpio-cells = <2>; 2794 #interrupt-cells = <2>; 2795 }; 2796 }; 2797}; 2798 2799#include "rk3588-base-pinctrl.dtsi" 2800