1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/power/rk3588-power.h> 10#include <dt-bindings/reset/rockchip,rk3588-cru.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/ata/ahci.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3588"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 gpio4 = &gpio4; 28 i2c0 = &i2c0; 29 i2c1 = &i2c1; 30 i2c2 = &i2c2; 31 i2c3 = &i2c3; 32 i2c4 = &i2c4; 33 i2c5 = &i2c5; 34 i2c6 = &i2c6; 35 i2c7 = &i2c7; 36 i2c8 = &i2c8; 37 serial0 = &uart0; 38 serial1 = &uart1; 39 serial2 = &uart2; 40 serial3 = &uart3; 41 serial4 = &uart4; 42 serial5 = &uart5; 43 serial6 = &uart6; 44 serial7 = &uart7; 45 serial8 = &uart8; 46 serial9 = &uart9; 47 spi0 = &spi0; 48 spi1 = &spi1; 49 spi2 = &spi2; 50 spi3 = &spi3; 51 spi4 = &spi4; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu_l0>; 62 }; 63 core1 { 64 cpu = <&cpu_l1>; 65 }; 66 core2 { 67 cpu = <&cpu_l2>; 68 }; 69 core3 { 70 cpu = <&cpu_l3>; 71 }; 72 }; 73 cluster1 { 74 core0 { 75 cpu = <&cpu_b0>; 76 }; 77 core1 { 78 cpu = <&cpu_b1>; 79 }; 80 }; 81 cluster2 { 82 core0 { 83 cpu = <&cpu_b2>; 84 }; 85 core1 { 86 cpu = <&cpu_b3>; 87 }; 88 }; 89 }; 90 91 cpu_l0: cpu@0 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0>; 95 enable-method = "psci"; 96 capacity-dmips-mhz = <530>; 97 clocks = <&scmi_clk SCMI_CLK_CPUL>; 98 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; 99 assigned-clock-rates = <816000000>; 100 cpu-idle-states = <&CPU_SLEEP>; 101 i-cache-size = <32768>; 102 i-cache-line-size = <64>; 103 i-cache-sets = <128>; 104 d-cache-size = <32768>; 105 d-cache-line-size = <64>; 106 d-cache-sets = <128>; 107 next-level-cache = <&l2_cache_l0>; 108 dynamic-power-coefficient = <228>; 109 #cooling-cells = <2>; 110 }; 111 112 cpu_l1: cpu@100 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a55"; 115 reg = <0x100>; 116 enable-method = "psci"; 117 capacity-dmips-mhz = <530>; 118 clocks = <&scmi_clk SCMI_CLK_CPUL>; 119 cpu-idle-states = <&CPU_SLEEP>; 120 i-cache-size = <32768>; 121 i-cache-line-size = <64>; 122 i-cache-sets = <128>; 123 d-cache-size = <32768>; 124 d-cache-line-size = <64>; 125 d-cache-sets = <128>; 126 next-level-cache = <&l2_cache_l1>; 127 dynamic-power-coefficient = <228>; 128 #cooling-cells = <2>; 129 }; 130 131 cpu_l2: cpu@200 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a55"; 134 reg = <0x200>; 135 enable-method = "psci"; 136 capacity-dmips-mhz = <530>; 137 clocks = <&scmi_clk SCMI_CLK_CPUL>; 138 cpu-idle-states = <&CPU_SLEEP>; 139 i-cache-size = <32768>; 140 i-cache-line-size = <64>; 141 i-cache-sets = <128>; 142 d-cache-size = <32768>; 143 d-cache-line-size = <64>; 144 d-cache-sets = <128>; 145 next-level-cache = <&l2_cache_l2>; 146 dynamic-power-coefficient = <228>; 147 #cooling-cells = <2>; 148 }; 149 150 cpu_l3: cpu@300 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a55"; 153 reg = <0x300>; 154 enable-method = "psci"; 155 capacity-dmips-mhz = <530>; 156 clocks = <&scmi_clk SCMI_CLK_CPUL>; 157 cpu-idle-states = <&CPU_SLEEP>; 158 i-cache-size = <32768>; 159 i-cache-line-size = <64>; 160 i-cache-sets = <128>; 161 d-cache-size = <32768>; 162 d-cache-line-size = <64>; 163 d-cache-sets = <128>; 164 next-level-cache = <&l2_cache_l3>; 165 dynamic-power-coefficient = <228>; 166 #cooling-cells = <2>; 167 }; 168 169 cpu_b0: cpu@400 { 170 device_type = "cpu"; 171 compatible = "arm,cortex-a76"; 172 reg = <0x400>; 173 enable-method = "psci"; 174 capacity-dmips-mhz = <1024>; 175 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 176 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; 177 assigned-clock-rates = <816000000>; 178 cpu-idle-states = <&CPU_SLEEP>; 179 i-cache-size = <65536>; 180 i-cache-line-size = <64>; 181 i-cache-sets = <256>; 182 d-cache-size = <65536>; 183 d-cache-line-size = <64>; 184 d-cache-sets = <256>; 185 next-level-cache = <&l2_cache_b0>; 186 dynamic-power-coefficient = <416>; 187 #cooling-cells = <2>; 188 }; 189 190 cpu_b1: cpu@500 { 191 device_type = "cpu"; 192 compatible = "arm,cortex-a76"; 193 reg = <0x500>; 194 enable-method = "psci"; 195 capacity-dmips-mhz = <1024>; 196 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 197 cpu-idle-states = <&CPU_SLEEP>; 198 i-cache-size = <65536>; 199 i-cache-line-size = <64>; 200 i-cache-sets = <256>; 201 d-cache-size = <65536>; 202 d-cache-line-size = <64>; 203 d-cache-sets = <256>; 204 next-level-cache = <&l2_cache_b1>; 205 dynamic-power-coefficient = <416>; 206 #cooling-cells = <2>; 207 }; 208 209 cpu_b2: cpu@600 { 210 device_type = "cpu"; 211 compatible = "arm,cortex-a76"; 212 reg = <0x600>; 213 enable-method = "psci"; 214 capacity-dmips-mhz = <1024>; 215 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 216 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; 217 assigned-clock-rates = <816000000>; 218 cpu-idle-states = <&CPU_SLEEP>; 219 i-cache-size = <65536>; 220 i-cache-line-size = <64>; 221 i-cache-sets = <256>; 222 d-cache-size = <65536>; 223 d-cache-line-size = <64>; 224 d-cache-sets = <256>; 225 next-level-cache = <&l2_cache_b2>; 226 dynamic-power-coefficient = <416>; 227 #cooling-cells = <2>; 228 }; 229 230 cpu_b3: cpu@700 { 231 device_type = "cpu"; 232 compatible = "arm,cortex-a76"; 233 reg = <0x700>; 234 enable-method = "psci"; 235 capacity-dmips-mhz = <1024>; 236 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 237 cpu-idle-states = <&CPU_SLEEP>; 238 i-cache-size = <65536>; 239 i-cache-line-size = <64>; 240 i-cache-sets = <256>; 241 d-cache-size = <65536>; 242 d-cache-line-size = <64>; 243 d-cache-sets = <256>; 244 next-level-cache = <&l2_cache_b3>; 245 dynamic-power-coefficient = <416>; 246 #cooling-cells = <2>; 247 }; 248 249 idle-states { 250 entry-method = "psci"; 251 CPU_SLEEP: cpu-sleep { 252 compatible = "arm,idle-state"; 253 local-timer-stop; 254 arm,psci-suspend-param = <0x0010000>; 255 entry-latency-us = <100>; 256 exit-latency-us = <120>; 257 min-residency-us = <1000>; 258 }; 259 }; 260 261 l2_cache_l0: l2-cache-l0 { 262 compatible = "cache"; 263 cache-size = <131072>; 264 cache-line-size = <64>; 265 cache-sets = <512>; 266 cache-level = <2>; 267 cache-unified; 268 next-level-cache = <&l3_cache>; 269 }; 270 271 l2_cache_l1: l2-cache-l1 { 272 compatible = "cache"; 273 cache-size = <131072>; 274 cache-line-size = <64>; 275 cache-sets = <512>; 276 cache-level = <2>; 277 cache-unified; 278 next-level-cache = <&l3_cache>; 279 }; 280 281 l2_cache_l2: l2-cache-l2 { 282 compatible = "cache"; 283 cache-size = <131072>; 284 cache-line-size = <64>; 285 cache-sets = <512>; 286 cache-level = <2>; 287 cache-unified; 288 next-level-cache = <&l3_cache>; 289 }; 290 291 l2_cache_l3: l2-cache-l3 { 292 compatible = "cache"; 293 cache-size = <131072>; 294 cache-line-size = <64>; 295 cache-sets = <512>; 296 cache-level = <2>; 297 cache-unified; 298 next-level-cache = <&l3_cache>; 299 }; 300 301 l2_cache_b0: l2-cache-b0 { 302 compatible = "cache"; 303 cache-size = <524288>; 304 cache-line-size = <64>; 305 cache-sets = <1024>; 306 cache-level = <2>; 307 cache-unified; 308 next-level-cache = <&l3_cache>; 309 }; 310 311 l2_cache_b1: l2-cache-b1 { 312 compatible = "cache"; 313 cache-size = <524288>; 314 cache-line-size = <64>; 315 cache-sets = <1024>; 316 cache-level = <2>; 317 cache-unified; 318 next-level-cache = <&l3_cache>; 319 }; 320 321 l2_cache_b2: l2-cache-b2 { 322 compatible = "cache"; 323 cache-size = <524288>; 324 cache-line-size = <64>; 325 cache-sets = <1024>; 326 cache-level = <2>; 327 cache-unified; 328 next-level-cache = <&l3_cache>; 329 }; 330 331 l2_cache_b3: l2-cache-b3 { 332 compatible = "cache"; 333 cache-size = <524288>; 334 cache-line-size = <64>; 335 cache-sets = <1024>; 336 cache-level = <2>; 337 cache-unified; 338 next-level-cache = <&l3_cache>; 339 }; 340 }; 341 342 /* 343 * The L3 cache belongs to the DynamIQ Shared Unit (DSU), 344 * so it's represented here, outside the "cpus" node 345 */ 346 l3_cache: l3-cache { 347 compatible = "cache"; 348 cache-size = <3145728>; 349 cache-line-size = <64>; 350 cache-sets = <4096>; 351 cache-level = <3>; 352 cache-unified; 353 }; 354 355 display_subsystem: display-subsystem { 356 compatible = "rockchip,display-subsystem"; 357 ports = <&vop_out>; 358 }; 359 360 firmware { 361 optee: optee { 362 compatible = "linaro,optee-tz"; 363 method = "smc"; 364 }; 365 366 scmi: scmi { 367 compatible = "arm,scmi-smc"; 368 arm,smc-id = <0x82000010>; 369 shmem = <&scmi_shmem>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 373 scmi_clk: protocol@14 { 374 reg = <0x14>; 375 #clock-cells = <1>; 376 }; 377 378 scmi_reset: protocol@16 { 379 reg = <0x16>; 380 #reset-cells = <1>; 381 }; 382 }; 383 }; 384 385 pmu-a55 { 386 compatible = "arm,cortex-a55-pmu"; 387 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; 388 }; 389 390 pmu-a76 { 391 compatible = "arm,cortex-a76-pmu"; 392 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; 393 }; 394 395 psci { 396 compatible = "arm,psci-1.0"; 397 method = "smc"; 398 }; 399 400 spll: clock-0 { 401 compatible = "fixed-clock"; 402 clock-frequency = <702000000>; 403 clock-output-names = "spll"; 404 #clock-cells = <0>; 405 }; 406 407 timer { 408 compatible = "arm,armv8-timer"; 409 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 410 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 411 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 412 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, 413 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 414 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 415 }; 416 417 xin24m: clock-1 { 418 compatible = "fixed-clock"; 419 clock-frequency = <24000000>; 420 clock-output-names = "xin24m"; 421 #clock-cells = <0>; 422 }; 423 424 xin32k: clock-2 { 425 compatible = "fixed-clock"; 426 clock-frequency = <32768>; 427 clock-output-names = "xin32k"; 428 #clock-cells = <0>; 429 }; 430 431 pmu_sram: sram@10f000 { 432 compatible = "mmio-sram"; 433 reg = <0x0 0x0010f000 0x0 0x100>; 434 ranges = <0 0x0 0x0010f000 0x100>; 435 #address-cells = <1>; 436 #size-cells = <1>; 437 438 scmi_shmem: sram@0 { 439 compatible = "arm,scmi-shmem"; 440 reg = <0x0 0x100>; 441 }; 442 }; 443 444 gpu: gpu@fb000000 { 445 compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; 446 reg = <0x0 0xfb000000 0x0 0x200000>; 447 #cooling-cells = <2>; 448 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 449 assigned-clock-rates = <200000000>; 450 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, 451 <&cru CLK_GPU_STACKS>; 452 clock-names = "core", "coregroup", "stacks"; 453 dynamic-power-coefficient = <2982>; 454 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, 455 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, 456 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>; 457 interrupt-names = "job", "mmu", "gpu"; 458 power-domains = <&power RK3588_PD_GPU>; 459 status = "disabled"; 460 }; 461 462 usb_host0_xhci: usb@fc000000 { 463 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 464 reg = <0x0 0xfc000000 0x0 0x400000>; 465 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 466 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, 467 <&cru ACLK_USB3OTG0>; 468 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 469 dr_mode = "otg"; 470 phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; 471 phy-names = "usb2-phy", "usb3-phy"; 472 phy_type = "utmi_wide"; 473 power-domains = <&power RK3588_PD_USB>; 474 resets = <&cru SRST_A_USB3OTG0>; 475 snps,dis_enblslpm_quirk; 476 snps,dis-u1-entry-quirk; 477 snps,dis-u2-entry-quirk; 478 snps,dis-u2-freeclk-exists-quirk; 479 snps,dis-del-phy-power-chg-quirk; 480 snps,dis-tx-ipgap-linecheck-quirk; 481 status = "disabled"; 482 }; 483 484 usb_host0_ehci: usb@fc800000 { 485 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 486 reg = <0x0 0xfc800000 0x0 0x40000>; 487 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; 488 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 489 phys = <&u2phy2_host>; 490 phy-names = "usb"; 491 power-domains = <&power RK3588_PD_USB>; 492 status = "disabled"; 493 }; 494 495 usb_host0_ohci: usb@fc840000 { 496 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 497 reg = <0x0 0xfc840000 0x0 0x40000>; 498 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; 499 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 500 phys = <&u2phy2_host>; 501 phy-names = "usb"; 502 power-domains = <&power RK3588_PD_USB>; 503 status = "disabled"; 504 }; 505 506 usb_host1_ehci: usb@fc880000 { 507 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 508 reg = <0x0 0xfc880000 0x0 0x40000>; 509 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; 510 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 511 phys = <&u2phy3_host>; 512 phy-names = "usb"; 513 power-domains = <&power RK3588_PD_USB>; 514 status = "disabled"; 515 }; 516 517 usb_host1_ohci: usb@fc8c0000 { 518 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 519 reg = <0x0 0xfc8c0000 0x0 0x40000>; 520 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; 521 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 522 phys = <&u2phy3_host>; 523 phy-names = "usb"; 524 power-domains = <&power RK3588_PD_USB>; 525 status = "disabled"; 526 }; 527 528 usb_host2_xhci: usb@fcd00000 { 529 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 530 reg = <0x0 0xfcd00000 0x0 0x400000>; 531 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; 532 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, 533 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, 534 <&cru CLK_PIPEPHY2_PIPE_U3_G>; 535 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; 536 dr_mode = "host"; 537 phys = <&combphy2_psu PHY_TYPE_USB3>; 538 phy-names = "usb3-phy"; 539 phy_type = "utmi_wide"; 540 resets = <&cru SRST_A_USB3OTG2>; 541 snps,dis_enblslpm_quirk; 542 snps,dis-u2-freeclk-exists-quirk; 543 snps,dis-del-phy-power-chg-quirk; 544 snps,dis-tx-ipgap-linecheck-quirk; 545 snps,dis_rxdet_inp3_quirk; 546 status = "disabled"; 547 }; 548 549 mmu600_pcie: iommu@fc900000 { 550 compatible = "arm,smmu-v3"; 551 reg = <0x0 0xfc900000 0x0 0x200000>; 552 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>, 553 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>, 554 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, 555 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>; 556 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 557 #iommu-cells = <1>; 558 status = "disabled"; 559 }; 560 561 mmu600_php: iommu@fcb00000 { 562 compatible = "arm,smmu-v3"; 563 reg = <0x0 0xfcb00000 0x0 0x200000>; 564 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>, 565 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, 566 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>, 567 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; 568 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 569 #iommu-cells = <1>; 570 status = "disabled"; 571 }; 572 573 pmu1grf: syscon@fd58a000 { 574 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; 575 reg = <0x0 0xfd58a000 0x0 0x10000>; 576 }; 577 578 sys_grf: syscon@fd58c000 { 579 compatible = "rockchip,rk3588-sys-grf", "syscon"; 580 reg = <0x0 0xfd58c000 0x0 0x1000>; 581 }; 582 583 vop_grf: syscon@fd5a4000 { 584 compatible = "rockchip,rk3588-vop-grf", "syscon"; 585 reg = <0x0 0xfd5a4000 0x0 0x2000>; 586 }; 587 588 vo0_grf: syscon@fd5a6000 { 589 compatible = "rockchip,rk3588-vo0-grf", "syscon"; 590 reg = <0x0 0xfd5a6000 0x0 0x2000>; 591 clocks = <&cru PCLK_VO0GRF>; 592 }; 593 594 vo1_grf: syscon@fd5a8000 { 595 compatible = "rockchip,rk3588-vo1-grf", "syscon"; 596 reg = <0x0 0xfd5a8000 0x0 0x4000>; 597 clocks = <&cru PCLK_VO1GRF>; 598 }; 599 600 usb_grf: syscon@fd5ac000 { 601 compatible = "rockchip,rk3588-usb-grf", "syscon"; 602 reg = <0x0 0xfd5ac000 0x0 0x4000>; 603 }; 604 605 php_grf: syscon@fd5b0000 { 606 compatible = "rockchip,rk3588-php-grf", "syscon"; 607 reg = <0x0 0xfd5b0000 0x0 0x1000>; 608 }; 609 610 pipe_phy0_grf: syscon@fd5bc000 { 611 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 612 reg = <0x0 0xfd5bc000 0x0 0x100>; 613 }; 614 615 pipe_phy2_grf: syscon@fd5c4000 { 616 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 617 reg = <0x0 0xfd5c4000 0x0 0x100>; 618 }; 619 620 usbdpphy0_grf: syscon@fd5c8000 { 621 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 622 reg = <0x0 0xfd5c8000 0x0 0x4000>; 623 }; 624 625 usb2phy0_grf: syscon@fd5d0000 { 626 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 627 reg = <0x0 0xfd5d0000 0x0 0x4000>; 628 #address-cells = <1>; 629 #size-cells = <1>; 630 631 u2phy0: usb2phy@0 { 632 compatible = "rockchip,rk3588-usb2phy"; 633 reg = <0x0 0x10>; 634 #clock-cells = <0>; 635 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 636 clock-names = "phyclk"; 637 clock-output-names = "usb480m_phy0"; 638 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; 639 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; 640 reset-names = "phy", "apb"; 641 status = "disabled"; 642 643 u2phy0_otg: otg-port { 644 #phy-cells = <0>; 645 status = "disabled"; 646 }; 647 }; 648 }; 649 650 usb2phy2_grf: syscon@fd5d8000 { 651 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 652 reg = <0x0 0xfd5d8000 0x0 0x4000>; 653 #address-cells = <1>; 654 #size-cells = <1>; 655 656 u2phy2: usb2phy@8000 { 657 compatible = "rockchip,rk3588-usb2phy"; 658 reg = <0x8000 0x10>; 659 #clock-cells = <0>; 660 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 661 clock-names = "phyclk"; 662 clock-output-names = "usb480m_phy2"; 663 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 664 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 665 reset-names = "phy", "apb"; 666 status = "disabled"; 667 668 u2phy2_host: host-port { 669 #phy-cells = <0>; 670 status = "disabled"; 671 }; 672 }; 673 }; 674 675 usb2phy3_grf: syscon@fd5dc000 { 676 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 677 reg = <0x0 0xfd5dc000 0x0 0x4000>; 678 #address-cells = <1>; 679 #size-cells = <1>; 680 681 u2phy3: usb2phy@c000 { 682 compatible = "rockchip,rk3588-usb2phy"; 683 reg = <0xc000 0x10>; 684 #clock-cells = <0>; 685 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 686 clock-names = "phyclk"; 687 clock-output-names = "usb480m_phy3"; 688 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 689 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 690 reset-names = "phy", "apb"; 691 status = "disabled"; 692 693 u2phy3_host: host-port { 694 #phy-cells = <0>; 695 status = "disabled"; 696 }; 697 }; 698 }; 699 700 hdptxphy0_grf: syscon@fd5e0000 { 701 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 702 reg = <0x0 0xfd5e0000 0x0 0x100>; 703 }; 704 705 ioc: syscon@fd5f0000 { 706 compatible = "rockchip,rk3588-ioc", "syscon"; 707 reg = <0x0 0xfd5f0000 0x0 0x10000>; 708 }; 709 710 system_sram1: sram@fd600000 { 711 compatible = "mmio-sram"; 712 reg = <0x0 0xfd600000 0x0 0x100000>; 713 ranges = <0x0 0x0 0xfd600000 0x100000>; 714 #address-cells = <1>; 715 #size-cells = <1>; 716 }; 717 718 cru: clock-controller@fd7c0000 { 719 compatible = "rockchip,rk3588-cru"; 720 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 721 assigned-clocks = 722 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 723 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 724 <&cru ACLK_CENTER_ROOT>, 725 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 726 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 727 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 728 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, 729 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 730 <&cru CLK_GPU>; 731 assigned-clock-rates = 732 <1100000000>, <786432000>, 733 <850000000>, <1188000000>, 734 <702000000>, 735 <400000000>, <500000000>, 736 <800000000>, <100000000>, 737 <400000000>, <100000000>, 738 <200000000>, <500000000>, 739 <375000000>, <150000000>, 740 <200000000>; 741 rockchip,grf = <&php_grf>; 742 #clock-cells = <1>; 743 #reset-cells = <1>; 744 }; 745 746 i2c0: i2c@fd880000 { 747 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 748 reg = <0x0 0xfd880000 0x0 0x1000>; 749 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; 750 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 751 clock-names = "i2c", "pclk"; 752 pinctrl-0 = <&i2c0m0_xfer>; 753 pinctrl-names = "default"; 754 #address-cells = <1>; 755 #size-cells = <0>; 756 status = "disabled"; 757 }; 758 759 uart0: serial@fd890000 { 760 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 761 reg = <0x0 0xfd890000 0x0 0x100>; 762 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 763 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 764 clock-names = "baudclk", "apb_pclk"; 765 dmas = <&dmac0 6>, <&dmac0 7>; 766 dma-names = "tx", "rx"; 767 pinctrl-0 = <&uart0m1_xfer>; 768 pinctrl-names = "default"; 769 reg-shift = <2>; 770 reg-io-width = <4>; 771 status = "disabled"; 772 }; 773 774 pwm0: pwm@fd8b0000 { 775 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 776 reg = <0x0 0xfd8b0000 0x0 0x10>; 777 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 778 clock-names = "pwm", "pclk"; 779 pinctrl-0 = <&pwm0m0_pins>; 780 pinctrl-names = "default"; 781 #pwm-cells = <3>; 782 status = "disabled"; 783 }; 784 785 pwm1: pwm@fd8b0010 { 786 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 787 reg = <0x0 0xfd8b0010 0x0 0x10>; 788 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 789 clock-names = "pwm", "pclk"; 790 pinctrl-0 = <&pwm1m0_pins>; 791 pinctrl-names = "default"; 792 #pwm-cells = <3>; 793 status = "disabled"; 794 }; 795 796 pwm2: pwm@fd8b0020 { 797 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 798 reg = <0x0 0xfd8b0020 0x0 0x10>; 799 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 800 clock-names = "pwm", "pclk"; 801 pinctrl-0 = <&pwm2m0_pins>; 802 pinctrl-names = "default"; 803 #pwm-cells = <3>; 804 status = "disabled"; 805 }; 806 807 pwm3: pwm@fd8b0030 { 808 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 809 reg = <0x0 0xfd8b0030 0x0 0x10>; 810 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 811 clock-names = "pwm", "pclk"; 812 pinctrl-0 = <&pwm3m0_pins>; 813 pinctrl-names = "default"; 814 #pwm-cells = <3>; 815 status = "disabled"; 816 }; 817 818 pmu: power-management@fd8d8000 { 819 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 820 reg = <0x0 0xfd8d8000 0x0 0x400>; 821 822 power: power-controller { 823 compatible = "rockchip,rk3588-power-controller"; 824 #address-cells = <1>; 825 #power-domain-cells = <1>; 826 #size-cells = <0>; 827 status = "okay"; 828 829 /* These power domains are grouped by VD_NPU */ 830 power-domain@RK3588_PD_NPU { 831 reg = <RK3588_PD_NPU>; 832 #power-domain-cells = <0>; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 836 power-domain@RK3588_PD_NPUTOP { 837 reg = <RK3588_PD_NPUTOP>; 838 clocks = <&cru HCLK_NPU_ROOT>, 839 <&cru PCLK_NPU_ROOT>, 840 <&cru CLK_NPU_DSU0>, 841 <&cru HCLK_NPU_CM0_ROOT>; 842 pm_qos = <&qos_npu0_mwr>, 843 <&qos_npu0_mro>, 844 <&qos_mcu_npu>; 845 #power-domain-cells = <0>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 849 power-domain@RK3588_PD_NPU1 { 850 reg = <RK3588_PD_NPU1>; 851 clocks = <&cru HCLK_NPU_ROOT>, 852 <&cru PCLK_NPU_ROOT>, 853 <&cru CLK_NPU_DSU0>; 854 pm_qos = <&qos_npu1>; 855 #power-domain-cells = <0>; 856 }; 857 power-domain@RK3588_PD_NPU2 { 858 reg = <RK3588_PD_NPU2>; 859 clocks = <&cru HCLK_NPU_ROOT>, 860 <&cru PCLK_NPU_ROOT>, 861 <&cru CLK_NPU_DSU0>; 862 pm_qos = <&qos_npu2>; 863 #power-domain-cells = <0>; 864 }; 865 }; 866 }; 867 /* These power domains are grouped by VD_GPU */ 868 power-domain@RK3588_PD_GPU { 869 reg = <RK3588_PD_GPU>; 870 clocks = <&cru CLK_GPU>, 871 <&cru CLK_GPU_COREGROUP>, 872 <&cru CLK_GPU_STACKS>; 873 pm_qos = <&qos_gpu_m0>, 874 <&qos_gpu_m1>, 875 <&qos_gpu_m2>, 876 <&qos_gpu_m3>; 877 #power-domain-cells = <0>; 878 }; 879 /* These power domains are grouped by VD_VCODEC */ 880 power-domain@RK3588_PD_VCODEC { 881 reg = <RK3588_PD_VCODEC>; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 #power-domain-cells = <0>; 885 886 power-domain@RK3588_PD_RKVDEC0 { 887 reg = <RK3588_PD_RKVDEC0>; 888 clocks = <&cru HCLK_RKVDEC0>, 889 <&cru HCLK_VDPU_ROOT>, 890 <&cru ACLK_VDPU_ROOT>, 891 <&cru ACLK_RKVDEC0>, 892 <&cru ACLK_RKVDEC_CCU>; 893 pm_qos = <&qos_rkvdec0>; 894 #power-domain-cells = <0>; 895 }; 896 power-domain@RK3588_PD_RKVDEC1 { 897 reg = <RK3588_PD_RKVDEC1>; 898 clocks = <&cru HCLK_RKVDEC1>, 899 <&cru HCLK_VDPU_ROOT>, 900 <&cru ACLK_VDPU_ROOT>, 901 <&cru ACLK_RKVDEC1>; 902 pm_qos = <&qos_rkvdec1>; 903 #power-domain-cells = <0>; 904 }; 905 power-domain@RK3588_PD_VENC0 { 906 reg = <RK3588_PD_VENC0>; 907 clocks = <&cru HCLK_RKVENC0>, 908 <&cru ACLK_RKVENC0>; 909 pm_qos = <&qos_rkvenc0_m0ro>, 910 <&qos_rkvenc0_m1ro>, 911 <&qos_rkvenc0_m2wo>; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 #power-domain-cells = <0>; 915 916 power-domain@RK3588_PD_VENC1 { 917 reg = <RK3588_PD_VENC1>; 918 clocks = <&cru HCLK_RKVENC1>, 919 <&cru HCLK_RKVENC0>, 920 <&cru ACLK_RKVENC0>, 921 <&cru ACLK_RKVENC1>; 922 pm_qos = <&qos_rkvenc1_m0ro>, 923 <&qos_rkvenc1_m1ro>, 924 <&qos_rkvenc1_m2wo>; 925 #power-domain-cells = <0>; 926 }; 927 }; 928 }; 929 /* These power domains are grouped by VD_LOGIC */ 930 power-domain@RK3588_PD_VDPU { 931 reg = <RK3588_PD_VDPU>; 932 clocks = <&cru HCLK_VDPU_ROOT>, 933 <&cru ACLK_VDPU_LOW_ROOT>, 934 <&cru ACLK_VDPU_ROOT>, 935 <&cru ACLK_JPEG_DECODER_ROOT>, 936 <&cru ACLK_IEP2P0>, 937 <&cru HCLK_IEP2P0>, 938 <&cru ACLK_JPEG_ENCODER0>, 939 <&cru HCLK_JPEG_ENCODER0>, 940 <&cru ACLK_JPEG_ENCODER1>, 941 <&cru HCLK_JPEG_ENCODER1>, 942 <&cru ACLK_JPEG_ENCODER2>, 943 <&cru HCLK_JPEG_ENCODER2>, 944 <&cru ACLK_JPEG_ENCODER3>, 945 <&cru HCLK_JPEG_ENCODER3>, 946 <&cru ACLK_JPEG_DECODER>, 947 <&cru HCLK_JPEG_DECODER>, 948 <&cru ACLK_RGA2>, 949 <&cru HCLK_RGA2>; 950 pm_qos = <&qos_iep>, 951 <&qos_jpeg_dec>, 952 <&qos_jpeg_enc0>, 953 <&qos_jpeg_enc1>, 954 <&qos_jpeg_enc2>, 955 <&qos_jpeg_enc3>, 956 <&qos_rga2_mro>, 957 <&qos_rga2_mwo>; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 #power-domain-cells = <0>; 961 962 963 power-domain@RK3588_PD_AV1 { 964 reg = <RK3588_PD_AV1>; 965 clocks = <&cru PCLK_AV1>, 966 <&cru ACLK_AV1>, 967 <&cru HCLK_VDPU_ROOT>; 968 pm_qos = <&qos_av1>; 969 #power-domain-cells = <0>; 970 }; 971 power-domain@RK3588_PD_RKVDEC0 { 972 reg = <RK3588_PD_RKVDEC0>; 973 clocks = <&cru HCLK_RKVDEC0>, 974 <&cru HCLK_VDPU_ROOT>, 975 <&cru ACLK_VDPU_ROOT>, 976 <&cru ACLK_RKVDEC0>; 977 pm_qos = <&qos_rkvdec0>; 978 #power-domain-cells = <0>; 979 }; 980 power-domain@RK3588_PD_RKVDEC1 { 981 reg = <RK3588_PD_RKVDEC1>; 982 clocks = <&cru HCLK_RKVDEC1>, 983 <&cru HCLK_VDPU_ROOT>, 984 <&cru ACLK_VDPU_ROOT>; 985 pm_qos = <&qos_rkvdec1>; 986 #power-domain-cells = <0>; 987 }; 988 power-domain@RK3588_PD_RGA30 { 989 reg = <RK3588_PD_RGA30>; 990 clocks = <&cru ACLK_RGA3_0>, 991 <&cru HCLK_RGA3_0>; 992 pm_qos = <&qos_rga3_0>; 993 #power-domain-cells = <0>; 994 }; 995 }; 996 power-domain@RK3588_PD_VOP { 997 reg = <RK3588_PD_VOP>; 998 clocks = <&cru PCLK_VOP_ROOT>, 999 <&cru HCLK_VOP_ROOT>, 1000 <&cru ACLK_VOP>; 1001 pm_qos = <&qos_vop_m0>, 1002 <&qos_vop_m1>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 #power-domain-cells = <0>; 1006 1007 power-domain@RK3588_PD_VO0 { 1008 reg = <RK3588_PD_VO0>; 1009 clocks = <&cru PCLK_VO0_ROOT>, 1010 <&cru PCLK_VO0_S_ROOT>, 1011 <&cru HCLK_VO0_S_ROOT>, 1012 <&cru ACLK_VO0_ROOT>, 1013 <&cru HCLK_HDCP0>, 1014 <&cru ACLK_HDCP0>, 1015 <&cru HCLK_VOP_ROOT>; 1016 pm_qos = <&qos_hdcp0>; 1017 #power-domain-cells = <0>; 1018 }; 1019 }; 1020 power-domain@RK3588_PD_VO1 { 1021 reg = <RK3588_PD_VO1>; 1022 clocks = <&cru PCLK_VO1_ROOT>, 1023 <&cru PCLK_VO1_S_ROOT>, 1024 <&cru HCLK_VO1_S_ROOT>, 1025 <&cru HCLK_HDCP1>, 1026 <&cru ACLK_HDCP1>, 1027 <&cru ACLK_HDMIRX_ROOT>, 1028 <&cru HCLK_VO1USB_TOP_ROOT>; 1029 pm_qos = <&qos_hdcp1>, 1030 <&qos_hdmirx>; 1031 #power-domain-cells = <0>; 1032 }; 1033 power-domain@RK3588_PD_VI { 1034 reg = <RK3588_PD_VI>; 1035 clocks = <&cru HCLK_VI_ROOT>, 1036 <&cru PCLK_VI_ROOT>, 1037 <&cru HCLK_ISP0>, 1038 <&cru ACLK_ISP0>, 1039 <&cru HCLK_VICAP>, 1040 <&cru ACLK_VICAP>; 1041 pm_qos = <&qos_isp0_mro>, 1042 <&qos_isp0_mwo>, 1043 <&qos_vicap_m0>, 1044 <&qos_vicap_m1>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 #power-domain-cells = <0>; 1048 1049 power-domain@RK3588_PD_ISP1 { 1050 reg = <RK3588_PD_ISP1>; 1051 clocks = <&cru HCLK_ISP1>, 1052 <&cru ACLK_ISP1>, 1053 <&cru HCLK_VI_ROOT>, 1054 <&cru PCLK_VI_ROOT>; 1055 pm_qos = <&qos_isp1_mwo>, 1056 <&qos_isp1_mro>; 1057 #power-domain-cells = <0>; 1058 }; 1059 power-domain@RK3588_PD_FEC { 1060 reg = <RK3588_PD_FEC>; 1061 clocks = <&cru HCLK_FISHEYE0>, 1062 <&cru ACLK_FISHEYE0>, 1063 <&cru HCLK_FISHEYE1>, 1064 <&cru ACLK_FISHEYE1>, 1065 <&cru PCLK_VI_ROOT>; 1066 pm_qos = <&qos_fisheye0>, 1067 <&qos_fisheye1>; 1068 #power-domain-cells = <0>; 1069 }; 1070 }; 1071 power-domain@RK3588_PD_RGA31 { 1072 reg = <RK3588_PD_RGA31>; 1073 clocks = <&cru HCLK_RGA3_1>, 1074 <&cru ACLK_RGA3_1>; 1075 pm_qos = <&qos_rga3_1>; 1076 #power-domain-cells = <0>; 1077 }; 1078 power-domain@RK3588_PD_USB { 1079 reg = <RK3588_PD_USB>; 1080 clocks = <&cru PCLK_PHP_ROOT>, 1081 <&cru ACLK_USB_ROOT>, 1082 <&cru ACLK_USB>, 1083 <&cru HCLK_USB_ROOT>, 1084 <&cru HCLK_HOST0>, 1085 <&cru HCLK_HOST_ARB0>, 1086 <&cru HCLK_HOST1>, 1087 <&cru HCLK_HOST_ARB1>; 1088 pm_qos = <&qos_usb3_0>, 1089 <&qos_usb3_1>, 1090 <&qos_usb2host_0>, 1091 <&qos_usb2host_1>; 1092 #power-domain-cells = <0>; 1093 }; 1094 power-domain@RK3588_PD_GMAC { 1095 reg = <RK3588_PD_GMAC>; 1096 clocks = <&cru PCLK_PHP_ROOT>, 1097 <&cru ACLK_PCIE_ROOT>, 1098 <&cru ACLK_PHP_ROOT>; 1099 #power-domain-cells = <0>; 1100 }; 1101 power-domain@RK3588_PD_PCIE { 1102 reg = <RK3588_PD_PCIE>; 1103 clocks = <&cru PCLK_PHP_ROOT>, 1104 <&cru ACLK_PCIE_ROOT>, 1105 <&cru ACLK_PHP_ROOT>; 1106 #power-domain-cells = <0>; 1107 }; 1108 power-domain@RK3588_PD_SDIO { 1109 reg = <RK3588_PD_SDIO>; 1110 clocks = <&cru HCLK_SDIO>, 1111 <&cru HCLK_NVM_ROOT>; 1112 pm_qos = <&qos_sdio>; 1113 #power-domain-cells = <0>; 1114 }; 1115 power-domain@RK3588_PD_AUDIO { 1116 reg = <RK3588_PD_AUDIO>; 1117 clocks = <&cru HCLK_AUDIO_ROOT>, 1118 <&cru PCLK_AUDIO_ROOT>; 1119 #power-domain-cells = <0>; 1120 }; 1121 power-domain@RK3588_PD_SDMMC { 1122 reg = <RK3588_PD_SDMMC>; 1123 pm_qos = <&qos_sdmmc>; 1124 #power-domain-cells = <0>; 1125 }; 1126 }; 1127 }; 1128 1129 vpu121: video-codec@fdb50000 { 1130 compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu"; 1131 reg = <0x0 0xfdb50000 0x0 0x800>; 1132 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1133 interrupt-names = "vdpu"; 1134 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1135 clock-names = "aclk", "hclk"; 1136 iommus = <&vpu121_mmu>; 1137 power-domains = <&power RK3588_PD_VDPU>; 1138 }; 1139 1140 vpu121_mmu: iommu@fdb50800 { 1141 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1142 reg = <0x0 0xfdb50800 0x0 0x40>; 1143 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1144 clock-names = "aclk", "iface"; 1145 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1146 power-domains = <&power RK3588_PD_VDPU>; 1147 #iommu-cells = <0>; 1148 }; 1149 1150 rga: rga@fdb80000 { 1151 compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga"; 1152 reg = <0x0 0xfdb80000 0x0 0x180>; 1153 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1154 clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>; 1155 clock-names = "aclk", "hclk", "sclk"; 1156 resets = <&cru SRST_RGA2_CORE>, <&cru SRST_A_RGA2>, <&cru SRST_H_RGA2>; 1157 reset-names = "core", "axi", "ahb"; 1158 power-domains = <&power RK3588_PD_VDPU>; 1159 }; 1160 1161 vepu121_0: video-codec@fdba0000 { 1162 compatible = "rockchip,rk3588-vepu121"; 1163 reg = <0x0 0xfdba0000 0x0 0x800>; 1164 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>; 1165 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 1166 clock-names = "aclk", "hclk"; 1167 iommus = <&vepu121_0_mmu>; 1168 power-domains = <&power RK3588_PD_VDPU>; 1169 }; 1170 1171 vepu121_0_mmu: iommu@fdba0800 { 1172 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1173 reg = <0x0 0xfdba0800 0x0 0x40>; 1174 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 1175 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 1176 clock-names = "aclk", "iface"; 1177 power-domains = <&power RK3588_PD_VDPU>; 1178 #iommu-cells = <0>; 1179 }; 1180 1181 vepu121_1: video-codec@fdba4000 { 1182 compatible = "rockchip,rk3588-vepu121"; 1183 reg = <0x0 0xfdba4000 0x0 0x800>; 1184 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>; 1185 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 1186 clock-names = "aclk", "hclk"; 1187 iommus = <&vepu121_1_mmu>; 1188 power-domains = <&power RK3588_PD_VDPU>; 1189 }; 1190 1191 vepu121_1_mmu: iommu@fdba4800 { 1192 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1193 reg = <0x0 0xfdba4800 0x0 0x40>; 1194 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>; 1195 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 1196 clock-names = "aclk", "iface"; 1197 power-domains = <&power RK3588_PD_VDPU>; 1198 #iommu-cells = <0>; 1199 }; 1200 1201 vepu121_2: video-codec@fdba8000 { 1202 compatible = "rockchip,rk3588-vepu121"; 1203 reg = <0x0 0xfdba8000 0x0 0x800>; 1204 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>; 1205 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 1206 clock-names = "aclk", "hclk"; 1207 iommus = <&vepu121_2_mmu>; 1208 power-domains = <&power RK3588_PD_VDPU>; 1209 }; 1210 1211 vepu121_2_mmu: iommu@fdba8800 { 1212 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1213 reg = <0x0 0xfdba8800 0x0 0x40>; 1214 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>; 1215 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 1216 clock-names = "aclk", "iface"; 1217 power-domains = <&power RK3588_PD_VDPU>; 1218 #iommu-cells = <0>; 1219 }; 1220 1221 vepu121_3: video-codec@fdbac000 { 1222 compatible = "rockchip,rk3588-vepu121"; 1223 reg = <0x0 0xfdbac000 0x0 0x800>; 1224 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; 1225 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 1226 clock-names = "aclk", "hclk"; 1227 iommus = <&vepu121_3_mmu>; 1228 power-domains = <&power RK3588_PD_VDPU>; 1229 }; 1230 1231 vepu121_3_mmu: iommu@fdbac800 { 1232 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1233 reg = <0x0 0xfdbac800 0x0 0x40>; 1234 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>; 1235 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 1236 clock-names = "aclk", "iface"; 1237 power-domains = <&power RK3588_PD_VDPU>; 1238 #iommu-cells = <0>; 1239 }; 1240 1241 av1d: video-codec@fdc70000 { 1242 compatible = "rockchip,rk3588-av1-vpu"; 1243 reg = <0x0 0xfdc70000 0x0 0x800>; 1244 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 1245 interrupt-names = "vdpu"; 1246 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1247 assigned-clock-rates = <400000000>, <400000000>; 1248 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1249 clock-names = "aclk", "hclk"; 1250 power-domains = <&power RK3588_PD_AV1>; 1251 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; 1252 }; 1253 1254 vop: vop@fdd90000 { 1255 compatible = "rockchip,rk3588-vop"; 1256 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; 1257 reg-names = "vop", "gamma-lut"; 1258 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1259 clocks = <&cru ACLK_VOP>, 1260 <&cru HCLK_VOP>, 1261 <&cru DCLK_VOP0>, 1262 <&cru DCLK_VOP1>, 1263 <&cru DCLK_VOP2>, 1264 <&cru DCLK_VOP3>, 1265 <&cru PCLK_VOP_ROOT>; 1266 clock-names = "aclk", 1267 "hclk", 1268 "dclk_vp0", 1269 "dclk_vp1", 1270 "dclk_vp2", 1271 "dclk_vp3", 1272 "pclk_vop"; 1273 iommus = <&vop_mmu>; 1274 power-domains = <&power RK3588_PD_VOP>; 1275 rockchip,grf = <&sys_grf>; 1276 rockchip,vop-grf = <&vop_grf>; 1277 rockchip,vo1-grf = <&vo1_grf>; 1278 rockchip,pmu = <&pmu>; 1279 status = "disabled"; 1280 1281 vop_out: ports { 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 1285 vp0: port@0 { 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 reg = <0>; 1289 }; 1290 1291 vp1: port@1 { 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 reg = <1>; 1295 }; 1296 1297 vp2: port@2 { 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 reg = <2>; 1301 }; 1302 1303 vp3: port@3 { 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 reg = <3>; 1307 }; 1308 }; 1309 }; 1310 1311 vop_mmu: iommu@fdd97e00 { 1312 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1313 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 1314 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1315 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1316 clock-names = "aclk", "iface"; 1317 #iommu-cells = <0>; 1318 power-domains = <&power RK3588_PD_VOP>; 1319 status = "disabled"; 1320 }; 1321 1322 i2s4_8ch: i2s@fddc0000 { 1323 compatible = "rockchip,rk3588-i2s-tdm"; 1324 reg = <0x0 0xfddc0000 0x0 0x1000>; 1325 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; 1326 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 1327 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1328 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 1329 assigned-clock-parents = <&cru PLL_AUPLL>; 1330 dmas = <&dmac2 0>; 1331 dma-names = "tx"; 1332 power-domains = <&power RK3588_PD_VO0>; 1333 resets = <&cru SRST_M_I2S4_8CH_TX>; 1334 reset-names = "tx-m"; 1335 #sound-dai-cells = <0>; 1336 status = "disabled"; 1337 }; 1338 1339 i2s5_8ch: i2s@fddf0000 { 1340 compatible = "rockchip,rk3588-i2s-tdm"; 1341 reg = <0x0 0xfddf0000 0x0 0x1000>; 1342 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; 1343 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 1344 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1345 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 1346 assigned-clock-parents = <&cru PLL_AUPLL>; 1347 dmas = <&dmac2 2>; 1348 dma-names = "tx"; 1349 power-domains = <&power RK3588_PD_VO1>; 1350 resets = <&cru SRST_M_I2S5_8CH_TX>; 1351 reset-names = "tx-m"; 1352 #sound-dai-cells = <0>; 1353 status = "disabled"; 1354 }; 1355 1356 i2s9_8ch: i2s@fddfc000 { 1357 compatible = "rockchip,rk3588-i2s-tdm"; 1358 reg = <0x0 0xfddfc000 0x0 0x1000>; 1359 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; 1360 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 1361 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1362 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 1363 assigned-clock-parents = <&cru PLL_AUPLL>; 1364 dmas = <&dmac2 23>; 1365 dma-names = "rx"; 1366 power-domains = <&power RK3588_PD_VO1>; 1367 resets = <&cru SRST_M_I2S9_8CH_RX>; 1368 reset-names = "rx-m"; 1369 #sound-dai-cells = <0>; 1370 status = "disabled"; 1371 }; 1372 1373 qos_gpu_m0: qos@fdf35000 { 1374 compatible = "rockchip,rk3588-qos", "syscon"; 1375 reg = <0x0 0xfdf35000 0x0 0x20>; 1376 }; 1377 1378 qos_gpu_m1: qos@fdf35200 { 1379 compatible = "rockchip,rk3588-qos", "syscon"; 1380 reg = <0x0 0xfdf35200 0x0 0x20>; 1381 }; 1382 1383 qos_gpu_m2: qos@fdf35400 { 1384 compatible = "rockchip,rk3588-qos", "syscon"; 1385 reg = <0x0 0xfdf35400 0x0 0x20>; 1386 }; 1387 1388 qos_gpu_m3: qos@fdf35600 { 1389 compatible = "rockchip,rk3588-qos", "syscon"; 1390 reg = <0x0 0xfdf35600 0x0 0x20>; 1391 }; 1392 1393 qos_rga3_1: qos@fdf36000 { 1394 compatible = "rockchip,rk3588-qos", "syscon"; 1395 reg = <0x0 0xfdf36000 0x0 0x20>; 1396 }; 1397 1398 qos_sdio: qos@fdf39000 { 1399 compatible = "rockchip,rk3588-qos", "syscon"; 1400 reg = <0x0 0xfdf39000 0x0 0x20>; 1401 }; 1402 1403 qos_sdmmc: qos@fdf3d800 { 1404 compatible = "rockchip,rk3588-qos", "syscon"; 1405 reg = <0x0 0xfdf3d800 0x0 0x20>; 1406 }; 1407 1408 qos_usb3_1: qos@fdf3e000 { 1409 compatible = "rockchip,rk3588-qos", "syscon"; 1410 reg = <0x0 0xfdf3e000 0x0 0x20>; 1411 }; 1412 1413 qos_usb3_0: qos@fdf3e200 { 1414 compatible = "rockchip,rk3588-qos", "syscon"; 1415 reg = <0x0 0xfdf3e200 0x0 0x20>; 1416 }; 1417 1418 qos_usb2host_0: qos@fdf3e400 { 1419 compatible = "rockchip,rk3588-qos", "syscon"; 1420 reg = <0x0 0xfdf3e400 0x0 0x20>; 1421 }; 1422 1423 qos_usb2host_1: qos@fdf3e600 { 1424 compatible = "rockchip,rk3588-qos", "syscon"; 1425 reg = <0x0 0xfdf3e600 0x0 0x20>; 1426 }; 1427 1428 qos_fisheye0: qos@fdf40000 { 1429 compatible = "rockchip,rk3588-qos", "syscon"; 1430 reg = <0x0 0xfdf40000 0x0 0x20>; 1431 }; 1432 1433 qos_fisheye1: qos@fdf40200 { 1434 compatible = "rockchip,rk3588-qos", "syscon"; 1435 reg = <0x0 0xfdf40200 0x0 0x20>; 1436 }; 1437 1438 qos_isp0_mro: qos@fdf40400 { 1439 compatible = "rockchip,rk3588-qos", "syscon"; 1440 reg = <0x0 0xfdf40400 0x0 0x20>; 1441 }; 1442 1443 qos_isp0_mwo: qos@fdf40500 { 1444 compatible = "rockchip,rk3588-qos", "syscon"; 1445 reg = <0x0 0xfdf40500 0x0 0x20>; 1446 }; 1447 1448 qos_vicap_m0: qos@fdf40600 { 1449 compatible = "rockchip,rk3588-qos", "syscon"; 1450 reg = <0x0 0xfdf40600 0x0 0x20>; 1451 }; 1452 1453 qos_vicap_m1: qos@fdf40800 { 1454 compatible = "rockchip,rk3588-qos", "syscon"; 1455 reg = <0x0 0xfdf40800 0x0 0x20>; 1456 }; 1457 1458 qos_isp1_mwo: qos@fdf41000 { 1459 compatible = "rockchip,rk3588-qos", "syscon"; 1460 reg = <0x0 0xfdf41000 0x0 0x20>; 1461 }; 1462 1463 qos_isp1_mro: qos@fdf41100 { 1464 compatible = "rockchip,rk3588-qos", "syscon"; 1465 reg = <0x0 0xfdf41100 0x0 0x20>; 1466 }; 1467 1468 qos_rkvenc0_m0ro: qos@fdf60000 { 1469 compatible = "rockchip,rk3588-qos", "syscon"; 1470 reg = <0x0 0xfdf60000 0x0 0x20>; 1471 }; 1472 1473 qos_rkvenc0_m1ro: qos@fdf60200 { 1474 compatible = "rockchip,rk3588-qos", "syscon"; 1475 reg = <0x0 0xfdf60200 0x0 0x20>; 1476 }; 1477 1478 qos_rkvenc0_m2wo: qos@fdf60400 { 1479 compatible = "rockchip,rk3588-qos", "syscon"; 1480 reg = <0x0 0xfdf60400 0x0 0x20>; 1481 }; 1482 1483 qos_rkvenc1_m0ro: qos@fdf61000 { 1484 compatible = "rockchip,rk3588-qos", "syscon"; 1485 reg = <0x0 0xfdf61000 0x0 0x20>; 1486 }; 1487 1488 qos_rkvenc1_m1ro: qos@fdf61200 { 1489 compatible = "rockchip,rk3588-qos", "syscon"; 1490 reg = <0x0 0xfdf61200 0x0 0x20>; 1491 }; 1492 1493 qos_rkvenc1_m2wo: qos@fdf61400 { 1494 compatible = "rockchip,rk3588-qos", "syscon"; 1495 reg = <0x0 0xfdf61400 0x0 0x20>; 1496 }; 1497 1498 qos_rkvdec0: qos@fdf62000 { 1499 compatible = "rockchip,rk3588-qos", "syscon"; 1500 reg = <0x0 0xfdf62000 0x0 0x20>; 1501 }; 1502 1503 qos_rkvdec1: qos@fdf63000 { 1504 compatible = "rockchip,rk3588-qos", "syscon"; 1505 reg = <0x0 0xfdf63000 0x0 0x20>; 1506 }; 1507 1508 qos_av1: qos@fdf64000 { 1509 compatible = "rockchip,rk3588-qos", "syscon"; 1510 reg = <0x0 0xfdf64000 0x0 0x20>; 1511 }; 1512 1513 qos_iep: qos@fdf66000 { 1514 compatible = "rockchip,rk3588-qos", "syscon"; 1515 reg = <0x0 0xfdf66000 0x0 0x20>; 1516 }; 1517 1518 qos_jpeg_dec: qos@fdf66200 { 1519 compatible = "rockchip,rk3588-qos", "syscon"; 1520 reg = <0x0 0xfdf66200 0x0 0x20>; 1521 }; 1522 1523 qos_jpeg_enc0: qos@fdf66400 { 1524 compatible = "rockchip,rk3588-qos", "syscon"; 1525 reg = <0x0 0xfdf66400 0x0 0x20>; 1526 }; 1527 1528 qos_jpeg_enc1: qos@fdf66600 { 1529 compatible = "rockchip,rk3588-qos", "syscon"; 1530 reg = <0x0 0xfdf66600 0x0 0x20>; 1531 }; 1532 1533 qos_jpeg_enc2: qos@fdf66800 { 1534 compatible = "rockchip,rk3588-qos", "syscon"; 1535 reg = <0x0 0xfdf66800 0x0 0x20>; 1536 }; 1537 1538 qos_jpeg_enc3: qos@fdf66a00 { 1539 compatible = "rockchip,rk3588-qos", "syscon"; 1540 reg = <0x0 0xfdf66a00 0x0 0x20>; 1541 }; 1542 1543 qos_rga2_mro: qos@fdf66c00 { 1544 compatible = "rockchip,rk3588-qos", "syscon"; 1545 reg = <0x0 0xfdf66c00 0x0 0x20>; 1546 }; 1547 1548 qos_rga2_mwo: qos@fdf66e00 { 1549 compatible = "rockchip,rk3588-qos", "syscon"; 1550 reg = <0x0 0xfdf66e00 0x0 0x20>; 1551 }; 1552 1553 qos_rga3_0: qos@fdf67000 { 1554 compatible = "rockchip,rk3588-qos", "syscon"; 1555 reg = <0x0 0xfdf67000 0x0 0x20>; 1556 }; 1557 1558 qos_vdpu: qos@fdf67200 { 1559 compatible = "rockchip,rk3588-qos", "syscon"; 1560 reg = <0x0 0xfdf67200 0x0 0x20>; 1561 }; 1562 1563 qos_npu1: qos@fdf70000 { 1564 compatible = "rockchip,rk3588-qos", "syscon"; 1565 reg = <0x0 0xfdf70000 0x0 0x20>; 1566 }; 1567 1568 qos_npu2: qos@fdf71000 { 1569 compatible = "rockchip,rk3588-qos", "syscon"; 1570 reg = <0x0 0xfdf71000 0x0 0x20>; 1571 }; 1572 1573 qos_npu0_mwr: qos@fdf72000 { 1574 compatible = "rockchip,rk3588-qos", "syscon"; 1575 reg = <0x0 0xfdf72000 0x0 0x20>; 1576 }; 1577 1578 qos_npu0_mro: qos@fdf72200 { 1579 compatible = "rockchip,rk3588-qos", "syscon"; 1580 reg = <0x0 0xfdf72200 0x0 0x20>; 1581 }; 1582 1583 qos_mcu_npu: qos@fdf72400 { 1584 compatible = "rockchip,rk3588-qos", "syscon"; 1585 reg = <0x0 0xfdf72400 0x0 0x20>; 1586 }; 1587 1588 qos_hdcp0: qos@fdf80000 { 1589 compatible = "rockchip,rk3588-qos", "syscon"; 1590 reg = <0x0 0xfdf80000 0x0 0x20>; 1591 }; 1592 1593 qos_hdcp1: qos@fdf81000 { 1594 compatible = "rockchip,rk3588-qos", "syscon"; 1595 reg = <0x0 0xfdf81000 0x0 0x20>; 1596 }; 1597 1598 qos_hdmirx: qos@fdf81200 { 1599 compatible = "rockchip,rk3588-qos", "syscon"; 1600 reg = <0x0 0xfdf81200 0x0 0x20>; 1601 }; 1602 1603 qos_vop_m0: qos@fdf82000 { 1604 compatible = "rockchip,rk3588-qos", "syscon"; 1605 reg = <0x0 0xfdf82000 0x0 0x20>; 1606 }; 1607 1608 qos_vop_m1: qos@fdf82200 { 1609 compatible = "rockchip,rk3588-qos", "syscon"; 1610 reg = <0x0 0xfdf82200 0x0 0x20>; 1611 }; 1612 1613 dfi: dfi@fe060000 { 1614 reg = <0x00 0xfe060000 0x00 0x10000>; 1615 compatible = "rockchip,rk3588-dfi"; 1616 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, 1617 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, 1618 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, 1619 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1620 rockchip,pmu = <&pmu1grf>; 1621 }; 1622 1623 pcie2x1l1: pcie@fe180000 { 1624 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1625 bus-range = <0x30 0x3f>; 1626 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 1627 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 1628 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; 1629 clock-names = "aclk_mst", "aclk_slv", 1630 "aclk_dbi", "pclk", 1631 "aux", "pipe"; 1632 device_type = "pci"; 1633 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, 1634 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, 1635 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, 1636 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, 1637 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; 1638 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1639 #interrupt-cells = <1>; 1640 interrupt-map-mask = <0 0 0 7>; 1641 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 1642 <0 0 0 2 &pcie2x1l1_intc 1>, 1643 <0 0 0 3 &pcie2x1l1_intc 2>, 1644 <0 0 0 4 &pcie2x1l1_intc 3>; 1645 linux,pci-domain = <3>; 1646 max-link-speed = <2>; 1647 msi-map = <0x3000 &its0 0x3000 0x1000>; 1648 num-lanes = <1>; 1649 phys = <&combphy2_psu PHY_TYPE_PCIE>; 1650 phy-names = "pcie-phy"; 1651 power-domains = <&power RK3588_PD_PCIE>; 1652 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, 1653 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, 1654 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; 1655 reg = <0xa 0x40c00000 0x0 0x00400000>, 1656 <0x0 0xfe180000 0x0 0x00010000>, 1657 <0x0 0xf3000000 0x0 0x00100000>; 1658 reg-names = "dbi", "apb", "config"; 1659 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; 1660 reset-names = "pwr", "pipe"; 1661 #address-cells = <3>; 1662 #size-cells = <2>; 1663 status = "disabled"; 1664 1665 pcie2x1l1_intc: legacy-interrupt-controller { 1666 interrupt-controller; 1667 #address-cells = <0>; 1668 #interrupt-cells = <1>; 1669 interrupt-parent = <&gic>; 1670 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; 1671 }; 1672 }; 1673 1674 pcie2x1l2: pcie@fe190000 { 1675 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1676 bus-range = <0x40 0x4f>; 1677 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 1678 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 1679 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; 1680 clock-names = "aclk_mst", "aclk_slv", 1681 "aclk_dbi", "pclk", 1682 "aux", "pipe"; 1683 device_type = "pci"; 1684 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, 1685 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, 1686 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, 1687 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, 1688 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; 1689 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1690 #interrupt-cells = <1>; 1691 interrupt-map-mask = <0 0 0 7>; 1692 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 1693 <0 0 0 2 &pcie2x1l2_intc 1>, 1694 <0 0 0 3 &pcie2x1l2_intc 2>, 1695 <0 0 0 4 &pcie2x1l2_intc 3>; 1696 linux,pci-domain = <4>; 1697 max-link-speed = <2>; 1698 msi-map = <0x4000 &its0 0x4000 0x1000>; 1699 num-lanes = <1>; 1700 phys = <&combphy0_ps PHY_TYPE_PCIE>; 1701 phy-names = "pcie-phy"; 1702 power-domains = <&power RK3588_PD_PCIE>; 1703 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 1704 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, 1705 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; 1706 reg = <0xa 0x41000000 0x0 0x00400000>, 1707 <0x0 0xfe190000 0x0 0x00010000>, 1708 <0x0 0xf4000000 0x0 0x00100000>; 1709 reg-names = "dbi", "apb", "config"; 1710 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; 1711 reset-names = "pwr", "pipe"; 1712 #address-cells = <3>; 1713 #size-cells = <2>; 1714 status = "disabled"; 1715 1716 pcie2x1l2_intc: legacy-interrupt-controller { 1717 interrupt-controller; 1718 #address-cells = <0>; 1719 #interrupt-cells = <1>; 1720 interrupt-parent = <&gic>; 1721 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; 1722 }; 1723 }; 1724 1725 gmac1: ethernet@fe1c0000 { 1726 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1727 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1728 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, 1729 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 1730 interrupt-names = "macirq", "eth_wake_irq"; 1731 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 1732 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1733 <&cru CLK_GMAC1_PTP_REF>; 1734 clock-names = "stmmaceth", "clk_mac_ref", 1735 "pclk_mac", "aclk_mac", 1736 "ptp_ref"; 1737 power-domains = <&power RK3588_PD_GMAC>; 1738 resets = <&cru SRST_A_GMAC1>; 1739 reset-names = "stmmaceth"; 1740 rockchip,grf = <&sys_grf>; 1741 rockchip,php-grf = <&php_grf>; 1742 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1743 snps,mixed-burst; 1744 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1745 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1746 snps,tso; 1747 status = "disabled"; 1748 1749 mdio1: mdio { 1750 compatible = "snps,dwmac-mdio"; 1751 #address-cells = <0x1>; 1752 #size-cells = <0x0>; 1753 }; 1754 1755 gmac1_stmmac_axi_setup: stmmac-axi-config { 1756 snps,blen = <0 0 0 0 16 8 4>; 1757 snps,wr_osr_lmt = <4>; 1758 snps,rd_osr_lmt = <8>; 1759 }; 1760 1761 gmac1_mtl_rx_setup: rx-queues-config { 1762 snps,rx-queues-to-use = <2>; 1763 queue0 {}; 1764 queue1 {}; 1765 }; 1766 1767 gmac1_mtl_tx_setup: tx-queues-config { 1768 snps,tx-queues-to-use = <2>; 1769 queue0 {}; 1770 queue1 {}; 1771 }; 1772 }; 1773 1774 sata0: sata@fe210000 { 1775 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1776 reg = <0 0xfe210000 0 0x1000>; 1777 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; 1778 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1779 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, 1780 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; 1781 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1782 ports-implemented = <0x1>; 1783 #address-cells = <1>; 1784 #size-cells = <0>; 1785 status = "disabled"; 1786 1787 sata-port@0 { 1788 reg = <0>; 1789 hba-port-cap = <HBA_PORT_FBSCP>; 1790 phys = <&combphy0_ps PHY_TYPE_SATA>; 1791 phy-names = "sata-phy"; 1792 snps,rx-ts-max = <32>; 1793 snps,tx-ts-max = <32>; 1794 }; 1795 }; 1796 1797 sata2: sata@fe230000 { 1798 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1799 reg = <0 0xfe230000 0 0x1000>; 1800 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; 1801 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 1802 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, 1803 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; 1804 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1805 ports-implemented = <0x1>; 1806 #address-cells = <1>; 1807 #size-cells = <0>; 1808 status = "disabled"; 1809 1810 sata-port@0 { 1811 reg = <0>; 1812 hba-port-cap = <HBA_PORT_FBSCP>; 1813 phys = <&combphy2_psu PHY_TYPE_SATA>; 1814 phy-names = "sata-phy"; 1815 snps,rx-ts-max = <32>; 1816 snps,tx-ts-max = <32>; 1817 }; 1818 }; 1819 1820 sfc: spi@fe2b0000 { 1821 compatible = "rockchip,sfc"; 1822 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1823 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; 1824 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1825 clock-names = "clk_sfc", "hclk_sfc"; 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 status = "disabled"; 1829 }; 1830 1831 sdmmc: mmc@fe2c0000 { 1832 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1833 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1834 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 1835 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 1836 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1837 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1838 fifo-depth = <0x100>; 1839 max-frequency = <200000000>; 1840 pinctrl-names = "default"; 1841 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1842 power-domains = <&power RK3588_PD_SDMMC>; 1843 status = "disabled"; 1844 }; 1845 1846 sdio: mmc@fe2d0000 { 1847 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1848 reg = <0x00 0xfe2d0000 0x00 0x4000>; 1849 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; 1850 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 1851 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1852 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1853 fifo-depth = <0x100>; 1854 max-frequency = <200000000>; 1855 pinctrl-names = "default"; 1856 pinctrl-0 = <&sdiom1_pins>; 1857 power-domains = <&power RK3588_PD_SDIO>; 1858 status = "disabled"; 1859 }; 1860 1861 sdhci: mmc@fe2e0000 { 1862 compatible = "rockchip,rk3588-dwcmshc"; 1863 reg = <0x0 0xfe2e0000 0x0 0x10000>; 1864 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 1865 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 1866 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1867 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1868 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1869 <&cru TMCLK_EMMC>; 1870 clock-names = "core", "bus", "axi", "block", "timer"; 1871 max-frequency = <200000000>; 1872 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 1873 <&emmc_cmd>, <&emmc_data_strobe>; 1874 pinctrl-names = "default"; 1875 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1876 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1877 <&cru SRST_T_EMMC>; 1878 reset-names = "core", "bus", "axi", "block", "timer"; 1879 status = "disabled"; 1880 }; 1881 1882 i2s0_8ch: i2s@fe470000 { 1883 compatible = "rockchip,rk3588-i2s-tdm"; 1884 reg = <0x0 0xfe470000 0x0 0x1000>; 1885 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; 1886 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1887 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1888 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1889 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 1890 dmas = <&dmac0 0>, <&dmac0 1>; 1891 dma-names = "tx", "rx"; 1892 power-domains = <&power RK3588_PD_AUDIO>; 1893 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1894 reset-names = "tx-m", "rx-m"; 1895 rockchip,trcm-sync-tx-only; 1896 pinctrl-names = "default"; 1897 pinctrl-0 = <&i2s0_lrck 1898 &i2s0_sclk 1899 &i2s0_sdi0 1900 &i2s0_sdi1 1901 &i2s0_sdi2 1902 &i2s0_sdi3 1903 &i2s0_sdo0 1904 &i2s0_sdo1 1905 &i2s0_sdo2 1906 &i2s0_sdo3>; 1907 #sound-dai-cells = <0>; 1908 status = "disabled"; 1909 }; 1910 1911 i2s1_8ch: i2s@fe480000 { 1912 compatible = "rockchip,rk3588-i2s-tdm"; 1913 reg = <0x0 0xfe480000 0x0 0x1000>; 1914 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; 1915 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1916 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1917 dmas = <&dmac0 2>, <&dmac0 3>; 1918 dma-names = "tx", "rx"; 1919 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1920 reset-names = "tx-m", "rx-m"; 1921 rockchip,trcm-sync-tx-only; 1922 pinctrl-names = "default"; 1923 pinctrl-0 = <&i2s1m0_lrck 1924 &i2s1m0_sclk 1925 &i2s1m0_sdi0 1926 &i2s1m0_sdi1 1927 &i2s1m0_sdi2 1928 &i2s1m0_sdi3 1929 &i2s1m0_sdo0 1930 &i2s1m0_sdo1 1931 &i2s1m0_sdo2 1932 &i2s1m0_sdo3>; 1933 #sound-dai-cells = <0>; 1934 status = "disabled"; 1935 }; 1936 1937 i2s2_2ch: i2s@fe490000 { 1938 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1939 reg = <0x0 0xfe490000 0x0 0x1000>; 1940 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; 1941 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1942 clock-names = "i2s_clk", "i2s_hclk"; 1943 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1944 assigned-clock-parents = <&cru PLL_AUPLL>; 1945 dmas = <&dmac1 0>, <&dmac1 1>; 1946 dma-names = "tx", "rx"; 1947 power-domains = <&power RK3588_PD_AUDIO>; 1948 pinctrl-names = "default"; 1949 pinctrl-0 = <&i2s2m1_lrck 1950 &i2s2m1_sclk 1951 &i2s2m1_sdi 1952 &i2s2m1_sdo>; 1953 #sound-dai-cells = <0>; 1954 status = "disabled"; 1955 }; 1956 1957 i2s3_2ch: i2s@fe4a0000 { 1958 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1959 reg = <0x0 0xfe4a0000 0x0 0x1000>; 1960 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; 1961 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 1962 clock-names = "i2s_clk", "i2s_hclk"; 1963 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 1964 assigned-clock-parents = <&cru PLL_AUPLL>; 1965 dmas = <&dmac1 2>, <&dmac1 3>; 1966 dma-names = "tx", "rx"; 1967 power-domains = <&power RK3588_PD_AUDIO>; 1968 pinctrl-names = "default"; 1969 pinctrl-0 = <&i2s3_lrck 1970 &i2s3_sclk 1971 &i2s3_sdi 1972 &i2s3_sdo>; 1973 #sound-dai-cells = <0>; 1974 status = "disabled"; 1975 }; 1976 1977 gic: interrupt-controller@fe600000 { 1978 compatible = "arm,gic-v3"; 1979 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 1980 <0x0 0xfe680000 0 0x100000>; /* GICR */ 1981 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 1982 interrupt-controller; 1983 mbi-alias = <0x0 0xfe610000>; 1984 mbi-ranges = <424 56>; 1985 msi-controller; 1986 ranges; 1987 #address-cells = <2>; 1988 #interrupt-cells = <4>; 1989 #size-cells = <2>; 1990 1991 its0: msi-controller@fe640000 { 1992 compatible = "arm,gic-v3-its"; 1993 reg = <0x0 0xfe640000 0x0 0x20000>; 1994 msi-controller; 1995 #msi-cells = <1>; 1996 }; 1997 1998 its1: msi-controller@fe660000 { 1999 compatible = "arm,gic-v3-its"; 2000 reg = <0x0 0xfe660000 0x0 0x20000>; 2001 msi-controller; 2002 #msi-cells = <1>; 2003 }; 2004 2005 ppi-partitions { 2006 ppi_partition0: interrupt-partition-0 { 2007 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 2008 }; 2009 2010 ppi_partition1: interrupt-partition-1 { 2011 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; 2012 }; 2013 }; 2014 }; 2015 2016 dmac0: dma-controller@fea10000 { 2017 compatible = "arm,pl330", "arm,primecell"; 2018 reg = <0x0 0xfea10000 0x0 0x4000>; 2019 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, 2020 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; 2021 arm,pl330-periph-burst; 2022 clocks = <&cru ACLK_DMAC0>; 2023 clock-names = "apb_pclk"; 2024 #dma-cells = <1>; 2025 }; 2026 2027 dmac1: dma-controller@fea30000 { 2028 compatible = "arm,pl330", "arm,primecell"; 2029 reg = <0x0 0xfea30000 0x0 0x4000>; 2030 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, 2031 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; 2032 arm,pl330-periph-burst; 2033 clocks = <&cru ACLK_DMAC1>; 2034 clock-names = "apb_pclk"; 2035 #dma-cells = <1>; 2036 }; 2037 2038 i2c1: i2c@fea90000 { 2039 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2040 reg = <0x0 0xfea90000 0x0 0x1000>; 2041 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 2042 clock-names = "i2c", "pclk"; 2043 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; 2044 pinctrl-0 = <&i2c1m0_xfer>; 2045 pinctrl-names = "default"; 2046 #address-cells = <1>; 2047 #size-cells = <0>; 2048 status = "disabled"; 2049 }; 2050 2051 i2c2: i2c@feaa0000 { 2052 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2053 reg = <0x0 0xfeaa0000 0x0 0x1000>; 2054 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 2055 clock-names = "i2c", "pclk"; 2056 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; 2057 pinctrl-0 = <&i2c2m0_xfer>; 2058 pinctrl-names = "default"; 2059 #address-cells = <1>; 2060 #size-cells = <0>; 2061 status = "disabled"; 2062 }; 2063 2064 i2c3: i2c@feab0000 { 2065 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2066 reg = <0x0 0xfeab0000 0x0 0x1000>; 2067 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 2068 clock-names = "i2c", "pclk"; 2069 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; 2070 pinctrl-0 = <&i2c3m0_xfer>; 2071 pinctrl-names = "default"; 2072 #address-cells = <1>; 2073 #size-cells = <0>; 2074 status = "disabled"; 2075 }; 2076 2077 i2c4: i2c@feac0000 { 2078 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2079 reg = <0x0 0xfeac0000 0x0 0x1000>; 2080 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2081 clock-names = "i2c", "pclk"; 2082 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; 2083 pinctrl-0 = <&i2c4m0_xfer>; 2084 pinctrl-names = "default"; 2085 #address-cells = <1>; 2086 #size-cells = <0>; 2087 status = "disabled"; 2088 }; 2089 2090 i2c5: i2c@fead0000 { 2091 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2092 reg = <0x0 0xfead0000 0x0 0x1000>; 2093 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2094 clock-names = "i2c", "pclk"; 2095 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; 2096 pinctrl-0 = <&i2c5m0_xfer>; 2097 pinctrl-names = "default"; 2098 #address-cells = <1>; 2099 #size-cells = <0>; 2100 status = "disabled"; 2101 }; 2102 2103 timer0: timer@feae0000 { 2104 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 2105 reg = <0x0 0xfeae0000 0x0 0x20>; 2106 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; 2107 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 2108 clock-names = "pclk", "timer"; 2109 }; 2110 2111 wdt: watchdog@feaf0000 { 2112 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; 2113 reg = <0x0 0xfeaf0000 0x0 0x100>; 2114 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 2115 clock-names = "tclk", "pclk"; 2116 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; 2117 }; 2118 2119 spi0: spi@feb00000 { 2120 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2121 reg = <0x0 0xfeb00000 0x0 0x1000>; 2122 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; 2123 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 2124 clock-names = "spiclk", "apb_pclk"; 2125 dmas = <&dmac0 14>, <&dmac0 15>; 2126 dma-names = "tx", "rx"; 2127 num-cs = <2>; 2128 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 2129 pinctrl-names = "default"; 2130 #address-cells = <1>; 2131 #size-cells = <0>; 2132 status = "disabled"; 2133 }; 2134 2135 spi1: spi@feb10000 { 2136 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2137 reg = <0x0 0xfeb10000 0x0 0x1000>; 2138 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; 2139 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 2140 clock-names = "spiclk", "apb_pclk"; 2141 dmas = <&dmac0 16>, <&dmac0 17>; 2142 dma-names = "tx", "rx"; 2143 num-cs = <2>; 2144 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 2145 pinctrl-names = "default"; 2146 #address-cells = <1>; 2147 #size-cells = <0>; 2148 status = "disabled"; 2149 }; 2150 2151 spi2: spi@feb20000 { 2152 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2153 reg = <0x0 0xfeb20000 0x0 0x1000>; 2154 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; 2155 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 2156 clock-names = "spiclk", "apb_pclk"; 2157 dmas = <&dmac1 15>, <&dmac1 16>; 2158 dma-names = "tx", "rx"; 2159 num-cs = <2>; 2160 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 2161 pinctrl-names = "default"; 2162 #address-cells = <1>; 2163 #size-cells = <0>; 2164 status = "disabled"; 2165 }; 2166 2167 spi3: spi@feb30000 { 2168 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2169 reg = <0x0 0xfeb30000 0x0 0x1000>; 2170 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; 2171 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 2172 clock-names = "spiclk", "apb_pclk"; 2173 dmas = <&dmac1 17>, <&dmac1 18>; 2174 dma-names = "tx", "rx"; 2175 num-cs = <2>; 2176 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 2177 pinctrl-names = "default"; 2178 #address-cells = <1>; 2179 #size-cells = <0>; 2180 status = "disabled"; 2181 }; 2182 2183 uart1: serial@feb40000 { 2184 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2185 reg = <0x0 0xfeb40000 0x0 0x100>; 2186 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; 2187 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 2188 clock-names = "baudclk", "apb_pclk"; 2189 dmas = <&dmac0 8>, <&dmac0 9>; 2190 dma-names = "tx", "rx"; 2191 pinctrl-0 = <&uart1m1_xfer>; 2192 pinctrl-names = "default"; 2193 reg-io-width = <4>; 2194 reg-shift = <2>; 2195 status = "disabled"; 2196 }; 2197 2198 uart2: serial@feb50000 { 2199 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2200 reg = <0x0 0xfeb50000 0x0 0x100>; 2201 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; 2202 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 2203 clock-names = "baudclk", "apb_pclk"; 2204 dmas = <&dmac0 10>, <&dmac0 11>; 2205 dma-names = "tx", "rx"; 2206 pinctrl-0 = <&uart2m1_xfer>; 2207 pinctrl-names = "default"; 2208 reg-io-width = <4>; 2209 reg-shift = <2>; 2210 status = "disabled"; 2211 }; 2212 2213 uart3: serial@feb60000 { 2214 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2215 reg = <0x0 0xfeb60000 0x0 0x100>; 2216 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; 2217 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 2218 clock-names = "baudclk", "apb_pclk"; 2219 dmas = <&dmac0 12>, <&dmac0 13>; 2220 dma-names = "tx", "rx"; 2221 pinctrl-0 = <&uart3m1_xfer>; 2222 pinctrl-names = "default"; 2223 reg-io-width = <4>; 2224 reg-shift = <2>; 2225 status = "disabled"; 2226 }; 2227 2228 uart4: serial@feb70000 { 2229 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2230 reg = <0x0 0xfeb70000 0x0 0x100>; 2231 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; 2232 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 2233 clock-names = "baudclk", "apb_pclk"; 2234 dmas = <&dmac1 9>, <&dmac1 10>; 2235 dma-names = "tx", "rx"; 2236 pinctrl-0 = <&uart4m1_xfer>; 2237 pinctrl-names = "default"; 2238 reg-io-width = <4>; 2239 reg-shift = <2>; 2240 status = "disabled"; 2241 }; 2242 2243 uart5: serial@feb80000 { 2244 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2245 reg = <0x0 0xfeb80000 0x0 0x100>; 2246 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; 2247 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2248 clock-names = "baudclk", "apb_pclk"; 2249 dmas = <&dmac1 11>, <&dmac1 12>; 2250 dma-names = "tx", "rx"; 2251 pinctrl-0 = <&uart5m1_xfer>; 2252 pinctrl-names = "default"; 2253 reg-io-width = <4>; 2254 reg-shift = <2>; 2255 status = "disabled"; 2256 }; 2257 2258 uart6: serial@feb90000 { 2259 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2260 reg = <0x0 0xfeb90000 0x0 0x100>; 2261 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; 2262 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2263 clock-names = "baudclk", "apb_pclk"; 2264 dmas = <&dmac1 13>, <&dmac1 14>; 2265 dma-names = "tx", "rx"; 2266 pinctrl-0 = <&uart6m1_xfer>; 2267 pinctrl-names = "default"; 2268 reg-io-width = <4>; 2269 reg-shift = <2>; 2270 status = "disabled"; 2271 }; 2272 2273 uart7: serial@feba0000 { 2274 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2275 reg = <0x0 0xfeba0000 0x0 0x100>; 2276 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; 2277 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2278 clock-names = "baudclk", "apb_pclk"; 2279 dmas = <&dmac2 7>, <&dmac2 8>; 2280 dma-names = "tx", "rx"; 2281 pinctrl-0 = <&uart7m1_xfer>; 2282 pinctrl-names = "default"; 2283 reg-io-width = <4>; 2284 reg-shift = <2>; 2285 status = "disabled"; 2286 }; 2287 2288 uart8: serial@febb0000 { 2289 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2290 reg = <0x0 0xfebb0000 0x0 0x100>; 2291 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; 2292 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2293 clock-names = "baudclk", "apb_pclk"; 2294 dmas = <&dmac2 9>, <&dmac2 10>; 2295 dma-names = "tx", "rx"; 2296 pinctrl-0 = <&uart8m1_xfer>; 2297 pinctrl-names = "default"; 2298 reg-io-width = <4>; 2299 reg-shift = <2>; 2300 status = "disabled"; 2301 }; 2302 2303 uart9: serial@febc0000 { 2304 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2305 reg = <0x0 0xfebc0000 0x0 0x100>; 2306 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; 2307 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2308 clock-names = "baudclk", "apb_pclk"; 2309 dmas = <&dmac2 11>, <&dmac2 12>; 2310 dma-names = "tx", "rx"; 2311 pinctrl-0 = <&uart9m1_xfer>; 2312 pinctrl-names = "default"; 2313 reg-io-width = <4>; 2314 reg-shift = <2>; 2315 status = "disabled"; 2316 }; 2317 2318 pwm4: pwm@febd0000 { 2319 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2320 reg = <0x0 0xfebd0000 0x0 0x10>; 2321 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2322 clock-names = "pwm", "pclk"; 2323 pinctrl-0 = <&pwm4m0_pins>; 2324 pinctrl-names = "default"; 2325 #pwm-cells = <3>; 2326 status = "disabled"; 2327 }; 2328 2329 pwm5: pwm@febd0010 { 2330 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2331 reg = <0x0 0xfebd0010 0x0 0x10>; 2332 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2333 clock-names = "pwm", "pclk"; 2334 pinctrl-0 = <&pwm5m0_pins>; 2335 pinctrl-names = "default"; 2336 #pwm-cells = <3>; 2337 status = "disabled"; 2338 }; 2339 2340 pwm6: pwm@febd0020 { 2341 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2342 reg = <0x0 0xfebd0020 0x0 0x10>; 2343 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2344 clock-names = "pwm", "pclk"; 2345 pinctrl-0 = <&pwm6m0_pins>; 2346 pinctrl-names = "default"; 2347 #pwm-cells = <3>; 2348 status = "disabled"; 2349 }; 2350 2351 pwm7: pwm@febd0030 { 2352 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2353 reg = <0x0 0xfebd0030 0x0 0x10>; 2354 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2355 clock-names = "pwm", "pclk"; 2356 pinctrl-0 = <&pwm7m0_pins>; 2357 pinctrl-names = "default"; 2358 #pwm-cells = <3>; 2359 status = "disabled"; 2360 }; 2361 2362 pwm8: pwm@febe0000 { 2363 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2364 reg = <0x0 0xfebe0000 0x0 0x10>; 2365 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2366 clock-names = "pwm", "pclk"; 2367 pinctrl-0 = <&pwm8m0_pins>; 2368 pinctrl-names = "default"; 2369 #pwm-cells = <3>; 2370 status = "disabled"; 2371 }; 2372 2373 pwm9: pwm@febe0010 { 2374 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2375 reg = <0x0 0xfebe0010 0x0 0x10>; 2376 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2377 clock-names = "pwm", "pclk"; 2378 pinctrl-0 = <&pwm9m0_pins>; 2379 pinctrl-names = "default"; 2380 #pwm-cells = <3>; 2381 status = "disabled"; 2382 }; 2383 2384 pwm10: pwm@febe0020 { 2385 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2386 reg = <0x0 0xfebe0020 0x0 0x10>; 2387 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2388 clock-names = "pwm", "pclk"; 2389 pinctrl-0 = <&pwm10m0_pins>; 2390 pinctrl-names = "default"; 2391 #pwm-cells = <3>; 2392 status = "disabled"; 2393 }; 2394 2395 pwm11: pwm@febe0030 { 2396 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2397 reg = <0x0 0xfebe0030 0x0 0x10>; 2398 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2399 clock-names = "pwm", "pclk"; 2400 pinctrl-0 = <&pwm11m0_pins>; 2401 pinctrl-names = "default"; 2402 #pwm-cells = <3>; 2403 status = "disabled"; 2404 }; 2405 2406 pwm12: pwm@febf0000 { 2407 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2408 reg = <0x0 0xfebf0000 0x0 0x10>; 2409 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2410 clock-names = "pwm", "pclk"; 2411 pinctrl-0 = <&pwm12m0_pins>; 2412 pinctrl-names = "default"; 2413 #pwm-cells = <3>; 2414 status = "disabled"; 2415 }; 2416 2417 pwm13: pwm@febf0010 { 2418 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2419 reg = <0x0 0xfebf0010 0x0 0x10>; 2420 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2421 clock-names = "pwm", "pclk"; 2422 pinctrl-0 = <&pwm13m0_pins>; 2423 pinctrl-names = "default"; 2424 #pwm-cells = <3>; 2425 status = "disabled"; 2426 }; 2427 2428 pwm14: pwm@febf0020 { 2429 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2430 reg = <0x0 0xfebf0020 0x0 0x10>; 2431 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2432 clock-names = "pwm", "pclk"; 2433 pinctrl-0 = <&pwm14m0_pins>; 2434 pinctrl-names = "default"; 2435 #pwm-cells = <3>; 2436 status = "disabled"; 2437 }; 2438 2439 pwm15: pwm@febf0030 { 2440 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2441 reg = <0x0 0xfebf0030 0x0 0x10>; 2442 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2443 clock-names = "pwm", "pclk"; 2444 pinctrl-0 = <&pwm15m0_pins>; 2445 pinctrl-names = "default"; 2446 #pwm-cells = <3>; 2447 status = "disabled"; 2448 }; 2449 2450 thermal_zones: thermal-zones { 2451 /* sensor near the center of the SoC */ 2452 package_thermal: package-thermal { 2453 polling-delay-passive = <0>; 2454 polling-delay = <0>; 2455 thermal-sensors = <&tsadc 0>; 2456 2457 trips { 2458 package_crit: package-crit { 2459 temperature = <115000>; 2460 hysteresis = <0>; 2461 type = "critical"; 2462 }; 2463 }; 2464 }; 2465 2466 /* sensor between A76 cores 0 and 1 */ 2467 bigcore0_thermal: bigcore0-thermal { 2468 polling-delay-passive = <100>; 2469 polling-delay = <0>; 2470 thermal-sensors = <&tsadc 1>; 2471 2472 trips { 2473 bigcore0_alert: bigcore0-alert { 2474 temperature = <85000>; 2475 hysteresis = <2000>; 2476 type = "passive"; 2477 }; 2478 2479 bigcore0_crit: bigcore0-crit { 2480 temperature = <115000>; 2481 hysteresis = <0>; 2482 type = "critical"; 2483 }; 2484 }; 2485 2486 cooling-maps { 2487 map0 { 2488 trip = <&bigcore0_alert>; 2489 cooling-device = 2490 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2491 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2492 }; 2493 }; 2494 }; 2495 2496 /* sensor between A76 cores 2 and 3 */ 2497 bigcore2_thermal: bigcore2-thermal { 2498 polling-delay-passive = <100>; 2499 polling-delay = <0>; 2500 thermal-sensors = <&tsadc 2>; 2501 2502 trips { 2503 bigcore2_alert: bigcore2-alert { 2504 temperature = <85000>; 2505 hysteresis = <2000>; 2506 type = "passive"; 2507 }; 2508 2509 bigcore2_crit: bigcore2-crit { 2510 temperature = <115000>; 2511 hysteresis = <0>; 2512 type = "critical"; 2513 }; 2514 }; 2515 2516 cooling-maps { 2517 map0 { 2518 trip = <&bigcore2_alert>; 2519 cooling-device = 2520 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2521 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2522 }; 2523 }; 2524 }; 2525 2526 /* sensor between the four A55 cores */ 2527 little_core_thermal: littlecore-thermal { 2528 polling-delay-passive = <100>; 2529 polling-delay = <0>; 2530 thermal-sensors = <&tsadc 3>; 2531 2532 trips { 2533 littlecore_alert: littlecore-alert { 2534 temperature = <85000>; 2535 hysteresis = <2000>; 2536 type = "passive"; 2537 }; 2538 2539 littlecore_crit: littlecore-crit { 2540 temperature = <115000>; 2541 hysteresis = <0>; 2542 type = "critical"; 2543 }; 2544 }; 2545 2546 cooling-maps { 2547 map0 { 2548 trip = <&littlecore_alert>; 2549 cooling-device = 2550 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2551 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2552 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2553 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2554 }; 2555 }; 2556 }; 2557 2558 /* sensor near the PD_CENTER power domain */ 2559 center_thermal: center-thermal { 2560 polling-delay-passive = <0>; 2561 polling-delay = <0>; 2562 thermal-sensors = <&tsadc 4>; 2563 2564 trips { 2565 center_crit: center-crit { 2566 temperature = <115000>; 2567 hysteresis = <0>; 2568 type = "critical"; 2569 }; 2570 }; 2571 }; 2572 2573 gpu_thermal: gpu-thermal { 2574 polling-delay-passive = <100>; 2575 polling-delay = <0>; 2576 thermal-sensors = <&tsadc 5>; 2577 2578 trips { 2579 gpu_alert: gpu-alert { 2580 temperature = <85000>; 2581 hysteresis = <2000>; 2582 type = "passive"; 2583 }; 2584 2585 gpu_crit: gpu-crit { 2586 temperature = <115000>; 2587 hysteresis = <0>; 2588 type = "critical"; 2589 }; 2590 }; 2591 2592 cooling-maps { 2593 map0 { 2594 trip = <&gpu_alert>; 2595 cooling-device = 2596 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2597 }; 2598 }; 2599 }; 2600 2601 npu_thermal: npu-thermal { 2602 polling-delay-passive = <0>; 2603 polling-delay = <0>; 2604 thermal-sensors = <&tsadc 6>; 2605 2606 trips { 2607 npu_crit: npu-crit { 2608 temperature = <115000>; 2609 hysteresis = <0>; 2610 type = "critical"; 2611 }; 2612 }; 2613 }; 2614 }; 2615 2616 tsadc: tsadc@fec00000 { 2617 compatible = "rockchip,rk3588-tsadc"; 2618 reg = <0x0 0xfec00000 0x0 0x400>; 2619 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; 2620 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2621 clock-names = "tsadc", "apb_pclk"; 2622 assigned-clocks = <&cru CLK_TSADC>; 2623 assigned-clock-rates = <2000000>; 2624 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 2625 reset-names = "tsadc-apb", "tsadc"; 2626 rockchip,hw-tshut-temp = <120000>; 2627 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 2628 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2629 pinctrl-0 = <&tsadc_gpio_func>; 2630 pinctrl-1 = <&tsadc_shut>; 2631 pinctrl-names = "gpio", "otpout"; 2632 #thermal-sensor-cells = <1>; 2633 status = "disabled"; 2634 }; 2635 2636 saradc: adc@fec10000 { 2637 compatible = "rockchip,rk3588-saradc"; 2638 reg = <0x0 0xfec10000 0x0 0x10000>; 2639 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; 2640 #io-channel-cells = <1>; 2641 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2642 clock-names = "saradc", "apb_pclk"; 2643 resets = <&cru SRST_P_SARADC>; 2644 reset-names = "saradc-apb"; 2645 status = "disabled"; 2646 }; 2647 2648 i2c6: i2c@fec80000 { 2649 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2650 reg = <0x0 0xfec80000 0x0 0x1000>; 2651 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2652 clock-names = "i2c", "pclk"; 2653 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; 2654 pinctrl-0 = <&i2c6m0_xfer>; 2655 pinctrl-names = "default"; 2656 #address-cells = <1>; 2657 #size-cells = <0>; 2658 status = "disabled"; 2659 }; 2660 2661 i2c7: i2c@fec90000 { 2662 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2663 reg = <0x0 0xfec90000 0x0 0x1000>; 2664 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2665 clock-names = "i2c", "pclk"; 2666 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 2667 pinctrl-0 = <&i2c7m0_xfer>; 2668 pinctrl-names = "default"; 2669 #address-cells = <1>; 2670 #size-cells = <0>; 2671 status = "disabled"; 2672 }; 2673 2674 i2c8: i2c@feca0000 { 2675 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2676 reg = <0x0 0xfeca0000 0x0 0x1000>; 2677 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2678 clock-names = "i2c", "pclk"; 2679 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; 2680 pinctrl-0 = <&i2c8m0_xfer>; 2681 pinctrl-names = "default"; 2682 #address-cells = <1>; 2683 #size-cells = <0>; 2684 status = "disabled"; 2685 }; 2686 2687 spi4: spi@fecb0000 { 2688 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2689 reg = <0x0 0xfecb0000 0x0 0x1000>; 2690 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; 2691 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2692 clock-names = "spiclk", "apb_pclk"; 2693 dmas = <&dmac2 13>, <&dmac2 14>; 2694 dma-names = "tx", "rx"; 2695 num-cs = <2>; 2696 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 2697 pinctrl-names = "default"; 2698 #address-cells = <1>; 2699 #size-cells = <0>; 2700 status = "disabled"; 2701 }; 2702 2703 otp: efuse@fecc0000 { 2704 compatible = "rockchip,rk3588-otp"; 2705 reg = <0x0 0xfecc0000 0x0 0x400>; 2706 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 2707 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; 2708 clock-names = "otp", "apb_pclk", "phy", "arb"; 2709 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 2710 <&cru SRST_OTPC_ARB>; 2711 reset-names = "otp", "apb", "arb"; 2712 #address-cells = <1>; 2713 #size-cells = <1>; 2714 2715 cpu_code: cpu-code@2 { 2716 reg = <0x02 0x2>; 2717 }; 2718 2719 otp_id: id@7 { 2720 reg = <0x07 0x10>; 2721 }; 2722 2723 cpub0_leakage: cpu-leakage@17 { 2724 reg = <0x17 0x1>; 2725 }; 2726 2727 cpub1_leakage: cpu-leakage@18 { 2728 reg = <0x18 0x1>; 2729 }; 2730 2731 cpul_leakage: cpu-leakage@19 { 2732 reg = <0x19 0x1>; 2733 }; 2734 2735 log_leakage: log-leakage@1a { 2736 reg = <0x1a 0x1>; 2737 }; 2738 2739 gpu_leakage: gpu-leakage@1b { 2740 reg = <0x1b 0x1>; 2741 }; 2742 2743 otp_cpu_version: cpu-version@1c { 2744 reg = <0x1c 0x1>; 2745 bits = <3 3>; 2746 }; 2747 2748 npu_leakage: npu-leakage@28 { 2749 reg = <0x28 0x1>; 2750 }; 2751 2752 codec_leakage: codec-leakage@29 { 2753 reg = <0x29 0x1>; 2754 }; 2755 }; 2756 2757 dmac2: dma-controller@fed10000 { 2758 compatible = "arm,pl330", "arm,primecell"; 2759 reg = <0x0 0xfed10000 0x0 0x4000>; 2760 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, 2761 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; 2762 arm,pl330-periph-burst; 2763 clocks = <&cru ACLK_DMAC2>; 2764 clock-names = "apb_pclk"; 2765 #dma-cells = <1>; 2766 }; 2767 2768 hdptxphy_hdmi0: phy@fed60000 { 2769 compatible = "rockchip,rk3588-hdptx-phy"; 2770 reg = <0x0 0xfed60000 0x0 0x2000>; 2771 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 2772 clock-names = "ref", "apb"; 2773 #phy-cells = <0>; 2774 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, 2775 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, 2776 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, 2777 <&cru SRST_HDPTX0_LCPLL>; 2778 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 2779 "lcpll"; 2780 rockchip,grf = <&hdptxphy0_grf>; 2781 status = "disabled"; 2782 }; 2783 2784 usbdp_phy0: phy@fed80000 { 2785 compatible = "rockchip,rk3588-usbdp-phy"; 2786 reg = <0x0 0xfed80000 0x0 0x10000>; 2787 #phy-cells = <1>; 2788 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 2789 <&cru CLK_USBDP_PHY0_IMMORTAL>, 2790 <&cru PCLK_USBDPPHY0>, 2791 <&u2phy0>; 2792 clock-names = "refclk", "immortal", "pclk", "utmi"; 2793 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 2794 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 2795 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 2796 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 2797 <&cru SRST_P_USBDPPHY0>; 2798 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 2799 rockchip,u2phy-grf = <&usb2phy0_grf>; 2800 rockchip,usb-grf = <&usb_grf>; 2801 rockchip,usbdpphy-grf = <&usbdpphy0_grf>; 2802 rockchip,vo-grf = <&vo0_grf>; 2803 status = "disabled"; 2804 }; 2805 2806 combphy0_ps: phy@fee00000 { 2807 compatible = "rockchip,rk3588-naneng-combphy"; 2808 reg = <0x0 0xfee00000 0x0 0x100>; 2809 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, 2810 <&cru PCLK_PHP_ROOT>; 2811 clock-names = "ref", "apb", "pipe"; 2812 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 2813 assigned-clock-rates = <100000000>; 2814 #phy-cells = <1>; 2815 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; 2816 reset-names = "phy", "apb"; 2817 rockchip,pipe-grf = <&php_grf>; 2818 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 2819 status = "disabled"; 2820 }; 2821 2822 combphy2_psu: phy@fee20000 { 2823 compatible = "rockchip,rk3588-naneng-combphy"; 2824 reg = <0x0 0xfee20000 0x0 0x100>; 2825 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, 2826 <&cru PCLK_PHP_ROOT>; 2827 clock-names = "ref", "apb", "pipe"; 2828 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 2829 assigned-clock-rates = <100000000>; 2830 #phy-cells = <1>; 2831 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; 2832 reset-names = "phy", "apb"; 2833 rockchip,pipe-grf = <&php_grf>; 2834 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 2835 status = "disabled"; 2836 }; 2837 2838 system_sram2: sram@ff001000 { 2839 compatible = "mmio-sram"; 2840 reg = <0x0 0xff001000 0x0 0xef000>; 2841 ranges = <0x0 0x0 0xff001000 0xef000>; 2842 #address-cells = <1>; 2843 #size-cells = <1>; 2844 }; 2845 2846 pinctrl: pinctrl { 2847 compatible = "rockchip,rk3588-pinctrl"; 2848 ranges; 2849 rockchip,grf = <&ioc>; 2850 #address-cells = <2>; 2851 #size-cells = <2>; 2852 2853 gpio0: gpio@fd8a0000 { 2854 compatible = "rockchip,gpio-bank"; 2855 reg = <0x0 0xfd8a0000 0x0 0x100>; 2856 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 2857 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 2858 gpio-controller; 2859 gpio-ranges = <&pinctrl 0 0 32>; 2860 interrupt-controller; 2861 #gpio-cells = <2>; 2862 #interrupt-cells = <2>; 2863 }; 2864 2865 gpio1: gpio@fec20000 { 2866 compatible = "rockchip,gpio-bank"; 2867 reg = <0x0 0xfec20000 0x0 0x100>; 2868 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; 2869 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2870 gpio-controller; 2871 gpio-ranges = <&pinctrl 0 32 32>; 2872 interrupt-controller; 2873 #gpio-cells = <2>; 2874 #interrupt-cells = <2>; 2875 }; 2876 2877 gpio2: gpio@fec30000 { 2878 compatible = "rockchip,gpio-bank"; 2879 reg = <0x0 0xfec30000 0x0 0x100>; 2880 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; 2881 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2882 gpio-controller; 2883 gpio-ranges = <&pinctrl 0 64 32>; 2884 interrupt-controller; 2885 #gpio-cells = <2>; 2886 #interrupt-cells = <2>; 2887 }; 2888 2889 gpio3: gpio@fec40000 { 2890 compatible = "rockchip,gpio-bank"; 2891 reg = <0x0 0xfec40000 0x0 0x100>; 2892 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; 2893 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2894 gpio-controller; 2895 gpio-ranges = <&pinctrl 0 96 32>; 2896 interrupt-controller; 2897 #gpio-cells = <2>; 2898 #interrupt-cells = <2>; 2899 }; 2900 2901 gpio4: gpio@fec50000 { 2902 compatible = "rockchip,gpio-bank"; 2903 reg = <0x0 0xfec50000 0x0 0x100>; 2904 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; 2905 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2906 gpio-controller; 2907 gpio-ranges = <&pinctrl 0 128 32>; 2908 interrupt-controller; 2909 #gpio-cells = <2>; 2910 #interrupt-cells = <2>; 2911 }; 2912 }; 2913}; 2914 2915#include "rk3588-base-pinctrl.dtsi" 2916