1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/power/rk3588-power.h> 10#include <dt-bindings/reset/rockchip,rk3588-cru.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/ata/ahci.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3588"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 gpio4 = &gpio4; 28 i2c0 = &i2c0; 29 i2c1 = &i2c1; 30 i2c2 = &i2c2; 31 i2c3 = &i2c3; 32 i2c4 = &i2c4; 33 i2c5 = &i2c5; 34 i2c6 = &i2c6; 35 i2c7 = &i2c7; 36 i2c8 = &i2c8; 37 serial0 = &uart0; 38 serial1 = &uart1; 39 serial2 = &uart2; 40 serial3 = &uart3; 41 serial4 = &uart4; 42 serial5 = &uart5; 43 serial6 = &uart6; 44 serial7 = &uart7; 45 serial8 = &uart8; 46 serial9 = &uart9; 47 spi0 = &spi0; 48 spi1 = &spi1; 49 spi2 = &spi2; 50 spi3 = &spi3; 51 spi4 = &spi4; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu_l0>; 62 }; 63 core1 { 64 cpu = <&cpu_l1>; 65 }; 66 core2 { 67 cpu = <&cpu_l2>; 68 }; 69 core3 { 70 cpu = <&cpu_l3>; 71 }; 72 }; 73 cluster1 { 74 core0 { 75 cpu = <&cpu_b0>; 76 }; 77 core1 { 78 cpu = <&cpu_b1>; 79 }; 80 }; 81 cluster2 { 82 core0 { 83 cpu = <&cpu_b2>; 84 }; 85 core1 { 86 cpu = <&cpu_b3>; 87 }; 88 }; 89 }; 90 91 cpu_l0: cpu@0 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0>; 95 enable-method = "psci"; 96 capacity-dmips-mhz = <530>; 97 clocks = <&scmi_clk SCMI_CLK_CPUL>; 98 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; 99 assigned-clock-rates = <816000000>; 100 cpu-idle-states = <&CPU_SLEEP>; 101 i-cache-size = <32768>; 102 i-cache-line-size = <64>; 103 i-cache-sets = <128>; 104 d-cache-size = <32768>; 105 d-cache-line-size = <64>; 106 d-cache-sets = <128>; 107 next-level-cache = <&l2_cache_l0>; 108 dynamic-power-coefficient = <228>; 109 #cooling-cells = <2>; 110 }; 111 112 cpu_l1: cpu@100 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a55"; 115 reg = <0x100>; 116 enable-method = "psci"; 117 capacity-dmips-mhz = <530>; 118 clocks = <&scmi_clk SCMI_CLK_CPUL>; 119 cpu-idle-states = <&CPU_SLEEP>; 120 i-cache-size = <32768>; 121 i-cache-line-size = <64>; 122 i-cache-sets = <128>; 123 d-cache-size = <32768>; 124 d-cache-line-size = <64>; 125 d-cache-sets = <128>; 126 next-level-cache = <&l2_cache_l1>; 127 dynamic-power-coefficient = <228>; 128 #cooling-cells = <2>; 129 }; 130 131 cpu_l2: cpu@200 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a55"; 134 reg = <0x200>; 135 enable-method = "psci"; 136 capacity-dmips-mhz = <530>; 137 clocks = <&scmi_clk SCMI_CLK_CPUL>; 138 cpu-idle-states = <&CPU_SLEEP>; 139 i-cache-size = <32768>; 140 i-cache-line-size = <64>; 141 i-cache-sets = <128>; 142 d-cache-size = <32768>; 143 d-cache-line-size = <64>; 144 d-cache-sets = <128>; 145 next-level-cache = <&l2_cache_l2>; 146 dynamic-power-coefficient = <228>; 147 #cooling-cells = <2>; 148 }; 149 150 cpu_l3: cpu@300 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a55"; 153 reg = <0x300>; 154 enable-method = "psci"; 155 capacity-dmips-mhz = <530>; 156 clocks = <&scmi_clk SCMI_CLK_CPUL>; 157 cpu-idle-states = <&CPU_SLEEP>; 158 i-cache-size = <32768>; 159 i-cache-line-size = <64>; 160 i-cache-sets = <128>; 161 d-cache-size = <32768>; 162 d-cache-line-size = <64>; 163 d-cache-sets = <128>; 164 next-level-cache = <&l2_cache_l3>; 165 dynamic-power-coefficient = <228>; 166 #cooling-cells = <2>; 167 }; 168 169 cpu_b0: cpu@400 { 170 device_type = "cpu"; 171 compatible = "arm,cortex-a76"; 172 reg = <0x400>; 173 enable-method = "psci"; 174 capacity-dmips-mhz = <1024>; 175 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 176 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; 177 assigned-clock-rates = <816000000>; 178 cpu-idle-states = <&CPU_SLEEP>; 179 i-cache-size = <65536>; 180 i-cache-line-size = <64>; 181 i-cache-sets = <256>; 182 d-cache-size = <65536>; 183 d-cache-line-size = <64>; 184 d-cache-sets = <256>; 185 next-level-cache = <&l2_cache_b0>; 186 dynamic-power-coefficient = <416>; 187 #cooling-cells = <2>; 188 }; 189 190 cpu_b1: cpu@500 { 191 device_type = "cpu"; 192 compatible = "arm,cortex-a76"; 193 reg = <0x500>; 194 enable-method = "psci"; 195 capacity-dmips-mhz = <1024>; 196 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 197 cpu-idle-states = <&CPU_SLEEP>; 198 i-cache-size = <65536>; 199 i-cache-line-size = <64>; 200 i-cache-sets = <256>; 201 d-cache-size = <65536>; 202 d-cache-line-size = <64>; 203 d-cache-sets = <256>; 204 next-level-cache = <&l2_cache_b1>; 205 dynamic-power-coefficient = <416>; 206 #cooling-cells = <2>; 207 }; 208 209 cpu_b2: cpu@600 { 210 device_type = "cpu"; 211 compatible = "arm,cortex-a76"; 212 reg = <0x600>; 213 enable-method = "psci"; 214 capacity-dmips-mhz = <1024>; 215 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 216 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; 217 assigned-clock-rates = <816000000>; 218 cpu-idle-states = <&CPU_SLEEP>; 219 i-cache-size = <65536>; 220 i-cache-line-size = <64>; 221 i-cache-sets = <256>; 222 d-cache-size = <65536>; 223 d-cache-line-size = <64>; 224 d-cache-sets = <256>; 225 next-level-cache = <&l2_cache_b2>; 226 dynamic-power-coefficient = <416>; 227 #cooling-cells = <2>; 228 }; 229 230 cpu_b3: cpu@700 { 231 device_type = "cpu"; 232 compatible = "arm,cortex-a76"; 233 reg = <0x700>; 234 enable-method = "psci"; 235 capacity-dmips-mhz = <1024>; 236 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 237 cpu-idle-states = <&CPU_SLEEP>; 238 i-cache-size = <65536>; 239 i-cache-line-size = <64>; 240 i-cache-sets = <256>; 241 d-cache-size = <65536>; 242 d-cache-line-size = <64>; 243 d-cache-sets = <256>; 244 next-level-cache = <&l2_cache_b3>; 245 dynamic-power-coefficient = <416>; 246 #cooling-cells = <2>; 247 }; 248 249 idle-states { 250 entry-method = "psci"; 251 CPU_SLEEP: cpu-sleep { 252 compatible = "arm,idle-state"; 253 local-timer-stop; 254 arm,psci-suspend-param = <0x0010000>; 255 entry-latency-us = <100>; 256 exit-latency-us = <120>; 257 min-residency-us = <1000>; 258 }; 259 }; 260 261 l2_cache_l0: l2-cache-l0 { 262 compatible = "cache"; 263 cache-size = <131072>; 264 cache-line-size = <64>; 265 cache-sets = <512>; 266 cache-level = <2>; 267 cache-unified; 268 next-level-cache = <&l3_cache>; 269 }; 270 271 l2_cache_l1: l2-cache-l1 { 272 compatible = "cache"; 273 cache-size = <131072>; 274 cache-line-size = <64>; 275 cache-sets = <512>; 276 cache-level = <2>; 277 cache-unified; 278 next-level-cache = <&l3_cache>; 279 }; 280 281 l2_cache_l2: l2-cache-l2 { 282 compatible = "cache"; 283 cache-size = <131072>; 284 cache-line-size = <64>; 285 cache-sets = <512>; 286 cache-level = <2>; 287 cache-unified; 288 next-level-cache = <&l3_cache>; 289 }; 290 291 l2_cache_l3: l2-cache-l3 { 292 compatible = "cache"; 293 cache-size = <131072>; 294 cache-line-size = <64>; 295 cache-sets = <512>; 296 cache-level = <2>; 297 cache-unified; 298 next-level-cache = <&l3_cache>; 299 }; 300 301 l2_cache_b0: l2-cache-b0 { 302 compatible = "cache"; 303 cache-size = <524288>; 304 cache-line-size = <64>; 305 cache-sets = <1024>; 306 cache-level = <2>; 307 cache-unified; 308 next-level-cache = <&l3_cache>; 309 }; 310 311 l2_cache_b1: l2-cache-b1 { 312 compatible = "cache"; 313 cache-size = <524288>; 314 cache-line-size = <64>; 315 cache-sets = <1024>; 316 cache-level = <2>; 317 cache-unified; 318 next-level-cache = <&l3_cache>; 319 }; 320 321 l2_cache_b2: l2-cache-b2 { 322 compatible = "cache"; 323 cache-size = <524288>; 324 cache-line-size = <64>; 325 cache-sets = <1024>; 326 cache-level = <2>; 327 cache-unified; 328 next-level-cache = <&l3_cache>; 329 }; 330 331 l2_cache_b3: l2-cache-b3 { 332 compatible = "cache"; 333 cache-size = <524288>; 334 cache-line-size = <64>; 335 cache-sets = <1024>; 336 cache-level = <2>; 337 cache-unified; 338 next-level-cache = <&l3_cache>; 339 }; 340 }; 341 342 /* 343 * The L3 cache belongs to the DynamIQ Shared Unit (DSU), 344 * so it's represented here, outside the "cpus" node 345 */ 346 l3_cache: l3-cache { 347 compatible = "cache"; 348 cache-size = <3145728>; 349 cache-line-size = <64>; 350 cache-sets = <4096>; 351 cache-level = <3>; 352 cache-unified; 353 }; 354 355 display_subsystem: display-subsystem { 356 compatible = "rockchip,display-subsystem"; 357 ports = <&vop_out>; 358 }; 359 360 firmware { 361 optee: optee { 362 compatible = "linaro,optee-tz"; 363 method = "smc"; 364 }; 365 366 scmi: scmi { 367 compatible = "arm,scmi-smc"; 368 arm,smc-id = <0x82000010>; 369 shmem = <&scmi_shmem>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 373 scmi_clk: protocol@14 { 374 reg = <0x14>; 375 #clock-cells = <1>; 376 }; 377 378 scmi_reset: protocol@16 { 379 reg = <0x16>; 380 #reset-cells = <1>; 381 }; 382 }; 383 }; 384 385 pmu-a55 { 386 compatible = "arm,cortex-a55-pmu"; 387 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; 388 }; 389 390 pmu-a76 { 391 compatible = "arm,cortex-a76-pmu"; 392 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; 393 }; 394 395 psci { 396 compatible = "arm,psci-1.0"; 397 method = "smc"; 398 }; 399 400 spll: clock-0 { 401 compatible = "fixed-clock"; 402 clock-frequency = <702000000>; 403 clock-output-names = "spll"; 404 #clock-cells = <0>; 405 }; 406 407 timer { 408 compatible = "arm,armv8-timer"; 409 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 410 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 411 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 412 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, 413 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 414 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 415 }; 416 417 xin24m: clock-1 { 418 compatible = "fixed-clock"; 419 clock-frequency = <24000000>; 420 clock-output-names = "xin24m"; 421 #clock-cells = <0>; 422 }; 423 424 xin32k: clock-2 { 425 compatible = "fixed-clock"; 426 clock-frequency = <32768>; 427 clock-output-names = "xin32k"; 428 #clock-cells = <0>; 429 }; 430 431 pmu_sram: sram@10f000 { 432 compatible = "mmio-sram"; 433 reg = <0x0 0x0010f000 0x0 0x100>; 434 ranges = <0 0x0 0x0010f000 0x100>; 435 #address-cells = <1>; 436 #size-cells = <1>; 437 438 scmi_shmem: sram@0 { 439 compatible = "arm,scmi-shmem"; 440 reg = <0x0 0x100>; 441 }; 442 }; 443 444 gpu: gpu@fb000000 { 445 compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; 446 reg = <0x0 0xfb000000 0x0 0x200000>; 447 #cooling-cells = <2>; 448 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 449 assigned-clock-rates = <200000000>; 450 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, 451 <&cru CLK_GPU_STACKS>; 452 clock-names = "core", "coregroup", "stacks"; 453 dynamic-power-coefficient = <2982>; 454 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, 455 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, 456 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>; 457 interrupt-names = "job", "mmu", "gpu"; 458 power-domains = <&power RK3588_PD_GPU>; 459 status = "disabled"; 460 }; 461 462 usb_host0_xhci: usb@fc000000 { 463 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 464 reg = <0x0 0xfc000000 0x0 0x400000>; 465 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 466 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, 467 <&cru ACLK_USB3OTG0>; 468 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 469 dr_mode = "otg"; 470 phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; 471 phy-names = "usb2-phy", "usb3-phy"; 472 phy_type = "utmi_wide"; 473 power-domains = <&power RK3588_PD_USB>; 474 resets = <&cru SRST_A_USB3OTG0>; 475 snps,dis_enblslpm_quirk; 476 snps,dis-u1-entry-quirk; 477 snps,dis-u2-entry-quirk; 478 snps,dis-u2-freeclk-exists-quirk; 479 snps,dis-del-phy-power-chg-quirk; 480 snps,dis-tx-ipgap-linecheck-quirk; 481 status = "disabled"; 482 }; 483 484 usb_host0_ehci: usb@fc800000 { 485 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 486 reg = <0x0 0xfc800000 0x0 0x40000>; 487 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; 488 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 489 phys = <&u2phy2_host>; 490 phy-names = "usb"; 491 power-domains = <&power RK3588_PD_USB>; 492 status = "disabled"; 493 }; 494 495 usb_host0_ohci: usb@fc840000 { 496 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 497 reg = <0x0 0xfc840000 0x0 0x40000>; 498 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; 499 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 500 phys = <&u2phy2_host>; 501 phy-names = "usb"; 502 power-domains = <&power RK3588_PD_USB>; 503 status = "disabled"; 504 }; 505 506 usb_host1_ehci: usb@fc880000 { 507 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 508 reg = <0x0 0xfc880000 0x0 0x40000>; 509 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; 510 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 511 phys = <&u2phy3_host>; 512 phy-names = "usb"; 513 power-domains = <&power RK3588_PD_USB>; 514 status = "disabled"; 515 }; 516 517 usb_host1_ohci: usb@fc8c0000 { 518 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 519 reg = <0x0 0xfc8c0000 0x0 0x40000>; 520 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; 521 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 522 phys = <&u2phy3_host>; 523 phy-names = "usb"; 524 power-domains = <&power RK3588_PD_USB>; 525 status = "disabled"; 526 }; 527 528 usb_host2_xhci: usb@fcd00000 { 529 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 530 reg = <0x0 0xfcd00000 0x0 0x400000>; 531 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; 532 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, 533 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, 534 <&cru CLK_PIPEPHY2_PIPE_U3_G>; 535 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; 536 dr_mode = "host"; 537 phys = <&combphy2_psu PHY_TYPE_USB3>; 538 phy-names = "usb3-phy"; 539 phy_type = "utmi_wide"; 540 resets = <&cru SRST_A_USB3OTG2>; 541 snps,dis_enblslpm_quirk; 542 snps,dis-u2-freeclk-exists-quirk; 543 snps,dis-del-phy-power-chg-quirk; 544 snps,dis-tx-ipgap-linecheck-quirk; 545 snps,dis_rxdet_inp3_quirk; 546 status = "disabled"; 547 }; 548 549 mmu600_pcie: iommu@fc900000 { 550 compatible = "arm,smmu-v3"; 551 reg = <0x0 0xfc900000 0x0 0x200000>; 552 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>, 553 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>, 554 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, 555 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>; 556 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 557 #iommu-cells = <1>; 558 status = "disabled"; 559 }; 560 561 mmu600_php: iommu@fcb00000 { 562 compatible = "arm,smmu-v3"; 563 reg = <0x0 0xfcb00000 0x0 0x200000>; 564 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>, 565 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, 566 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>, 567 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; 568 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 569 #iommu-cells = <1>; 570 status = "disabled"; 571 }; 572 573 pmu1grf: syscon@fd58a000 { 574 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; 575 reg = <0x0 0xfd58a000 0x0 0x10000>; 576 }; 577 578 sys_grf: syscon@fd58c000 { 579 compatible = "rockchip,rk3588-sys-grf", "syscon"; 580 reg = <0x0 0xfd58c000 0x0 0x1000>; 581 }; 582 583 vop_grf: syscon@fd5a4000 { 584 compatible = "rockchip,rk3588-vop-grf", "syscon"; 585 reg = <0x0 0xfd5a4000 0x0 0x2000>; 586 }; 587 588 vo0_grf: syscon@fd5a6000 { 589 compatible = "rockchip,rk3588-vo0-grf", "syscon"; 590 reg = <0x0 0xfd5a6000 0x0 0x2000>; 591 clocks = <&cru PCLK_VO0GRF>; 592 }; 593 594 vo1_grf: syscon@fd5a8000 { 595 compatible = "rockchip,rk3588-vo1-grf", "syscon"; 596 reg = <0x0 0xfd5a8000 0x0 0x4000>; 597 clocks = <&cru PCLK_VO1GRF>; 598 }; 599 600 usb_grf: syscon@fd5ac000 { 601 compatible = "rockchip,rk3588-usb-grf", "syscon"; 602 reg = <0x0 0xfd5ac000 0x0 0x4000>; 603 }; 604 605 php_grf: syscon@fd5b0000 { 606 compatible = "rockchip,rk3588-php-grf", "syscon"; 607 reg = <0x0 0xfd5b0000 0x0 0x1000>; 608 }; 609 610 pipe_phy0_grf: syscon@fd5bc000 { 611 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 612 reg = <0x0 0xfd5bc000 0x0 0x100>; 613 }; 614 615 pipe_phy2_grf: syscon@fd5c4000 { 616 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 617 reg = <0x0 0xfd5c4000 0x0 0x100>; 618 }; 619 620 usbdpphy0_grf: syscon@fd5c8000 { 621 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 622 reg = <0x0 0xfd5c8000 0x0 0x4000>; 623 }; 624 625 usb2phy0_grf: syscon@fd5d0000 { 626 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 627 reg = <0x0 0xfd5d0000 0x0 0x4000>; 628 #address-cells = <1>; 629 #size-cells = <1>; 630 631 u2phy0: usb2phy@0 { 632 compatible = "rockchip,rk3588-usb2phy"; 633 reg = <0x0 0x10>; 634 #clock-cells = <0>; 635 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 636 clock-names = "phyclk"; 637 clock-output-names = "usb480m_phy0"; 638 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; 639 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; 640 reset-names = "phy", "apb"; 641 status = "disabled"; 642 643 u2phy0_otg: otg-port { 644 #phy-cells = <0>; 645 status = "disabled"; 646 }; 647 }; 648 }; 649 650 usb2phy2_grf: syscon@fd5d8000 { 651 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 652 reg = <0x0 0xfd5d8000 0x0 0x4000>; 653 #address-cells = <1>; 654 #size-cells = <1>; 655 656 u2phy2: usb2phy@8000 { 657 compatible = "rockchip,rk3588-usb2phy"; 658 reg = <0x8000 0x10>; 659 #clock-cells = <0>; 660 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 661 clock-names = "phyclk"; 662 clock-output-names = "usb480m_phy2"; 663 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 664 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 665 reset-names = "phy", "apb"; 666 status = "disabled"; 667 668 u2phy2_host: host-port { 669 #phy-cells = <0>; 670 status = "disabled"; 671 }; 672 }; 673 }; 674 675 usb2phy3_grf: syscon@fd5dc000 { 676 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 677 reg = <0x0 0xfd5dc000 0x0 0x4000>; 678 #address-cells = <1>; 679 #size-cells = <1>; 680 681 u2phy3: usb2phy@c000 { 682 compatible = "rockchip,rk3588-usb2phy"; 683 reg = <0xc000 0x10>; 684 #clock-cells = <0>; 685 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 686 clock-names = "phyclk"; 687 clock-output-names = "usb480m_phy3"; 688 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 689 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 690 reset-names = "phy", "apb"; 691 status = "disabled"; 692 693 u2phy3_host: host-port { 694 #phy-cells = <0>; 695 status = "disabled"; 696 }; 697 }; 698 }; 699 700 hdptxphy0_grf: syscon@fd5e0000 { 701 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 702 reg = <0x0 0xfd5e0000 0x0 0x100>; 703 }; 704 705 ioc: syscon@fd5f0000 { 706 compatible = "rockchip,rk3588-ioc", "syscon"; 707 reg = <0x0 0xfd5f0000 0x0 0x10000>; 708 }; 709 710 system_sram1: sram@fd600000 { 711 compatible = "mmio-sram"; 712 reg = <0x0 0xfd600000 0x0 0x100000>; 713 ranges = <0x0 0x0 0xfd600000 0x100000>; 714 #address-cells = <1>; 715 #size-cells = <1>; 716 }; 717 718 cru: clock-controller@fd7c0000 { 719 compatible = "rockchip,rk3588-cru"; 720 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 721 assigned-clocks = 722 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 723 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 724 <&cru ACLK_CENTER_ROOT>, 725 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 726 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 727 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 728 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, 729 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 730 <&cru CLK_GPU>; 731 assigned-clock-rates = 732 <1100000000>, <786432000>, 733 <850000000>, <1188000000>, 734 <702000000>, 735 <400000000>, <500000000>, 736 <800000000>, <100000000>, 737 <400000000>, <100000000>, 738 <200000000>, <500000000>, 739 <375000000>, <150000000>, 740 <200000000>; 741 rockchip,grf = <&php_grf>; 742 #clock-cells = <1>; 743 #reset-cells = <1>; 744 }; 745 746 i2c0: i2c@fd880000 { 747 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 748 reg = <0x0 0xfd880000 0x0 0x1000>; 749 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; 750 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 751 clock-names = "i2c", "pclk"; 752 pinctrl-0 = <&i2c0m0_xfer>; 753 pinctrl-names = "default"; 754 #address-cells = <1>; 755 #size-cells = <0>; 756 status = "disabled"; 757 }; 758 759 uart0: serial@fd890000 { 760 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 761 reg = <0x0 0xfd890000 0x0 0x100>; 762 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 763 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 764 clock-names = "baudclk", "apb_pclk"; 765 dmas = <&dmac0 6>, <&dmac0 7>; 766 dma-names = "tx", "rx"; 767 pinctrl-0 = <&uart0m1_xfer>; 768 pinctrl-names = "default"; 769 reg-shift = <2>; 770 reg-io-width = <4>; 771 status = "disabled"; 772 }; 773 774 pwm0: pwm@fd8b0000 { 775 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 776 reg = <0x0 0xfd8b0000 0x0 0x10>; 777 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 778 clock-names = "pwm", "pclk"; 779 pinctrl-0 = <&pwm0m0_pins>; 780 pinctrl-names = "default"; 781 #pwm-cells = <3>; 782 status = "disabled"; 783 }; 784 785 pwm1: pwm@fd8b0010 { 786 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 787 reg = <0x0 0xfd8b0010 0x0 0x10>; 788 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 789 clock-names = "pwm", "pclk"; 790 pinctrl-0 = <&pwm1m0_pins>; 791 pinctrl-names = "default"; 792 #pwm-cells = <3>; 793 status = "disabled"; 794 }; 795 796 pwm2: pwm@fd8b0020 { 797 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 798 reg = <0x0 0xfd8b0020 0x0 0x10>; 799 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 800 clock-names = "pwm", "pclk"; 801 pinctrl-0 = <&pwm2m0_pins>; 802 pinctrl-names = "default"; 803 #pwm-cells = <3>; 804 status = "disabled"; 805 }; 806 807 pwm3: pwm@fd8b0030 { 808 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 809 reg = <0x0 0xfd8b0030 0x0 0x10>; 810 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 811 clock-names = "pwm", "pclk"; 812 pinctrl-0 = <&pwm3m0_pins>; 813 pinctrl-names = "default"; 814 #pwm-cells = <3>; 815 status = "disabled"; 816 }; 817 818 pmu: power-management@fd8d8000 { 819 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 820 reg = <0x0 0xfd8d8000 0x0 0x400>; 821 822 power: power-controller { 823 compatible = "rockchip,rk3588-power-controller"; 824 #address-cells = <1>; 825 #power-domain-cells = <1>; 826 #size-cells = <0>; 827 status = "okay"; 828 829 /* These power domains are grouped by VD_NPU */ 830 power-domain@RK3588_PD_NPU { 831 reg = <RK3588_PD_NPU>; 832 #power-domain-cells = <0>; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 836 power-domain@RK3588_PD_NPUTOP { 837 reg = <RK3588_PD_NPUTOP>; 838 clocks = <&cru HCLK_NPU_ROOT>, 839 <&cru PCLK_NPU_ROOT>, 840 <&cru CLK_NPU_DSU0>, 841 <&cru HCLK_NPU_CM0_ROOT>; 842 pm_qos = <&qos_npu0_mwr>, 843 <&qos_npu0_mro>, 844 <&qos_mcu_npu>; 845 #power-domain-cells = <0>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 849 power-domain@RK3588_PD_NPU1 { 850 reg = <RK3588_PD_NPU1>; 851 clocks = <&cru HCLK_NPU_ROOT>, 852 <&cru PCLK_NPU_ROOT>, 853 <&cru CLK_NPU_DSU0>; 854 pm_qos = <&qos_npu1>; 855 #power-domain-cells = <0>; 856 }; 857 power-domain@RK3588_PD_NPU2 { 858 reg = <RK3588_PD_NPU2>; 859 clocks = <&cru HCLK_NPU_ROOT>, 860 <&cru PCLK_NPU_ROOT>, 861 <&cru CLK_NPU_DSU0>; 862 pm_qos = <&qos_npu2>; 863 #power-domain-cells = <0>; 864 }; 865 }; 866 }; 867 /* These power domains are grouped by VD_GPU */ 868 power-domain@RK3588_PD_GPU { 869 reg = <RK3588_PD_GPU>; 870 clocks = <&cru CLK_GPU>, 871 <&cru CLK_GPU_COREGROUP>, 872 <&cru CLK_GPU_STACKS>; 873 pm_qos = <&qos_gpu_m0>, 874 <&qos_gpu_m1>, 875 <&qos_gpu_m2>, 876 <&qos_gpu_m3>; 877 #power-domain-cells = <0>; 878 }; 879 /* These power domains are grouped by VD_VCODEC */ 880 power-domain@RK3588_PD_VCODEC { 881 reg = <RK3588_PD_VCODEC>; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 #power-domain-cells = <0>; 885 886 power-domain@RK3588_PD_RKVDEC0 { 887 reg = <RK3588_PD_RKVDEC0>; 888 clocks = <&cru HCLK_RKVDEC0>, 889 <&cru HCLK_VDPU_ROOT>, 890 <&cru ACLK_VDPU_ROOT>, 891 <&cru ACLK_RKVDEC0>, 892 <&cru ACLK_RKVDEC_CCU>; 893 pm_qos = <&qos_rkvdec0>; 894 #power-domain-cells = <0>; 895 }; 896 power-domain@RK3588_PD_RKVDEC1 { 897 reg = <RK3588_PD_RKVDEC1>; 898 clocks = <&cru HCLK_RKVDEC1>, 899 <&cru HCLK_VDPU_ROOT>, 900 <&cru ACLK_VDPU_ROOT>, 901 <&cru ACLK_RKVDEC1>; 902 pm_qos = <&qos_rkvdec1>; 903 #power-domain-cells = <0>; 904 }; 905 power-domain@RK3588_PD_VENC0 { 906 reg = <RK3588_PD_VENC0>; 907 clocks = <&cru HCLK_RKVENC0>, 908 <&cru ACLK_RKVENC0>; 909 pm_qos = <&qos_rkvenc0_m0ro>, 910 <&qos_rkvenc0_m1ro>, 911 <&qos_rkvenc0_m2wo>; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 #power-domain-cells = <0>; 915 916 power-domain@RK3588_PD_VENC1 { 917 reg = <RK3588_PD_VENC1>; 918 clocks = <&cru HCLK_RKVENC1>, 919 <&cru HCLK_RKVENC0>, 920 <&cru ACLK_RKVENC0>, 921 <&cru ACLK_RKVENC1>; 922 pm_qos = <&qos_rkvenc1_m0ro>, 923 <&qos_rkvenc1_m1ro>, 924 <&qos_rkvenc1_m2wo>; 925 #power-domain-cells = <0>; 926 }; 927 }; 928 }; 929 /* These power domains are grouped by VD_LOGIC */ 930 power-domain@RK3588_PD_VDPU { 931 reg = <RK3588_PD_VDPU>; 932 clocks = <&cru HCLK_VDPU_ROOT>, 933 <&cru ACLK_VDPU_LOW_ROOT>, 934 <&cru ACLK_VDPU_ROOT>, 935 <&cru ACLK_JPEG_DECODER_ROOT>, 936 <&cru ACLK_IEP2P0>, 937 <&cru HCLK_IEP2P0>, 938 <&cru ACLK_JPEG_ENCODER0>, 939 <&cru HCLK_JPEG_ENCODER0>, 940 <&cru ACLK_JPEG_ENCODER1>, 941 <&cru HCLK_JPEG_ENCODER1>, 942 <&cru ACLK_JPEG_ENCODER2>, 943 <&cru HCLK_JPEG_ENCODER2>, 944 <&cru ACLK_JPEG_ENCODER3>, 945 <&cru HCLK_JPEG_ENCODER3>, 946 <&cru ACLK_JPEG_DECODER>, 947 <&cru HCLK_JPEG_DECODER>, 948 <&cru ACLK_RGA2>, 949 <&cru HCLK_RGA2>; 950 pm_qos = <&qos_iep>, 951 <&qos_jpeg_dec>, 952 <&qos_jpeg_enc0>, 953 <&qos_jpeg_enc1>, 954 <&qos_jpeg_enc2>, 955 <&qos_jpeg_enc3>, 956 <&qos_rga2_mro>, 957 <&qos_rga2_mwo>; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 #power-domain-cells = <0>; 961 962 963 power-domain@RK3588_PD_AV1 { 964 reg = <RK3588_PD_AV1>; 965 clocks = <&cru PCLK_AV1>, 966 <&cru ACLK_AV1>, 967 <&cru HCLK_VDPU_ROOT>; 968 pm_qos = <&qos_av1>; 969 #power-domain-cells = <0>; 970 }; 971 power-domain@RK3588_PD_RKVDEC0 { 972 reg = <RK3588_PD_RKVDEC0>; 973 clocks = <&cru HCLK_RKVDEC0>, 974 <&cru HCLK_VDPU_ROOT>, 975 <&cru ACLK_VDPU_ROOT>, 976 <&cru ACLK_RKVDEC0>; 977 pm_qos = <&qos_rkvdec0>; 978 #power-domain-cells = <0>; 979 }; 980 power-domain@RK3588_PD_RKVDEC1 { 981 reg = <RK3588_PD_RKVDEC1>; 982 clocks = <&cru HCLK_RKVDEC1>, 983 <&cru HCLK_VDPU_ROOT>, 984 <&cru ACLK_VDPU_ROOT>; 985 pm_qos = <&qos_rkvdec1>; 986 #power-domain-cells = <0>; 987 }; 988 power-domain@RK3588_PD_RGA30 { 989 reg = <RK3588_PD_RGA30>; 990 clocks = <&cru ACLK_RGA3_0>, 991 <&cru HCLK_RGA3_0>; 992 pm_qos = <&qos_rga3_0>; 993 #power-domain-cells = <0>; 994 }; 995 }; 996 power-domain@RK3588_PD_VOP { 997 reg = <RK3588_PD_VOP>; 998 clocks = <&cru PCLK_VOP_ROOT>, 999 <&cru HCLK_VOP_ROOT>, 1000 <&cru ACLK_VOP>; 1001 pm_qos = <&qos_vop_m0>, 1002 <&qos_vop_m1>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 #power-domain-cells = <0>; 1006 1007 power-domain@RK3588_PD_VO0 { 1008 reg = <RK3588_PD_VO0>; 1009 clocks = <&cru PCLK_VO0_ROOT>, 1010 <&cru PCLK_VO0_S_ROOT>, 1011 <&cru HCLK_VO0_S_ROOT>, 1012 <&cru ACLK_VO0_ROOT>, 1013 <&cru HCLK_HDCP0>, 1014 <&cru ACLK_HDCP0>, 1015 <&cru HCLK_VOP_ROOT>; 1016 pm_qos = <&qos_hdcp0>; 1017 #power-domain-cells = <0>; 1018 }; 1019 }; 1020 power-domain@RK3588_PD_VO1 { 1021 reg = <RK3588_PD_VO1>; 1022 clocks = <&cru PCLK_VO1_ROOT>, 1023 <&cru PCLK_VO1_S_ROOT>, 1024 <&cru HCLK_VO1_S_ROOT>, 1025 <&cru HCLK_HDCP1>, 1026 <&cru ACLK_HDCP1>, 1027 <&cru ACLK_HDMIRX_ROOT>, 1028 <&cru HCLK_VO1USB_TOP_ROOT>; 1029 pm_qos = <&qos_hdcp1>, 1030 <&qos_hdmirx>; 1031 #power-domain-cells = <0>; 1032 }; 1033 power-domain@RK3588_PD_VI { 1034 reg = <RK3588_PD_VI>; 1035 clocks = <&cru HCLK_VI_ROOT>, 1036 <&cru PCLK_VI_ROOT>, 1037 <&cru HCLK_ISP0>, 1038 <&cru ACLK_ISP0>, 1039 <&cru HCLK_VICAP>, 1040 <&cru ACLK_VICAP>; 1041 pm_qos = <&qos_isp0_mro>, 1042 <&qos_isp0_mwo>, 1043 <&qos_vicap_m0>, 1044 <&qos_vicap_m1>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 #power-domain-cells = <0>; 1048 1049 power-domain@RK3588_PD_ISP1 { 1050 reg = <RK3588_PD_ISP1>; 1051 clocks = <&cru HCLK_ISP1>, 1052 <&cru ACLK_ISP1>, 1053 <&cru HCLK_VI_ROOT>, 1054 <&cru PCLK_VI_ROOT>; 1055 pm_qos = <&qos_isp1_mwo>, 1056 <&qos_isp1_mro>; 1057 #power-domain-cells = <0>; 1058 }; 1059 power-domain@RK3588_PD_FEC { 1060 reg = <RK3588_PD_FEC>; 1061 clocks = <&cru HCLK_FISHEYE0>, 1062 <&cru ACLK_FISHEYE0>, 1063 <&cru HCLK_FISHEYE1>, 1064 <&cru ACLK_FISHEYE1>, 1065 <&cru PCLK_VI_ROOT>; 1066 pm_qos = <&qos_fisheye0>, 1067 <&qos_fisheye1>; 1068 #power-domain-cells = <0>; 1069 }; 1070 }; 1071 power-domain@RK3588_PD_RGA31 { 1072 reg = <RK3588_PD_RGA31>; 1073 clocks = <&cru HCLK_RGA3_1>, 1074 <&cru ACLK_RGA3_1>; 1075 pm_qos = <&qos_rga3_1>; 1076 #power-domain-cells = <0>; 1077 }; 1078 power-domain@RK3588_PD_USB { 1079 reg = <RK3588_PD_USB>; 1080 clocks = <&cru PCLK_PHP_ROOT>, 1081 <&cru ACLK_USB_ROOT>, 1082 <&cru ACLK_USB>, 1083 <&cru HCLK_USB_ROOT>, 1084 <&cru HCLK_HOST0>, 1085 <&cru HCLK_HOST_ARB0>, 1086 <&cru HCLK_HOST1>, 1087 <&cru HCLK_HOST_ARB1>; 1088 pm_qos = <&qos_usb3_0>, 1089 <&qos_usb3_1>, 1090 <&qos_usb2host_0>, 1091 <&qos_usb2host_1>; 1092 #power-domain-cells = <0>; 1093 }; 1094 power-domain@RK3588_PD_GMAC { 1095 reg = <RK3588_PD_GMAC>; 1096 clocks = <&cru PCLK_PHP_ROOT>, 1097 <&cru ACLK_PCIE_ROOT>, 1098 <&cru ACLK_PHP_ROOT>; 1099 #power-domain-cells = <0>; 1100 }; 1101 power-domain@RK3588_PD_PCIE { 1102 reg = <RK3588_PD_PCIE>; 1103 clocks = <&cru PCLK_PHP_ROOT>, 1104 <&cru ACLK_PCIE_ROOT>, 1105 <&cru ACLK_PHP_ROOT>; 1106 #power-domain-cells = <0>; 1107 }; 1108 power-domain@RK3588_PD_SDIO { 1109 reg = <RK3588_PD_SDIO>; 1110 clocks = <&cru HCLK_SDIO>, 1111 <&cru HCLK_NVM_ROOT>; 1112 pm_qos = <&qos_sdio>; 1113 #power-domain-cells = <0>; 1114 }; 1115 power-domain@RK3588_PD_AUDIO { 1116 reg = <RK3588_PD_AUDIO>; 1117 clocks = <&cru HCLK_AUDIO_ROOT>, 1118 <&cru PCLK_AUDIO_ROOT>; 1119 #power-domain-cells = <0>; 1120 }; 1121 power-domain@RK3588_PD_SDMMC { 1122 reg = <RK3588_PD_SDMMC>; 1123 pm_qos = <&qos_sdmmc>; 1124 #power-domain-cells = <0>; 1125 }; 1126 }; 1127 }; 1128 1129 vpu121: video-codec@fdb50000 { 1130 compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu"; 1131 reg = <0x0 0xfdb50000 0x0 0x800>; 1132 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1133 interrupt-names = "vdpu"; 1134 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1135 clock-names = "aclk", "hclk"; 1136 iommus = <&vpu121_mmu>; 1137 power-domains = <&power RK3588_PD_VDPU>; 1138 }; 1139 1140 vpu121_mmu: iommu@fdb50800 { 1141 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1142 reg = <0x0 0xfdb50800 0x0 0x40>; 1143 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1144 clock-names = "aclk", "iface"; 1145 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1146 power-domains = <&power RK3588_PD_VDPU>; 1147 #iommu-cells = <0>; 1148 }; 1149 1150 rga: rga@fdb80000 { 1151 compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga"; 1152 reg = <0x0 0xfdb80000 0x0 0x180>; 1153 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1154 clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>; 1155 clock-names = "aclk", "hclk", "sclk"; 1156 resets = <&cru SRST_RGA2_CORE>, <&cru SRST_A_RGA2>, <&cru SRST_H_RGA2>; 1157 reset-names = "core", "axi", "ahb"; 1158 power-domains = <&power RK3588_PD_VDPU>; 1159 }; 1160 1161 vepu121_0: video-codec@fdba0000 { 1162 compatible = "rockchip,rk3588-vepu121"; 1163 reg = <0x0 0xfdba0000 0x0 0x800>; 1164 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>; 1165 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 1166 clock-names = "aclk", "hclk"; 1167 iommus = <&vepu121_0_mmu>; 1168 power-domains = <&power RK3588_PD_VDPU>; 1169 }; 1170 1171 vepu121_0_mmu: iommu@fdba0800 { 1172 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1173 reg = <0x0 0xfdba0800 0x0 0x40>; 1174 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 1175 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 1176 clock-names = "aclk", "iface"; 1177 power-domains = <&power RK3588_PD_VDPU>; 1178 #iommu-cells = <0>; 1179 }; 1180 1181 vepu121_1: video-codec@fdba4000 { 1182 compatible = "rockchip,rk3588-vepu121"; 1183 reg = <0x0 0xfdba4000 0x0 0x800>; 1184 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>; 1185 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 1186 clock-names = "aclk", "hclk"; 1187 iommus = <&vepu121_1_mmu>; 1188 power-domains = <&power RK3588_PD_VDPU>; 1189 }; 1190 1191 vepu121_1_mmu: iommu@fdba4800 { 1192 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1193 reg = <0x0 0xfdba4800 0x0 0x40>; 1194 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>; 1195 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 1196 clock-names = "aclk", "iface"; 1197 power-domains = <&power RK3588_PD_VDPU>; 1198 #iommu-cells = <0>; 1199 }; 1200 1201 vepu121_2: video-codec@fdba8000 { 1202 compatible = "rockchip,rk3588-vepu121"; 1203 reg = <0x0 0xfdba8000 0x0 0x800>; 1204 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>; 1205 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 1206 clock-names = "aclk", "hclk"; 1207 iommus = <&vepu121_2_mmu>; 1208 power-domains = <&power RK3588_PD_VDPU>; 1209 }; 1210 1211 vepu121_2_mmu: iommu@fdba8800 { 1212 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1213 reg = <0x0 0xfdba8800 0x0 0x40>; 1214 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>; 1215 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 1216 clock-names = "aclk", "iface"; 1217 power-domains = <&power RK3588_PD_VDPU>; 1218 #iommu-cells = <0>; 1219 }; 1220 1221 vepu121_3: video-codec@fdbac000 { 1222 compatible = "rockchip,rk3588-vepu121"; 1223 reg = <0x0 0xfdbac000 0x0 0x800>; 1224 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; 1225 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 1226 clock-names = "aclk", "hclk"; 1227 iommus = <&vepu121_3_mmu>; 1228 power-domains = <&power RK3588_PD_VDPU>; 1229 }; 1230 1231 vepu121_3_mmu: iommu@fdbac800 { 1232 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1233 reg = <0x0 0xfdbac800 0x0 0x40>; 1234 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>; 1235 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 1236 clock-names = "aclk", "iface"; 1237 power-domains = <&power RK3588_PD_VDPU>; 1238 #iommu-cells = <0>; 1239 }; 1240 1241 av1d: video-codec@fdc70000 { 1242 compatible = "rockchip,rk3588-av1-vpu"; 1243 reg = <0x0 0xfdc70000 0x0 0x800>; 1244 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 1245 interrupt-names = "vdpu"; 1246 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1247 assigned-clock-rates = <400000000>, <400000000>; 1248 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1249 clock-names = "aclk", "hclk"; 1250 power-domains = <&power RK3588_PD_AV1>; 1251 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; 1252 }; 1253 1254 vop: vop@fdd90000 { 1255 compatible = "rockchip,rk3588-vop"; 1256 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; 1257 reg-names = "vop", "gamma-lut"; 1258 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1259 clocks = <&cru ACLK_VOP>, 1260 <&cru HCLK_VOP>, 1261 <&cru DCLK_VOP0>, 1262 <&cru DCLK_VOP1>, 1263 <&cru DCLK_VOP2>, 1264 <&cru DCLK_VOP3>, 1265 <&cru PCLK_VOP_ROOT>; 1266 clock-names = "aclk", 1267 "hclk", 1268 "dclk_vp0", 1269 "dclk_vp1", 1270 "dclk_vp2", 1271 "dclk_vp3", 1272 "pclk_vop"; 1273 iommus = <&vop_mmu>; 1274 power-domains = <&power RK3588_PD_VOP>; 1275 rockchip,grf = <&sys_grf>; 1276 rockchip,vop-grf = <&vop_grf>; 1277 rockchip,vo1-grf = <&vo1_grf>; 1278 rockchip,pmu = <&pmu>; 1279 status = "disabled"; 1280 1281 vop_out: ports { 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 1285 vp0: port@0 { 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 reg = <0>; 1289 }; 1290 1291 vp1: port@1 { 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 reg = <1>; 1295 }; 1296 1297 vp2: port@2 { 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 reg = <2>; 1301 }; 1302 1303 vp3: port@3 { 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 reg = <3>; 1307 }; 1308 }; 1309 }; 1310 1311 vop_mmu: iommu@fdd97e00 { 1312 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1313 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 1314 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1315 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1316 clock-names = "aclk", "iface"; 1317 #iommu-cells = <0>; 1318 power-domains = <&power RK3588_PD_VOP>; 1319 status = "disabled"; 1320 }; 1321 1322 i2s4_8ch: i2s@fddc0000 { 1323 compatible = "rockchip,rk3588-i2s-tdm"; 1324 reg = <0x0 0xfddc0000 0x0 0x1000>; 1325 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; 1326 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 1327 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1328 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 1329 assigned-clock-parents = <&cru PLL_AUPLL>; 1330 dmas = <&dmac2 0>; 1331 dma-names = "tx"; 1332 power-domains = <&power RK3588_PD_VO0>; 1333 resets = <&cru SRST_M_I2S4_8CH_TX>; 1334 reset-names = "tx-m"; 1335 #sound-dai-cells = <0>; 1336 status = "disabled"; 1337 }; 1338 1339 i2s5_8ch: i2s@fddf0000 { 1340 compatible = "rockchip,rk3588-i2s-tdm"; 1341 reg = <0x0 0xfddf0000 0x0 0x1000>; 1342 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; 1343 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 1344 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1345 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 1346 assigned-clock-parents = <&cru PLL_AUPLL>; 1347 dmas = <&dmac2 2>; 1348 dma-names = "tx"; 1349 power-domains = <&power RK3588_PD_VO1>; 1350 resets = <&cru SRST_M_I2S5_8CH_TX>; 1351 reset-names = "tx-m"; 1352 #sound-dai-cells = <0>; 1353 status = "disabled"; 1354 }; 1355 1356 i2s9_8ch: i2s@fddfc000 { 1357 compatible = "rockchip,rk3588-i2s-tdm"; 1358 reg = <0x0 0xfddfc000 0x0 0x1000>; 1359 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; 1360 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 1361 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1362 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 1363 assigned-clock-parents = <&cru PLL_AUPLL>; 1364 dmas = <&dmac2 23>; 1365 dma-names = "rx"; 1366 power-domains = <&power RK3588_PD_VO1>; 1367 resets = <&cru SRST_M_I2S9_8CH_RX>; 1368 reset-names = "rx-m"; 1369 #sound-dai-cells = <0>; 1370 status = "disabled"; 1371 }; 1372 1373 hdmi0: hdmi@fde80000 { 1374 compatible = "rockchip,rk3588-dw-hdmi-qp"; 1375 reg = <0x0 0xfde80000 0x0 0x20000>; 1376 clocks = <&cru PCLK_HDMITX0>, 1377 <&cru CLK_HDMITX0_EARC>, 1378 <&cru CLK_HDMITX0_REF>, 1379 <&cru MCLK_I2S5_8CH_TX>, 1380 <&cru CLK_HDMIHDP0>, 1381 <&cru HCLK_VO1>; 1382 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; 1383 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>, 1384 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>, 1385 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>, 1386 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>, 1387 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>; 1388 interrupt-names = "avp", "cec", "earc", "main", "hpd"; 1389 phys = <&hdptxphy_hdmi0>; 1390 pinctrl-names = "default"; 1391 pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd 1392 &hdmim0_tx0_scl &hdmim0_tx0_sda>; 1393 power-domains = <&power RK3588_PD_VO1>; 1394 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; 1395 reset-names = "ref", "hdp"; 1396 rockchip,grf = <&sys_grf>; 1397 rockchip,vo-grf = <&vo1_grf>; 1398 status = "disabled"; 1399 1400 ports { 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 1404 hdmi0_in: port@0 { 1405 reg = <0>; 1406 }; 1407 1408 hdmi0_out: port@1 { 1409 reg = <1>; 1410 }; 1411 }; 1412 }; 1413 1414 qos_gpu_m0: qos@fdf35000 { 1415 compatible = "rockchip,rk3588-qos", "syscon"; 1416 reg = <0x0 0xfdf35000 0x0 0x20>; 1417 }; 1418 1419 qos_gpu_m1: qos@fdf35200 { 1420 compatible = "rockchip,rk3588-qos", "syscon"; 1421 reg = <0x0 0xfdf35200 0x0 0x20>; 1422 }; 1423 1424 qos_gpu_m2: qos@fdf35400 { 1425 compatible = "rockchip,rk3588-qos", "syscon"; 1426 reg = <0x0 0xfdf35400 0x0 0x20>; 1427 }; 1428 1429 qos_gpu_m3: qos@fdf35600 { 1430 compatible = "rockchip,rk3588-qos", "syscon"; 1431 reg = <0x0 0xfdf35600 0x0 0x20>; 1432 }; 1433 1434 qos_rga3_1: qos@fdf36000 { 1435 compatible = "rockchip,rk3588-qos", "syscon"; 1436 reg = <0x0 0xfdf36000 0x0 0x20>; 1437 }; 1438 1439 qos_sdio: qos@fdf39000 { 1440 compatible = "rockchip,rk3588-qos", "syscon"; 1441 reg = <0x0 0xfdf39000 0x0 0x20>; 1442 }; 1443 1444 qos_sdmmc: qos@fdf3d800 { 1445 compatible = "rockchip,rk3588-qos", "syscon"; 1446 reg = <0x0 0xfdf3d800 0x0 0x20>; 1447 }; 1448 1449 qos_usb3_1: qos@fdf3e000 { 1450 compatible = "rockchip,rk3588-qos", "syscon"; 1451 reg = <0x0 0xfdf3e000 0x0 0x20>; 1452 }; 1453 1454 qos_usb3_0: qos@fdf3e200 { 1455 compatible = "rockchip,rk3588-qos", "syscon"; 1456 reg = <0x0 0xfdf3e200 0x0 0x20>; 1457 }; 1458 1459 qos_usb2host_0: qos@fdf3e400 { 1460 compatible = "rockchip,rk3588-qos", "syscon"; 1461 reg = <0x0 0xfdf3e400 0x0 0x20>; 1462 }; 1463 1464 qos_usb2host_1: qos@fdf3e600 { 1465 compatible = "rockchip,rk3588-qos", "syscon"; 1466 reg = <0x0 0xfdf3e600 0x0 0x20>; 1467 }; 1468 1469 qos_fisheye0: qos@fdf40000 { 1470 compatible = "rockchip,rk3588-qos", "syscon"; 1471 reg = <0x0 0xfdf40000 0x0 0x20>; 1472 }; 1473 1474 qos_fisheye1: qos@fdf40200 { 1475 compatible = "rockchip,rk3588-qos", "syscon"; 1476 reg = <0x0 0xfdf40200 0x0 0x20>; 1477 }; 1478 1479 qos_isp0_mro: qos@fdf40400 { 1480 compatible = "rockchip,rk3588-qos", "syscon"; 1481 reg = <0x0 0xfdf40400 0x0 0x20>; 1482 }; 1483 1484 qos_isp0_mwo: qos@fdf40500 { 1485 compatible = "rockchip,rk3588-qos", "syscon"; 1486 reg = <0x0 0xfdf40500 0x0 0x20>; 1487 }; 1488 1489 qos_vicap_m0: qos@fdf40600 { 1490 compatible = "rockchip,rk3588-qos", "syscon"; 1491 reg = <0x0 0xfdf40600 0x0 0x20>; 1492 }; 1493 1494 qos_vicap_m1: qos@fdf40800 { 1495 compatible = "rockchip,rk3588-qos", "syscon"; 1496 reg = <0x0 0xfdf40800 0x0 0x20>; 1497 }; 1498 1499 qos_isp1_mwo: qos@fdf41000 { 1500 compatible = "rockchip,rk3588-qos", "syscon"; 1501 reg = <0x0 0xfdf41000 0x0 0x20>; 1502 }; 1503 1504 qos_isp1_mro: qos@fdf41100 { 1505 compatible = "rockchip,rk3588-qos", "syscon"; 1506 reg = <0x0 0xfdf41100 0x0 0x20>; 1507 }; 1508 1509 qos_rkvenc0_m0ro: qos@fdf60000 { 1510 compatible = "rockchip,rk3588-qos", "syscon"; 1511 reg = <0x0 0xfdf60000 0x0 0x20>; 1512 }; 1513 1514 qos_rkvenc0_m1ro: qos@fdf60200 { 1515 compatible = "rockchip,rk3588-qos", "syscon"; 1516 reg = <0x0 0xfdf60200 0x0 0x20>; 1517 }; 1518 1519 qos_rkvenc0_m2wo: qos@fdf60400 { 1520 compatible = "rockchip,rk3588-qos", "syscon"; 1521 reg = <0x0 0xfdf60400 0x0 0x20>; 1522 }; 1523 1524 qos_rkvenc1_m0ro: qos@fdf61000 { 1525 compatible = "rockchip,rk3588-qos", "syscon"; 1526 reg = <0x0 0xfdf61000 0x0 0x20>; 1527 }; 1528 1529 qos_rkvenc1_m1ro: qos@fdf61200 { 1530 compatible = "rockchip,rk3588-qos", "syscon"; 1531 reg = <0x0 0xfdf61200 0x0 0x20>; 1532 }; 1533 1534 qos_rkvenc1_m2wo: qos@fdf61400 { 1535 compatible = "rockchip,rk3588-qos", "syscon"; 1536 reg = <0x0 0xfdf61400 0x0 0x20>; 1537 }; 1538 1539 qos_rkvdec0: qos@fdf62000 { 1540 compatible = "rockchip,rk3588-qos", "syscon"; 1541 reg = <0x0 0xfdf62000 0x0 0x20>; 1542 }; 1543 1544 qos_rkvdec1: qos@fdf63000 { 1545 compatible = "rockchip,rk3588-qos", "syscon"; 1546 reg = <0x0 0xfdf63000 0x0 0x20>; 1547 }; 1548 1549 qos_av1: qos@fdf64000 { 1550 compatible = "rockchip,rk3588-qos", "syscon"; 1551 reg = <0x0 0xfdf64000 0x0 0x20>; 1552 }; 1553 1554 qos_iep: qos@fdf66000 { 1555 compatible = "rockchip,rk3588-qos", "syscon"; 1556 reg = <0x0 0xfdf66000 0x0 0x20>; 1557 }; 1558 1559 qos_jpeg_dec: qos@fdf66200 { 1560 compatible = "rockchip,rk3588-qos", "syscon"; 1561 reg = <0x0 0xfdf66200 0x0 0x20>; 1562 }; 1563 1564 qos_jpeg_enc0: qos@fdf66400 { 1565 compatible = "rockchip,rk3588-qos", "syscon"; 1566 reg = <0x0 0xfdf66400 0x0 0x20>; 1567 }; 1568 1569 qos_jpeg_enc1: qos@fdf66600 { 1570 compatible = "rockchip,rk3588-qos", "syscon"; 1571 reg = <0x0 0xfdf66600 0x0 0x20>; 1572 }; 1573 1574 qos_jpeg_enc2: qos@fdf66800 { 1575 compatible = "rockchip,rk3588-qos", "syscon"; 1576 reg = <0x0 0xfdf66800 0x0 0x20>; 1577 }; 1578 1579 qos_jpeg_enc3: qos@fdf66a00 { 1580 compatible = "rockchip,rk3588-qos", "syscon"; 1581 reg = <0x0 0xfdf66a00 0x0 0x20>; 1582 }; 1583 1584 qos_rga2_mro: qos@fdf66c00 { 1585 compatible = "rockchip,rk3588-qos", "syscon"; 1586 reg = <0x0 0xfdf66c00 0x0 0x20>; 1587 }; 1588 1589 qos_rga2_mwo: qos@fdf66e00 { 1590 compatible = "rockchip,rk3588-qos", "syscon"; 1591 reg = <0x0 0xfdf66e00 0x0 0x20>; 1592 }; 1593 1594 qos_rga3_0: qos@fdf67000 { 1595 compatible = "rockchip,rk3588-qos", "syscon"; 1596 reg = <0x0 0xfdf67000 0x0 0x20>; 1597 }; 1598 1599 qos_vdpu: qos@fdf67200 { 1600 compatible = "rockchip,rk3588-qos", "syscon"; 1601 reg = <0x0 0xfdf67200 0x0 0x20>; 1602 }; 1603 1604 qos_npu1: qos@fdf70000 { 1605 compatible = "rockchip,rk3588-qos", "syscon"; 1606 reg = <0x0 0xfdf70000 0x0 0x20>; 1607 }; 1608 1609 qos_npu2: qos@fdf71000 { 1610 compatible = "rockchip,rk3588-qos", "syscon"; 1611 reg = <0x0 0xfdf71000 0x0 0x20>; 1612 }; 1613 1614 qos_npu0_mwr: qos@fdf72000 { 1615 compatible = "rockchip,rk3588-qos", "syscon"; 1616 reg = <0x0 0xfdf72000 0x0 0x20>; 1617 }; 1618 1619 qos_npu0_mro: qos@fdf72200 { 1620 compatible = "rockchip,rk3588-qos", "syscon"; 1621 reg = <0x0 0xfdf72200 0x0 0x20>; 1622 }; 1623 1624 qos_mcu_npu: qos@fdf72400 { 1625 compatible = "rockchip,rk3588-qos", "syscon"; 1626 reg = <0x0 0xfdf72400 0x0 0x20>; 1627 }; 1628 1629 qos_hdcp0: qos@fdf80000 { 1630 compatible = "rockchip,rk3588-qos", "syscon"; 1631 reg = <0x0 0xfdf80000 0x0 0x20>; 1632 }; 1633 1634 qos_hdcp1: qos@fdf81000 { 1635 compatible = "rockchip,rk3588-qos", "syscon"; 1636 reg = <0x0 0xfdf81000 0x0 0x20>; 1637 }; 1638 1639 qos_hdmirx: qos@fdf81200 { 1640 compatible = "rockchip,rk3588-qos", "syscon"; 1641 reg = <0x0 0xfdf81200 0x0 0x20>; 1642 }; 1643 1644 qos_vop_m0: qos@fdf82000 { 1645 compatible = "rockchip,rk3588-qos", "syscon"; 1646 reg = <0x0 0xfdf82000 0x0 0x20>; 1647 }; 1648 1649 qos_vop_m1: qos@fdf82200 { 1650 compatible = "rockchip,rk3588-qos", "syscon"; 1651 reg = <0x0 0xfdf82200 0x0 0x20>; 1652 }; 1653 1654 dfi: dfi@fe060000 { 1655 reg = <0x00 0xfe060000 0x00 0x10000>; 1656 compatible = "rockchip,rk3588-dfi"; 1657 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, 1658 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, 1659 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, 1660 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1661 rockchip,pmu = <&pmu1grf>; 1662 }; 1663 1664 pcie2x1l1: pcie@fe180000 { 1665 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1666 bus-range = <0x30 0x3f>; 1667 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 1668 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 1669 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; 1670 clock-names = "aclk_mst", "aclk_slv", 1671 "aclk_dbi", "pclk", 1672 "aux", "pipe"; 1673 device_type = "pci"; 1674 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, 1675 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, 1676 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, 1677 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, 1678 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; 1679 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1680 #interrupt-cells = <1>; 1681 interrupt-map-mask = <0 0 0 7>; 1682 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 1683 <0 0 0 2 &pcie2x1l1_intc 1>, 1684 <0 0 0 3 &pcie2x1l1_intc 2>, 1685 <0 0 0 4 &pcie2x1l1_intc 3>; 1686 linux,pci-domain = <3>; 1687 max-link-speed = <2>; 1688 msi-map = <0x3000 &its0 0x3000 0x1000>; 1689 num-lanes = <1>; 1690 phys = <&combphy2_psu PHY_TYPE_PCIE>; 1691 phy-names = "pcie-phy"; 1692 power-domains = <&power RK3588_PD_PCIE>; 1693 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, 1694 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, 1695 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; 1696 reg = <0xa 0x40c00000 0x0 0x00400000>, 1697 <0x0 0xfe180000 0x0 0x00010000>, 1698 <0x0 0xf3000000 0x0 0x00100000>; 1699 reg-names = "dbi", "apb", "config"; 1700 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; 1701 reset-names = "pwr", "pipe"; 1702 #address-cells = <3>; 1703 #size-cells = <2>; 1704 status = "disabled"; 1705 1706 pcie2x1l1_intc: legacy-interrupt-controller { 1707 interrupt-controller; 1708 #address-cells = <0>; 1709 #interrupt-cells = <1>; 1710 interrupt-parent = <&gic>; 1711 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; 1712 }; 1713 }; 1714 1715 pcie2x1l2: pcie@fe190000 { 1716 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1717 bus-range = <0x40 0x4f>; 1718 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 1719 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 1720 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; 1721 clock-names = "aclk_mst", "aclk_slv", 1722 "aclk_dbi", "pclk", 1723 "aux", "pipe"; 1724 device_type = "pci"; 1725 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, 1726 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, 1727 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, 1728 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, 1729 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; 1730 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1731 #interrupt-cells = <1>; 1732 interrupt-map-mask = <0 0 0 7>; 1733 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 1734 <0 0 0 2 &pcie2x1l2_intc 1>, 1735 <0 0 0 3 &pcie2x1l2_intc 2>, 1736 <0 0 0 4 &pcie2x1l2_intc 3>; 1737 linux,pci-domain = <4>; 1738 max-link-speed = <2>; 1739 msi-map = <0x4000 &its0 0x4000 0x1000>; 1740 num-lanes = <1>; 1741 phys = <&combphy0_ps PHY_TYPE_PCIE>; 1742 phy-names = "pcie-phy"; 1743 power-domains = <&power RK3588_PD_PCIE>; 1744 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 1745 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, 1746 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; 1747 reg = <0xa 0x41000000 0x0 0x00400000>, 1748 <0x0 0xfe190000 0x0 0x00010000>, 1749 <0x0 0xf4000000 0x0 0x00100000>; 1750 reg-names = "dbi", "apb", "config"; 1751 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; 1752 reset-names = "pwr", "pipe"; 1753 #address-cells = <3>; 1754 #size-cells = <2>; 1755 status = "disabled"; 1756 1757 pcie2x1l2_intc: legacy-interrupt-controller { 1758 interrupt-controller; 1759 #address-cells = <0>; 1760 #interrupt-cells = <1>; 1761 interrupt-parent = <&gic>; 1762 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; 1763 }; 1764 }; 1765 1766 gmac1: ethernet@fe1c0000 { 1767 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1768 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1769 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, 1770 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 1771 interrupt-names = "macirq", "eth_wake_irq"; 1772 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 1773 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1774 <&cru CLK_GMAC1_PTP_REF>; 1775 clock-names = "stmmaceth", "clk_mac_ref", 1776 "pclk_mac", "aclk_mac", 1777 "ptp_ref"; 1778 power-domains = <&power RK3588_PD_GMAC>; 1779 resets = <&cru SRST_A_GMAC1>; 1780 reset-names = "stmmaceth"; 1781 rockchip,grf = <&sys_grf>; 1782 rockchip,php-grf = <&php_grf>; 1783 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1784 snps,mixed-burst; 1785 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1786 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1787 snps,tso; 1788 status = "disabled"; 1789 1790 mdio1: mdio { 1791 compatible = "snps,dwmac-mdio"; 1792 #address-cells = <0x1>; 1793 #size-cells = <0x0>; 1794 }; 1795 1796 gmac1_stmmac_axi_setup: stmmac-axi-config { 1797 snps,blen = <0 0 0 0 16 8 4>; 1798 snps,wr_osr_lmt = <4>; 1799 snps,rd_osr_lmt = <8>; 1800 }; 1801 1802 gmac1_mtl_rx_setup: rx-queues-config { 1803 snps,rx-queues-to-use = <2>; 1804 queue0 {}; 1805 queue1 {}; 1806 }; 1807 1808 gmac1_mtl_tx_setup: tx-queues-config { 1809 snps,tx-queues-to-use = <2>; 1810 queue0 {}; 1811 queue1 {}; 1812 }; 1813 }; 1814 1815 sata0: sata@fe210000 { 1816 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1817 reg = <0 0xfe210000 0 0x1000>; 1818 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; 1819 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1820 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, 1821 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; 1822 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1823 ports-implemented = <0x1>; 1824 #address-cells = <1>; 1825 #size-cells = <0>; 1826 status = "disabled"; 1827 1828 sata-port@0 { 1829 reg = <0>; 1830 hba-port-cap = <HBA_PORT_FBSCP>; 1831 phys = <&combphy0_ps PHY_TYPE_SATA>; 1832 phy-names = "sata-phy"; 1833 snps,rx-ts-max = <32>; 1834 snps,tx-ts-max = <32>; 1835 }; 1836 }; 1837 1838 sata2: sata@fe230000 { 1839 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1840 reg = <0 0xfe230000 0 0x1000>; 1841 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; 1842 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 1843 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, 1844 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; 1845 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1846 ports-implemented = <0x1>; 1847 #address-cells = <1>; 1848 #size-cells = <0>; 1849 status = "disabled"; 1850 1851 sata-port@0 { 1852 reg = <0>; 1853 hba-port-cap = <HBA_PORT_FBSCP>; 1854 phys = <&combphy2_psu PHY_TYPE_SATA>; 1855 phy-names = "sata-phy"; 1856 snps,rx-ts-max = <32>; 1857 snps,tx-ts-max = <32>; 1858 }; 1859 }; 1860 1861 sfc: spi@fe2b0000 { 1862 compatible = "rockchip,sfc"; 1863 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1864 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; 1865 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1866 clock-names = "clk_sfc", "hclk_sfc"; 1867 #address-cells = <1>; 1868 #size-cells = <0>; 1869 status = "disabled"; 1870 }; 1871 1872 sdmmc: mmc@fe2c0000 { 1873 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1874 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1875 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 1876 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 1877 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1878 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1879 fifo-depth = <0x100>; 1880 max-frequency = <200000000>; 1881 pinctrl-names = "default"; 1882 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1883 power-domains = <&power RK3588_PD_SDMMC>; 1884 status = "disabled"; 1885 }; 1886 1887 sdio: mmc@fe2d0000 { 1888 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1889 reg = <0x00 0xfe2d0000 0x00 0x4000>; 1890 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; 1891 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 1892 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1893 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1894 fifo-depth = <0x100>; 1895 max-frequency = <200000000>; 1896 pinctrl-names = "default"; 1897 pinctrl-0 = <&sdiom1_pins>; 1898 power-domains = <&power RK3588_PD_SDIO>; 1899 status = "disabled"; 1900 }; 1901 1902 sdhci: mmc@fe2e0000 { 1903 compatible = "rockchip,rk3588-dwcmshc"; 1904 reg = <0x0 0xfe2e0000 0x0 0x10000>; 1905 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 1906 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 1907 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1908 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1909 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1910 <&cru TMCLK_EMMC>; 1911 clock-names = "core", "bus", "axi", "block", "timer"; 1912 max-frequency = <200000000>; 1913 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 1914 <&emmc_cmd>, <&emmc_data_strobe>; 1915 pinctrl-names = "default"; 1916 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1917 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1918 <&cru SRST_T_EMMC>; 1919 reset-names = "core", "bus", "axi", "block", "timer"; 1920 status = "disabled"; 1921 }; 1922 1923 i2s0_8ch: i2s@fe470000 { 1924 compatible = "rockchip,rk3588-i2s-tdm"; 1925 reg = <0x0 0xfe470000 0x0 0x1000>; 1926 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; 1927 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1928 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1929 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1930 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 1931 dmas = <&dmac0 0>, <&dmac0 1>; 1932 dma-names = "tx", "rx"; 1933 power-domains = <&power RK3588_PD_AUDIO>; 1934 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1935 reset-names = "tx-m", "rx-m"; 1936 rockchip,trcm-sync-tx-only; 1937 pinctrl-names = "default"; 1938 pinctrl-0 = <&i2s0_lrck 1939 &i2s0_sclk 1940 &i2s0_sdi0 1941 &i2s0_sdi1 1942 &i2s0_sdi2 1943 &i2s0_sdi3 1944 &i2s0_sdo0 1945 &i2s0_sdo1 1946 &i2s0_sdo2 1947 &i2s0_sdo3>; 1948 #sound-dai-cells = <0>; 1949 status = "disabled"; 1950 }; 1951 1952 i2s1_8ch: i2s@fe480000 { 1953 compatible = "rockchip,rk3588-i2s-tdm"; 1954 reg = <0x0 0xfe480000 0x0 0x1000>; 1955 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; 1956 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1957 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1958 dmas = <&dmac0 2>, <&dmac0 3>; 1959 dma-names = "tx", "rx"; 1960 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1961 reset-names = "tx-m", "rx-m"; 1962 rockchip,trcm-sync-tx-only; 1963 pinctrl-names = "default"; 1964 pinctrl-0 = <&i2s1m0_lrck 1965 &i2s1m0_sclk 1966 &i2s1m0_sdi0 1967 &i2s1m0_sdi1 1968 &i2s1m0_sdi2 1969 &i2s1m0_sdi3 1970 &i2s1m0_sdo0 1971 &i2s1m0_sdo1 1972 &i2s1m0_sdo2 1973 &i2s1m0_sdo3>; 1974 #sound-dai-cells = <0>; 1975 status = "disabled"; 1976 }; 1977 1978 i2s2_2ch: i2s@fe490000 { 1979 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1980 reg = <0x0 0xfe490000 0x0 0x1000>; 1981 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; 1982 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1983 clock-names = "i2s_clk", "i2s_hclk"; 1984 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1985 assigned-clock-parents = <&cru PLL_AUPLL>; 1986 dmas = <&dmac1 0>, <&dmac1 1>; 1987 dma-names = "tx", "rx"; 1988 power-domains = <&power RK3588_PD_AUDIO>; 1989 pinctrl-names = "default"; 1990 pinctrl-0 = <&i2s2m1_lrck 1991 &i2s2m1_sclk 1992 &i2s2m1_sdi 1993 &i2s2m1_sdo>; 1994 #sound-dai-cells = <0>; 1995 status = "disabled"; 1996 }; 1997 1998 i2s3_2ch: i2s@fe4a0000 { 1999 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 2000 reg = <0x0 0xfe4a0000 0x0 0x1000>; 2001 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; 2002 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 2003 clock-names = "i2s_clk", "i2s_hclk"; 2004 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 2005 assigned-clock-parents = <&cru PLL_AUPLL>; 2006 dmas = <&dmac1 2>, <&dmac1 3>; 2007 dma-names = "tx", "rx"; 2008 power-domains = <&power RK3588_PD_AUDIO>; 2009 pinctrl-names = "default"; 2010 pinctrl-0 = <&i2s3_lrck 2011 &i2s3_sclk 2012 &i2s3_sdi 2013 &i2s3_sdo>; 2014 #sound-dai-cells = <0>; 2015 status = "disabled"; 2016 }; 2017 2018 gic: interrupt-controller@fe600000 { 2019 compatible = "arm,gic-v3"; 2020 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 2021 <0x0 0xfe680000 0 0x100000>; /* GICR */ 2022 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 2023 interrupt-controller; 2024 mbi-alias = <0x0 0xfe610000>; 2025 mbi-ranges = <424 56>; 2026 msi-controller; 2027 ranges; 2028 #address-cells = <2>; 2029 #interrupt-cells = <4>; 2030 #size-cells = <2>; 2031 2032 its0: msi-controller@fe640000 { 2033 compatible = "arm,gic-v3-its"; 2034 reg = <0x0 0xfe640000 0x0 0x20000>; 2035 msi-controller; 2036 #msi-cells = <1>; 2037 }; 2038 2039 its1: msi-controller@fe660000 { 2040 compatible = "arm,gic-v3-its"; 2041 reg = <0x0 0xfe660000 0x0 0x20000>; 2042 msi-controller; 2043 #msi-cells = <1>; 2044 }; 2045 2046 ppi-partitions { 2047 ppi_partition0: interrupt-partition-0 { 2048 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 2049 }; 2050 2051 ppi_partition1: interrupt-partition-1 { 2052 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; 2053 }; 2054 }; 2055 }; 2056 2057 dmac0: dma-controller@fea10000 { 2058 compatible = "arm,pl330", "arm,primecell"; 2059 reg = <0x0 0xfea10000 0x0 0x4000>; 2060 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, 2061 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; 2062 arm,pl330-periph-burst; 2063 clocks = <&cru ACLK_DMAC0>; 2064 clock-names = "apb_pclk"; 2065 #dma-cells = <1>; 2066 }; 2067 2068 dmac1: dma-controller@fea30000 { 2069 compatible = "arm,pl330", "arm,primecell"; 2070 reg = <0x0 0xfea30000 0x0 0x4000>; 2071 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, 2072 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; 2073 arm,pl330-periph-burst; 2074 clocks = <&cru ACLK_DMAC1>; 2075 clock-names = "apb_pclk"; 2076 #dma-cells = <1>; 2077 }; 2078 2079 i2c1: i2c@fea90000 { 2080 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2081 reg = <0x0 0xfea90000 0x0 0x1000>; 2082 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 2083 clock-names = "i2c", "pclk"; 2084 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; 2085 pinctrl-0 = <&i2c1m0_xfer>; 2086 pinctrl-names = "default"; 2087 #address-cells = <1>; 2088 #size-cells = <0>; 2089 status = "disabled"; 2090 }; 2091 2092 i2c2: i2c@feaa0000 { 2093 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2094 reg = <0x0 0xfeaa0000 0x0 0x1000>; 2095 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 2096 clock-names = "i2c", "pclk"; 2097 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; 2098 pinctrl-0 = <&i2c2m0_xfer>; 2099 pinctrl-names = "default"; 2100 #address-cells = <1>; 2101 #size-cells = <0>; 2102 status = "disabled"; 2103 }; 2104 2105 i2c3: i2c@feab0000 { 2106 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2107 reg = <0x0 0xfeab0000 0x0 0x1000>; 2108 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 2109 clock-names = "i2c", "pclk"; 2110 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; 2111 pinctrl-0 = <&i2c3m0_xfer>; 2112 pinctrl-names = "default"; 2113 #address-cells = <1>; 2114 #size-cells = <0>; 2115 status = "disabled"; 2116 }; 2117 2118 i2c4: i2c@feac0000 { 2119 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2120 reg = <0x0 0xfeac0000 0x0 0x1000>; 2121 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2122 clock-names = "i2c", "pclk"; 2123 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; 2124 pinctrl-0 = <&i2c4m0_xfer>; 2125 pinctrl-names = "default"; 2126 #address-cells = <1>; 2127 #size-cells = <0>; 2128 status = "disabled"; 2129 }; 2130 2131 i2c5: i2c@fead0000 { 2132 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2133 reg = <0x0 0xfead0000 0x0 0x1000>; 2134 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2135 clock-names = "i2c", "pclk"; 2136 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; 2137 pinctrl-0 = <&i2c5m0_xfer>; 2138 pinctrl-names = "default"; 2139 #address-cells = <1>; 2140 #size-cells = <0>; 2141 status = "disabled"; 2142 }; 2143 2144 timer0: timer@feae0000 { 2145 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 2146 reg = <0x0 0xfeae0000 0x0 0x20>; 2147 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; 2148 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 2149 clock-names = "pclk", "timer"; 2150 }; 2151 2152 wdt: watchdog@feaf0000 { 2153 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; 2154 reg = <0x0 0xfeaf0000 0x0 0x100>; 2155 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 2156 clock-names = "tclk", "pclk"; 2157 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; 2158 }; 2159 2160 spi0: spi@feb00000 { 2161 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2162 reg = <0x0 0xfeb00000 0x0 0x1000>; 2163 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; 2164 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 2165 clock-names = "spiclk", "apb_pclk"; 2166 dmas = <&dmac0 14>, <&dmac0 15>; 2167 dma-names = "tx", "rx"; 2168 num-cs = <2>; 2169 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 2170 pinctrl-names = "default"; 2171 #address-cells = <1>; 2172 #size-cells = <0>; 2173 status = "disabled"; 2174 }; 2175 2176 spi1: spi@feb10000 { 2177 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2178 reg = <0x0 0xfeb10000 0x0 0x1000>; 2179 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; 2180 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 2181 clock-names = "spiclk", "apb_pclk"; 2182 dmas = <&dmac0 16>, <&dmac0 17>; 2183 dma-names = "tx", "rx"; 2184 num-cs = <2>; 2185 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 2186 pinctrl-names = "default"; 2187 #address-cells = <1>; 2188 #size-cells = <0>; 2189 status = "disabled"; 2190 }; 2191 2192 spi2: spi@feb20000 { 2193 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2194 reg = <0x0 0xfeb20000 0x0 0x1000>; 2195 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; 2196 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 2197 clock-names = "spiclk", "apb_pclk"; 2198 dmas = <&dmac1 15>, <&dmac1 16>; 2199 dma-names = "tx", "rx"; 2200 num-cs = <2>; 2201 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 2202 pinctrl-names = "default"; 2203 #address-cells = <1>; 2204 #size-cells = <0>; 2205 status = "disabled"; 2206 }; 2207 2208 spi3: spi@feb30000 { 2209 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2210 reg = <0x0 0xfeb30000 0x0 0x1000>; 2211 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; 2212 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 2213 clock-names = "spiclk", "apb_pclk"; 2214 dmas = <&dmac1 17>, <&dmac1 18>; 2215 dma-names = "tx", "rx"; 2216 num-cs = <2>; 2217 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 2218 pinctrl-names = "default"; 2219 #address-cells = <1>; 2220 #size-cells = <0>; 2221 status = "disabled"; 2222 }; 2223 2224 uart1: serial@feb40000 { 2225 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2226 reg = <0x0 0xfeb40000 0x0 0x100>; 2227 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; 2228 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 2229 clock-names = "baudclk", "apb_pclk"; 2230 dmas = <&dmac0 8>, <&dmac0 9>; 2231 dma-names = "tx", "rx"; 2232 pinctrl-0 = <&uart1m1_xfer>; 2233 pinctrl-names = "default"; 2234 reg-io-width = <4>; 2235 reg-shift = <2>; 2236 status = "disabled"; 2237 }; 2238 2239 uart2: serial@feb50000 { 2240 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2241 reg = <0x0 0xfeb50000 0x0 0x100>; 2242 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; 2243 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 2244 clock-names = "baudclk", "apb_pclk"; 2245 dmas = <&dmac0 10>, <&dmac0 11>; 2246 dma-names = "tx", "rx"; 2247 pinctrl-0 = <&uart2m1_xfer>; 2248 pinctrl-names = "default"; 2249 reg-io-width = <4>; 2250 reg-shift = <2>; 2251 status = "disabled"; 2252 }; 2253 2254 uart3: serial@feb60000 { 2255 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2256 reg = <0x0 0xfeb60000 0x0 0x100>; 2257 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; 2258 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 2259 clock-names = "baudclk", "apb_pclk"; 2260 dmas = <&dmac0 12>, <&dmac0 13>; 2261 dma-names = "tx", "rx"; 2262 pinctrl-0 = <&uart3m1_xfer>; 2263 pinctrl-names = "default"; 2264 reg-io-width = <4>; 2265 reg-shift = <2>; 2266 status = "disabled"; 2267 }; 2268 2269 uart4: serial@feb70000 { 2270 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2271 reg = <0x0 0xfeb70000 0x0 0x100>; 2272 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; 2273 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 2274 clock-names = "baudclk", "apb_pclk"; 2275 dmas = <&dmac1 9>, <&dmac1 10>; 2276 dma-names = "tx", "rx"; 2277 pinctrl-0 = <&uart4m1_xfer>; 2278 pinctrl-names = "default"; 2279 reg-io-width = <4>; 2280 reg-shift = <2>; 2281 status = "disabled"; 2282 }; 2283 2284 uart5: serial@feb80000 { 2285 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2286 reg = <0x0 0xfeb80000 0x0 0x100>; 2287 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; 2288 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2289 clock-names = "baudclk", "apb_pclk"; 2290 dmas = <&dmac1 11>, <&dmac1 12>; 2291 dma-names = "tx", "rx"; 2292 pinctrl-0 = <&uart5m1_xfer>; 2293 pinctrl-names = "default"; 2294 reg-io-width = <4>; 2295 reg-shift = <2>; 2296 status = "disabled"; 2297 }; 2298 2299 uart6: serial@feb90000 { 2300 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2301 reg = <0x0 0xfeb90000 0x0 0x100>; 2302 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; 2303 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2304 clock-names = "baudclk", "apb_pclk"; 2305 dmas = <&dmac1 13>, <&dmac1 14>; 2306 dma-names = "tx", "rx"; 2307 pinctrl-0 = <&uart6m1_xfer>; 2308 pinctrl-names = "default"; 2309 reg-io-width = <4>; 2310 reg-shift = <2>; 2311 status = "disabled"; 2312 }; 2313 2314 uart7: serial@feba0000 { 2315 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2316 reg = <0x0 0xfeba0000 0x0 0x100>; 2317 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; 2318 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2319 clock-names = "baudclk", "apb_pclk"; 2320 dmas = <&dmac2 7>, <&dmac2 8>; 2321 dma-names = "tx", "rx"; 2322 pinctrl-0 = <&uart7m1_xfer>; 2323 pinctrl-names = "default"; 2324 reg-io-width = <4>; 2325 reg-shift = <2>; 2326 status = "disabled"; 2327 }; 2328 2329 uart8: serial@febb0000 { 2330 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2331 reg = <0x0 0xfebb0000 0x0 0x100>; 2332 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; 2333 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2334 clock-names = "baudclk", "apb_pclk"; 2335 dmas = <&dmac2 9>, <&dmac2 10>; 2336 dma-names = "tx", "rx"; 2337 pinctrl-0 = <&uart8m1_xfer>; 2338 pinctrl-names = "default"; 2339 reg-io-width = <4>; 2340 reg-shift = <2>; 2341 status = "disabled"; 2342 }; 2343 2344 uart9: serial@febc0000 { 2345 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2346 reg = <0x0 0xfebc0000 0x0 0x100>; 2347 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; 2348 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2349 clock-names = "baudclk", "apb_pclk"; 2350 dmas = <&dmac2 11>, <&dmac2 12>; 2351 dma-names = "tx", "rx"; 2352 pinctrl-0 = <&uart9m1_xfer>; 2353 pinctrl-names = "default"; 2354 reg-io-width = <4>; 2355 reg-shift = <2>; 2356 status = "disabled"; 2357 }; 2358 2359 pwm4: pwm@febd0000 { 2360 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2361 reg = <0x0 0xfebd0000 0x0 0x10>; 2362 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2363 clock-names = "pwm", "pclk"; 2364 pinctrl-0 = <&pwm4m0_pins>; 2365 pinctrl-names = "default"; 2366 #pwm-cells = <3>; 2367 status = "disabled"; 2368 }; 2369 2370 pwm5: pwm@febd0010 { 2371 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2372 reg = <0x0 0xfebd0010 0x0 0x10>; 2373 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2374 clock-names = "pwm", "pclk"; 2375 pinctrl-0 = <&pwm5m0_pins>; 2376 pinctrl-names = "default"; 2377 #pwm-cells = <3>; 2378 status = "disabled"; 2379 }; 2380 2381 pwm6: pwm@febd0020 { 2382 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2383 reg = <0x0 0xfebd0020 0x0 0x10>; 2384 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2385 clock-names = "pwm", "pclk"; 2386 pinctrl-0 = <&pwm6m0_pins>; 2387 pinctrl-names = "default"; 2388 #pwm-cells = <3>; 2389 status = "disabled"; 2390 }; 2391 2392 pwm7: pwm@febd0030 { 2393 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2394 reg = <0x0 0xfebd0030 0x0 0x10>; 2395 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2396 clock-names = "pwm", "pclk"; 2397 pinctrl-0 = <&pwm7m0_pins>; 2398 pinctrl-names = "default"; 2399 #pwm-cells = <3>; 2400 status = "disabled"; 2401 }; 2402 2403 pwm8: pwm@febe0000 { 2404 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2405 reg = <0x0 0xfebe0000 0x0 0x10>; 2406 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2407 clock-names = "pwm", "pclk"; 2408 pinctrl-0 = <&pwm8m0_pins>; 2409 pinctrl-names = "default"; 2410 #pwm-cells = <3>; 2411 status = "disabled"; 2412 }; 2413 2414 pwm9: pwm@febe0010 { 2415 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2416 reg = <0x0 0xfebe0010 0x0 0x10>; 2417 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2418 clock-names = "pwm", "pclk"; 2419 pinctrl-0 = <&pwm9m0_pins>; 2420 pinctrl-names = "default"; 2421 #pwm-cells = <3>; 2422 status = "disabled"; 2423 }; 2424 2425 pwm10: pwm@febe0020 { 2426 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2427 reg = <0x0 0xfebe0020 0x0 0x10>; 2428 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2429 clock-names = "pwm", "pclk"; 2430 pinctrl-0 = <&pwm10m0_pins>; 2431 pinctrl-names = "default"; 2432 #pwm-cells = <3>; 2433 status = "disabled"; 2434 }; 2435 2436 pwm11: pwm@febe0030 { 2437 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2438 reg = <0x0 0xfebe0030 0x0 0x10>; 2439 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2440 clock-names = "pwm", "pclk"; 2441 pinctrl-0 = <&pwm11m0_pins>; 2442 pinctrl-names = "default"; 2443 #pwm-cells = <3>; 2444 status = "disabled"; 2445 }; 2446 2447 pwm12: pwm@febf0000 { 2448 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2449 reg = <0x0 0xfebf0000 0x0 0x10>; 2450 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2451 clock-names = "pwm", "pclk"; 2452 pinctrl-0 = <&pwm12m0_pins>; 2453 pinctrl-names = "default"; 2454 #pwm-cells = <3>; 2455 status = "disabled"; 2456 }; 2457 2458 pwm13: pwm@febf0010 { 2459 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2460 reg = <0x0 0xfebf0010 0x0 0x10>; 2461 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2462 clock-names = "pwm", "pclk"; 2463 pinctrl-0 = <&pwm13m0_pins>; 2464 pinctrl-names = "default"; 2465 #pwm-cells = <3>; 2466 status = "disabled"; 2467 }; 2468 2469 pwm14: pwm@febf0020 { 2470 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2471 reg = <0x0 0xfebf0020 0x0 0x10>; 2472 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2473 clock-names = "pwm", "pclk"; 2474 pinctrl-0 = <&pwm14m0_pins>; 2475 pinctrl-names = "default"; 2476 #pwm-cells = <3>; 2477 status = "disabled"; 2478 }; 2479 2480 pwm15: pwm@febf0030 { 2481 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2482 reg = <0x0 0xfebf0030 0x0 0x10>; 2483 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2484 clock-names = "pwm", "pclk"; 2485 pinctrl-0 = <&pwm15m0_pins>; 2486 pinctrl-names = "default"; 2487 #pwm-cells = <3>; 2488 status = "disabled"; 2489 }; 2490 2491 thermal_zones: thermal-zones { 2492 /* sensor near the center of the SoC */ 2493 package_thermal: package-thermal { 2494 polling-delay-passive = <0>; 2495 polling-delay = <0>; 2496 thermal-sensors = <&tsadc 0>; 2497 2498 trips { 2499 package_crit: package-crit { 2500 temperature = <115000>; 2501 hysteresis = <0>; 2502 type = "critical"; 2503 }; 2504 }; 2505 }; 2506 2507 /* sensor between A76 cores 0 and 1 */ 2508 bigcore0_thermal: bigcore0-thermal { 2509 polling-delay-passive = <100>; 2510 polling-delay = <0>; 2511 thermal-sensors = <&tsadc 1>; 2512 2513 trips { 2514 bigcore0_alert: bigcore0-alert { 2515 temperature = <85000>; 2516 hysteresis = <2000>; 2517 type = "passive"; 2518 }; 2519 2520 bigcore0_crit: bigcore0-crit { 2521 temperature = <115000>; 2522 hysteresis = <0>; 2523 type = "critical"; 2524 }; 2525 }; 2526 2527 cooling-maps { 2528 map0 { 2529 trip = <&bigcore0_alert>; 2530 cooling-device = 2531 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2532 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2533 }; 2534 }; 2535 }; 2536 2537 /* sensor between A76 cores 2 and 3 */ 2538 bigcore2_thermal: bigcore2-thermal { 2539 polling-delay-passive = <100>; 2540 polling-delay = <0>; 2541 thermal-sensors = <&tsadc 2>; 2542 2543 trips { 2544 bigcore2_alert: bigcore2-alert { 2545 temperature = <85000>; 2546 hysteresis = <2000>; 2547 type = "passive"; 2548 }; 2549 2550 bigcore2_crit: bigcore2-crit { 2551 temperature = <115000>; 2552 hysteresis = <0>; 2553 type = "critical"; 2554 }; 2555 }; 2556 2557 cooling-maps { 2558 map0 { 2559 trip = <&bigcore2_alert>; 2560 cooling-device = 2561 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2562 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2563 }; 2564 }; 2565 }; 2566 2567 /* sensor between the four A55 cores */ 2568 little_core_thermal: littlecore-thermal { 2569 polling-delay-passive = <100>; 2570 polling-delay = <0>; 2571 thermal-sensors = <&tsadc 3>; 2572 2573 trips { 2574 littlecore_alert: littlecore-alert { 2575 temperature = <85000>; 2576 hysteresis = <2000>; 2577 type = "passive"; 2578 }; 2579 2580 littlecore_crit: littlecore-crit { 2581 temperature = <115000>; 2582 hysteresis = <0>; 2583 type = "critical"; 2584 }; 2585 }; 2586 2587 cooling-maps { 2588 map0 { 2589 trip = <&littlecore_alert>; 2590 cooling-device = 2591 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2592 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2593 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2594 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2595 }; 2596 }; 2597 }; 2598 2599 /* sensor near the PD_CENTER power domain */ 2600 center_thermal: center-thermal { 2601 polling-delay-passive = <0>; 2602 polling-delay = <0>; 2603 thermal-sensors = <&tsadc 4>; 2604 2605 trips { 2606 center_crit: center-crit { 2607 temperature = <115000>; 2608 hysteresis = <0>; 2609 type = "critical"; 2610 }; 2611 }; 2612 }; 2613 2614 gpu_thermal: gpu-thermal { 2615 polling-delay-passive = <100>; 2616 polling-delay = <0>; 2617 thermal-sensors = <&tsadc 5>; 2618 2619 trips { 2620 gpu_alert: gpu-alert { 2621 temperature = <85000>; 2622 hysteresis = <2000>; 2623 type = "passive"; 2624 }; 2625 2626 gpu_crit: gpu-crit { 2627 temperature = <115000>; 2628 hysteresis = <0>; 2629 type = "critical"; 2630 }; 2631 }; 2632 2633 cooling-maps { 2634 map0 { 2635 trip = <&gpu_alert>; 2636 cooling-device = 2637 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2638 }; 2639 }; 2640 }; 2641 2642 npu_thermal: npu-thermal { 2643 polling-delay-passive = <0>; 2644 polling-delay = <0>; 2645 thermal-sensors = <&tsadc 6>; 2646 2647 trips { 2648 npu_crit: npu-crit { 2649 temperature = <115000>; 2650 hysteresis = <0>; 2651 type = "critical"; 2652 }; 2653 }; 2654 }; 2655 }; 2656 2657 tsadc: tsadc@fec00000 { 2658 compatible = "rockchip,rk3588-tsadc"; 2659 reg = <0x0 0xfec00000 0x0 0x400>; 2660 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; 2661 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2662 clock-names = "tsadc", "apb_pclk"; 2663 assigned-clocks = <&cru CLK_TSADC>; 2664 assigned-clock-rates = <2000000>; 2665 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 2666 reset-names = "tsadc-apb", "tsadc"; 2667 rockchip,hw-tshut-temp = <120000>; 2668 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 2669 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2670 pinctrl-0 = <&tsadc_gpio_func>; 2671 pinctrl-1 = <&tsadc_shut>; 2672 pinctrl-names = "gpio", "otpout"; 2673 #thermal-sensor-cells = <1>; 2674 status = "disabled"; 2675 }; 2676 2677 saradc: adc@fec10000 { 2678 compatible = "rockchip,rk3588-saradc"; 2679 reg = <0x0 0xfec10000 0x0 0x10000>; 2680 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; 2681 #io-channel-cells = <1>; 2682 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2683 clock-names = "saradc", "apb_pclk"; 2684 resets = <&cru SRST_P_SARADC>; 2685 reset-names = "saradc-apb"; 2686 status = "disabled"; 2687 }; 2688 2689 i2c6: i2c@fec80000 { 2690 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2691 reg = <0x0 0xfec80000 0x0 0x1000>; 2692 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2693 clock-names = "i2c", "pclk"; 2694 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; 2695 pinctrl-0 = <&i2c6m0_xfer>; 2696 pinctrl-names = "default"; 2697 #address-cells = <1>; 2698 #size-cells = <0>; 2699 status = "disabled"; 2700 }; 2701 2702 i2c7: i2c@fec90000 { 2703 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2704 reg = <0x0 0xfec90000 0x0 0x1000>; 2705 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2706 clock-names = "i2c", "pclk"; 2707 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 2708 pinctrl-0 = <&i2c7m0_xfer>; 2709 pinctrl-names = "default"; 2710 #address-cells = <1>; 2711 #size-cells = <0>; 2712 status = "disabled"; 2713 }; 2714 2715 i2c8: i2c@feca0000 { 2716 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2717 reg = <0x0 0xfeca0000 0x0 0x1000>; 2718 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2719 clock-names = "i2c", "pclk"; 2720 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; 2721 pinctrl-0 = <&i2c8m0_xfer>; 2722 pinctrl-names = "default"; 2723 #address-cells = <1>; 2724 #size-cells = <0>; 2725 status = "disabled"; 2726 }; 2727 2728 spi4: spi@fecb0000 { 2729 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2730 reg = <0x0 0xfecb0000 0x0 0x1000>; 2731 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; 2732 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2733 clock-names = "spiclk", "apb_pclk"; 2734 dmas = <&dmac2 13>, <&dmac2 14>; 2735 dma-names = "tx", "rx"; 2736 num-cs = <2>; 2737 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 2738 pinctrl-names = "default"; 2739 #address-cells = <1>; 2740 #size-cells = <0>; 2741 status = "disabled"; 2742 }; 2743 2744 otp: efuse@fecc0000 { 2745 compatible = "rockchip,rk3588-otp"; 2746 reg = <0x0 0xfecc0000 0x0 0x400>; 2747 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 2748 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; 2749 clock-names = "otp", "apb_pclk", "phy", "arb"; 2750 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 2751 <&cru SRST_OTPC_ARB>; 2752 reset-names = "otp", "apb", "arb"; 2753 #address-cells = <1>; 2754 #size-cells = <1>; 2755 2756 cpu_code: cpu-code@2 { 2757 reg = <0x02 0x2>; 2758 }; 2759 2760 otp_id: id@7 { 2761 reg = <0x07 0x10>; 2762 }; 2763 2764 cpub0_leakage: cpu-leakage@17 { 2765 reg = <0x17 0x1>; 2766 }; 2767 2768 cpub1_leakage: cpu-leakage@18 { 2769 reg = <0x18 0x1>; 2770 }; 2771 2772 cpul_leakage: cpu-leakage@19 { 2773 reg = <0x19 0x1>; 2774 }; 2775 2776 log_leakage: log-leakage@1a { 2777 reg = <0x1a 0x1>; 2778 }; 2779 2780 gpu_leakage: gpu-leakage@1b { 2781 reg = <0x1b 0x1>; 2782 }; 2783 2784 otp_cpu_version: cpu-version@1c { 2785 reg = <0x1c 0x1>; 2786 bits = <3 3>; 2787 }; 2788 2789 npu_leakage: npu-leakage@28 { 2790 reg = <0x28 0x1>; 2791 }; 2792 2793 codec_leakage: codec-leakage@29 { 2794 reg = <0x29 0x1>; 2795 }; 2796 }; 2797 2798 dmac2: dma-controller@fed10000 { 2799 compatible = "arm,pl330", "arm,primecell"; 2800 reg = <0x0 0xfed10000 0x0 0x4000>; 2801 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, 2802 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; 2803 arm,pl330-periph-burst; 2804 clocks = <&cru ACLK_DMAC2>; 2805 clock-names = "apb_pclk"; 2806 #dma-cells = <1>; 2807 }; 2808 2809 hdptxphy_hdmi0: phy@fed60000 { 2810 compatible = "rockchip,rk3588-hdptx-phy"; 2811 reg = <0x0 0xfed60000 0x0 0x2000>; 2812 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 2813 clock-names = "ref", "apb"; 2814 #phy-cells = <0>; 2815 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, 2816 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, 2817 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, 2818 <&cru SRST_HDPTX0_LCPLL>; 2819 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 2820 "lcpll"; 2821 rockchip,grf = <&hdptxphy0_grf>; 2822 status = "disabled"; 2823 }; 2824 2825 usbdp_phy0: phy@fed80000 { 2826 compatible = "rockchip,rk3588-usbdp-phy"; 2827 reg = <0x0 0xfed80000 0x0 0x10000>; 2828 #phy-cells = <1>; 2829 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 2830 <&cru CLK_USBDP_PHY0_IMMORTAL>, 2831 <&cru PCLK_USBDPPHY0>, 2832 <&u2phy0>; 2833 clock-names = "refclk", "immortal", "pclk", "utmi"; 2834 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 2835 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 2836 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 2837 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 2838 <&cru SRST_P_USBDPPHY0>; 2839 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 2840 rockchip,u2phy-grf = <&usb2phy0_grf>; 2841 rockchip,usb-grf = <&usb_grf>; 2842 rockchip,usbdpphy-grf = <&usbdpphy0_grf>; 2843 rockchip,vo-grf = <&vo0_grf>; 2844 status = "disabled"; 2845 }; 2846 2847 combphy0_ps: phy@fee00000 { 2848 compatible = "rockchip,rk3588-naneng-combphy"; 2849 reg = <0x0 0xfee00000 0x0 0x100>; 2850 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, 2851 <&cru PCLK_PHP_ROOT>; 2852 clock-names = "ref", "apb", "pipe"; 2853 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 2854 assigned-clock-rates = <100000000>; 2855 #phy-cells = <1>; 2856 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; 2857 reset-names = "phy", "apb"; 2858 rockchip,pipe-grf = <&php_grf>; 2859 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 2860 status = "disabled"; 2861 }; 2862 2863 combphy2_psu: phy@fee20000 { 2864 compatible = "rockchip,rk3588-naneng-combphy"; 2865 reg = <0x0 0xfee20000 0x0 0x100>; 2866 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, 2867 <&cru PCLK_PHP_ROOT>; 2868 clock-names = "ref", "apb", "pipe"; 2869 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 2870 assigned-clock-rates = <100000000>; 2871 #phy-cells = <1>; 2872 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; 2873 reset-names = "phy", "apb"; 2874 rockchip,pipe-grf = <&php_grf>; 2875 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 2876 status = "disabled"; 2877 }; 2878 2879 system_sram2: sram@ff001000 { 2880 compatible = "mmio-sram"; 2881 reg = <0x0 0xff001000 0x0 0xef000>; 2882 ranges = <0x0 0x0 0xff001000 0xef000>; 2883 #address-cells = <1>; 2884 #size-cells = <1>; 2885 }; 2886 2887 pinctrl: pinctrl { 2888 compatible = "rockchip,rk3588-pinctrl"; 2889 ranges; 2890 rockchip,grf = <&ioc>; 2891 #address-cells = <2>; 2892 #size-cells = <2>; 2893 2894 gpio0: gpio@fd8a0000 { 2895 compatible = "rockchip,gpio-bank"; 2896 reg = <0x0 0xfd8a0000 0x0 0x100>; 2897 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 2898 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 2899 gpio-controller; 2900 gpio-ranges = <&pinctrl 0 0 32>; 2901 interrupt-controller; 2902 #gpio-cells = <2>; 2903 #interrupt-cells = <2>; 2904 }; 2905 2906 gpio1: gpio@fec20000 { 2907 compatible = "rockchip,gpio-bank"; 2908 reg = <0x0 0xfec20000 0x0 0x100>; 2909 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; 2910 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2911 gpio-controller; 2912 gpio-ranges = <&pinctrl 0 32 32>; 2913 interrupt-controller; 2914 #gpio-cells = <2>; 2915 #interrupt-cells = <2>; 2916 }; 2917 2918 gpio2: gpio@fec30000 { 2919 compatible = "rockchip,gpio-bank"; 2920 reg = <0x0 0xfec30000 0x0 0x100>; 2921 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; 2922 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2923 gpio-controller; 2924 gpio-ranges = <&pinctrl 0 64 32>; 2925 interrupt-controller; 2926 #gpio-cells = <2>; 2927 #interrupt-cells = <2>; 2928 }; 2929 2930 gpio3: gpio@fec40000 { 2931 compatible = "rockchip,gpio-bank"; 2932 reg = <0x0 0xfec40000 0x0 0x100>; 2933 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; 2934 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2935 gpio-controller; 2936 gpio-ranges = <&pinctrl 0 96 32>; 2937 interrupt-controller; 2938 #gpio-cells = <2>; 2939 #interrupt-cells = <2>; 2940 }; 2941 2942 gpio4: gpio@fec50000 { 2943 compatible = "rockchip,gpio-bank"; 2944 reg = <0x0 0xfec50000 0x0 0x100>; 2945 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; 2946 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2947 gpio-controller; 2948 gpio-ranges = <&pinctrl 0 128 32>; 2949 interrupt-controller; 2950 #gpio-cells = <2>; 2951 #interrupt-cells = <2>; 2952 }; 2953 }; 2954}; 2955 2956#include "rk3588-base-pinctrl.dtsi" 2957