1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/power/rk3588-power.h> 10#include <dt-bindings/reset/rockchip,rk3588-cru.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/ata/ahci.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3588"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 gpio4 = &gpio4; 28 i2c0 = &i2c0; 29 i2c1 = &i2c1; 30 i2c2 = &i2c2; 31 i2c3 = &i2c3; 32 i2c4 = &i2c4; 33 i2c5 = &i2c5; 34 i2c6 = &i2c6; 35 i2c7 = &i2c7; 36 i2c8 = &i2c8; 37 serial0 = &uart0; 38 serial1 = &uart1; 39 serial2 = &uart2; 40 serial3 = &uart3; 41 serial4 = &uart4; 42 serial5 = &uart5; 43 serial6 = &uart6; 44 serial7 = &uart7; 45 serial8 = &uart8; 46 serial9 = &uart9; 47 spi0 = &spi0; 48 spi1 = &spi1; 49 spi2 = &spi2; 50 spi3 = &spi3; 51 spi4 = &spi4; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu_l0>; 62 }; 63 core1 { 64 cpu = <&cpu_l1>; 65 }; 66 core2 { 67 cpu = <&cpu_l2>; 68 }; 69 core3 { 70 cpu = <&cpu_l3>; 71 }; 72 }; 73 cluster1 { 74 core0 { 75 cpu = <&cpu_b0>; 76 }; 77 core1 { 78 cpu = <&cpu_b1>; 79 }; 80 }; 81 cluster2 { 82 core0 { 83 cpu = <&cpu_b2>; 84 }; 85 core1 { 86 cpu = <&cpu_b3>; 87 }; 88 }; 89 }; 90 91 cpu_l0: cpu@0 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0>; 95 enable-method = "psci"; 96 capacity-dmips-mhz = <530>; 97 clocks = <&scmi_clk SCMI_CLK_CPUL>; 98 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; 99 assigned-clock-rates = <816000000>; 100 cpu-idle-states = <&CPU_SLEEP>; 101 i-cache-size = <32768>; 102 i-cache-line-size = <64>; 103 i-cache-sets = <128>; 104 d-cache-size = <32768>; 105 d-cache-line-size = <64>; 106 d-cache-sets = <128>; 107 next-level-cache = <&l2_cache_l0>; 108 dynamic-power-coefficient = <228>; 109 #cooling-cells = <2>; 110 }; 111 112 cpu_l1: cpu@100 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a55"; 115 reg = <0x100>; 116 enable-method = "psci"; 117 capacity-dmips-mhz = <530>; 118 clocks = <&scmi_clk SCMI_CLK_CPUL>; 119 cpu-idle-states = <&CPU_SLEEP>; 120 i-cache-size = <32768>; 121 i-cache-line-size = <64>; 122 i-cache-sets = <128>; 123 d-cache-size = <32768>; 124 d-cache-line-size = <64>; 125 d-cache-sets = <128>; 126 next-level-cache = <&l2_cache_l1>; 127 dynamic-power-coefficient = <228>; 128 #cooling-cells = <2>; 129 }; 130 131 cpu_l2: cpu@200 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a55"; 134 reg = <0x200>; 135 enable-method = "psci"; 136 capacity-dmips-mhz = <530>; 137 clocks = <&scmi_clk SCMI_CLK_CPUL>; 138 cpu-idle-states = <&CPU_SLEEP>; 139 i-cache-size = <32768>; 140 i-cache-line-size = <64>; 141 i-cache-sets = <128>; 142 d-cache-size = <32768>; 143 d-cache-line-size = <64>; 144 d-cache-sets = <128>; 145 next-level-cache = <&l2_cache_l2>; 146 dynamic-power-coefficient = <228>; 147 #cooling-cells = <2>; 148 }; 149 150 cpu_l3: cpu@300 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a55"; 153 reg = <0x300>; 154 enable-method = "psci"; 155 capacity-dmips-mhz = <530>; 156 clocks = <&scmi_clk SCMI_CLK_CPUL>; 157 cpu-idle-states = <&CPU_SLEEP>; 158 i-cache-size = <32768>; 159 i-cache-line-size = <64>; 160 i-cache-sets = <128>; 161 d-cache-size = <32768>; 162 d-cache-line-size = <64>; 163 d-cache-sets = <128>; 164 next-level-cache = <&l2_cache_l3>; 165 dynamic-power-coefficient = <228>; 166 #cooling-cells = <2>; 167 }; 168 169 cpu_b0: cpu@400 { 170 device_type = "cpu"; 171 compatible = "arm,cortex-a76"; 172 reg = <0x400>; 173 enable-method = "psci"; 174 capacity-dmips-mhz = <1024>; 175 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 176 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; 177 assigned-clock-rates = <816000000>; 178 cpu-idle-states = <&CPU_SLEEP>; 179 i-cache-size = <65536>; 180 i-cache-line-size = <64>; 181 i-cache-sets = <256>; 182 d-cache-size = <65536>; 183 d-cache-line-size = <64>; 184 d-cache-sets = <256>; 185 next-level-cache = <&l2_cache_b0>; 186 dynamic-power-coefficient = <416>; 187 #cooling-cells = <2>; 188 }; 189 190 cpu_b1: cpu@500 { 191 device_type = "cpu"; 192 compatible = "arm,cortex-a76"; 193 reg = <0x500>; 194 enable-method = "psci"; 195 capacity-dmips-mhz = <1024>; 196 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 197 cpu-idle-states = <&CPU_SLEEP>; 198 i-cache-size = <65536>; 199 i-cache-line-size = <64>; 200 i-cache-sets = <256>; 201 d-cache-size = <65536>; 202 d-cache-line-size = <64>; 203 d-cache-sets = <256>; 204 next-level-cache = <&l2_cache_b1>; 205 dynamic-power-coefficient = <416>; 206 #cooling-cells = <2>; 207 }; 208 209 cpu_b2: cpu@600 { 210 device_type = "cpu"; 211 compatible = "arm,cortex-a76"; 212 reg = <0x600>; 213 enable-method = "psci"; 214 capacity-dmips-mhz = <1024>; 215 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 216 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; 217 assigned-clock-rates = <816000000>; 218 cpu-idle-states = <&CPU_SLEEP>; 219 i-cache-size = <65536>; 220 i-cache-line-size = <64>; 221 i-cache-sets = <256>; 222 d-cache-size = <65536>; 223 d-cache-line-size = <64>; 224 d-cache-sets = <256>; 225 next-level-cache = <&l2_cache_b2>; 226 dynamic-power-coefficient = <416>; 227 #cooling-cells = <2>; 228 }; 229 230 cpu_b3: cpu@700 { 231 device_type = "cpu"; 232 compatible = "arm,cortex-a76"; 233 reg = <0x700>; 234 enable-method = "psci"; 235 capacity-dmips-mhz = <1024>; 236 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 237 cpu-idle-states = <&CPU_SLEEP>; 238 i-cache-size = <65536>; 239 i-cache-line-size = <64>; 240 i-cache-sets = <256>; 241 d-cache-size = <65536>; 242 d-cache-line-size = <64>; 243 d-cache-sets = <256>; 244 next-level-cache = <&l2_cache_b3>; 245 dynamic-power-coefficient = <416>; 246 #cooling-cells = <2>; 247 }; 248 249 idle-states { 250 entry-method = "psci"; 251 CPU_SLEEP: cpu-sleep { 252 compatible = "arm,idle-state"; 253 local-timer-stop; 254 arm,psci-suspend-param = <0x0010000>; 255 entry-latency-us = <100>; 256 exit-latency-us = <120>; 257 min-residency-us = <1000>; 258 }; 259 }; 260 261 l2_cache_l0: l2-cache-l0 { 262 compatible = "cache"; 263 cache-size = <131072>; 264 cache-line-size = <64>; 265 cache-sets = <512>; 266 cache-level = <2>; 267 cache-unified; 268 next-level-cache = <&l3_cache>; 269 }; 270 271 l2_cache_l1: l2-cache-l1 { 272 compatible = "cache"; 273 cache-size = <131072>; 274 cache-line-size = <64>; 275 cache-sets = <512>; 276 cache-level = <2>; 277 cache-unified; 278 next-level-cache = <&l3_cache>; 279 }; 280 281 l2_cache_l2: l2-cache-l2 { 282 compatible = "cache"; 283 cache-size = <131072>; 284 cache-line-size = <64>; 285 cache-sets = <512>; 286 cache-level = <2>; 287 cache-unified; 288 next-level-cache = <&l3_cache>; 289 }; 290 291 l2_cache_l3: l2-cache-l3 { 292 compatible = "cache"; 293 cache-size = <131072>; 294 cache-line-size = <64>; 295 cache-sets = <512>; 296 cache-level = <2>; 297 cache-unified; 298 next-level-cache = <&l3_cache>; 299 }; 300 301 l2_cache_b0: l2-cache-b0 { 302 compatible = "cache"; 303 cache-size = <524288>; 304 cache-line-size = <64>; 305 cache-sets = <1024>; 306 cache-level = <2>; 307 cache-unified; 308 next-level-cache = <&l3_cache>; 309 }; 310 311 l2_cache_b1: l2-cache-b1 { 312 compatible = "cache"; 313 cache-size = <524288>; 314 cache-line-size = <64>; 315 cache-sets = <1024>; 316 cache-level = <2>; 317 cache-unified; 318 next-level-cache = <&l3_cache>; 319 }; 320 321 l2_cache_b2: l2-cache-b2 { 322 compatible = "cache"; 323 cache-size = <524288>; 324 cache-line-size = <64>; 325 cache-sets = <1024>; 326 cache-level = <2>; 327 cache-unified; 328 next-level-cache = <&l3_cache>; 329 }; 330 331 l2_cache_b3: l2-cache-b3 { 332 compatible = "cache"; 333 cache-size = <524288>; 334 cache-line-size = <64>; 335 cache-sets = <1024>; 336 cache-level = <2>; 337 cache-unified; 338 next-level-cache = <&l3_cache>; 339 }; 340 341 l3_cache: l3-cache { 342 compatible = "cache"; 343 cache-size = <3145728>; 344 cache-line-size = <64>; 345 cache-sets = <4096>; 346 cache-level = <3>; 347 cache-unified; 348 }; 349 }; 350 351 display_subsystem: display-subsystem { 352 compatible = "rockchip,display-subsystem"; 353 ports = <&vop_out>; 354 }; 355 356 firmware { 357 optee: optee { 358 compatible = "linaro,optee-tz"; 359 method = "smc"; 360 }; 361 362 scmi: scmi { 363 compatible = "arm,scmi-smc"; 364 arm,smc-id = <0x82000010>; 365 shmem = <&scmi_shmem>; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 369 scmi_clk: protocol@14 { 370 reg = <0x14>; 371 #clock-cells = <1>; 372 }; 373 374 scmi_reset: protocol@16 { 375 reg = <0x16>; 376 #reset-cells = <1>; 377 }; 378 }; 379 }; 380 381 pmu-a55 { 382 compatible = "arm,cortex-a55-pmu"; 383 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; 384 }; 385 386 pmu-a76 { 387 compatible = "arm,cortex-a76-pmu"; 388 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; 389 }; 390 391 psci { 392 compatible = "arm,psci-1.0"; 393 method = "smc"; 394 }; 395 396 spll: clock-0 { 397 compatible = "fixed-clock"; 398 clock-frequency = <702000000>; 399 clock-output-names = "spll"; 400 #clock-cells = <0>; 401 }; 402 403 timer { 404 compatible = "arm,armv8-timer"; 405 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 406 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 407 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 408 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, 409 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 410 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 411 }; 412 413 xin24m: clock-1 { 414 compatible = "fixed-clock"; 415 clock-frequency = <24000000>; 416 clock-output-names = "xin24m"; 417 #clock-cells = <0>; 418 }; 419 420 xin32k: clock-2 { 421 compatible = "fixed-clock"; 422 clock-frequency = <32768>; 423 clock-output-names = "xin32k"; 424 #clock-cells = <0>; 425 }; 426 427 pmu_sram: sram@10f000 { 428 compatible = "mmio-sram"; 429 reg = <0x0 0x0010f000 0x0 0x100>; 430 ranges = <0 0x0 0x0010f000 0x100>; 431 #address-cells = <1>; 432 #size-cells = <1>; 433 434 scmi_shmem: sram@0 { 435 compatible = "arm,scmi-shmem"; 436 reg = <0x0 0x100>; 437 }; 438 }; 439 440 gpu: gpu@fb000000 { 441 compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; 442 reg = <0x0 0xfb000000 0x0 0x200000>; 443 #cooling-cells = <2>; 444 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 445 assigned-clock-rates = <200000000>; 446 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, 447 <&cru CLK_GPU_STACKS>; 448 clock-names = "core", "coregroup", "stacks"; 449 dynamic-power-coefficient = <2982>; 450 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, 451 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, 452 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>; 453 interrupt-names = "job", "mmu", "gpu"; 454 power-domains = <&power RK3588_PD_GPU>; 455 status = "disabled"; 456 }; 457 458 usb_host0_xhci: usb@fc000000 { 459 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 460 reg = <0x0 0xfc000000 0x0 0x400000>; 461 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 462 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, 463 <&cru ACLK_USB3OTG0>; 464 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 465 dr_mode = "otg"; 466 phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; 467 phy-names = "usb2-phy", "usb3-phy"; 468 phy_type = "utmi_wide"; 469 power-domains = <&power RK3588_PD_USB>; 470 resets = <&cru SRST_A_USB3OTG0>; 471 snps,dis_enblslpm_quirk; 472 snps,dis-u1-entry-quirk; 473 snps,dis-u2-entry-quirk; 474 snps,dis-u2-freeclk-exists-quirk; 475 snps,dis-del-phy-power-chg-quirk; 476 snps,dis-tx-ipgap-linecheck-quirk; 477 status = "disabled"; 478 }; 479 480 usb_host0_ehci: usb@fc800000 { 481 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 482 reg = <0x0 0xfc800000 0x0 0x40000>; 483 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; 484 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 485 phys = <&u2phy2_host>; 486 phy-names = "usb"; 487 power-domains = <&power RK3588_PD_USB>; 488 status = "disabled"; 489 }; 490 491 usb_host0_ohci: usb@fc840000 { 492 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 493 reg = <0x0 0xfc840000 0x0 0x40000>; 494 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; 495 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 496 phys = <&u2phy2_host>; 497 phy-names = "usb"; 498 power-domains = <&power RK3588_PD_USB>; 499 status = "disabled"; 500 }; 501 502 usb_host1_ehci: usb@fc880000 { 503 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 504 reg = <0x0 0xfc880000 0x0 0x40000>; 505 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; 506 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 507 phys = <&u2phy3_host>; 508 phy-names = "usb"; 509 power-domains = <&power RK3588_PD_USB>; 510 status = "disabled"; 511 }; 512 513 usb_host1_ohci: usb@fc8c0000 { 514 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 515 reg = <0x0 0xfc8c0000 0x0 0x40000>; 516 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; 517 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 518 phys = <&u2phy3_host>; 519 phy-names = "usb"; 520 power-domains = <&power RK3588_PD_USB>; 521 status = "disabled"; 522 }; 523 524 usb_host2_xhci: usb@fcd00000 { 525 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 526 reg = <0x0 0xfcd00000 0x0 0x400000>; 527 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; 528 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, 529 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, 530 <&cru CLK_PIPEPHY2_PIPE_U3_G>; 531 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; 532 dr_mode = "host"; 533 phys = <&combphy2_psu PHY_TYPE_USB3>; 534 phy-names = "usb3-phy"; 535 phy_type = "utmi_wide"; 536 resets = <&cru SRST_A_USB3OTG2>; 537 snps,dis_enblslpm_quirk; 538 snps,dis-u2-freeclk-exists-quirk; 539 snps,dis-del-phy-power-chg-quirk; 540 snps,dis-tx-ipgap-linecheck-quirk; 541 snps,dis_rxdet_inp3_quirk; 542 status = "disabled"; 543 }; 544 545 mmu600_pcie: iommu@fc900000 { 546 compatible = "arm,smmu-v3"; 547 reg = <0x0 0xfc900000 0x0 0x200000>; 548 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>, 549 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>, 550 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, 551 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>; 552 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 553 #iommu-cells = <1>; 554 status = "disabled"; 555 }; 556 557 mmu600_php: iommu@fcb00000 { 558 compatible = "arm,smmu-v3"; 559 reg = <0x0 0xfcb00000 0x0 0x200000>; 560 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>, 561 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, 562 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>, 563 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; 564 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 565 #iommu-cells = <1>; 566 status = "disabled"; 567 }; 568 569 pmu1grf: syscon@fd58a000 { 570 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; 571 reg = <0x0 0xfd58a000 0x0 0x10000>; 572 }; 573 574 sys_grf: syscon@fd58c000 { 575 compatible = "rockchip,rk3588-sys-grf", "syscon"; 576 reg = <0x0 0xfd58c000 0x0 0x1000>; 577 }; 578 579 vop_grf: syscon@fd5a4000 { 580 compatible = "rockchip,rk3588-vop-grf", "syscon"; 581 reg = <0x0 0xfd5a4000 0x0 0x2000>; 582 }; 583 584 vo0_grf: syscon@fd5a6000 { 585 compatible = "rockchip,rk3588-vo0-grf", "syscon"; 586 reg = <0x0 0xfd5a6000 0x0 0x2000>; 587 clocks = <&cru PCLK_VO0GRF>; 588 }; 589 590 vo1_grf: syscon@fd5a8000 { 591 compatible = "rockchip,rk3588-vo1-grf", "syscon"; 592 reg = <0x0 0xfd5a8000 0x0 0x4000>; 593 clocks = <&cru PCLK_VO1GRF>; 594 }; 595 596 usb_grf: syscon@fd5ac000 { 597 compatible = "rockchip,rk3588-usb-grf", "syscon"; 598 reg = <0x0 0xfd5ac000 0x0 0x4000>; 599 }; 600 601 php_grf: syscon@fd5b0000 { 602 compatible = "rockchip,rk3588-php-grf", "syscon"; 603 reg = <0x0 0xfd5b0000 0x0 0x1000>; 604 }; 605 606 pipe_phy0_grf: syscon@fd5bc000 { 607 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 608 reg = <0x0 0xfd5bc000 0x0 0x100>; 609 }; 610 611 pipe_phy2_grf: syscon@fd5c4000 { 612 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 613 reg = <0x0 0xfd5c4000 0x0 0x100>; 614 }; 615 616 usbdpphy0_grf: syscon@fd5c8000 { 617 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 618 reg = <0x0 0xfd5c8000 0x0 0x4000>; 619 }; 620 621 usb2phy0_grf: syscon@fd5d0000 { 622 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 623 reg = <0x0 0xfd5d0000 0x0 0x4000>; 624 #address-cells = <1>; 625 #size-cells = <1>; 626 627 u2phy0: usb2phy@0 { 628 compatible = "rockchip,rk3588-usb2phy"; 629 reg = <0x0 0x10>; 630 #clock-cells = <0>; 631 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 632 clock-names = "phyclk"; 633 clock-output-names = "usb480m_phy0"; 634 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; 635 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; 636 reset-names = "phy", "apb"; 637 status = "disabled"; 638 639 u2phy0_otg: otg-port { 640 #phy-cells = <0>; 641 status = "disabled"; 642 }; 643 }; 644 }; 645 646 usb2phy2_grf: syscon@fd5d8000 { 647 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 648 reg = <0x0 0xfd5d8000 0x0 0x4000>; 649 #address-cells = <1>; 650 #size-cells = <1>; 651 652 u2phy2: usb2phy@8000 { 653 compatible = "rockchip,rk3588-usb2phy"; 654 reg = <0x8000 0x10>; 655 #clock-cells = <0>; 656 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 657 clock-names = "phyclk"; 658 clock-output-names = "usb480m_phy2"; 659 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 660 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 661 reset-names = "phy", "apb"; 662 status = "disabled"; 663 664 u2phy2_host: host-port { 665 #phy-cells = <0>; 666 status = "disabled"; 667 }; 668 }; 669 }; 670 671 usb2phy3_grf: syscon@fd5dc000 { 672 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 673 reg = <0x0 0xfd5dc000 0x0 0x4000>; 674 #address-cells = <1>; 675 #size-cells = <1>; 676 677 u2phy3: usb2phy@c000 { 678 compatible = "rockchip,rk3588-usb2phy"; 679 reg = <0xc000 0x10>; 680 #clock-cells = <0>; 681 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 682 clock-names = "phyclk"; 683 clock-output-names = "usb480m_phy3"; 684 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 685 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 686 reset-names = "phy", "apb"; 687 status = "disabled"; 688 689 u2phy3_host: host-port { 690 #phy-cells = <0>; 691 status = "disabled"; 692 }; 693 }; 694 }; 695 696 hdptxphy0_grf: syscon@fd5e0000 { 697 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 698 reg = <0x0 0xfd5e0000 0x0 0x100>; 699 }; 700 701 ioc: syscon@fd5f0000 { 702 compatible = "rockchip,rk3588-ioc", "syscon"; 703 reg = <0x0 0xfd5f0000 0x0 0x10000>; 704 }; 705 706 system_sram1: sram@fd600000 { 707 compatible = "mmio-sram"; 708 reg = <0x0 0xfd600000 0x0 0x100000>; 709 ranges = <0x0 0x0 0xfd600000 0x100000>; 710 #address-cells = <1>; 711 #size-cells = <1>; 712 }; 713 714 cru: clock-controller@fd7c0000 { 715 compatible = "rockchip,rk3588-cru"; 716 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 717 assigned-clocks = 718 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 719 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 720 <&cru ACLK_CENTER_ROOT>, 721 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 722 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 723 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 724 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, 725 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 726 <&cru CLK_GPU>; 727 assigned-clock-rates = 728 <1100000000>, <786432000>, 729 <850000000>, <1188000000>, 730 <702000000>, 731 <400000000>, <500000000>, 732 <800000000>, <100000000>, 733 <400000000>, <100000000>, 734 <200000000>, <500000000>, 735 <375000000>, <150000000>, 736 <200000000>; 737 rockchip,grf = <&php_grf>; 738 #clock-cells = <1>; 739 #reset-cells = <1>; 740 }; 741 742 i2c0: i2c@fd880000 { 743 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 744 reg = <0x0 0xfd880000 0x0 0x1000>; 745 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; 746 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 747 clock-names = "i2c", "pclk"; 748 pinctrl-0 = <&i2c0m0_xfer>; 749 pinctrl-names = "default"; 750 #address-cells = <1>; 751 #size-cells = <0>; 752 status = "disabled"; 753 }; 754 755 uart0: serial@fd890000 { 756 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 757 reg = <0x0 0xfd890000 0x0 0x100>; 758 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 759 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 760 clock-names = "baudclk", "apb_pclk"; 761 dmas = <&dmac0 6>, <&dmac0 7>; 762 dma-names = "tx", "rx"; 763 pinctrl-0 = <&uart0m1_xfer>; 764 pinctrl-names = "default"; 765 reg-shift = <2>; 766 reg-io-width = <4>; 767 status = "disabled"; 768 }; 769 770 pwm0: pwm@fd8b0000 { 771 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 772 reg = <0x0 0xfd8b0000 0x0 0x10>; 773 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 774 clock-names = "pwm", "pclk"; 775 pinctrl-0 = <&pwm0m0_pins>; 776 pinctrl-names = "default"; 777 #pwm-cells = <3>; 778 status = "disabled"; 779 }; 780 781 pwm1: pwm@fd8b0010 { 782 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 783 reg = <0x0 0xfd8b0010 0x0 0x10>; 784 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 785 clock-names = "pwm", "pclk"; 786 pinctrl-0 = <&pwm1m0_pins>; 787 pinctrl-names = "default"; 788 #pwm-cells = <3>; 789 status = "disabled"; 790 }; 791 792 pwm2: pwm@fd8b0020 { 793 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 794 reg = <0x0 0xfd8b0020 0x0 0x10>; 795 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 796 clock-names = "pwm", "pclk"; 797 pinctrl-0 = <&pwm2m0_pins>; 798 pinctrl-names = "default"; 799 #pwm-cells = <3>; 800 status = "disabled"; 801 }; 802 803 pwm3: pwm@fd8b0030 { 804 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 805 reg = <0x0 0xfd8b0030 0x0 0x10>; 806 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 807 clock-names = "pwm", "pclk"; 808 pinctrl-0 = <&pwm3m0_pins>; 809 pinctrl-names = "default"; 810 #pwm-cells = <3>; 811 status = "disabled"; 812 }; 813 814 pmu: power-management@fd8d8000 { 815 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 816 reg = <0x0 0xfd8d8000 0x0 0x400>; 817 818 power: power-controller { 819 compatible = "rockchip,rk3588-power-controller"; 820 #address-cells = <1>; 821 #power-domain-cells = <1>; 822 #size-cells = <0>; 823 status = "okay"; 824 825 /* These power domains are grouped by VD_NPU */ 826 power-domain@RK3588_PD_NPU { 827 reg = <RK3588_PD_NPU>; 828 #power-domain-cells = <0>; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 832 power-domain@RK3588_PD_NPUTOP { 833 reg = <RK3588_PD_NPUTOP>; 834 clocks = <&cru HCLK_NPU_ROOT>, 835 <&cru PCLK_NPU_ROOT>, 836 <&cru CLK_NPU_DSU0>, 837 <&cru HCLK_NPU_CM0_ROOT>; 838 pm_qos = <&qos_npu0_mwr>, 839 <&qos_npu0_mro>, 840 <&qos_mcu_npu>; 841 #power-domain-cells = <0>; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 845 power-domain@RK3588_PD_NPU1 { 846 reg = <RK3588_PD_NPU1>; 847 clocks = <&cru HCLK_NPU_ROOT>, 848 <&cru PCLK_NPU_ROOT>, 849 <&cru CLK_NPU_DSU0>; 850 pm_qos = <&qos_npu1>; 851 #power-domain-cells = <0>; 852 }; 853 power-domain@RK3588_PD_NPU2 { 854 reg = <RK3588_PD_NPU2>; 855 clocks = <&cru HCLK_NPU_ROOT>, 856 <&cru PCLK_NPU_ROOT>, 857 <&cru CLK_NPU_DSU0>; 858 pm_qos = <&qos_npu2>; 859 #power-domain-cells = <0>; 860 }; 861 }; 862 }; 863 /* These power domains are grouped by VD_GPU */ 864 power-domain@RK3588_PD_GPU { 865 reg = <RK3588_PD_GPU>; 866 clocks = <&cru CLK_GPU>, 867 <&cru CLK_GPU_COREGROUP>, 868 <&cru CLK_GPU_STACKS>; 869 pm_qos = <&qos_gpu_m0>, 870 <&qos_gpu_m1>, 871 <&qos_gpu_m2>, 872 <&qos_gpu_m3>; 873 #power-domain-cells = <0>; 874 }; 875 /* These power domains are grouped by VD_VCODEC */ 876 power-domain@RK3588_PD_VCODEC { 877 reg = <RK3588_PD_VCODEC>; 878 #address-cells = <1>; 879 #size-cells = <0>; 880 #power-domain-cells = <0>; 881 882 power-domain@RK3588_PD_RKVDEC0 { 883 reg = <RK3588_PD_RKVDEC0>; 884 clocks = <&cru HCLK_RKVDEC0>, 885 <&cru HCLK_VDPU_ROOT>, 886 <&cru ACLK_VDPU_ROOT>, 887 <&cru ACLK_RKVDEC0>, 888 <&cru ACLK_RKVDEC_CCU>; 889 pm_qos = <&qos_rkvdec0>; 890 #power-domain-cells = <0>; 891 }; 892 power-domain@RK3588_PD_RKVDEC1 { 893 reg = <RK3588_PD_RKVDEC1>; 894 clocks = <&cru HCLK_RKVDEC1>, 895 <&cru HCLK_VDPU_ROOT>, 896 <&cru ACLK_VDPU_ROOT>, 897 <&cru ACLK_RKVDEC1>; 898 pm_qos = <&qos_rkvdec1>; 899 #power-domain-cells = <0>; 900 }; 901 power-domain@RK3588_PD_VENC0 { 902 reg = <RK3588_PD_VENC0>; 903 clocks = <&cru HCLK_RKVENC0>, 904 <&cru ACLK_RKVENC0>; 905 pm_qos = <&qos_rkvenc0_m0ro>, 906 <&qos_rkvenc0_m1ro>, 907 <&qos_rkvenc0_m2wo>; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 #power-domain-cells = <0>; 911 912 power-domain@RK3588_PD_VENC1 { 913 reg = <RK3588_PD_VENC1>; 914 clocks = <&cru HCLK_RKVENC1>, 915 <&cru HCLK_RKVENC0>, 916 <&cru ACLK_RKVENC0>, 917 <&cru ACLK_RKVENC1>; 918 pm_qos = <&qos_rkvenc1_m0ro>, 919 <&qos_rkvenc1_m1ro>, 920 <&qos_rkvenc1_m2wo>; 921 #power-domain-cells = <0>; 922 }; 923 }; 924 }; 925 /* These power domains are grouped by VD_LOGIC */ 926 power-domain@RK3588_PD_VDPU { 927 reg = <RK3588_PD_VDPU>; 928 clocks = <&cru HCLK_VDPU_ROOT>, 929 <&cru ACLK_VDPU_LOW_ROOT>, 930 <&cru ACLK_VDPU_ROOT>, 931 <&cru ACLK_JPEG_DECODER_ROOT>, 932 <&cru ACLK_IEP2P0>, 933 <&cru HCLK_IEP2P0>, 934 <&cru ACLK_JPEG_ENCODER0>, 935 <&cru HCLK_JPEG_ENCODER0>, 936 <&cru ACLK_JPEG_ENCODER1>, 937 <&cru HCLK_JPEG_ENCODER1>, 938 <&cru ACLK_JPEG_ENCODER2>, 939 <&cru HCLK_JPEG_ENCODER2>, 940 <&cru ACLK_JPEG_ENCODER3>, 941 <&cru HCLK_JPEG_ENCODER3>, 942 <&cru ACLK_JPEG_DECODER>, 943 <&cru HCLK_JPEG_DECODER>, 944 <&cru ACLK_RGA2>, 945 <&cru HCLK_RGA2>; 946 pm_qos = <&qos_iep>, 947 <&qos_jpeg_dec>, 948 <&qos_jpeg_enc0>, 949 <&qos_jpeg_enc1>, 950 <&qos_jpeg_enc2>, 951 <&qos_jpeg_enc3>, 952 <&qos_rga2_mro>, 953 <&qos_rga2_mwo>; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 #power-domain-cells = <0>; 957 958 959 power-domain@RK3588_PD_AV1 { 960 reg = <RK3588_PD_AV1>; 961 clocks = <&cru PCLK_AV1>, 962 <&cru ACLK_AV1>, 963 <&cru HCLK_VDPU_ROOT>; 964 pm_qos = <&qos_av1>; 965 #power-domain-cells = <0>; 966 }; 967 power-domain@RK3588_PD_RKVDEC0 { 968 reg = <RK3588_PD_RKVDEC0>; 969 clocks = <&cru HCLK_RKVDEC0>, 970 <&cru HCLK_VDPU_ROOT>, 971 <&cru ACLK_VDPU_ROOT>, 972 <&cru ACLK_RKVDEC0>; 973 pm_qos = <&qos_rkvdec0>; 974 #power-domain-cells = <0>; 975 }; 976 power-domain@RK3588_PD_RKVDEC1 { 977 reg = <RK3588_PD_RKVDEC1>; 978 clocks = <&cru HCLK_RKVDEC1>, 979 <&cru HCLK_VDPU_ROOT>, 980 <&cru ACLK_VDPU_ROOT>; 981 pm_qos = <&qos_rkvdec1>; 982 #power-domain-cells = <0>; 983 }; 984 power-domain@RK3588_PD_RGA30 { 985 reg = <RK3588_PD_RGA30>; 986 clocks = <&cru ACLK_RGA3_0>, 987 <&cru HCLK_RGA3_0>; 988 pm_qos = <&qos_rga3_0>; 989 #power-domain-cells = <0>; 990 }; 991 }; 992 power-domain@RK3588_PD_VOP { 993 reg = <RK3588_PD_VOP>; 994 clocks = <&cru PCLK_VOP_ROOT>, 995 <&cru HCLK_VOP_ROOT>, 996 <&cru ACLK_VOP>; 997 pm_qos = <&qos_vop_m0>, 998 <&qos_vop_m1>; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 #power-domain-cells = <0>; 1002 1003 power-domain@RK3588_PD_VO0 { 1004 reg = <RK3588_PD_VO0>; 1005 clocks = <&cru PCLK_VO0_ROOT>, 1006 <&cru PCLK_VO0_S_ROOT>, 1007 <&cru HCLK_VO0_S_ROOT>, 1008 <&cru ACLK_VO0_ROOT>, 1009 <&cru HCLK_HDCP0>, 1010 <&cru ACLK_HDCP0>, 1011 <&cru HCLK_VOP_ROOT>; 1012 pm_qos = <&qos_hdcp0>; 1013 #power-domain-cells = <0>; 1014 }; 1015 }; 1016 power-domain@RK3588_PD_VO1 { 1017 reg = <RK3588_PD_VO1>; 1018 clocks = <&cru PCLK_VO1_ROOT>, 1019 <&cru PCLK_VO1_S_ROOT>, 1020 <&cru HCLK_VO1_S_ROOT>, 1021 <&cru HCLK_HDCP1>, 1022 <&cru ACLK_HDCP1>, 1023 <&cru ACLK_HDMIRX_ROOT>, 1024 <&cru HCLK_VO1USB_TOP_ROOT>; 1025 pm_qos = <&qos_hdcp1>, 1026 <&qos_hdmirx>; 1027 #power-domain-cells = <0>; 1028 }; 1029 power-domain@RK3588_PD_VI { 1030 reg = <RK3588_PD_VI>; 1031 clocks = <&cru HCLK_VI_ROOT>, 1032 <&cru PCLK_VI_ROOT>, 1033 <&cru HCLK_ISP0>, 1034 <&cru ACLK_ISP0>, 1035 <&cru HCLK_VICAP>, 1036 <&cru ACLK_VICAP>; 1037 pm_qos = <&qos_isp0_mro>, 1038 <&qos_isp0_mwo>, 1039 <&qos_vicap_m0>, 1040 <&qos_vicap_m1>; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 #power-domain-cells = <0>; 1044 1045 power-domain@RK3588_PD_ISP1 { 1046 reg = <RK3588_PD_ISP1>; 1047 clocks = <&cru HCLK_ISP1>, 1048 <&cru ACLK_ISP1>, 1049 <&cru HCLK_VI_ROOT>, 1050 <&cru PCLK_VI_ROOT>; 1051 pm_qos = <&qos_isp1_mwo>, 1052 <&qos_isp1_mro>; 1053 #power-domain-cells = <0>; 1054 }; 1055 power-domain@RK3588_PD_FEC { 1056 reg = <RK3588_PD_FEC>; 1057 clocks = <&cru HCLK_FISHEYE0>, 1058 <&cru ACLK_FISHEYE0>, 1059 <&cru HCLK_FISHEYE1>, 1060 <&cru ACLK_FISHEYE1>, 1061 <&cru PCLK_VI_ROOT>; 1062 pm_qos = <&qos_fisheye0>, 1063 <&qos_fisheye1>; 1064 #power-domain-cells = <0>; 1065 }; 1066 }; 1067 power-domain@RK3588_PD_RGA31 { 1068 reg = <RK3588_PD_RGA31>; 1069 clocks = <&cru HCLK_RGA3_1>, 1070 <&cru ACLK_RGA3_1>; 1071 pm_qos = <&qos_rga3_1>; 1072 #power-domain-cells = <0>; 1073 }; 1074 power-domain@RK3588_PD_USB { 1075 reg = <RK3588_PD_USB>; 1076 clocks = <&cru PCLK_PHP_ROOT>, 1077 <&cru ACLK_USB_ROOT>, 1078 <&cru ACLK_USB>, 1079 <&cru HCLK_USB_ROOT>, 1080 <&cru HCLK_HOST0>, 1081 <&cru HCLK_HOST_ARB0>, 1082 <&cru HCLK_HOST1>, 1083 <&cru HCLK_HOST_ARB1>; 1084 pm_qos = <&qos_usb3_0>, 1085 <&qos_usb3_1>, 1086 <&qos_usb2host_0>, 1087 <&qos_usb2host_1>; 1088 #power-domain-cells = <0>; 1089 }; 1090 power-domain@RK3588_PD_GMAC { 1091 reg = <RK3588_PD_GMAC>; 1092 clocks = <&cru PCLK_PHP_ROOT>, 1093 <&cru ACLK_PCIE_ROOT>, 1094 <&cru ACLK_PHP_ROOT>; 1095 #power-domain-cells = <0>; 1096 }; 1097 power-domain@RK3588_PD_PCIE { 1098 reg = <RK3588_PD_PCIE>; 1099 clocks = <&cru PCLK_PHP_ROOT>, 1100 <&cru ACLK_PCIE_ROOT>, 1101 <&cru ACLK_PHP_ROOT>; 1102 #power-domain-cells = <0>; 1103 }; 1104 power-domain@RK3588_PD_SDIO { 1105 reg = <RK3588_PD_SDIO>; 1106 clocks = <&cru HCLK_SDIO>, 1107 <&cru HCLK_NVM_ROOT>; 1108 pm_qos = <&qos_sdio>; 1109 #power-domain-cells = <0>; 1110 }; 1111 power-domain@RK3588_PD_AUDIO { 1112 reg = <RK3588_PD_AUDIO>; 1113 clocks = <&cru HCLK_AUDIO_ROOT>, 1114 <&cru PCLK_AUDIO_ROOT>; 1115 #power-domain-cells = <0>; 1116 }; 1117 power-domain@RK3588_PD_SDMMC { 1118 reg = <RK3588_PD_SDMMC>; 1119 pm_qos = <&qos_sdmmc>; 1120 #power-domain-cells = <0>; 1121 }; 1122 }; 1123 }; 1124 1125 vpu121: video-codec@fdb50000 { 1126 compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu"; 1127 reg = <0x0 0xfdb50000 0x0 0x800>; 1128 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1129 interrupt-names = "vdpu"; 1130 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1131 clock-names = "aclk", "hclk"; 1132 iommus = <&vpu121_mmu>; 1133 power-domains = <&power RK3588_PD_VDPU>; 1134 }; 1135 1136 vpu121_mmu: iommu@fdb50800 { 1137 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1138 reg = <0x0 0xfdb50800 0x0 0x40>; 1139 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1140 clock-names = "aclk", "iface"; 1141 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1142 power-domains = <&power RK3588_PD_VDPU>; 1143 #iommu-cells = <0>; 1144 }; 1145 1146 rga: rga@fdb80000 { 1147 compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga"; 1148 reg = <0x0 0xfdb80000 0x0 0x180>; 1149 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1150 clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>; 1151 clock-names = "aclk", "hclk", "sclk"; 1152 resets = <&cru SRST_RGA2_CORE>, <&cru SRST_A_RGA2>, <&cru SRST_H_RGA2>; 1153 reset-names = "core", "axi", "ahb"; 1154 power-domains = <&power RK3588_PD_VDPU>; 1155 }; 1156 1157 vepu121_0: video-codec@fdba0000 { 1158 compatible = "rockchip,rk3588-vepu121"; 1159 reg = <0x0 0xfdba0000 0x0 0x800>; 1160 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>; 1161 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 1162 clock-names = "aclk", "hclk"; 1163 iommus = <&vepu121_0_mmu>; 1164 power-domains = <&power RK3588_PD_VDPU>; 1165 }; 1166 1167 vepu121_0_mmu: iommu@fdba0800 { 1168 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1169 reg = <0x0 0xfdba0800 0x0 0x40>; 1170 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 1171 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 1172 clock-names = "aclk", "iface"; 1173 power-domains = <&power RK3588_PD_VDPU>; 1174 #iommu-cells = <0>; 1175 }; 1176 1177 vepu121_1: video-codec@fdba4000 { 1178 compatible = "rockchip,rk3588-vepu121"; 1179 reg = <0x0 0xfdba4000 0x0 0x800>; 1180 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>; 1181 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 1182 clock-names = "aclk", "hclk"; 1183 iommus = <&vepu121_1_mmu>; 1184 power-domains = <&power RK3588_PD_VDPU>; 1185 }; 1186 1187 vepu121_1_mmu: iommu@fdba4800 { 1188 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1189 reg = <0x0 0xfdba4800 0x0 0x40>; 1190 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>; 1191 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 1192 clock-names = "aclk", "iface"; 1193 power-domains = <&power RK3588_PD_VDPU>; 1194 #iommu-cells = <0>; 1195 }; 1196 1197 vepu121_2: video-codec@fdba8000 { 1198 compatible = "rockchip,rk3588-vepu121"; 1199 reg = <0x0 0xfdba8000 0x0 0x800>; 1200 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>; 1201 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 1202 clock-names = "aclk", "hclk"; 1203 iommus = <&vepu121_2_mmu>; 1204 power-domains = <&power RK3588_PD_VDPU>; 1205 }; 1206 1207 vepu121_2_mmu: iommu@fdba8800 { 1208 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1209 reg = <0x0 0xfdba8800 0x0 0x40>; 1210 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>; 1211 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 1212 clock-names = "aclk", "iface"; 1213 power-domains = <&power RK3588_PD_VDPU>; 1214 #iommu-cells = <0>; 1215 }; 1216 1217 vepu121_3: video-codec@fdbac000 { 1218 compatible = "rockchip,rk3588-vepu121"; 1219 reg = <0x0 0xfdbac000 0x0 0x800>; 1220 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; 1221 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 1222 clock-names = "aclk", "hclk"; 1223 iommus = <&vepu121_3_mmu>; 1224 power-domains = <&power RK3588_PD_VDPU>; 1225 }; 1226 1227 vepu121_3_mmu: iommu@fdbac800 { 1228 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1229 reg = <0x0 0xfdbac800 0x0 0x40>; 1230 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>; 1231 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 1232 clock-names = "aclk", "iface"; 1233 power-domains = <&power RK3588_PD_VDPU>; 1234 #iommu-cells = <0>; 1235 }; 1236 1237 av1d: video-codec@fdc70000 { 1238 compatible = "rockchip,rk3588-av1-vpu"; 1239 reg = <0x0 0xfdc70000 0x0 0x800>; 1240 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 1241 interrupt-names = "vdpu"; 1242 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1243 assigned-clock-rates = <400000000>, <400000000>; 1244 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1245 clock-names = "aclk", "hclk"; 1246 power-domains = <&power RK3588_PD_AV1>; 1247 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; 1248 }; 1249 1250 vop: vop@fdd90000 { 1251 compatible = "rockchip,rk3588-vop"; 1252 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; 1253 reg-names = "vop", "gamma-lut"; 1254 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1255 clocks = <&cru ACLK_VOP>, 1256 <&cru HCLK_VOP>, 1257 <&cru DCLK_VOP0>, 1258 <&cru DCLK_VOP1>, 1259 <&cru DCLK_VOP2>, 1260 <&cru DCLK_VOP3>, 1261 <&cru PCLK_VOP_ROOT>; 1262 clock-names = "aclk", 1263 "hclk", 1264 "dclk_vp0", 1265 "dclk_vp1", 1266 "dclk_vp2", 1267 "dclk_vp3", 1268 "pclk_vop"; 1269 iommus = <&vop_mmu>; 1270 power-domains = <&power RK3588_PD_VOP>; 1271 rockchip,grf = <&sys_grf>; 1272 rockchip,vop-grf = <&vop_grf>; 1273 rockchip,vo1-grf = <&vo1_grf>; 1274 rockchip,pmu = <&pmu>; 1275 status = "disabled"; 1276 1277 vop_out: ports { 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 1281 vp0: port@0 { 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 reg = <0>; 1285 }; 1286 1287 vp1: port@1 { 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 reg = <1>; 1291 }; 1292 1293 vp2: port@2 { 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 reg = <2>; 1297 }; 1298 1299 vp3: port@3 { 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 reg = <3>; 1303 }; 1304 }; 1305 }; 1306 1307 vop_mmu: iommu@fdd97e00 { 1308 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1309 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 1310 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1311 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1312 clock-names = "aclk", "iface"; 1313 #iommu-cells = <0>; 1314 power-domains = <&power RK3588_PD_VOP>; 1315 status = "disabled"; 1316 }; 1317 1318 i2s4_8ch: i2s@fddc0000 { 1319 compatible = "rockchip,rk3588-i2s-tdm"; 1320 reg = <0x0 0xfddc0000 0x0 0x1000>; 1321 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; 1322 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 1323 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1324 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 1325 assigned-clock-parents = <&cru PLL_AUPLL>; 1326 dmas = <&dmac2 0>; 1327 dma-names = "tx"; 1328 power-domains = <&power RK3588_PD_VO0>; 1329 resets = <&cru SRST_M_I2S4_8CH_TX>; 1330 reset-names = "tx-m"; 1331 #sound-dai-cells = <0>; 1332 status = "disabled"; 1333 }; 1334 1335 i2s5_8ch: i2s@fddf0000 { 1336 compatible = "rockchip,rk3588-i2s-tdm"; 1337 reg = <0x0 0xfddf0000 0x0 0x1000>; 1338 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; 1339 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 1340 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1341 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 1342 assigned-clock-parents = <&cru PLL_AUPLL>; 1343 dmas = <&dmac2 2>; 1344 dma-names = "tx"; 1345 power-domains = <&power RK3588_PD_VO1>; 1346 resets = <&cru SRST_M_I2S5_8CH_TX>; 1347 reset-names = "tx-m"; 1348 #sound-dai-cells = <0>; 1349 status = "disabled"; 1350 }; 1351 1352 i2s9_8ch: i2s@fddfc000 { 1353 compatible = "rockchip,rk3588-i2s-tdm"; 1354 reg = <0x0 0xfddfc000 0x0 0x1000>; 1355 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; 1356 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 1357 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1358 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 1359 assigned-clock-parents = <&cru PLL_AUPLL>; 1360 dmas = <&dmac2 23>; 1361 dma-names = "rx"; 1362 power-domains = <&power RK3588_PD_VO1>; 1363 resets = <&cru SRST_M_I2S9_8CH_RX>; 1364 reset-names = "rx-m"; 1365 #sound-dai-cells = <0>; 1366 status = "disabled"; 1367 }; 1368 1369 hdmi0: hdmi@fde80000 { 1370 compatible = "rockchip,rk3588-dw-hdmi-qp"; 1371 reg = <0x0 0xfde80000 0x0 0x20000>; 1372 clocks = <&cru PCLK_HDMITX0>, 1373 <&cru CLK_HDMITX0_EARC>, 1374 <&cru CLK_HDMITX0_REF>, 1375 <&cru MCLK_I2S5_8CH_TX>, 1376 <&cru CLK_HDMIHDP0>, 1377 <&cru HCLK_VO1>; 1378 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; 1379 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>, 1380 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>, 1381 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>, 1382 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>, 1383 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>; 1384 interrupt-names = "avp", "cec", "earc", "main", "hpd"; 1385 phys = <&hdptxphy_hdmi0>; 1386 pinctrl-names = "default"; 1387 pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd 1388 &hdmim0_tx0_scl &hdmim0_tx0_sda>; 1389 power-domains = <&power RK3588_PD_VO1>; 1390 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; 1391 reset-names = "ref", "hdp"; 1392 rockchip,grf = <&sys_grf>; 1393 rockchip,vo-grf = <&vo1_grf>; 1394 status = "disabled"; 1395 1396 ports { 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 1400 hdmi0_in: port@0 { 1401 reg = <0>; 1402 }; 1403 1404 hdmi0_out: port@1 { 1405 reg = <1>; 1406 }; 1407 }; 1408 }; 1409 1410 qos_gpu_m0: qos@fdf35000 { 1411 compatible = "rockchip,rk3588-qos", "syscon"; 1412 reg = <0x0 0xfdf35000 0x0 0x20>; 1413 }; 1414 1415 qos_gpu_m1: qos@fdf35200 { 1416 compatible = "rockchip,rk3588-qos", "syscon"; 1417 reg = <0x0 0xfdf35200 0x0 0x20>; 1418 }; 1419 1420 qos_gpu_m2: qos@fdf35400 { 1421 compatible = "rockchip,rk3588-qos", "syscon"; 1422 reg = <0x0 0xfdf35400 0x0 0x20>; 1423 }; 1424 1425 qos_gpu_m3: qos@fdf35600 { 1426 compatible = "rockchip,rk3588-qos", "syscon"; 1427 reg = <0x0 0xfdf35600 0x0 0x20>; 1428 }; 1429 1430 qos_rga3_1: qos@fdf36000 { 1431 compatible = "rockchip,rk3588-qos", "syscon"; 1432 reg = <0x0 0xfdf36000 0x0 0x20>; 1433 }; 1434 1435 qos_sdio: qos@fdf39000 { 1436 compatible = "rockchip,rk3588-qos", "syscon"; 1437 reg = <0x0 0xfdf39000 0x0 0x20>; 1438 }; 1439 1440 qos_sdmmc: qos@fdf3d800 { 1441 compatible = "rockchip,rk3588-qos", "syscon"; 1442 reg = <0x0 0xfdf3d800 0x0 0x20>; 1443 }; 1444 1445 qos_usb3_1: qos@fdf3e000 { 1446 compatible = "rockchip,rk3588-qos", "syscon"; 1447 reg = <0x0 0xfdf3e000 0x0 0x20>; 1448 }; 1449 1450 qos_usb3_0: qos@fdf3e200 { 1451 compatible = "rockchip,rk3588-qos", "syscon"; 1452 reg = <0x0 0xfdf3e200 0x0 0x20>; 1453 }; 1454 1455 qos_usb2host_0: qos@fdf3e400 { 1456 compatible = "rockchip,rk3588-qos", "syscon"; 1457 reg = <0x0 0xfdf3e400 0x0 0x20>; 1458 }; 1459 1460 qos_usb2host_1: qos@fdf3e600 { 1461 compatible = "rockchip,rk3588-qos", "syscon"; 1462 reg = <0x0 0xfdf3e600 0x0 0x20>; 1463 }; 1464 1465 qos_fisheye0: qos@fdf40000 { 1466 compatible = "rockchip,rk3588-qos", "syscon"; 1467 reg = <0x0 0xfdf40000 0x0 0x20>; 1468 }; 1469 1470 qos_fisheye1: qos@fdf40200 { 1471 compatible = "rockchip,rk3588-qos", "syscon"; 1472 reg = <0x0 0xfdf40200 0x0 0x20>; 1473 }; 1474 1475 qos_isp0_mro: qos@fdf40400 { 1476 compatible = "rockchip,rk3588-qos", "syscon"; 1477 reg = <0x0 0xfdf40400 0x0 0x20>; 1478 }; 1479 1480 qos_isp0_mwo: qos@fdf40500 { 1481 compatible = "rockchip,rk3588-qos", "syscon"; 1482 reg = <0x0 0xfdf40500 0x0 0x20>; 1483 }; 1484 1485 qos_vicap_m0: qos@fdf40600 { 1486 compatible = "rockchip,rk3588-qos", "syscon"; 1487 reg = <0x0 0xfdf40600 0x0 0x20>; 1488 }; 1489 1490 qos_vicap_m1: qos@fdf40800 { 1491 compatible = "rockchip,rk3588-qos", "syscon"; 1492 reg = <0x0 0xfdf40800 0x0 0x20>; 1493 }; 1494 1495 qos_isp1_mwo: qos@fdf41000 { 1496 compatible = "rockchip,rk3588-qos", "syscon"; 1497 reg = <0x0 0xfdf41000 0x0 0x20>; 1498 }; 1499 1500 qos_isp1_mro: qos@fdf41100 { 1501 compatible = "rockchip,rk3588-qos", "syscon"; 1502 reg = <0x0 0xfdf41100 0x0 0x20>; 1503 }; 1504 1505 qos_rkvenc0_m0ro: qos@fdf60000 { 1506 compatible = "rockchip,rk3588-qos", "syscon"; 1507 reg = <0x0 0xfdf60000 0x0 0x20>; 1508 }; 1509 1510 qos_rkvenc0_m1ro: qos@fdf60200 { 1511 compatible = "rockchip,rk3588-qos", "syscon"; 1512 reg = <0x0 0xfdf60200 0x0 0x20>; 1513 }; 1514 1515 qos_rkvenc0_m2wo: qos@fdf60400 { 1516 compatible = "rockchip,rk3588-qos", "syscon"; 1517 reg = <0x0 0xfdf60400 0x0 0x20>; 1518 }; 1519 1520 qos_rkvenc1_m0ro: qos@fdf61000 { 1521 compatible = "rockchip,rk3588-qos", "syscon"; 1522 reg = <0x0 0xfdf61000 0x0 0x20>; 1523 }; 1524 1525 qos_rkvenc1_m1ro: qos@fdf61200 { 1526 compatible = "rockchip,rk3588-qos", "syscon"; 1527 reg = <0x0 0xfdf61200 0x0 0x20>; 1528 }; 1529 1530 qos_rkvenc1_m2wo: qos@fdf61400 { 1531 compatible = "rockchip,rk3588-qos", "syscon"; 1532 reg = <0x0 0xfdf61400 0x0 0x20>; 1533 }; 1534 1535 qos_rkvdec0: qos@fdf62000 { 1536 compatible = "rockchip,rk3588-qos", "syscon"; 1537 reg = <0x0 0xfdf62000 0x0 0x20>; 1538 }; 1539 1540 qos_rkvdec1: qos@fdf63000 { 1541 compatible = "rockchip,rk3588-qos", "syscon"; 1542 reg = <0x0 0xfdf63000 0x0 0x20>; 1543 }; 1544 1545 qos_av1: qos@fdf64000 { 1546 compatible = "rockchip,rk3588-qos", "syscon"; 1547 reg = <0x0 0xfdf64000 0x0 0x20>; 1548 }; 1549 1550 qos_iep: qos@fdf66000 { 1551 compatible = "rockchip,rk3588-qos", "syscon"; 1552 reg = <0x0 0xfdf66000 0x0 0x20>; 1553 }; 1554 1555 qos_jpeg_dec: qos@fdf66200 { 1556 compatible = "rockchip,rk3588-qos", "syscon"; 1557 reg = <0x0 0xfdf66200 0x0 0x20>; 1558 }; 1559 1560 qos_jpeg_enc0: qos@fdf66400 { 1561 compatible = "rockchip,rk3588-qos", "syscon"; 1562 reg = <0x0 0xfdf66400 0x0 0x20>; 1563 }; 1564 1565 qos_jpeg_enc1: qos@fdf66600 { 1566 compatible = "rockchip,rk3588-qos", "syscon"; 1567 reg = <0x0 0xfdf66600 0x0 0x20>; 1568 }; 1569 1570 qos_jpeg_enc2: qos@fdf66800 { 1571 compatible = "rockchip,rk3588-qos", "syscon"; 1572 reg = <0x0 0xfdf66800 0x0 0x20>; 1573 }; 1574 1575 qos_jpeg_enc3: qos@fdf66a00 { 1576 compatible = "rockchip,rk3588-qos", "syscon"; 1577 reg = <0x0 0xfdf66a00 0x0 0x20>; 1578 }; 1579 1580 qos_rga2_mro: qos@fdf66c00 { 1581 compatible = "rockchip,rk3588-qos", "syscon"; 1582 reg = <0x0 0xfdf66c00 0x0 0x20>; 1583 }; 1584 1585 qos_rga2_mwo: qos@fdf66e00 { 1586 compatible = "rockchip,rk3588-qos", "syscon"; 1587 reg = <0x0 0xfdf66e00 0x0 0x20>; 1588 }; 1589 1590 qos_rga3_0: qos@fdf67000 { 1591 compatible = "rockchip,rk3588-qos", "syscon"; 1592 reg = <0x0 0xfdf67000 0x0 0x20>; 1593 }; 1594 1595 qos_vdpu: qos@fdf67200 { 1596 compatible = "rockchip,rk3588-qos", "syscon"; 1597 reg = <0x0 0xfdf67200 0x0 0x20>; 1598 }; 1599 1600 qos_npu1: qos@fdf70000 { 1601 compatible = "rockchip,rk3588-qos", "syscon"; 1602 reg = <0x0 0xfdf70000 0x0 0x20>; 1603 }; 1604 1605 qos_npu2: qos@fdf71000 { 1606 compatible = "rockchip,rk3588-qos", "syscon"; 1607 reg = <0x0 0xfdf71000 0x0 0x20>; 1608 }; 1609 1610 qos_npu0_mwr: qos@fdf72000 { 1611 compatible = "rockchip,rk3588-qos", "syscon"; 1612 reg = <0x0 0xfdf72000 0x0 0x20>; 1613 }; 1614 1615 qos_npu0_mro: qos@fdf72200 { 1616 compatible = "rockchip,rk3588-qos", "syscon"; 1617 reg = <0x0 0xfdf72200 0x0 0x20>; 1618 }; 1619 1620 qos_mcu_npu: qos@fdf72400 { 1621 compatible = "rockchip,rk3588-qos", "syscon"; 1622 reg = <0x0 0xfdf72400 0x0 0x20>; 1623 }; 1624 1625 qos_hdcp0: qos@fdf80000 { 1626 compatible = "rockchip,rk3588-qos", "syscon"; 1627 reg = <0x0 0xfdf80000 0x0 0x20>; 1628 }; 1629 1630 qos_hdcp1: qos@fdf81000 { 1631 compatible = "rockchip,rk3588-qos", "syscon"; 1632 reg = <0x0 0xfdf81000 0x0 0x20>; 1633 }; 1634 1635 qos_hdmirx: qos@fdf81200 { 1636 compatible = "rockchip,rk3588-qos", "syscon"; 1637 reg = <0x0 0xfdf81200 0x0 0x20>; 1638 }; 1639 1640 qos_vop_m0: qos@fdf82000 { 1641 compatible = "rockchip,rk3588-qos", "syscon"; 1642 reg = <0x0 0xfdf82000 0x0 0x20>; 1643 }; 1644 1645 qos_vop_m1: qos@fdf82200 { 1646 compatible = "rockchip,rk3588-qos", "syscon"; 1647 reg = <0x0 0xfdf82200 0x0 0x20>; 1648 }; 1649 1650 dfi: dfi@fe060000 { 1651 reg = <0x00 0xfe060000 0x00 0x10000>; 1652 compatible = "rockchip,rk3588-dfi"; 1653 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, 1654 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, 1655 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, 1656 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1657 rockchip,pmu = <&pmu1grf>; 1658 }; 1659 1660 pcie2x1l1: pcie@fe180000 { 1661 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1662 bus-range = <0x30 0x3f>; 1663 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 1664 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 1665 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; 1666 clock-names = "aclk_mst", "aclk_slv", 1667 "aclk_dbi", "pclk", 1668 "aux", "pipe"; 1669 device_type = "pci"; 1670 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, 1671 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, 1672 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, 1673 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, 1674 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; 1675 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1676 #interrupt-cells = <1>; 1677 interrupt-map-mask = <0 0 0 7>; 1678 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 1679 <0 0 0 2 &pcie2x1l1_intc 1>, 1680 <0 0 0 3 &pcie2x1l1_intc 2>, 1681 <0 0 0 4 &pcie2x1l1_intc 3>; 1682 linux,pci-domain = <3>; 1683 max-link-speed = <2>; 1684 msi-map = <0x3000 &its0 0x3000 0x1000>; 1685 num-lanes = <1>; 1686 phys = <&combphy2_psu PHY_TYPE_PCIE>; 1687 phy-names = "pcie-phy"; 1688 power-domains = <&power RK3588_PD_PCIE>; 1689 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, 1690 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, 1691 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; 1692 reg = <0xa 0x40c00000 0x0 0x00400000>, 1693 <0x0 0xfe180000 0x0 0x00010000>, 1694 <0x0 0xf3000000 0x0 0x00100000>; 1695 reg-names = "dbi", "apb", "config"; 1696 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; 1697 reset-names = "pwr", "pipe"; 1698 #address-cells = <3>; 1699 #size-cells = <2>; 1700 status = "disabled"; 1701 1702 pcie2x1l1_intc: legacy-interrupt-controller { 1703 interrupt-controller; 1704 #address-cells = <0>; 1705 #interrupt-cells = <1>; 1706 interrupt-parent = <&gic>; 1707 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; 1708 }; 1709 }; 1710 1711 pcie2x1l2: pcie@fe190000 { 1712 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1713 bus-range = <0x40 0x4f>; 1714 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 1715 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 1716 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; 1717 clock-names = "aclk_mst", "aclk_slv", 1718 "aclk_dbi", "pclk", 1719 "aux", "pipe"; 1720 device_type = "pci"; 1721 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, 1722 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, 1723 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, 1724 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, 1725 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; 1726 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1727 #interrupt-cells = <1>; 1728 interrupt-map-mask = <0 0 0 7>; 1729 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 1730 <0 0 0 2 &pcie2x1l2_intc 1>, 1731 <0 0 0 3 &pcie2x1l2_intc 2>, 1732 <0 0 0 4 &pcie2x1l2_intc 3>; 1733 linux,pci-domain = <4>; 1734 max-link-speed = <2>; 1735 msi-map = <0x4000 &its0 0x4000 0x1000>; 1736 num-lanes = <1>; 1737 phys = <&combphy0_ps PHY_TYPE_PCIE>; 1738 phy-names = "pcie-phy"; 1739 power-domains = <&power RK3588_PD_PCIE>; 1740 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 1741 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, 1742 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; 1743 reg = <0xa 0x41000000 0x0 0x00400000>, 1744 <0x0 0xfe190000 0x0 0x00010000>, 1745 <0x0 0xf4000000 0x0 0x00100000>; 1746 reg-names = "dbi", "apb", "config"; 1747 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; 1748 reset-names = "pwr", "pipe"; 1749 #address-cells = <3>; 1750 #size-cells = <2>; 1751 status = "disabled"; 1752 1753 pcie2x1l2_intc: legacy-interrupt-controller { 1754 interrupt-controller; 1755 #address-cells = <0>; 1756 #interrupt-cells = <1>; 1757 interrupt-parent = <&gic>; 1758 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; 1759 }; 1760 }; 1761 1762 gmac1: ethernet@fe1c0000 { 1763 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1764 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1765 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, 1766 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 1767 interrupt-names = "macirq", "eth_wake_irq"; 1768 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 1769 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1770 <&cru CLK_GMAC1_PTP_REF>; 1771 clock-names = "stmmaceth", "clk_mac_ref", 1772 "pclk_mac", "aclk_mac", 1773 "ptp_ref"; 1774 power-domains = <&power RK3588_PD_GMAC>; 1775 resets = <&cru SRST_A_GMAC1>; 1776 reset-names = "stmmaceth"; 1777 rockchip,grf = <&sys_grf>; 1778 rockchip,php-grf = <&php_grf>; 1779 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1780 snps,mixed-burst; 1781 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1782 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1783 snps,tso; 1784 status = "disabled"; 1785 1786 mdio1: mdio { 1787 compatible = "snps,dwmac-mdio"; 1788 #address-cells = <0x1>; 1789 #size-cells = <0x0>; 1790 }; 1791 1792 gmac1_stmmac_axi_setup: stmmac-axi-config { 1793 snps,blen = <0 0 0 0 16 8 4>; 1794 snps,wr_osr_lmt = <4>; 1795 snps,rd_osr_lmt = <8>; 1796 }; 1797 1798 gmac1_mtl_rx_setup: rx-queues-config { 1799 snps,rx-queues-to-use = <2>; 1800 queue0 {}; 1801 queue1 {}; 1802 }; 1803 1804 gmac1_mtl_tx_setup: tx-queues-config { 1805 snps,tx-queues-to-use = <2>; 1806 queue0 {}; 1807 queue1 {}; 1808 }; 1809 }; 1810 1811 sata0: sata@fe210000 { 1812 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1813 reg = <0 0xfe210000 0 0x1000>; 1814 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; 1815 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1816 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, 1817 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; 1818 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1819 ports-implemented = <0x1>; 1820 #address-cells = <1>; 1821 #size-cells = <0>; 1822 status = "disabled"; 1823 1824 sata-port@0 { 1825 reg = <0>; 1826 hba-port-cap = <HBA_PORT_FBSCP>; 1827 phys = <&combphy0_ps PHY_TYPE_SATA>; 1828 phy-names = "sata-phy"; 1829 snps,rx-ts-max = <32>; 1830 snps,tx-ts-max = <32>; 1831 }; 1832 }; 1833 1834 sata2: sata@fe230000 { 1835 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1836 reg = <0 0xfe230000 0 0x1000>; 1837 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; 1838 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 1839 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, 1840 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; 1841 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1842 ports-implemented = <0x1>; 1843 #address-cells = <1>; 1844 #size-cells = <0>; 1845 status = "disabled"; 1846 1847 sata-port@0 { 1848 reg = <0>; 1849 hba-port-cap = <HBA_PORT_FBSCP>; 1850 phys = <&combphy2_psu PHY_TYPE_SATA>; 1851 phy-names = "sata-phy"; 1852 snps,rx-ts-max = <32>; 1853 snps,tx-ts-max = <32>; 1854 }; 1855 }; 1856 1857 sfc: spi@fe2b0000 { 1858 compatible = "rockchip,sfc"; 1859 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1860 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; 1861 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1862 clock-names = "clk_sfc", "hclk_sfc"; 1863 #address-cells = <1>; 1864 #size-cells = <0>; 1865 status = "disabled"; 1866 }; 1867 1868 sdmmc: mmc@fe2c0000 { 1869 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1870 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1871 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 1872 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 1873 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1874 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1875 fifo-depth = <0x100>; 1876 max-frequency = <200000000>; 1877 pinctrl-names = "default"; 1878 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1879 power-domains = <&power RK3588_PD_SDMMC>; 1880 status = "disabled"; 1881 }; 1882 1883 sdio: mmc@fe2d0000 { 1884 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1885 reg = <0x00 0xfe2d0000 0x00 0x4000>; 1886 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; 1887 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 1888 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1889 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1890 fifo-depth = <0x100>; 1891 max-frequency = <200000000>; 1892 pinctrl-names = "default"; 1893 pinctrl-0 = <&sdiom1_pins>; 1894 power-domains = <&power RK3588_PD_SDIO>; 1895 status = "disabled"; 1896 }; 1897 1898 sdhci: mmc@fe2e0000 { 1899 compatible = "rockchip,rk3588-dwcmshc"; 1900 reg = <0x0 0xfe2e0000 0x0 0x10000>; 1901 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 1902 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 1903 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1904 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1905 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1906 <&cru TMCLK_EMMC>; 1907 clock-names = "core", "bus", "axi", "block", "timer"; 1908 max-frequency = <200000000>; 1909 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 1910 <&emmc_cmd>, <&emmc_data_strobe>; 1911 pinctrl-names = "default"; 1912 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1913 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1914 <&cru SRST_T_EMMC>; 1915 reset-names = "core", "bus", "axi", "block", "timer"; 1916 status = "disabled"; 1917 }; 1918 1919 i2s0_8ch: i2s@fe470000 { 1920 compatible = "rockchip,rk3588-i2s-tdm"; 1921 reg = <0x0 0xfe470000 0x0 0x1000>; 1922 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; 1923 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1924 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1925 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1926 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 1927 dmas = <&dmac0 0>, <&dmac0 1>; 1928 dma-names = "tx", "rx"; 1929 power-domains = <&power RK3588_PD_AUDIO>; 1930 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1931 reset-names = "tx-m", "rx-m"; 1932 rockchip,trcm-sync-tx-only; 1933 pinctrl-names = "default"; 1934 pinctrl-0 = <&i2s0_lrck 1935 &i2s0_sclk 1936 &i2s0_sdi0 1937 &i2s0_sdi1 1938 &i2s0_sdi2 1939 &i2s0_sdi3 1940 &i2s0_sdo0 1941 &i2s0_sdo1 1942 &i2s0_sdo2 1943 &i2s0_sdo3>; 1944 #sound-dai-cells = <0>; 1945 status = "disabled"; 1946 }; 1947 1948 i2s1_8ch: i2s@fe480000 { 1949 compatible = "rockchip,rk3588-i2s-tdm"; 1950 reg = <0x0 0xfe480000 0x0 0x1000>; 1951 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; 1952 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1953 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1954 dmas = <&dmac0 2>, <&dmac0 3>; 1955 dma-names = "tx", "rx"; 1956 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1957 reset-names = "tx-m", "rx-m"; 1958 rockchip,trcm-sync-tx-only; 1959 pinctrl-names = "default"; 1960 pinctrl-0 = <&i2s1m0_lrck 1961 &i2s1m0_sclk 1962 &i2s1m0_sdi0 1963 &i2s1m0_sdi1 1964 &i2s1m0_sdi2 1965 &i2s1m0_sdi3 1966 &i2s1m0_sdo0 1967 &i2s1m0_sdo1 1968 &i2s1m0_sdo2 1969 &i2s1m0_sdo3>; 1970 #sound-dai-cells = <0>; 1971 status = "disabled"; 1972 }; 1973 1974 i2s2_2ch: i2s@fe490000 { 1975 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1976 reg = <0x0 0xfe490000 0x0 0x1000>; 1977 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; 1978 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1979 clock-names = "i2s_clk", "i2s_hclk"; 1980 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1981 assigned-clock-parents = <&cru PLL_AUPLL>; 1982 dmas = <&dmac1 0>, <&dmac1 1>; 1983 dma-names = "tx", "rx"; 1984 power-domains = <&power RK3588_PD_AUDIO>; 1985 pinctrl-names = "default"; 1986 pinctrl-0 = <&i2s2m1_lrck 1987 &i2s2m1_sclk 1988 &i2s2m1_sdi 1989 &i2s2m1_sdo>; 1990 #sound-dai-cells = <0>; 1991 status = "disabled"; 1992 }; 1993 1994 i2s3_2ch: i2s@fe4a0000 { 1995 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1996 reg = <0x0 0xfe4a0000 0x0 0x1000>; 1997 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; 1998 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 1999 clock-names = "i2s_clk", "i2s_hclk"; 2000 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 2001 assigned-clock-parents = <&cru PLL_AUPLL>; 2002 dmas = <&dmac1 2>, <&dmac1 3>; 2003 dma-names = "tx", "rx"; 2004 power-domains = <&power RK3588_PD_AUDIO>; 2005 pinctrl-names = "default"; 2006 pinctrl-0 = <&i2s3_lrck 2007 &i2s3_sclk 2008 &i2s3_sdi 2009 &i2s3_sdo>; 2010 #sound-dai-cells = <0>; 2011 status = "disabled"; 2012 }; 2013 2014 gic: interrupt-controller@fe600000 { 2015 compatible = "arm,gic-v3"; 2016 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 2017 <0x0 0xfe680000 0 0x100000>; /* GICR */ 2018 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 2019 interrupt-controller; 2020 mbi-alias = <0x0 0xfe610000>; 2021 mbi-ranges = <424 56>; 2022 msi-controller; 2023 ranges; 2024 #address-cells = <2>; 2025 #interrupt-cells = <4>; 2026 #size-cells = <2>; 2027 2028 its0: msi-controller@fe640000 { 2029 compatible = "arm,gic-v3-its"; 2030 reg = <0x0 0xfe640000 0x0 0x20000>; 2031 msi-controller; 2032 #msi-cells = <1>; 2033 }; 2034 2035 its1: msi-controller@fe660000 { 2036 compatible = "arm,gic-v3-its"; 2037 reg = <0x0 0xfe660000 0x0 0x20000>; 2038 msi-controller; 2039 #msi-cells = <1>; 2040 }; 2041 2042 ppi-partitions { 2043 ppi_partition0: interrupt-partition-0 { 2044 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 2045 }; 2046 2047 ppi_partition1: interrupt-partition-1 { 2048 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; 2049 }; 2050 }; 2051 }; 2052 2053 dmac0: dma-controller@fea10000 { 2054 compatible = "arm,pl330", "arm,primecell"; 2055 reg = <0x0 0xfea10000 0x0 0x4000>; 2056 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, 2057 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; 2058 arm,pl330-periph-burst; 2059 clocks = <&cru ACLK_DMAC0>; 2060 clock-names = "apb_pclk"; 2061 #dma-cells = <1>; 2062 }; 2063 2064 dmac1: dma-controller@fea30000 { 2065 compatible = "arm,pl330", "arm,primecell"; 2066 reg = <0x0 0xfea30000 0x0 0x4000>; 2067 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, 2068 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; 2069 arm,pl330-periph-burst; 2070 clocks = <&cru ACLK_DMAC1>; 2071 clock-names = "apb_pclk"; 2072 #dma-cells = <1>; 2073 }; 2074 2075 i2c1: i2c@fea90000 { 2076 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2077 reg = <0x0 0xfea90000 0x0 0x1000>; 2078 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 2079 clock-names = "i2c", "pclk"; 2080 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; 2081 pinctrl-0 = <&i2c1m0_xfer>; 2082 pinctrl-names = "default"; 2083 #address-cells = <1>; 2084 #size-cells = <0>; 2085 status = "disabled"; 2086 }; 2087 2088 i2c2: i2c@feaa0000 { 2089 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2090 reg = <0x0 0xfeaa0000 0x0 0x1000>; 2091 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 2092 clock-names = "i2c", "pclk"; 2093 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; 2094 pinctrl-0 = <&i2c2m0_xfer>; 2095 pinctrl-names = "default"; 2096 #address-cells = <1>; 2097 #size-cells = <0>; 2098 status = "disabled"; 2099 }; 2100 2101 i2c3: i2c@feab0000 { 2102 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2103 reg = <0x0 0xfeab0000 0x0 0x1000>; 2104 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 2105 clock-names = "i2c", "pclk"; 2106 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; 2107 pinctrl-0 = <&i2c3m0_xfer>; 2108 pinctrl-names = "default"; 2109 #address-cells = <1>; 2110 #size-cells = <0>; 2111 status = "disabled"; 2112 }; 2113 2114 i2c4: i2c@feac0000 { 2115 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2116 reg = <0x0 0xfeac0000 0x0 0x1000>; 2117 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2118 clock-names = "i2c", "pclk"; 2119 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; 2120 pinctrl-0 = <&i2c4m0_xfer>; 2121 pinctrl-names = "default"; 2122 #address-cells = <1>; 2123 #size-cells = <0>; 2124 status = "disabled"; 2125 }; 2126 2127 i2c5: i2c@fead0000 { 2128 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2129 reg = <0x0 0xfead0000 0x0 0x1000>; 2130 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2131 clock-names = "i2c", "pclk"; 2132 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; 2133 pinctrl-0 = <&i2c5m0_xfer>; 2134 pinctrl-names = "default"; 2135 #address-cells = <1>; 2136 #size-cells = <0>; 2137 status = "disabled"; 2138 }; 2139 2140 timer0: timer@feae0000 { 2141 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 2142 reg = <0x0 0xfeae0000 0x0 0x20>; 2143 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; 2144 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 2145 clock-names = "pclk", "timer"; 2146 }; 2147 2148 wdt: watchdog@feaf0000 { 2149 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; 2150 reg = <0x0 0xfeaf0000 0x0 0x100>; 2151 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 2152 clock-names = "tclk", "pclk"; 2153 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; 2154 }; 2155 2156 spi0: spi@feb00000 { 2157 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2158 reg = <0x0 0xfeb00000 0x0 0x1000>; 2159 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; 2160 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 2161 clock-names = "spiclk", "apb_pclk"; 2162 dmas = <&dmac0 14>, <&dmac0 15>; 2163 dma-names = "tx", "rx"; 2164 num-cs = <2>; 2165 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 2166 pinctrl-names = "default"; 2167 #address-cells = <1>; 2168 #size-cells = <0>; 2169 status = "disabled"; 2170 }; 2171 2172 spi1: spi@feb10000 { 2173 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2174 reg = <0x0 0xfeb10000 0x0 0x1000>; 2175 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; 2176 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 2177 clock-names = "spiclk", "apb_pclk"; 2178 dmas = <&dmac0 16>, <&dmac0 17>; 2179 dma-names = "tx", "rx"; 2180 num-cs = <2>; 2181 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 2182 pinctrl-names = "default"; 2183 #address-cells = <1>; 2184 #size-cells = <0>; 2185 status = "disabled"; 2186 }; 2187 2188 spi2: spi@feb20000 { 2189 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2190 reg = <0x0 0xfeb20000 0x0 0x1000>; 2191 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; 2192 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 2193 clock-names = "spiclk", "apb_pclk"; 2194 dmas = <&dmac1 15>, <&dmac1 16>; 2195 dma-names = "tx", "rx"; 2196 num-cs = <2>; 2197 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 2198 pinctrl-names = "default"; 2199 #address-cells = <1>; 2200 #size-cells = <0>; 2201 status = "disabled"; 2202 }; 2203 2204 spi3: spi@feb30000 { 2205 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2206 reg = <0x0 0xfeb30000 0x0 0x1000>; 2207 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; 2208 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 2209 clock-names = "spiclk", "apb_pclk"; 2210 dmas = <&dmac1 17>, <&dmac1 18>; 2211 dma-names = "tx", "rx"; 2212 num-cs = <2>; 2213 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 2214 pinctrl-names = "default"; 2215 #address-cells = <1>; 2216 #size-cells = <0>; 2217 status = "disabled"; 2218 }; 2219 2220 uart1: serial@feb40000 { 2221 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2222 reg = <0x0 0xfeb40000 0x0 0x100>; 2223 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; 2224 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 2225 clock-names = "baudclk", "apb_pclk"; 2226 dmas = <&dmac0 8>, <&dmac0 9>; 2227 dma-names = "tx", "rx"; 2228 pinctrl-0 = <&uart1m1_xfer>; 2229 pinctrl-names = "default"; 2230 reg-io-width = <4>; 2231 reg-shift = <2>; 2232 status = "disabled"; 2233 }; 2234 2235 uart2: serial@feb50000 { 2236 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2237 reg = <0x0 0xfeb50000 0x0 0x100>; 2238 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; 2239 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 2240 clock-names = "baudclk", "apb_pclk"; 2241 dmas = <&dmac0 10>, <&dmac0 11>; 2242 dma-names = "tx", "rx"; 2243 pinctrl-0 = <&uart2m1_xfer>; 2244 pinctrl-names = "default"; 2245 reg-io-width = <4>; 2246 reg-shift = <2>; 2247 status = "disabled"; 2248 }; 2249 2250 uart3: serial@feb60000 { 2251 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2252 reg = <0x0 0xfeb60000 0x0 0x100>; 2253 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; 2254 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 2255 clock-names = "baudclk", "apb_pclk"; 2256 dmas = <&dmac0 12>, <&dmac0 13>; 2257 dma-names = "tx", "rx"; 2258 pinctrl-0 = <&uart3m1_xfer>; 2259 pinctrl-names = "default"; 2260 reg-io-width = <4>; 2261 reg-shift = <2>; 2262 status = "disabled"; 2263 }; 2264 2265 uart4: serial@feb70000 { 2266 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2267 reg = <0x0 0xfeb70000 0x0 0x100>; 2268 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; 2269 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 2270 clock-names = "baudclk", "apb_pclk"; 2271 dmas = <&dmac1 9>, <&dmac1 10>; 2272 dma-names = "tx", "rx"; 2273 pinctrl-0 = <&uart4m1_xfer>; 2274 pinctrl-names = "default"; 2275 reg-io-width = <4>; 2276 reg-shift = <2>; 2277 status = "disabled"; 2278 }; 2279 2280 uart5: serial@feb80000 { 2281 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2282 reg = <0x0 0xfeb80000 0x0 0x100>; 2283 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; 2284 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2285 clock-names = "baudclk", "apb_pclk"; 2286 dmas = <&dmac1 11>, <&dmac1 12>; 2287 dma-names = "tx", "rx"; 2288 pinctrl-0 = <&uart5m1_xfer>; 2289 pinctrl-names = "default"; 2290 reg-io-width = <4>; 2291 reg-shift = <2>; 2292 status = "disabled"; 2293 }; 2294 2295 uart6: serial@feb90000 { 2296 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2297 reg = <0x0 0xfeb90000 0x0 0x100>; 2298 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; 2299 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2300 clock-names = "baudclk", "apb_pclk"; 2301 dmas = <&dmac1 13>, <&dmac1 14>; 2302 dma-names = "tx", "rx"; 2303 pinctrl-0 = <&uart6m1_xfer>; 2304 pinctrl-names = "default"; 2305 reg-io-width = <4>; 2306 reg-shift = <2>; 2307 status = "disabled"; 2308 }; 2309 2310 uart7: serial@feba0000 { 2311 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2312 reg = <0x0 0xfeba0000 0x0 0x100>; 2313 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; 2314 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2315 clock-names = "baudclk", "apb_pclk"; 2316 dmas = <&dmac2 7>, <&dmac2 8>; 2317 dma-names = "tx", "rx"; 2318 pinctrl-0 = <&uart7m1_xfer>; 2319 pinctrl-names = "default"; 2320 reg-io-width = <4>; 2321 reg-shift = <2>; 2322 status = "disabled"; 2323 }; 2324 2325 uart8: serial@febb0000 { 2326 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2327 reg = <0x0 0xfebb0000 0x0 0x100>; 2328 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; 2329 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2330 clock-names = "baudclk", "apb_pclk"; 2331 dmas = <&dmac2 9>, <&dmac2 10>; 2332 dma-names = "tx", "rx"; 2333 pinctrl-0 = <&uart8m1_xfer>; 2334 pinctrl-names = "default"; 2335 reg-io-width = <4>; 2336 reg-shift = <2>; 2337 status = "disabled"; 2338 }; 2339 2340 uart9: serial@febc0000 { 2341 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2342 reg = <0x0 0xfebc0000 0x0 0x100>; 2343 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; 2344 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2345 clock-names = "baudclk", "apb_pclk"; 2346 dmas = <&dmac2 11>, <&dmac2 12>; 2347 dma-names = "tx", "rx"; 2348 pinctrl-0 = <&uart9m1_xfer>; 2349 pinctrl-names = "default"; 2350 reg-io-width = <4>; 2351 reg-shift = <2>; 2352 status = "disabled"; 2353 }; 2354 2355 pwm4: pwm@febd0000 { 2356 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2357 reg = <0x0 0xfebd0000 0x0 0x10>; 2358 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2359 clock-names = "pwm", "pclk"; 2360 pinctrl-0 = <&pwm4m0_pins>; 2361 pinctrl-names = "default"; 2362 #pwm-cells = <3>; 2363 status = "disabled"; 2364 }; 2365 2366 pwm5: pwm@febd0010 { 2367 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2368 reg = <0x0 0xfebd0010 0x0 0x10>; 2369 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2370 clock-names = "pwm", "pclk"; 2371 pinctrl-0 = <&pwm5m0_pins>; 2372 pinctrl-names = "default"; 2373 #pwm-cells = <3>; 2374 status = "disabled"; 2375 }; 2376 2377 pwm6: pwm@febd0020 { 2378 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2379 reg = <0x0 0xfebd0020 0x0 0x10>; 2380 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2381 clock-names = "pwm", "pclk"; 2382 pinctrl-0 = <&pwm6m0_pins>; 2383 pinctrl-names = "default"; 2384 #pwm-cells = <3>; 2385 status = "disabled"; 2386 }; 2387 2388 pwm7: pwm@febd0030 { 2389 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2390 reg = <0x0 0xfebd0030 0x0 0x10>; 2391 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2392 clock-names = "pwm", "pclk"; 2393 pinctrl-0 = <&pwm7m0_pins>; 2394 pinctrl-names = "default"; 2395 #pwm-cells = <3>; 2396 status = "disabled"; 2397 }; 2398 2399 pwm8: pwm@febe0000 { 2400 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2401 reg = <0x0 0xfebe0000 0x0 0x10>; 2402 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2403 clock-names = "pwm", "pclk"; 2404 pinctrl-0 = <&pwm8m0_pins>; 2405 pinctrl-names = "default"; 2406 #pwm-cells = <3>; 2407 status = "disabled"; 2408 }; 2409 2410 pwm9: pwm@febe0010 { 2411 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2412 reg = <0x0 0xfebe0010 0x0 0x10>; 2413 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2414 clock-names = "pwm", "pclk"; 2415 pinctrl-0 = <&pwm9m0_pins>; 2416 pinctrl-names = "default"; 2417 #pwm-cells = <3>; 2418 status = "disabled"; 2419 }; 2420 2421 pwm10: pwm@febe0020 { 2422 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2423 reg = <0x0 0xfebe0020 0x0 0x10>; 2424 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2425 clock-names = "pwm", "pclk"; 2426 pinctrl-0 = <&pwm10m0_pins>; 2427 pinctrl-names = "default"; 2428 #pwm-cells = <3>; 2429 status = "disabled"; 2430 }; 2431 2432 pwm11: pwm@febe0030 { 2433 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2434 reg = <0x0 0xfebe0030 0x0 0x10>; 2435 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2436 clock-names = "pwm", "pclk"; 2437 pinctrl-0 = <&pwm11m0_pins>; 2438 pinctrl-names = "default"; 2439 #pwm-cells = <3>; 2440 status = "disabled"; 2441 }; 2442 2443 pwm12: pwm@febf0000 { 2444 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2445 reg = <0x0 0xfebf0000 0x0 0x10>; 2446 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2447 clock-names = "pwm", "pclk"; 2448 pinctrl-0 = <&pwm12m0_pins>; 2449 pinctrl-names = "default"; 2450 #pwm-cells = <3>; 2451 status = "disabled"; 2452 }; 2453 2454 pwm13: pwm@febf0010 { 2455 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2456 reg = <0x0 0xfebf0010 0x0 0x10>; 2457 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2458 clock-names = "pwm", "pclk"; 2459 pinctrl-0 = <&pwm13m0_pins>; 2460 pinctrl-names = "default"; 2461 #pwm-cells = <3>; 2462 status = "disabled"; 2463 }; 2464 2465 pwm14: pwm@febf0020 { 2466 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2467 reg = <0x0 0xfebf0020 0x0 0x10>; 2468 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2469 clock-names = "pwm", "pclk"; 2470 pinctrl-0 = <&pwm14m0_pins>; 2471 pinctrl-names = "default"; 2472 #pwm-cells = <3>; 2473 status = "disabled"; 2474 }; 2475 2476 pwm15: pwm@febf0030 { 2477 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2478 reg = <0x0 0xfebf0030 0x0 0x10>; 2479 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2480 clock-names = "pwm", "pclk"; 2481 pinctrl-0 = <&pwm15m0_pins>; 2482 pinctrl-names = "default"; 2483 #pwm-cells = <3>; 2484 status = "disabled"; 2485 }; 2486 2487 thermal_zones: thermal-zones { 2488 /* sensor near the center of the SoC */ 2489 package_thermal: package-thermal { 2490 polling-delay-passive = <0>; 2491 polling-delay = <0>; 2492 thermal-sensors = <&tsadc 0>; 2493 2494 trips { 2495 package_crit: package-crit { 2496 temperature = <115000>; 2497 hysteresis = <0>; 2498 type = "critical"; 2499 }; 2500 }; 2501 }; 2502 2503 /* sensor between A76 cores 0 and 1 */ 2504 bigcore0_thermal: bigcore0-thermal { 2505 polling-delay-passive = <100>; 2506 polling-delay = <0>; 2507 thermal-sensors = <&tsadc 1>; 2508 2509 trips { 2510 bigcore0_alert: bigcore0-alert { 2511 temperature = <85000>; 2512 hysteresis = <2000>; 2513 type = "passive"; 2514 }; 2515 2516 bigcore0_crit: bigcore0-crit { 2517 temperature = <115000>; 2518 hysteresis = <0>; 2519 type = "critical"; 2520 }; 2521 }; 2522 2523 cooling-maps { 2524 map0 { 2525 trip = <&bigcore0_alert>; 2526 cooling-device = 2527 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2528 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2529 }; 2530 }; 2531 }; 2532 2533 /* sensor between A76 cores 2 and 3 */ 2534 bigcore2_thermal: bigcore2-thermal { 2535 polling-delay-passive = <100>; 2536 polling-delay = <0>; 2537 thermal-sensors = <&tsadc 2>; 2538 2539 trips { 2540 bigcore2_alert: bigcore2-alert { 2541 temperature = <85000>; 2542 hysteresis = <2000>; 2543 type = "passive"; 2544 }; 2545 2546 bigcore2_crit: bigcore2-crit { 2547 temperature = <115000>; 2548 hysteresis = <0>; 2549 type = "critical"; 2550 }; 2551 }; 2552 2553 cooling-maps { 2554 map0 { 2555 trip = <&bigcore2_alert>; 2556 cooling-device = 2557 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2558 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2559 }; 2560 }; 2561 }; 2562 2563 /* sensor between the four A55 cores */ 2564 little_core_thermal: littlecore-thermal { 2565 polling-delay-passive = <100>; 2566 polling-delay = <0>; 2567 thermal-sensors = <&tsadc 3>; 2568 2569 trips { 2570 littlecore_alert: littlecore-alert { 2571 temperature = <85000>; 2572 hysteresis = <2000>; 2573 type = "passive"; 2574 }; 2575 2576 littlecore_crit: littlecore-crit { 2577 temperature = <115000>; 2578 hysteresis = <0>; 2579 type = "critical"; 2580 }; 2581 }; 2582 2583 cooling-maps { 2584 map0 { 2585 trip = <&littlecore_alert>; 2586 cooling-device = 2587 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2588 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2589 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2590 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2591 }; 2592 }; 2593 }; 2594 2595 /* sensor near the PD_CENTER power domain */ 2596 center_thermal: center-thermal { 2597 polling-delay-passive = <0>; 2598 polling-delay = <0>; 2599 thermal-sensors = <&tsadc 4>; 2600 2601 trips { 2602 center_crit: center-crit { 2603 temperature = <115000>; 2604 hysteresis = <0>; 2605 type = "critical"; 2606 }; 2607 }; 2608 }; 2609 2610 gpu_thermal: gpu-thermal { 2611 polling-delay-passive = <100>; 2612 polling-delay = <0>; 2613 thermal-sensors = <&tsadc 5>; 2614 2615 trips { 2616 gpu_alert: gpu-alert { 2617 temperature = <85000>; 2618 hysteresis = <2000>; 2619 type = "passive"; 2620 }; 2621 2622 gpu_crit: gpu-crit { 2623 temperature = <115000>; 2624 hysteresis = <0>; 2625 type = "critical"; 2626 }; 2627 }; 2628 2629 cooling-maps { 2630 map0 { 2631 trip = <&gpu_alert>; 2632 cooling-device = 2633 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2634 }; 2635 }; 2636 }; 2637 2638 npu_thermal: npu-thermal { 2639 polling-delay-passive = <0>; 2640 polling-delay = <0>; 2641 thermal-sensors = <&tsadc 6>; 2642 2643 trips { 2644 npu_crit: npu-crit { 2645 temperature = <115000>; 2646 hysteresis = <0>; 2647 type = "critical"; 2648 }; 2649 }; 2650 }; 2651 }; 2652 2653 tsadc: tsadc@fec00000 { 2654 compatible = "rockchip,rk3588-tsadc"; 2655 reg = <0x0 0xfec00000 0x0 0x400>; 2656 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; 2657 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2658 clock-names = "tsadc", "apb_pclk"; 2659 assigned-clocks = <&cru CLK_TSADC>; 2660 assigned-clock-rates = <2000000>; 2661 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 2662 reset-names = "tsadc-apb", "tsadc"; 2663 rockchip,hw-tshut-temp = <120000>; 2664 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 2665 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2666 pinctrl-0 = <&tsadc_gpio_func>; 2667 pinctrl-1 = <&tsadc_shut>; 2668 pinctrl-names = "gpio", "otpout"; 2669 #thermal-sensor-cells = <1>; 2670 status = "disabled"; 2671 }; 2672 2673 saradc: adc@fec10000 { 2674 compatible = "rockchip,rk3588-saradc"; 2675 reg = <0x0 0xfec10000 0x0 0x10000>; 2676 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; 2677 #io-channel-cells = <1>; 2678 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2679 clock-names = "saradc", "apb_pclk"; 2680 resets = <&cru SRST_P_SARADC>; 2681 reset-names = "saradc-apb"; 2682 status = "disabled"; 2683 }; 2684 2685 i2c6: i2c@fec80000 { 2686 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2687 reg = <0x0 0xfec80000 0x0 0x1000>; 2688 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2689 clock-names = "i2c", "pclk"; 2690 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; 2691 pinctrl-0 = <&i2c6m0_xfer>; 2692 pinctrl-names = "default"; 2693 #address-cells = <1>; 2694 #size-cells = <0>; 2695 status = "disabled"; 2696 }; 2697 2698 i2c7: i2c@fec90000 { 2699 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2700 reg = <0x0 0xfec90000 0x0 0x1000>; 2701 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2702 clock-names = "i2c", "pclk"; 2703 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 2704 pinctrl-0 = <&i2c7m0_xfer>; 2705 pinctrl-names = "default"; 2706 #address-cells = <1>; 2707 #size-cells = <0>; 2708 status = "disabled"; 2709 }; 2710 2711 i2c8: i2c@feca0000 { 2712 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2713 reg = <0x0 0xfeca0000 0x0 0x1000>; 2714 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2715 clock-names = "i2c", "pclk"; 2716 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; 2717 pinctrl-0 = <&i2c8m0_xfer>; 2718 pinctrl-names = "default"; 2719 #address-cells = <1>; 2720 #size-cells = <0>; 2721 status = "disabled"; 2722 }; 2723 2724 spi4: spi@fecb0000 { 2725 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2726 reg = <0x0 0xfecb0000 0x0 0x1000>; 2727 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; 2728 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2729 clock-names = "spiclk", "apb_pclk"; 2730 dmas = <&dmac2 13>, <&dmac2 14>; 2731 dma-names = "tx", "rx"; 2732 num-cs = <2>; 2733 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 2734 pinctrl-names = "default"; 2735 #address-cells = <1>; 2736 #size-cells = <0>; 2737 status = "disabled"; 2738 }; 2739 2740 otp: efuse@fecc0000 { 2741 compatible = "rockchip,rk3588-otp"; 2742 reg = <0x0 0xfecc0000 0x0 0x400>; 2743 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 2744 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; 2745 clock-names = "otp", "apb_pclk", "phy", "arb"; 2746 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 2747 <&cru SRST_OTPC_ARB>; 2748 reset-names = "otp", "apb", "arb"; 2749 #address-cells = <1>; 2750 #size-cells = <1>; 2751 2752 cpu_code: cpu-code@2 { 2753 reg = <0x02 0x2>; 2754 }; 2755 2756 otp_id: id@7 { 2757 reg = <0x07 0x10>; 2758 }; 2759 2760 cpub0_leakage: cpu-leakage@17 { 2761 reg = <0x17 0x1>; 2762 }; 2763 2764 cpub1_leakage: cpu-leakage@18 { 2765 reg = <0x18 0x1>; 2766 }; 2767 2768 cpul_leakage: cpu-leakage@19 { 2769 reg = <0x19 0x1>; 2770 }; 2771 2772 log_leakage: log-leakage@1a { 2773 reg = <0x1a 0x1>; 2774 }; 2775 2776 gpu_leakage: gpu-leakage@1b { 2777 reg = <0x1b 0x1>; 2778 }; 2779 2780 otp_cpu_version: cpu-version@1c { 2781 reg = <0x1c 0x1>; 2782 bits = <3 3>; 2783 }; 2784 2785 npu_leakage: npu-leakage@28 { 2786 reg = <0x28 0x1>; 2787 }; 2788 2789 codec_leakage: codec-leakage@29 { 2790 reg = <0x29 0x1>; 2791 }; 2792 }; 2793 2794 dmac2: dma-controller@fed10000 { 2795 compatible = "arm,pl330", "arm,primecell"; 2796 reg = <0x0 0xfed10000 0x0 0x4000>; 2797 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, 2798 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; 2799 arm,pl330-periph-burst; 2800 clocks = <&cru ACLK_DMAC2>; 2801 clock-names = "apb_pclk"; 2802 #dma-cells = <1>; 2803 }; 2804 2805 hdptxphy_hdmi0: phy@fed60000 { 2806 compatible = "rockchip,rk3588-hdptx-phy"; 2807 reg = <0x0 0xfed60000 0x0 0x2000>; 2808 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 2809 clock-names = "ref", "apb"; 2810 #phy-cells = <0>; 2811 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, 2812 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, 2813 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, 2814 <&cru SRST_HDPTX0_LCPLL>; 2815 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 2816 "lcpll"; 2817 rockchip,grf = <&hdptxphy0_grf>; 2818 status = "disabled"; 2819 }; 2820 2821 usbdp_phy0: phy@fed80000 { 2822 compatible = "rockchip,rk3588-usbdp-phy"; 2823 reg = <0x0 0xfed80000 0x0 0x10000>; 2824 #phy-cells = <1>; 2825 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 2826 <&cru CLK_USBDP_PHY0_IMMORTAL>, 2827 <&cru PCLK_USBDPPHY0>, 2828 <&u2phy0>; 2829 clock-names = "refclk", "immortal", "pclk", "utmi"; 2830 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 2831 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 2832 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 2833 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 2834 <&cru SRST_P_USBDPPHY0>; 2835 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 2836 rockchip,u2phy-grf = <&usb2phy0_grf>; 2837 rockchip,usb-grf = <&usb_grf>; 2838 rockchip,usbdpphy-grf = <&usbdpphy0_grf>; 2839 rockchip,vo-grf = <&vo0_grf>; 2840 status = "disabled"; 2841 }; 2842 2843 combphy0_ps: phy@fee00000 { 2844 compatible = "rockchip,rk3588-naneng-combphy"; 2845 reg = <0x0 0xfee00000 0x0 0x100>; 2846 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, 2847 <&cru PCLK_PHP_ROOT>; 2848 clock-names = "ref", "apb", "pipe"; 2849 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 2850 assigned-clock-rates = <100000000>; 2851 #phy-cells = <1>; 2852 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; 2853 reset-names = "phy", "apb"; 2854 rockchip,pipe-grf = <&php_grf>; 2855 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 2856 status = "disabled"; 2857 }; 2858 2859 combphy2_psu: phy@fee20000 { 2860 compatible = "rockchip,rk3588-naneng-combphy"; 2861 reg = <0x0 0xfee20000 0x0 0x100>; 2862 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, 2863 <&cru PCLK_PHP_ROOT>; 2864 clock-names = "ref", "apb", "pipe"; 2865 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 2866 assigned-clock-rates = <100000000>; 2867 #phy-cells = <1>; 2868 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; 2869 reset-names = "phy", "apb"; 2870 rockchip,pipe-grf = <&php_grf>; 2871 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 2872 status = "disabled"; 2873 }; 2874 2875 system_sram2: sram@ff001000 { 2876 compatible = "mmio-sram"; 2877 reg = <0x0 0xff001000 0x0 0xef000>; 2878 ranges = <0x0 0x0 0xff001000 0xef000>; 2879 #address-cells = <1>; 2880 #size-cells = <1>; 2881 }; 2882 2883 pinctrl: pinctrl { 2884 compatible = "rockchip,rk3588-pinctrl"; 2885 ranges; 2886 rockchip,grf = <&ioc>; 2887 #address-cells = <2>; 2888 #size-cells = <2>; 2889 2890 gpio0: gpio@fd8a0000 { 2891 compatible = "rockchip,gpio-bank"; 2892 reg = <0x0 0xfd8a0000 0x0 0x100>; 2893 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 2894 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 2895 gpio-controller; 2896 gpio-ranges = <&pinctrl 0 0 32>; 2897 interrupt-controller; 2898 #gpio-cells = <2>; 2899 #interrupt-cells = <2>; 2900 }; 2901 2902 gpio1: gpio@fec20000 { 2903 compatible = "rockchip,gpio-bank"; 2904 reg = <0x0 0xfec20000 0x0 0x100>; 2905 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; 2906 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2907 gpio-controller; 2908 gpio-ranges = <&pinctrl 0 32 32>; 2909 interrupt-controller; 2910 #gpio-cells = <2>; 2911 #interrupt-cells = <2>; 2912 }; 2913 2914 gpio2: gpio@fec30000 { 2915 compatible = "rockchip,gpio-bank"; 2916 reg = <0x0 0xfec30000 0x0 0x100>; 2917 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; 2918 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2919 gpio-controller; 2920 gpio-ranges = <&pinctrl 0 64 32>; 2921 interrupt-controller; 2922 #gpio-cells = <2>; 2923 #interrupt-cells = <2>; 2924 }; 2925 2926 gpio3: gpio@fec40000 { 2927 compatible = "rockchip,gpio-bank"; 2928 reg = <0x0 0xfec40000 0x0 0x100>; 2929 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; 2930 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2931 gpio-controller; 2932 gpio-ranges = <&pinctrl 0 96 32>; 2933 interrupt-controller; 2934 #gpio-cells = <2>; 2935 #interrupt-cells = <2>; 2936 }; 2937 2938 gpio4: gpio@fec50000 { 2939 compatible = "rockchip,gpio-bank"; 2940 reg = <0x0 0xfec50000 0x0 0x100>; 2941 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; 2942 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2943 gpio-controller; 2944 gpio-ranges = <&pinctrl 0 128 32>; 2945 interrupt-controller; 2946 #gpio-cells = <2>; 2947 #interrupt-cells = <2>; 2948 }; 2949 }; 2950}; 2951 2952#include "rk3588-base-pinctrl.dtsi" 2953