1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3576-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rockchip,rk3576-power.h> 12#include <dt-bindings/reset/rockchip,rk3576-cru.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 compatible = "rockchip,rk3576"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 i2c5 = &i2c5; 30 i2c6 = &i2c6; 31 i2c7 = &i2c7; 32 i2c8 = &i2c8; 33 i2c9 = &i2c9; 34 serial0 = &uart0; 35 serial1 = &uart1; 36 serial2 = &uart2; 37 serial3 = &uart3; 38 serial4 = &uart4; 39 serial5 = &uart5; 40 serial6 = &uart6; 41 serial7 = &uart7; 42 serial8 = &uart8; 43 serial9 = &uart9; 44 serial10 = &uart10; 45 serial11 = &uart11; 46 spi0 = &spi0; 47 spi1 = &spi1; 48 spi2 = &spi2; 49 spi3 = &spi3; 50 spi4 = &spi4; 51 }; 52 53 xin32k: clock-xin32k { 54 compatible = "fixed-clock"; 55 clock-frequency = <32768>; 56 clock-output-names = "xin32k"; 57 #clock-cells = <0>; 58 }; 59 60 xin24m: clock-xin24m { 61 compatible = "fixed-clock"; 62 #clock-cells = <0>; 63 clock-frequency = <24000000>; 64 clock-output-names = "xin24m"; 65 }; 66 67 spll: clock-spll { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <702000000>; 71 clock-output-names = "spll"; 72 }; 73 74 cpus { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 cpu-map { 79 cluster0 { 80 core0 { 81 cpu = <&cpu_l0>; 82 }; 83 core1 { 84 cpu = <&cpu_l1>; 85 }; 86 core2 { 87 cpu = <&cpu_l2>; 88 }; 89 core3 { 90 cpu = <&cpu_l3>; 91 }; 92 }; 93 cluster1 { 94 core0 { 95 cpu = <&cpu_b0>; 96 }; 97 core1 { 98 cpu = <&cpu_b1>; 99 }; 100 core2 { 101 cpu = <&cpu_b2>; 102 }; 103 core3 { 104 cpu = <&cpu_b3>; 105 }; 106 }; 107 }; 108 109 cpu_l0: cpu@0 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a53"; 112 reg = <0x0>; 113 enable-method = "psci"; 114 capacity-dmips-mhz = <485>; 115 clocks = <&scmi_clk SCMI_ARMCLK_L>; 116 operating-points-v2 = <&cluster0_opp_table>; 117 dynamic-power-coefficient = <120>; 118 cpu-idle-states = <&CPU_SLEEP>; 119 #cooling-cells = <2>; 120 }; 121 122 cpu_l1: cpu@1 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a53"; 125 reg = <0x1>; 126 enable-method = "psci"; 127 capacity-dmips-mhz = <485>; 128 clocks = <&scmi_clk SCMI_ARMCLK_L>; 129 operating-points-v2 = <&cluster0_opp_table>; 130 cpu-idle-states = <&CPU_SLEEP>; 131 #cooling-cells = <2>; 132 }; 133 134 cpu_l2: cpu@2 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a53"; 137 reg = <0x2>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <485>; 140 clocks = <&scmi_clk SCMI_ARMCLK_L>; 141 operating-points-v2 = <&cluster0_opp_table>; 142 cpu-idle-states = <&CPU_SLEEP>; 143 #cooling-cells = <2>; 144 }; 145 146 cpu_l3: cpu@3 { 147 device_type = "cpu"; 148 compatible = "arm,cortex-a53"; 149 reg = <0x3>; 150 enable-method = "psci"; 151 capacity-dmips-mhz = <485>; 152 clocks = <&scmi_clk SCMI_ARMCLK_L>; 153 operating-points-v2 = <&cluster0_opp_table>; 154 cpu-idle-states = <&CPU_SLEEP>; 155 #cooling-cells = <2>; 156 }; 157 158 cpu_b0: cpu@100 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a72"; 161 reg = <0x100>; 162 enable-method = "psci"; 163 capacity-dmips-mhz = <1024>; 164 clocks = <&scmi_clk SCMI_ARMCLK_B>; 165 operating-points-v2 = <&cluster1_opp_table>; 166 dynamic-power-coefficient = <320>; 167 cpu-idle-states = <&CPU_SLEEP>; 168 #cooling-cells = <2>; 169 }; 170 171 cpu_b1: cpu@101 { 172 device_type = "cpu"; 173 compatible = "arm,cortex-a72"; 174 reg = <0x101>; 175 enable-method = "psci"; 176 capacity-dmips-mhz = <1024>; 177 clocks = <&scmi_clk SCMI_ARMCLK_B>; 178 operating-points-v2 = <&cluster1_opp_table>; 179 cpu-idle-states = <&CPU_SLEEP>; 180 #cooling-cells = <2>; 181 }; 182 183 cpu_b2: cpu@102 { 184 device_type = "cpu"; 185 compatible = "arm,cortex-a72"; 186 reg = <0x102>; 187 enable-method = "psci"; 188 capacity-dmips-mhz = <1024>; 189 clocks = <&scmi_clk SCMI_ARMCLK_B>; 190 operating-points-v2 = <&cluster1_opp_table>; 191 cpu-idle-states = <&CPU_SLEEP>; 192 #cooling-cells = <2>; 193 }; 194 195 cpu_b3: cpu@103 { 196 device_type = "cpu"; 197 compatible = "arm,cortex-a72"; 198 reg = <0x103>; 199 enable-method = "psci"; 200 capacity-dmips-mhz = <1024>; 201 clocks = <&scmi_clk SCMI_ARMCLK_B>; 202 operating-points-v2 = <&cluster1_opp_table>; 203 cpu-idle-states = <&CPU_SLEEP>; 204 #cooling-cells = <2>; 205 }; 206 207 idle-states { 208 entry-method = "psci"; 209 210 CPU_SLEEP: cpu-sleep { 211 compatible = "arm,idle-state"; 212 arm,psci-suspend-param = <0x0010000>; 213 entry-latency-us = <120>; 214 exit-latency-us = <250>; 215 min-residency-us = <900>; 216 local-timer-stop; 217 }; 218 }; 219 }; 220 221 cluster0_opp_table: opp-table-cluster0 { 222 compatible = "operating-points-v2"; 223 opp-shared; 224 225 opp-408000000 { 226 opp-hz = /bits/ 64 <408000000>; 227 opp-microvolt = <700000 700000 950000>; 228 clock-latency-ns = <40000>; 229 }; 230 231 opp-600000000 { 232 opp-hz = /bits/ 64 <600000000>; 233 opp-microvolt = <700000 700000 950000>; 234 clock-latency-ns = <40000>; 235 }; 236 237 opp-816000000 { 238 opp-hz = /bits/ 64 <816000000>; 239 opp-microvolt = <700000 700000 950000>; 240 clock-latency-ns = <40000>; 241 }; 242 243 opp-1008000000 { 244 opp-hz = /bits/ 64 <1008000000>; 245 opp-microvolt = <700000 700000 950000>; 246 clock-latency-ns = <40000>; 247 }; 248 249 opp-1200000000 { 250 opp-hz = /bits/ 64 <1200000000>; 251 opp-microvolt = <700000 700000 950000>; 252 clock-latency-ns = <40000>; 253 }; 254 255 opp-1416000000 { 256 opp-hz = /bits/ 64 <1416000000>; 257 opp-microvolt = <725000 725000 950000>; 258 clock-latency-ns = <40000>; 259 }; 260 261 opp-1608000000 { 262 opp-hz = /bits/ 64 <1608000000>; 263 opp-microvolt = <750000 750000 950000>; 264 clock-latency-ns = <40000>; 265 }; 266 267 opp-1800000000 { 268 opp-hz = /bits/ 64 <1800000000>; 269 opp-microvolt = <825000 825000 950000>; 270 clock-latency-ns = <40000>; 271 opp-suspend; 272 }; 273 274 opp-2016000000 { 275 opp-hz = /bits/ 64 <2016000000>; 276 opp-microvolt = <900000 900000 950000>; 277 clock-latency-ns = <40000>; 278 }; 279 280 opp-2208000000 { 281 opp-hz = /bits/ 64 <2208000000>; 282 opp-microvolt = <950000 950000 950000>; 283 clock-latency-ns = <40000>; 284 }; 285 }; 286 287 cluster1_opp_table: opp-table-cluster1 { 288 compatible = "operating-points-v2"; 289 opp-shared; 290 291 opp-408000000 { 292 opp-hz = /bits/ 64 <408000000>; 293 opp-microvolt = <700000 700000 950000>; 294 clock-latency-ns = <40000>; 295 opp-suspend; 296 }; 297 298 opp-600000000 { 299 opp-hz = /bits/ 64 <600000000>; 300 opp-microvolt = <700000 700000 950000>; 301 clock-latency-ns = <40000>; 302 }; 303 304 opp-816000000 { 305 opp-hz = /bits/ 64 <816000000>; 306 opp-microvolt = <700000 700000 950000>; 307 clock-latency-ns = <40000>; 308 }; 309 310 opp-1008000000 { 311 opp-hz = /bits/ 64 <1008000000>; 312 opp-microvolt = <700000 700000 950000>; 313 clock-latency-ns = <40000>; 314 }; 315 316 opp-1200000000 { 317 opp-hz = /bits/ 64 <1200000000>; 318 opp-microvolt = <700000 700000 950000>; 319 clock-latency-ns = <40000>; 320 }; 321 322 opp-1416000000 { 323 opp-hz = /bits/ 64 <1416000000>; 324 opp-microvolt = <712500 712500 950000>; 325 clock-latency-ns = <40000>; 326 }; 327 328 opp-1608000000 { 329 opp-hz = /bits/ 64 <1608000000>; 330 opp-microvolt = <737500 737500 950000>; 331 clock-latency-ns = <40000>; 332 }; 333 334 opp-1800000000 { 335 opp-hz = /bits/ 64 <1800000000>; 336 opp-microvolt = <800000 800000 950000>; 337 clock-latency-ns = <40000>; 338 }; 339 340 opp-2016000000 { 341 opp-hz = /bits/ 64 <2016000000>; 342 opp-microvolt = <862500 862500 950000>; 343 clock-latency-ns = <40000>; 344 }; 345 346 opp-2208000000 { 347 opp-hz = /bits/ 64 <2208000000>; 348 opp-microvolt = <925000 925000 950000>; 349 clock-latency-ns = <40000>; 350 }; 351 352 opp-2304000000 { 353 opp-hz = /bits/ 64 <2304000000>; 354 opp-microvolt = <950000 950000 950000>; 355 clock-latency-ns = <40000>; 356 }; 357 }; 358 359 gpu_opp_table: opp-table-gpu { 360 compatible = "operating-points-v2"; 361 362 opp-300000000 { 363 opp-hz = /bits/ 64 <300000000>; 364 opp-microvolt = <700000 700000 850000>; 365 }; 366 367 opp-400000000 { 368 opp-hz = /bits/ 64 <400000000>; 369 opp-microvolt = <700000 700000 850000>; 370 }; 371 372 opp-500000000 { 373 opp-hz = /bits/ 64 <500000000>; 374 opp-microvolt = <700000 700000 850000>; 375 }; 376 377 opp-600000000 { 378 opp-hz = /bits/ 64 <600000000>; 379 opp-microvolt = <700000 700000 850000>; 380 }; 381 382 opp-700000000 { 383 opp-hz = /bits/ 64 <700000000>; 384 opp-microvolt = <725000 725000 850000>; 385 }; 386 387 opp-800000000 { 388 opp-hz = /bits/ 64 <800000000>; 389 opp-microvolt = <775000 775000 850000>; 390 }; 391 392 opp-900000000 { 393 opp-hz = /bits/ 64 <900000000>; 394 opp-microvolt = <825000 825000 850000>; 395 }; 396 397 opp-950000000 { 398 opp-hz = /bits/ 64 <950000000>; 399 opp-microvolt = <850000 850000 850000>; 400 }; 401 }; 402 403 display_subsystem: display-subsystem { 404 compatible = "rockchip,display-subsystem"; 405 ports = <&vop_out>; 406 }; 407 408 firmware { 409 scmi: scmi { 410 compatible = "arm,scmi-smc"; 411 arm,smc-id = <0x82000010>; 412 shmem = <&scmi_shmem>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 416 scmi_clk: protocol@14 { 417 reg = <0x14>; 418 #clock-cells = <1>; 419 }; 420 }; 421 }; 422 423 hdmi_sound: hdmi-sound { 424 compatible = "simple-audio-card"; 425 simple-audio-card,name = "HDMI"; 426 simple-audio-card,format = "i2s"; 427 simple-audio-card,mclk-fs = <256>; 428 status = "disabled"; 429 430 simple-audio-card,codec { 431 sound-dai = <&hdmi>; 432 }; 433 434 simple-audio-card,cpu { 435 sound-dai = <&sai6>; 436 }; 437 }; 438 439 pinctrl: pinctrl { 440 compatible = "rockchip,rk3576-pinctrl"; 441 rockchip,grf = <&ioc_grf>; 442 #address-cells = <2>; 443 #size-cells = <2>; 444 ranges; 445 446 gpio0: gpio@27320000 { 447 compatible = "rockchip,gpio-bank"; 448 reg = <0x0 0x27320000 0x0 0x200>; 449 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 450 gpio-controller; 451 gpio-ranges = <&pinctrl 0 0 32>; 452 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 453 interrupt-controller; 454 #gpio-cells = <2>; 455 #interrupt-cells = <2>; 456 }; 457 458 gpio1: gpio@2ae10000 { 459 compatible = "rockchip,gpio-bank"; 460 reg = <0x0 0x2ae10000 0x0 0x200>; 461 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 462 gpio-controller; 463 gpio-ranges = <&pinctrl 0 32 32>; 464 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 465 interrupt-controller; 466 #gpio-cells = <2>; 467 #interrupt-cells = <2>; 468 }; 469 470 gpio2: gpio@2ae20000 { 471 compatible = "rockchip,gpio-bank"; 472 reg = <0x0 0x2ae20000 0x0 0x200>; 473 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 474 gpio-controller; 475 gpio-ranges = <&pinctrl 0 64 32>; 476 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 477 interrupt-controller; 478 #gpio-cells = <2>; 479 #interrupt-cells = <2>; 480 }; 481 482 gpio3: gpio@2ae30000 { 483 compatible = "rockchip,gpio-bank"; 484 reg = <0x0 0x2ae30000 0x0 0x200>; 485 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 486 gpio-controller; 487 gpio-ranges = <&pinctrl 0 96 32>; 488 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 489 interrupt-controller; 490 #gpio-cells = <2>; 491 #interrupt-cells = <2>; 492 }; 493 494 gpio4: gpio@2ae40000 { 495 compatible = "rockchip,gpio-bank"; 496 reg = <0x0 0x2ae40000 0x0 0x200>; 497 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 498 gpio-controller; 499 gpio-ranges = <&pinctrl 0 128 32>; 500 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 501 interrupt-controller; 502 #gpio-cells = <2>; 503 #interrupt-cells = <2>; 504 }; 505 }; 506 507 pmu_a53: pmu-a53 { 508 compatible = "arm,cortex-a53-pmu"; 509 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 513 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>; 514 }; 515 516 pmu_a72: pmu-a72 { 517 compatible = "arm,cortex-a72-pmu"; 518 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 522 interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; 523 }; 524 525 psci { 526 compatible = "arm,psci-1.0"; 527 method = "smc"; 528 }; 529 530 thermal_zones: thermal-zones { 531 /* sensor near the center of the SoC */ 532 package_thermal: package-thermal { 533 polling-delay-passive = <0>; 534 polling-delay = <0>; 535 thermal-sensors = <&tsadc 0>; 536 537 trips { 538 package_crit: package-crit { 539 temperature = <115000>; 540 hysteresis = <0>; 541 type = "critical"; 542 }; 543 }; 544 }; 545 546 /* sensor for cluster1 (big Cortex-A72 cores) */ 547 bigcore_thermal: bigcore-thermal { 548 polling-delay-passive = <100>; 549 polling-delay = <0>; 550 thermal-sensors = <&tsadc 1>; 551 552 trips { 553 bigcore_alert: bigcore-alert { 554 temperature = <85000>; 555 hysteresis = <2000>; 556 type = "passive"; 557 }; 558 559 bigcore_crit: bigcore-crit { 560 temperature = <115000>; 561 hysteresis = <0>; 562 type = "critical"; 563 }; 564 }; 565 566 cooling-maps { 567 map0 { 568 trip = <&bigcore_alert>; 569 cooling-device = 570 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 571 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 572 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 573 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 574 }; 575 }; 576 }; 577 578 /* sensor for cluster0 (little Cortex-A53 cores) */ 579 littlecore_thermal: littlecore-thermal { 580 polling-delay-passive = <100>; 581 polling-delay = <0>; 582 thermal-sensors = <&tsadc 2>; 583 584 trips { 585 littlecore_alert: littlecore-alert { 586 temperature = <85000>; 587 hysteresis = <2000>; 588 type = "passive"; 589 }; 590 591 littlecore_crit: littlecore-crit { 592 temperature = <115000>; 593 hysteresis = <0>; 594 type = "critical"; 595 }; 596 }; 597 598 cooling-maps { 599 map0 { 600 trip = <&littlecore_alert>; 601 cooling-device = 602 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 603 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 604 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 605 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 606 }; 607 }; 608 }; 609 610 gpu_thermal: gpu-thermal { 611 polling-delay-passive = <100>; 612 polling-delay = <0>; 613 thermal-sensors = <&tsadc 3>; 614 615 trips { 616 gpu_alert: gpu-alert { 617 temperature = <85000>; 618 hysteresis = <2000>; 619 type = "passive"; 620 }; 621 622 gpu_crit: gpu-crit { 623 temperature = <115000>; 624 hysteresis = <0>; 625 type = "critical"; 626 }; 627 }; 628 629 cooling-maps { 630 map0 { 631 trip = <&gpu_alert>; 632 cooling-device = 633 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 634 }; 635 }; 636 }; 637 638 npu_thermal: npu-thermal { 639 polling-delay-passive = <0>; 640 polling-delay = <0>; 641 thermal-sensors = <&tsadc 4>; 642 643 trips { 644 npu_crit: npu-crit { 645 temperature = <115000>; 646 hysteresis = <0>; 647 type = "critical"; 648 }; 649 }; 650 }; 651 652 ddr_thermal: ddr-thermal { 653 polling-delay-passive = <0>; 654 polling-delay = <0>; 655 thermal-sensors = <&tsadc 5>; 656 657 trips { 658 ddr_crit: ddr-crit { 659 temperature = <115000>; 660 hysteresis = <0>; 661 type = "critical"; 662 }; 663 }; 664 }; 665 }; 666 667 timer { 668 compatible = "arm,armv8-timer"; 669 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 670 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 671 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 672 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 673 }; 674 675 soc { 676 compatible = "simple-bus"; 677 #address-cells = <2>; 678 #size-cells = <2>; 679 ranges; 680 681 pcie0: pcie@22000000 { 682 compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; 683 reg = <0x0 0x22000000 0x0 0x00400000>, 684 <0x0 0x2a200000 0x0 0x00010000>, 685 <0x0 0x20000000 0x0 0x00100000>; 686 reg-names = "dbi", "apb", "config"; 687 bus-range = <0x0 0xf>; 688 clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, 689 <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, 690 <&cru CLK_PCIE0_AUX>; 691 clock-names = "aclk_mst", "aclk_slv", 692 "aclk_dbi", "pclk", 693 "aux"; 694 device_type = "pci"; 695 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>; 701 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; 702 #interrupt-cells = <1>; 703 interrupt-map-mask = <0 0 0 7>; 704 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 705 <0 0 0 2 &pcie0_intc 1>, 706 <0 0 0 3 &pcie0_intc 2>, 707 <0 0 0 4 &pcie0_intc 3>; 708 linux,pci-domain = <0>; 709 max-link-speed = <2>; 710 num-ib-windows = <8>; 711 num-viewport = <8>; 712 num-ob-windows = <2>; 713 num-lanes = <1>; 714 phys = <&combphy0_ps PHY_TYPE_PCIE>; 715 phy-names = "pcie-phy"; 716 power-domains = <&power RK3576_PD_PHP>; 717 ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000 718 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000 719 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; 720 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; 721 reset-names = "pwr", "pipe"; 722 #address-cells = <3>; 723 #size-cells = <2>; 724 status = "disabled"; 725 726 pcie0_intc: legacy-interrupt-controller { 727 interrupt-controller; 728 #address-cells = <0>; 729 #interrupt-cells = <1>; 730 interrupt-parent = <&gic>; 731 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; 732 }; 733 }; 734 735 pcie1: pcie@22400000 { 736 compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; 737 reg = <0x0 0x22400000 0x0 0x00400000>, 738 <0x0 0x2a210000 0x0 0x00010000>, 739 <0x0 0x21000000 0x0 0x00100000>; 740 reg-names = "dbi", "apb", "config"; 741 bus-range = <0x20 0x2f>; 742 clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, 743 <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, 744 <&cru CLK_PCIE1_AUX>; 745 clock-names = "aclk_mst", "aclk_slv", 746 "aclk_dbi", "pclk", 747 "aux"; 748 device_type = "pci"; 749 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 755 interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; 756 #interrupt-cells = <1>; 757 interrupt-map-mask = <0 0 0 7>; 758 interrupt-map = <0 0 0 1 &pcie1_intc 0>, 759 <0 0 0 2 &pcie1_intc 1>, 760 <0 0 0 3 &pcie1_intc 2>, 761 <0 0 0 4 &pcie1_intc 3>; 762 linux,pci-domain = <1>; 763 max-link-speed = <2>; 764 num-ib-windows = <8>; 765 num-viewport = <8>; 766 num-ob-windows = <2>; 767 num-lanes = <1>; 768 phys = <&combphy1_psu PHY_TYPE_PCIE>; 769 phy-names = "pcie-phy"; 770 power-domains = <&power RK3576_PD_SUBPHP>; 771 ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000 772 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000 773 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; 774 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; 775 reset-names = "pwr", "pipe"; 776 #address-cells = <3>; 777 #size-cells = <2>; 778 status = "disabled"; 779 780 pcie1_intc: legacy-interrupt-controller { 781 interrupt-controller; 782 #address-cells = <0>; 783 #interrupt-cells = <1>; 784 interrupt-parent = <&gic>; 785 interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>; 786 }; 787 }; 788 789 usb_drd0_dwc3: usb@23000000 { 790 compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; 791 reg = <0x0 0x23000000 0x0 0x400000>; 792 clocks = <&cru CLK_REF_USB3OTG0>, 793 <&cru CLK_SUSPEND_USB3OTG0>, 794 <&cru ACLK_USB3OTG0>; 795 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 796 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 797 power-domains = <&power RK3576_PD_USB>; 798 resets = <&cru SRST_A_USB3OTG0>; 799 dr_mode = "otg"; 800 phys = <&u2phy0_otg>, <&usbdp_phy PHY_TYPE_USB3>; 801 phy-names = "usb2-phy", "usb3-phy"; 802 phy_type = "utmi_wide"; 803 snps,dis_enblslpm_quirk; 804 snps,dis-u1-entry-quirk; 805 snps,dis-u2-entry-quirk; 806 snps,dis-u2-freeclk-exists-quirk; 807 snps,dis-del-phy-power-chg-quirk; 808 snps,dis-tx-ipgap-linecheck-quirk; 809 snps,parkmode-disable-hs-quirk; 810 snps,parkmode-disable-ss-quirk; 811 status = "disabled"; 812 }; 813 814 usb_drd1_dwc3: usb@23400000 { 815 compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; 816 reg = <0x0 0x23400000 0x0 0x400000>; 817 clocks = <&cru CLK_REF_USB3OTG1>, 818 <&cru CLK_SUSPEND_USB3OTG1>, 819 <&cru ACLK_USB3OTG1>; 820 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 821 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 822 power-domains = <&power RK3576_PD_PHP>; 823 resets = <&cru SRST_A_USB3OTG1>; 824 dr_mode = "otg"; 825 phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>; 826 phy-names = "usb2-phy", "usb3-phy"; 827 phy_type = "utmi_wide"; 828 snps,dis_enblslpm_quirk; 829 snps,dis-u1-entry-quirk; 830 snps,dis-u2-entry-quirk; 831 snps,dis-u2-freeclk-exists-quirk; 832 snps,dis-del-phy-power-chg-quirk; 833 snps,dis-tx-ipgap-linecheck-quirk; 834 snps,dis_rxdet_inp3_quirk; 835 snps,parkmode-disable-hs-quirk; 836 snps,parkmode-disable-ss-quirk; 837 dma-coherent; 838 status = "disabled"; 839 }; 840 841 sys_grf: syscon@2600a000 { 842 compatible = "rockchip,rk3576-sys-grf", "syscon"; 843 reg = <0x0 0x2600a000 0x0 0x2000>; 844 }; 845 846 bigcore_grf: syscon@2600c000 { 847 compatible = "rockchip,rk3576-bigcore-grf", "syscon"; 848 reg = <0x0 0x2600c000 0x0 0x2000>; 849 }; 850 851 litcore_grf: syscon@2600e000 { 852 compatible = "rockchip,rk3576-litcore-grf", "syscon"; 853 reg = <0x0 0x2600e000 0x0 0x2000>; 854 }; 855 856 cci_grf: syscon@26010000 { 857 compatible = "rockchip,rk3576-cci-grf", "syscon"; 858 reg = <0x0 0x26010000 0x0 0x2000>; 859 }; 860 861 gpu_grf: syscon@26016000 { 862 compatible = "rockchip,rk3576-gpu-grf", "syscon"; 863 reg = <0x0 0x26016000 0x0 0x2000>; 864 }; 865 866 npu_grf: syscon@26018000 { 867 compatible = "rockchip,rk3576-npu-grf", "syscon"; 868 reg = <0x0 0x26018000 0x0 0x2000>; 869 }; 870 871 vo0_grf: syscon@2601a000 { 872 compatible = "rockchip,rk3576-vo0-grf", "syscon"; 873 reg = <0x0 0x2601a000 0x0 0x2000>; 874 }; 875 876 usb_grf: syscon@2601e000 { 877 compatible = "rockchip,rk3576-usb-grf", "syscon"; 878 reg = <0x0 0x2601e000 0x0 0x1000>; 879 }; 880 881 php_grf: syscon@26020000 { 882 compatible = "rockchip,rk3576-php-grf", "syscon"; 883 reg = <0x0 0x26020000 0x0 0x2000>; 884 }; 885 886 pmu0_grf: syscon@26024000 { 887 compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd"; 888 reg = <0x0 0x26024000 0x0 0x1000>; 889 }; 890 891 pmu1_grf: syscon@26026000 { 892 compatible = "rockchip,rk3576-pmu1-grf", "syscon"; 893 reg = <0x0 0x26026000 0x0 0x1000>; 894 }; 895 896 pipe_phy0_grf: syscon@26028000 { 897 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 898 reg = <0x0 0x26028000 0x0 0x2000>; 899 }; 900 901 pipe_phy1_grf: syscon@2602a000 { 902 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 903 reg = <0x0 0x2602a000 0x0 0x2000>; 904 }; 905 906 usbdpphy_grf: syscon@2602c000 { 907 compatible = "rockchip,rk3576-usbdpphy-grf", "syscon"; 908 reg = <0x0 0x2602c000 0x0 0x2000>; 909 }; 910 911 usb2phy_grf: syscon@2602e000 { 912 compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd"; 913 reg = <0x0 0x2602e000 0x0 0x4000>; 914 #address-cells = <1>; 915 #size-cells = <1>; 916 917 u2phy0: usb2-phy@0 { 918 compatible = "rockchip,rk3576-usb2phy"; 919 reg = <0x0 0x10>; 920 resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>; 921 reset-names = "phy", "apb"; 922 clocks = <&cru CLK_PHY_REF_SRC>, 923 <&cru ACLK_MMU2>, 924 <&cru ACLK_SLV_MMU2>; 925 clock-names = "phyclk", "aclk", "aclk_slv"; 926 clock-output-names = "usb480m_phy0"; 927 #clock-cells = <0>; 928 status = "disabled"; 929 930 u2phy0_otg: otg-port { 931 #phy-cells = <0>; 932 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 935 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 936 status = "disabled"; 937 }; 938 }; 939 940 u2phy1: usb2-phy@2000 { 941 compatible = "rockchip,rk3576-usb2phy"; 942 reg = <0x2000 0x10>; 943 resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>; 944 reset-names = "phy", "apb"; 945 clocks = <&cru CLK_PHY_REF_SRC>, 946 <&cru ACLK_MMU1>, 947 <&cru ACLK_SLV_MMU1>; 948 clock-names = "phyclk", "aclk", "aclk_slv"; 949 clock-output-names = "usb480m_phy1"; 950 #clock-cells = <0>; 951 status = "disabled"; 952 953 u2phy1_otg: otg-port { 954 #phy-cells = <0>; 955 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 958 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 959 status = "disabled"; 960 }; 961 }; 962 }; 963 964 hdptxphy_grf: syscon@26032000 { 965 compatible = "rockchip,rk3576-hdptxphy-grf", "syscon"; 966 reg = <0x0 0x26032000 0x0 0x100>; 967 }; 968 969 mipidcphy_grf: syscon@26034000 { 970 compatible = "rockchip,rk3576-dcphy-grf", "syscon"; 971 reg = <0x0 0x26034000 0x0 0x2000>; 972 clocks = <&cru PCLK_PMUPHY_ROOT>; 973 }; 974 975 vo1_grf: syscon@26036000 { 976 compatible = "rockchip,rk3576-vo1-grf", "syscon"; 977 reg = <0x0 0x26036000 0x0 0x100>; 978 clocks = <&cru PCLK_VO1_ROOT>; 979 }; 980 981 sdgmac_grf: syscon@26038000 { 982 compatible = "rockchip,rk3576-sdgmac-grf", "syscon"; 983 reg = <0x0 0x26038000 0x0 0x1000>; 984 }; 985 986 ioc_grf: syscon@26040000 { 987 compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd"; 988 reg = <0x0 0x26040000 0x0 0xc000>; 989 }; 990 991 cru: clock-controller@27200000 { 992 compatible = "rockchip,rk3576-cru"; 993 reg = <0x0 0x27200000 0x0 0x50000>; 994 #clock-cells = <1>; 995 #reset-cells = <1>; 996 997 assigned-clocks = 998 <&cru CLK_AUDIO_FRAC_1_SRC>, 999 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1000 <&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>, 1001 <&cru CLK_UART_FRAC_1>, <&cru CLK_UART_FRAC_2>, 1002 <&cru CLK_AUDIO_FRAC_0>, <&cru CLK_AUDIO_FRAC_1>, 1003 <&cru CLK_CPLL_DIV2>, <&cru CLK_CPLL_DIV4>, 1004 <&cru CLK_CPLL_DIV10>, <&cru FCLK_DDR_CM0_CORE>, 1005 <&cru ACLK_PHP_ROOT>; 1006 assigned-clock-parents = <&cru PLL_AUPLL>; 1007 assigned-clock-rates = 1008 <0>, 1009 <1188000000>, <1000000000>, 1010 <786432000>, <18432000>, 1011 <96000000>, <128000000>, 1012 <45158400>, <49152000>, 1013 <500000000>, <250000000>, 1014 <100000000>, <500000000>, 1015 <250000000>; 1016 }; 1017 1018 i2c0: i2c@27300000 { 1019 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1020 reg = <0x0 0x27300000 0x0 0x1000>; 1021 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 1022 clock-names = "i2c", "pclk"; 1023 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&i2c0m0_xfer>; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 status = "disabled"; 1029 }; 1030 1031 uart1: serial@27310000 { 1032 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1033 reg = <0x0 0x27310000 0x0 0x100>; 1034 reg-shift = <2>; 1035 reg-io-width = <4>; 1036 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1037 clock-names = "baudclk", "apb_pclk"; 1038 dmas = <&dmac0 8>, <&dmac0 9>; 1039 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&uart1m0_xfer>; 1042 status = "disabled"; 1043 }; 1044 1045 pmu: power-management@27380000 { 1046 compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd"; 1047 reg = <0x0 0x27380000 0x0 0x800>; 1048 1049 power: power-controller { 1050 compatible = "rockchip,rk3576-power-controller"; 1051 #power-domain-cells = <1>; 1052 #address-cells = <1>; 1053 #size-cells = <0>; 1054 1055 power-domain@RK3576_PD_NPU { 1056 reg = <RK3576_PD_NPU>; 1057 #power-domain-cells = <1>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 1061 power-domain@RK3576_PD_NPUTOP { 1062 reg = <RK3576_PD_NPUTOP>; 1063 clocks = <&cru ACLK_RKNN0>, 1064 <&cru ACLK_RKNN1>, 1065 <&cru ACLK_RKNN_CBUF>, 1066 <&cru CLK_RKNN_DSU0>, 1067 <&cru HCLK_RKNN_CBUF>, 1068 <&cru HCLK_RKNN_ROOT>, 1069 <&cru HCLK_NPU_CM0_ROOT>, 1070 <&cru PCLK_NPUTOP_ROOT>; 1071 pm_qos = <&qos_npu_mcu>, 1072 <&qos_npu_nsp0>, 1073 <&qos_npu_nsp1>, 1074 <&qos_npu_m0ro>, 1075 <&qos_npu_m1ro>; 1076 #power-domain-cells = <1>; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 1080 power-domain@RK3576_PD_NPU0 { 1081 reg = <RK3576_PD_NPU0>; 1082 clocks = <&cru HCLK_RKNN_ROOT>, 1083 <&cru ACLK_RKNN0>; 1084 pm_qos = <&qos_npu_m0>; 1085 #power-domain-cells = <0>; 1086 }; 1087 power-domain@RK3576_PD_NPU1 { 1088 reg = <RK3576_PD_NPU1>; 1089 clocks = <&cru HCLK_RKNN_ROOT>, 1090 <&cru ACLK_RKNN1>; 1091 pm_qos = <&qos_npu_m1>; 1092 #power-domain-cells = <0>; 1093 }; 1094 }; 1095 }; 1096 1097 power-domain@RK3576_PD_GPU { 1098 reg = <RK3576_PD_GPU>; 1099 clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>; 1100 pm_qos = <&qos_gpu>; 1101 #power-domain-cells = <0>; 1102 }; 1103 1104 power-domain@RK3576_PD_NVM { 1105 reg = <RK3576_PD_NVM>; 1106 clocks = <&cru ACLK_EMMC>, <&cru HCLK_EMMC>; 1107 pm_qos = <&qos_emmc>, 1108 <&qos_fspi0>; 1109 #power-domain-cells = <1>; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 1113 power-domain@RK3576_PD_SDGMAC { 1114 reg = <RK3576_PD_SDGMAC>; 1115 clocks = <&cru ACLK_HSGPIO>, 1116 <&cru ACLK_GMAC0>, 1117 <&cru ACLK_GMAC1>, 1118 <&cru CCLK_SRC_SDIO>, 1119 <&cru CCLK_SRC_SDMMC0>, 1120 <&cru HCLK_HSGPIO>, 1121 <&cru HCLK_SDIO>, 1122 <&cru HCLK_SDMMC0>, 1123 <&cru PCLK_SDGMAC_ROOT>; 1124 pm_qos = <&qos_fspi1>, 1125 <&qos_gmac0>, 1126 <&qos_gmac1>, 1127 <&qos_sdio>, 1128 <&qos_sdmmc>, 1129 <&qos_flexbus>; 1130 #power-domain-cells = <0>; 1131 }; 1132 }; 1133 1134 power-domain@RK3576_PD_PHP { 1135 reg = <RK3576_PD_PHP>; 1136 clocks = <&cru ACLK_PHP_ROOT>, 1137 <&cru PCLK_PHP_ROOT>, 1138 <&cru ACLK_MMU0>, 1139 <&cru ACLK_MMU1>; 1140 pm_qos = <&qos_mmu0>, 1141 <&qos_mmu1>; 1142 #power-domain-cells = <1>; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 1146 power-domain@RK3576_PD_SUBPHP { 1147 reg = <RK3576_PD_SUBPHP>; 1148 #power-domain-cells = <0>; 1149 }; 1150 }; 1151 1152 power-domain@RK3576_PD_AUDIO { 1153 reg = <RK3576_PD_AUDIO>; 1154 #power-domain-cells = <0>; 1155 }; 1156 1157 power-domain@RK3576_PD_VEPU1 { 1158 reg = <RK3576_PD_VEPU1>; 1159 clocks = <&cru ACLK_VEPU1>, 1160 <&cru HCLK_VEPU1>; 1161 pm_qos = <&qos_vepu1>; 1162 #power-domain-cells = <0>; 1163 }; 1164 1165 power-domain@RK3576_PD_VPU { 1166 reg = <RK3576_PD_VPU>; 1167 clocks = <&cru ACLK_EBC>, 1168 <&cru HCLK_EBC>, 1169 <&cru ACLK_JPEG>, 1170 <&cru HCLK_JPEG>, 1171 <&cru ACLK_RGA2E_0>, 1172 <&cru HCLK_RGA2E_0>, 1173 <&cru ACLK_RGA2E_1>, 1174 <&cru HCLK_RGA2E_1>, 1175 <&cru ACLK_VDPP>, 1176 <&cru HCLK_VDPP>; 1177 pm_qos = <&qos_ebc>, 1178 <&qos_jpeg>, 1179 <&qos_rga0>, 1180 <&qos_rga1>, 1181 <&qos_vdpp>; 1182 #power-domain-cells = <0>; 1183 }; 1184 1185 power-domain@RK3576_PD_VDEC { 1186 reg = <RK3576_PD_VDEC>; 1187 clocks = <&cru ACLK_RKVDEC_ROOT>, 1188 <&cru HCLK_RKVDEC>; 1189 pm_qos = <&qos_rkvdec>; 1190 #power-domain-cells = <0>; 1191 }; 1192 1193 power-domain@RK3576_PD_VI { 1194 reg = <RK3576_PD_VI>; 1195 clocks = <&cru ACLK_VICAP>, 1196 <&cru HCLK_VICAP>, 1197 <&cru DCLK_VICAP>, 1198 <&cru ACLK_VI_ROOT>, 1199 <&cru HCLK_VI_ROOT>, 1200 <&cru PCLK_VI_ROOT>, 1201 <&cru CLK_ISP_CORE>, 1202 <&cru ACLK_ISP>, 1203 <&cru HCLK_ISP>, 1204 <&cru CLK_CORE_VPSS>, 1205 <&cru ACLK_VPSS>, 1206 <&cru HCLK_VPSS>; 1207 pm_qos = <&qos_isp_mro>, 1208 <&qos_isp_mwo>, 1209 <&qos_vicap_m0>, 1210 <&qos_vpss_mro>, 1211 <&qos_vpss_mwo>; 1212 #power-domain-cells = <1>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 1216 power-domain@RK3576_PD_VEPU0 { 1217 reg = <RK3576_PD_VEPU0>; 1218 clocks = <&cru ACLK_VEPU0>, 1219 <&cru HCLK_VEPU0>; 1220 pm_qos = <&qos_vepu0>; 1221 #power-domain-cells = <0>; 1222 }; 1223 }; 1224 1225 power-domain@RK3576_PD_VOP { 1226 reg = <RK3576_PD_VOP>; 1227 clocks = <&cru ACLK_VOP>, 1228 <&cru HCLK_VOP>, 1229 <&cru HCLK_VOP_ROOT>, 1230 <&cru PCLK_VOP_ROOT>; 1231 pm_qos = <&qos_vop_m0>, 1232 <&qos_vop_m1ro>; 1233 #power-domain-cells = <1>; 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 1237 power-domain@RK3576_PD_USB { 1238 reg = <RK3576_PD_USB>; 1239 clocks = <&cru PCLK_PHP_ROOT>, 1240 <&cru ACLK_USB_ROOT>, 1241 <&cru ACLK_MMU2>, 1242 <&cru ACLK_SLV_MMU2>, 1243 <&cru ACLK_UFS_SYS>; 1244 pm_qos = <&qos_mmu2>, 1245 <&qos_ufshc>; 1246 #power-domain-cells = <0>; 1247 }; 1248 1249 power-domain@RK3576_PD_VO0 { 1250 reg = <RK3576_PD_VO0>; 1251 clocks = <&cru ACLK_HDCP0>, 1252 <&cru HCLK_HDCP0>, 1253 <&cru ACLK_VO0_ROOT>, 1254 <&cru PCLK_VO0_ROOT>, 1255 <&cru HCLK_VOP_ROOT>; 1256 pm_qos = <&qos_hdcp0>; 1257 #power-domain-cells = <0>; 1258 }; 1259 1260 power-domain@RK3576_PD_VO1 { 1261 reg = <RK3576_PD_VO1>; 1262 clocks = <&cru ACLK_HDCP1>, 1263 <&cru HCLK_HDCP1>, 1264 <&cru ACLK_VO1_ROOT>, 1265 <&cru PCLK_VO1_ROOT>, 1266 <&cru HCLK_VOP_ROOT>; 1267 pm_qos = <&qos_hdcp1>; 1268 #power-domain-cells = <0>; 1269 }; 1270 }; 1271 }; 1272 }; 1273 1274 gpu: gpu@27800000 { 1275 compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; 1276 reg = <0x0 0x27800000 0x0 0x200000>; 1277 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 1278 assigned-clock-rates = <198000000>; 1279 clocks = <&cru CLK_GPU>; 1280 clock-names = "core"; 1281 dynamic-power-coefficient = <1625>; 1282 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 1285 interrupt-names = "job", "mmu", "gpu"; 1286 operating-points-v2 = <&gpu_opp_table>; 1287 power-domains = <&power RK3576_PD_GPU>; 1288 #cooling-cells = <2>; 1289 status = "disabled"; 1290 }; 1291 1292 vop: vop@27d00000 { 1293 compatible = "rockchip,rk3576-vop"; 1294 reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; 1295 reg-names = "vop", "gamma-lut"; 1296 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1300 interrupt-names = "sys", 1301 "vp0", 1302 "vp1", 1303 "vp2"; 1304 clocks = <&cru ACLK_VOP>, 1305 <&cru HCLK_VOP>, 1306 <&cru DCLK_VP0>, 1307 <&cru DCLK_VP1>, 1308 <&cru DCLK_VP2>, 1309 <&hdptxphy>; 1310 clock-names = "aclk", 1311 "hclk", 1312 "dclk_vp0", 1313 "dclk_vp1", 1314 "dclk_vp2", 1315 "pll_hdmiphy0"; 1316 iommus = <&vop_mmu>; 1317 power-domains = <&power RK3576_PD_VOP>; 1318 rockchip,grf = <&sys_grf>; 1319 rockchip,pmu = <&pmu>; 1320 status = "disabled"; 1321 1322 vop_out: ports { 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 1326 vp0: port@0 { 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 reg = <0>; 1330 }; 1331 1332 vp1: port@1 { 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 reg = <1>; 1336 }; 1337 1338 vp2: port@2 { 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 reg = <2>; 1342 }; 1343 }; 1344 }; 1345 1346 vop_mmu: iommu@27d07e00 { 1347 compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; 1348 reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>; 1349 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 1350 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1351 clock-names = "aclk", "iface"; 1352 #iommu-cells = <0>; 1353 power-domains = <&power RK3576_PD_VOP>; 1354 status = "disabled"; 1355 }; 1356 1357 sai5: sai@27d40000 { 1358 compatible = "rockchip,rk3576-sai"; 1359 reg = <0x0 0x27d40000 0x0 0x1000>; 1360 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1361 clocks = <&cru MCLK_SAI5_8CH>, <&cru HCLK_SAI5_8CH>; 1362 clock-names = "mclk", "hclk"; 1363 dmas = <&dmac2 3>; 1364 dma-names = "rx"; 1365 power-domains = <&power RK3576_PD_VO0>; 1366 resets = <&cru SRST_M_SAI5_8CH>, <&cru SRST_H_SAI5_8CH>; 1367 reset-names = "m", "h"; 1368 rockchip,sai-rx-route = <0 1 2 3>; 1369 #sound-dai-cells = <0>; 1370 sound-name-prefix = "SAI5"; 1371 status = "disabled"; 1372 }; 1373 1374 sai6: sai@27d50000 { 1375 compatible = "rockchip,rk3576-sai"; 1376 reg = <0x0 0x27d50000 0x0 0x1000>; 1377 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1378 clocks = <&cru MCLK_SAI6_8CH>, <&cru HCLK_SAI6_8CH>; 1379 clock-names = "mclk", "hclk"; 1380 dmas = <&dmac2 4>, <&dmac2 5>; 1381 dma-names = "tx", "rx"; 1382 power-domains = <&power RK3576_PD_VO0>; 1383 resets = <&cru SRST_M_SAI6_8CH>, <&cru SRST_H_SAI6_8CH>; 1384 reset-names = "m", "h"; 1385 rockchip,sai-rx-route = <0 1 2 3>; 1386 rockchip,sai-tx-route = <0 1 2 3>; 1387 #sound-dai-cells = <0>; 1388 sound-name-prefix = "SAI6"; 1389 status = "disabled"; 1390 }; 1391 1392 dsi: dsi@27d80000 { 1393 compatible = "rockchip,rk3576-mipi-dsi2"; 1394 reg = <0x0 0x27d80000 0x0 0x10000>; 1395 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 1396 clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; 1397 clock-names = "pclk", "sys"; 1398 power-domains = <&power RK3576_PD_VO0>; 1399 resets = <&cru SRST_P_DSIHOST0>; 1400 reset-names = "apb"; 1401 phys = <&mipidcphy PHY_TYPE_DPHY>; 1402 phy-names = "dcphy"; 1403 rockchip,grf = <&vo0_grf>; 1404 status = "disabled"; 1405 1406 ports { 1407 #address-cells = <1>; 1408 #size-cells = <0>; 1409 1410 dsi_in: port@0 { 1411 reg = <0>; 1412 }; 1413 1414 dsi_out: port@1 { 1415 reg = <1>; 1416 }; 1417 }; 1418 }; 1419 1420 hdmi: hdmi@27da0000 { 1421 compatible = "rockchip,rk3576-dw-hdmi-qp"; 1422 reg = <0x0 0x27da0000 0x0 0x20000>; 1423 clocks = <&cru PCLK_HDMITX0>, 1424 <&cru CLK_HDMITX0_EARC>, 1425 <&cru CLK_HDMITX0_REF>, 1426 <&cru MCLK_SAI6_8CH>, 1427 <&cru CLK_HDMITXHDP>, 1428 <&cru HCLK_VO0_ROOT>; 1429 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; 1430 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 1435 interrupt-names = "avp", "cec", "earc", "main", "hpd"; 1436 phys = <&hdptxphy>; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>; 1439 power-domains = <&power RK3576_PD_VO0>; 1440 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>; 1441 reset-names = "ref", "hdp"; 1442 rockchip,grf = <&ioc_grf>; 1443 rockchip,vo-grf = <&vo0_grf>; 1444 #sound-dai-cells = <0>; 1445 status = "disabled"; 1446 1447 ports { 1448 #address-cells = <1>; 1449 #size-cells = <0>; 1450 1451 hdmi_in: port@0 { 1452 reg = <0>; 1453 }; 1454 1455 hdmi_out: port@1 { 1456 reg = <1>; 1457 }; 1458 }; 1459 }; 1460 1461 sai7: sai@27ed0000 { 1462 compatible = "rockchip,rk3576-sai"; 1463 reg = <0x0 0x27ed0000 0x0 0x1000>; 1464 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1465 clocks = <&cru MCLK_SAI7_8CH>, <&cru HCLK_SAI7_8CH>; 1466 clock-names = "mclk", "hclk"; 1467 dmas = <&dmac2 19>; 1468 dma-names = "tx"; 1469 power-domains = <&power RK3576_PD_VO1>; 1470 resets = <&cru SRST_M_SAI7_8CH>, <&cru SRST_H_SAI7_8CH>; 1471 reset-names = "m", "h"; 1472 rockchip,sai-tx-route = <0 1 2 3>; 1473 #sound-dai-cells = <0>; 1474 sound-name-prefix = "SAI7"; 1475 status = "disabled"; 1476 }; 1477 1478 sai8: sai@27ee0000 { 1479 compatible = "rockchip,rk3576-sai"; 1480 reg = <0x0 0x27ee0000 0x0 0x1000>; 1481 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1482 clocks = <&cru MCLK_SAI8_8CH>, <&cru HCLK_SAI8_8CH>; 1483 clock-names = "mclk", "hclk"; 1484 dmas = <&dmac1 7>; 1485 dma-names = "tx"; 1486 power-domains = <&power RK3576_PD_VO1>; 1487 resets = <&cru SRST_M_SAI8_8CH>, <&cru SRST_H_SAI8_8CH>; 1488 reset-names = "m", "h"; 1489 rockchip,sai-tx-route = <0 1 2 3>; 1490 #sound-dai-cells = <0>; 1491 sound-name-prefix = "SAI8"; 1492 status = "disabled"; 1493 }; 1494 1495 sai9: sai@27ef0000 { 1496 compatible = "rockchip,rk3576-sai"; 1497 reg = <0x0 0x27ef0000 0x0 0x1000>; 1498 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1499 clocks = <&cru MCLK_SAI9_8CH>, <&cru HCLK_SAI9_8CH>; 1500 clock-names = "mclk", "hclk"; 1501 dmas = <&dmac0 26>; 1502 dma-names = "tx"; 1503 power-domains = <&power RK3576_PD_VO1>; 1504 resets = <&cru SRST_M_SAI9_8CH>, <&cru SRST_H_SAI9_8CH>; 1505 reset-names = "m", "h"; 1506 rockchip,sai-tx-route = <0 1 2 3>; 1507 #sound-dai-cells = <0>; 1508 sound-name-prefix = "SAI9"; 1509 status = "disabled"; 1510 }; 1511 1512 qos_hdcp1: qos@27f02000 { 1513 compatible = "rockchip,rk3576-qos", "syscon"; 1514 reg = <0x0 0x27f02000 0x0 0x20>; 1515 }; 1516 1517 qos_fspi1: qos@27f04000 { 1518 compatible = "rockchip,rk3576-qos", "syscon"; 1519 reg = <0x0 0x27f04000 0x0 0x20>; 1520 }; 1521 1522 qos_gmac0: qos@27f04080 { 1523 compatible = "rockchip,rk3576-qos", "syscon"; 1524 reg = <0x0 0x27f04080 0x0 0x20>; 1525 }; 1526 1527 qos_gmac1: qos@27f04100 { 1528 compatible = "rockchip,rk3576-qos", "syscon"; 1529 reg = <0x0 0x27f04100 0x0 0x20>; 1530 }; 1531 1532 qos_sdio: qos@27f04180 { 1533 compatible = "rockchip,rk3576-qos", "syscon"; 1534 reg = <0x0 0x27f04180 0x0 0x20>; 1535 }; 1536 1537 qos_sdmmc: qos@27f04200 { 1538 compatible = "rockchip,rk3576-qos", "syscon"; 1539 reg = <0x0 0x27f04200 0x0 0x20>; 1540 }; 1541 1542 qos_flexbus: qos@27f04280 { 1543 compatible = "rockchip,rk3576-qos", "syscon"; 1544 reg = <0x0 0x27f04280 0x0 0x20>; 1545 }; 1546 1547 qos_gpu: qos@27f05000 { 1548 compatible = "rockchip,rk3576-qos", "syscon"; 1549 reg = <0x0 0x27f05000 0x0 0x20>; 1550 }; 1551 1552 qos_vepu1: qos@27f06000 { 1553 compatible = "rockchip,rk3576-qos", "syscon"; 1554 reg = <0x0 0x27f06000 0x0 0x20>; 1555 }; 1556 1557 qos_npu_mcu: qos@27f08000 { 1558 compatible = "rockchip,rk3576-qos", "syscon"; 1559 reg = <0x0 0x27f08000 0x0 0x20>; 1560 }; 1561 1562 qos_npu_nsp0: qos@27f08080 { 1563 compatible = "rockchip,rk3576-qos", "syscon"; 1564 reg = <0x0 0x27f08080 0x0 0x20>; 1565 }; 1566 1567 qos_npu_nsp1: qos@27f08100 { 1568 compatible = "rockchip,rk3576-qos", "syscon"; 1569 reg = <0x0 0x27f08100 0x0 0x20>; 1570 }; 1571 1572 qos_emmc: qos@27f09000 { 1573 compatible = "rockchip,rk3576-qos", "syscon"; 1574 reg = <0x0 0x27f09000 0x0 0x20>; 1575 }; 1576 1577 qos_fspi0: qos@27f09080 { 1578 compatible = "rockchip,rk3576-qos", "syscon"; 1579 reg = <0x0 0x27f09080 0x0 0x20>; 1580 }; 1581 1582 qos_mmu0: qos@27f0a000 { 1583 compatible = "rockchip,rk3576-qos", "syscon"; 1584 reg = <0x0 0x27f0a000 0x0 0x20>; 1585 }; 1586 1587 qos_mmu1: qos@27f0a080 { 1588 compatible = "rockchip,rk3576-qos", "syscon"; 1589 reg = <0x0 0x27f0a080 0x0 0x20>; 1590 }; 1591 1592 qos_rkvdec: qos@27f0c000 { 1593 compatible = "rockchip,rk3576-qos", "syscon"; 1594 reg = <0x0 0x27f0c000 0x0 0x20>; 1595 }; 1596 1597 qos_crypto: qos@27f0d000 { 1598 compatible = "rockchip,rk3576-qos", "syscon"; 1599 reg = <0x0 0x27f0d000 0x0 0x20>; 1600 }; 1601 1602 qos_mmu2: qos@27f0e000 { 1603 compatible = "rockchip,rk3576-qos", "syscon"; 1604 reg = <0x0 0x27f0e000 0x0 0x20>; 1605 }; 1606 1607 qos_ufshc: qos@27f0e080 { 1608 compatible = "rockchip,rk3576-qos", "syscon"; 1609 reg = <0x0 0x27f0e080 0x0 0x20>; 1610 }; 1611 1612 qos_vepu0: qos@27f0f000 { 1613 compatible = "rockchip,rk3576-qos", "syscon"; 1614 reg = <0x0 0x27f0f000 0x0 0x20>; 1615 }; 1616 1617 qos_isp_mro: qos@27f10000 { 1618 compatible = "rockchip,rk3576-qos", "syscon"; 1619 reg = <0x0 0x27f10000 0x0 0x20>; 1620 }; 1621 1622 qos_isp_mwo: qos@27f10080 { 1623 compatible = "rockchip,rk3576-qos", "syscon"; 1624 reg = <0x0 0x27f10080 0x0 0x20>; 1625 }; 1626 1627 qos_vicap_m0: qos@27f10100 { 1628 compatible = "rockchip,rk3576-qos", "syscon"; 1629 reg = <0x0 0x27f10100 0x0 0x20>; 1630 }; 1631 1632 qos_vpss_mro: qos@27f10180 { 1633 compatible = "rockchip,rk3576-qos", "syscon"; 1634 reg = <0x0 0x27f10180 0x0 0x20>; 1635 }; 1636 1637 qos_vpss_mwo: qos@27f10200 { 1638 compatible = "rockchip,rk3576-qos", "syscon"; 1639 reg = <0x0 0x27f10200 0x0 0x20>; 1640 }; 1641 1642 qos_hdcp0: qos@27f11000 { 1643 compatible = "rockchip,rk3576-qos", "syscon"; 1644 reg = <0x0 0x27f11000 0x0 0x20>; 1645 }; 1646 1647 qos_vop_m0: qos@27f12800 { 1648 compatible = "rockchip,rk3576-qos", "syscon"; 1649 reg = <0x0 0x27f12800 0x0 0x20>; 1650 }; 1651 1652 qos_vop_m1ro: qos@27f12880 { 1653 compatible = "rockchip,rk3576-qos", "syscon"; 1654 reg = <0x0 0x27f12880 0x0 0x20>; 1655 }; 1656 1657 qos_ebc: qos@27f13000 { 1658 compatible = "rockchip,rk3576-qos", "syscon"; 1659 reg = <0x0 0x27f13000 0x0 0x20>; 1660 }; 1661 1662 qos_rga0: qos@27f13080 { 1663 compatible = "rockchip,rk3576-qos", "syscon"; 1664 reg = <0x0 0x27f13080 0x0 0x20>; 1665 }; 1666 1667 qos_rga1: qos@27f13100 { 1668 compatible = "rockchip,rk3576-qos", "syscon"; 1669 reg = <0x0 0x27f13100 0x0 0x20>; 1670 }; 1671 1672 qos_jpeg: qos@27f13180 { 1673 compatible = "rockchip,rk3576-qos", "syscon"; 1674 reg = <0x0 0x27f13180 0x0 0x20>; 1675 }; 1676 1677 qos_vdpp: qos@27f13200 { 1678 compatible = "rockchip,rk3576-qos", "syscon"; 1679 reg = <0x0 0x27f13200 0x0 0x20>; 1680 }; 1681 1682 qos_npu_m0: qos@27f20000 { 1683 compatible = "rockchip,rk3576-qos", "syscon"; 1684 reg = <0x0 0x27f20000 0x0 0x20>; 1685 }; 1686 1687 qos_npu_m1: qos@27f21000 { 1688 compatible = "rockchip,rk3576-qos", "syscon"; 1689 reg = <0x0 0x27f21000 0x0 0x20>; 1690 }; 1691 1692 qos_npu_m0ro: qos@27f22080 { 1693 compatible = "rockchip,rk3576-qos", "syscon"; 1694 reg = <0x0 0x27f22080 0x0 0x20>; 1695 }; 1696 1697 qos_npu_m1ro: qos@27f22100 { 1698 compatible = "rockchip,rk3576-qos", "syscon"; 1699 reg = <0x0 0x27f22100 0x0 0x20>; 1700 }; 1701 1702 gmac0: ethernet@2a220000 { 1703 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 1704 reg = <0x0 0x2a220000 0x0 0x10000>; 1705 clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>, 1706 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 1707 <&cru CLK_GMAC0_PTP_REF>; 1708 clock-names = "stmmaceth", "clk_mac_ref", 1709 "pclk_mac", "aclk_mac", 1710 "ptp_ref"; 1711 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1713 interrupt-names = "macirq", "eth_wake_irq"; 1714 power-domains = <&power RK3576_PD_SDGMAC>; 1715 resets = <&cru SRST_A_GMAC0>; 1716 reset-names = "stmmaceth"; 1717 rockchip,grf = <&sdgmac_grf>; 1718 rockchip,php-grf = <&ioc_grf>; 1719 snps,axi-config = <&gmac0_stmmac_axi_setup>; 1720 snps,mixed-burst; 1721 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 1722 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 1723 snps,tso; 1724 status = "disabled"; 1725 1726 mdio0: mdio { 1727 compatible = "snps,dwmac-mdio"; 1728 #address-cells = <0x1>; 1729 #size-cells = <0x0>; 1730 }; 1731 1732 gmac0_stmmac_axi_setup: stmmac-axi-config { 1733 snps,blen = <0 0 0 0 16 8 4>; 1734 snps,rd_osr_lmt = <8>; 1735 snps,wr_osr_lmt = <4>; 1736 }; 1737 1738 gmac0_mtl_rx_setup: rx-queues-config { 1739 snps,rx-queues-to-use = <1>; 1740 queue0 {}; 1741 }; 1742 1743 gmac0_mtl_tx_setup: tx-queues-config { 1744 snps,tx-queues-to-use = <1>; 1745 queue0 {}; 1746 }; 1747 }; 1748 1749 gmac1: ethernet@2a230000 { 1750 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 1751 reg = <0x0 0x2a230000 0x0 0x10000>; 1752 clocks = <&cru CLK_GMAC1_125M_SRC>, <&cru CLK_GMAC1_RMII_CRU>, 1753 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1754 <&cru CLK_GMAC1_PTP_REF>; 1755 clock-names = "stmmaceth", "clk_mac_ref", 1756 "pclk_mac", "aclk_mac", 1757 "ptp_ref"; 1758 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1760 interrupt-names = "macirq", "eth_wake_irq"; 1761 power-domains = <&power RK3576_PD_SDGMAC>; 1762 resets = <&cru SRST_A_GMAC1>; 1763 reset-names = "stmmaceth"; 1764 rockchip,grf = <&sdgmac_grf>; 1765 rockchip,php-grf = <&ioc_grf>; 1766 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1767 snps,mixed-burst; 1768 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1769 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1770 snps,tso; 1771 status = "disabled"; 1772 1773 mdio1: mdio { 1774 compatible = "snps,dwmac-mdio"; 1775 #address-cells = <0x1>; 1776 #size-cells = <0x0>; 1777 }; 1778 1779 gmac1_stmmac_axi_setup: stmmac-axi-config { 1780 snps,blen = <0 0 0 0 16 8 4>; 1781 snps,rd_osr_lmt = <8>; 1782 snps,wr_osr_lmt = <4>; 1783 }; 1784 1785 gmac1_mtl_rx_setup: rx-queues-config { 1786 snps,rx-queues-to-use = <1>; 1787 queue0 {}; 1788 }; 1789 1790 gmac1_mtl_tx_setup: tx-queues-config { 1791 snps,tx-queues-to-use = <1>; 1792 queue0 {}; 1793 }; 1794 }; 1795 1796 sata0: sata@2a240000 { 1797 compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci"; 1798 reg = <0x0 0x2a240000 0x0 0x1000>; 1799 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1800 <&cru CLK_RXOOB0>; 1801 clock-names = "sata", "pmalive", "rxoob"; 1802 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 1803 power-domains = <&power RK3576_PD_SUBPHP>; 1804 phys = <&combphy0_ps PHY_TYPE_SATA>; 1805 phy-names = "sata-phy"; 1806 ports-implemented = <0x1>; 1807 dma-coherent; 1808 status = "disabled"; 1809 }; 1810 1811 sata1: sata@2a250000 { 1812 compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci"; 1813 reg = <0x0 0x2a250000 0x0 0x1000>; 1814 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, 1815 <&cru CLK_RXOOB1>; 1816 clock-names = "sata", "pmalive", "rxoob"; 1817 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1818 power-domains = <&power RK3576_PD_SUBPHP>; 1819 phys = <&combphy1_psu PHY_TYPE_SATA>; 1820 phy-names = "sata-phy"; 1821 ports-implemented = <0x1>; 1822 dma-coherent; 1823 status = "disabled"; 1824 }; 1825 1826 ufshc: ufshc@2a2d0000 { 1827 compatible = "rockchip,rk3576-ufshc"; 1828 reg = <0x0 0x2a2d0000 0x0 0x10000>, 1829 <0x0 0x2b040000 0x0 0x10000>, 1830 <0x0 0x2601f000 0x0 0x1000>, 1831 <0x0 0x2603c000 0x0 0x1000>, 1832 <0x0 0x2a2e0000 0x0 0x10000>; 1833 reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; 1834 clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, 1835 <&cru CLK_REF_UFS_CLKOUT>; 1836 clock-names = "core", "pclk", "pclk_mphy", "ref_out"; 1837 assigned-clocks = <&cru CLK_REF_OSC_MPHY>; 1838 assigned-clock-parents = <&cru CLK_REF_MPHY_26M>; 1839 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1840 power-domains = <&power RK3576_PD_USB>; 1841 pinctrl-0 = <&ufs_refclk>; 1842 pinctrl-names = "default"; 1843 resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, 1844 <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; 1845 reset-names = "biu", "sys", "ufs", "grf"; 1846 reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; 1847 status = "disabled"; 1848 }; 1849 1850 sfc1: spi@2a300000 { 1851 compatible = "rockchip,sfc"; 1852 reg = <0x0 0x2a300000 0x0 0x4000>; 1853 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1854 clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>; 1855 clock-names = "clk_sfc", "hclk_sfc"; 1856 power-domains = <&power RK3576_PD_SDGMAC>; 1857 #address-cells = <1>; 1858 #size-cells = <0>; 1859 status = "disabled"; 1860 }; 1861 1862 sdmmc: mmc@2a310000 { 1863 compatible = "rockchip,rk3576-dw-mshc"; 1864 reg = <0x0 0x2a310000 0x0 0x4000>; 1865 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; 1866 clock-names = "biu", "ciu"; 1867 fifo-depth = <0x100>; 1868 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 1869 max-frequency = <200000000>; 1870 pinctrl-names = "default"; 1871 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>; 1872 power-domains = <&power RK3576_PD_SDGMAC>; 1873 resets = <&cru SRST_H_SDMMC0>; 1874 reset-names = "reset"; 1875 status = "disabled"; 1876 }; 1877 1878 sdio: mmc@2a320000 { 1879 compatible = "rockchip,rk3576-dw-mshc"; 1880 reg = <0x0 0x2a320000 0x0 0x4000>; 1881 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>; 1882 clock-names = "biu", "ciu"; 1883 fifo-depth = <0x100>; 1884 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 1885 max-frequency = <200000000>; 1886 pinctrl-0 = <&sdmmc1m0_clk &sdmmc1m0_cmd &sdmmc1m0_bus4>; 1887 pinctrl-names = "default"; 1888 power-domains = <&power RK3576_PD_SDGMAC>; 1889 resets = <&cru SRST_H_SDIO>; 1890 reset-names = "reset"; 1891 status = "disabled"; 1892 }; 1893 1894 sdhci: mmc@2a330000 { 1895 compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc"; 1896 reg = <0x0 0x2a330000 0x0 0x10000>; 1897 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>; 1898 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1899 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 1900 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1901 <&cru TCLK_EMMC>; 1902 clock-names = "core", "bus", "axi", "block", "timer"; 1903 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 1904 max-frequency = <200000000>; 1905 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 1906 <&emmc_cmd>, <&emmc_strb>; 1907 pinctrl-names = "default"; 1908 power-domains = <&power RK3576_PD_NVM>; 1909 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1910 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1911 <&cru SRST_T_EMMC>; 1912 reset-names = "core", "bus", "axi", "block", "timer"; 1913 supports-cqe; 1914 status = "disabled"; 1915 }; 1916 1917 sfc0: spi@2a340000 { 1918 compatible = "rockchip,sfc"; 1919 reg = <0x0 0x2a340000 0x0 0x4000>; 1920 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1921 clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>; 1922 clock-names = "clk_sfc", "hclk_sfc"; 1923 power-domains = <&power RK3576_PD_NVM>; 1924 #address-cells = <1>; 1925 #size-cells = <0>; 1926 status = "disabled"; 1927 }; 1928 1929 rng: rng@2a410000 { 1930 compatible = "rockchip,rk3576-rng"; 1931 reg = <0x0 0x2a410000 0x0 0x200>; 1932 clocks = <&cru HCLK_TRNG_NS>; 1933 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 1934 resets = <&cru SRST_H_TRNG_NS>; 1935 }; 1936 1937 otp: otp@2a580000 { 1938 compatible = "rockchip,rk3576-otp"; 1939 reg = <0x0 0x2a580000 0x0 0x400>; 1940 #address-cells = <1>; 1941 #size-cells = <1>; 1942 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 1943 <&cru CLK_OTP_PHY_G>; 1944 clock-names = "otp", "apb_pclk", "phy"; 1945 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>; 1946 reset-names = "otp", "apb"; 1947 1948 /* Data cells */ 1949 cpu_code: cpu-code@2 { 1950 reg = <0x02 0x2>; 1951 }; 1952 otp_cpu_version: cpu-version@5 { 1953 reg = <0x05 0x1>; 1954 bits = <3 3>; 1955 }; 1956 otp_id: id@a { 1957 reg = <0x0a 0x10>; 1958 }; 1959 cpub_leakage: cpub-leakage@1e { 1960 reg = <0x1e 0x1>; 1961 }; 1962 cpul_leakage: cpul-leakage@1f { 1963 reg = <0x1f 0x1>; 1964 }; 1965 npu_leakage: npu-leakage@20 { 1966 reg = <0x20 0x1>; 1967 }; 1968 gpu_leakage: gpu-leakage@21 { 1969 reg = <0x21 0x1>; 1970 }; 1971 log_leakage: log-leakage@22 { 1972 reg = <0x22 0x1>; 1973 }; 1974 bigcore_tsadc_trim: bigcore-tsadc-trim@24 { 1975 reg = <0x24 0x2>; 1976 bits = <0 10>; 1977 }; 1978 litcore_tsadc_trim: litcore-tsadc-trim@26 { 1979 reg = <0x26 0x2>; 1980 bits = <0 10>; 1981 }; 1982 ddr_tsadc_trim: ddr-tsadc-trim@28 { 1983 reg = <0x28 0x2>; 1984 bits = <0 10>; 1985 }; 1986 npu_tsadc_trim: npu-tsadc-trim@2a { 1987 reg = <0x2a 0x2>; 1988 bits = <0 10>; 1989 }; 1990 gpu_tsadc_trim: gpu-tsadc-trim@2c { 1991 reg = <0x2c 0x2>; 1992 bits = <0 10>; 1993 }; 1994 soc_tsadc_trim: soc-tsadc-trim@64 { 1995 reg = <0x64 0x2>; 1996 bits = <0 10>; 1997 }; 1998 }; 1999 2000 sai0: sai@2a600000 { 2001 compatible = "rockchip,rk3576-sai"; 2002 reg = <0x0 0x2a600000 0x0 0x1000>; 2003 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2004 clocks = <&cru MCLK_SAI0_8CH>, <&cru HCLK_SAI0_8CH>; 2005 clock-names = "mclk", "hclk"; 2006 dmas = <&dmac0 0>, <&dmac0 1>; 2007 dma-names = "tx", "rx"; 2008 power-domains = <&power RK3576_PD_AUDIO>; 2009 resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>; 2010 reset-names = "m", "h"; 2011 pinctrl-names = "default"; 2012 pinctrl-0 = <&sai0m0_lrck 2013 &sai0m0_sclk 2014 &sai0m0_sdi0 2015 &sai0m0_sdi1 2016 &sai0m0_sdi2 2017 &sai0m0_sdi3 2018 &sai0m0_sdo0 2019 &sai0m0_sdo1 2020 &sai0m0_sdo2 2021 &sai0m0_sdo3>; 2022 #sound-dai-cells = <0>; 2023 sound-name-prefix = "SAI0"; 2024 status = "disabled"; 2025 }; 2026 2027 sai1: sai@2a610000 { 2028 compatible = "rockchip,rk3576-sai"; 2029 reg = <0x0 0x2a610000 0x0 0x1000>; 2030 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2031 clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>; 2032 clock-names = "mclk", "hclk"; 2033 dmas = <&dmac0 2>, <&dmac0 3>; 2034 dma-names = "tx", "rx"; 2035 power-domains = <&power RK3576_PD_AUDIO>; 2036 resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>; 2037 reset-names = "m", "h"; 2038 pinctrl-names = "default"; 2039 pinctrl-0 = <&sai1m0_lrck 2040 &sai1m0_sclk 2041 &sai1m0_sdi0 2042 &sai1m0_sdo0 2043 &sai1m0_sdo1 2044 &sai1m0_sdo2 2045 &sai1m0_sdo3>; 2046 #sound-dai-cells = <0>; 2047 sound-name-prefix = "SAI1"; 2048 status = "disabled"; 2049 }; 2050 2051 sai2: sai@2a620000 { 2052 compatible = "rockchip,rk3576-sai"; 2053 reg = <0x0 0x2a620000 0x0 0x1000>; 2054 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2055 clocks = <&cru MCLK_SAI2_2CH>, <&cru HCLK_SAI2_2CH>; 2056 clock-names = "mclk", "hclk"; 2057 dmas = <&dmac1 0>, <&dmac1 1>; 2058 dma-names = "tx", "rx"; 2059 power-domains = <&power RK3576_PD_AUDIO>; 2060 resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>; 2061 reset-names = "m", "h"; 2062 pinctrl-names = "default"; 2063 pinctrl-0 = <&sai2m0_lrck 2064 &sai2m0_sclk 2065 &sai2m0_sdi 2066 &sai2m0_sdo>; 2067 #sound-dai-cells = <0>; 2068 sound-name-prefix = "SAI2"; 2069 status = "disabled"; 2070 }; 2071 2072 sai3: sai@2a630000 { 2073 compatible = "rockchip,rk3576-sai"; 2074 reg = <0x0 0x2a630000 0x0 0x1000>; 2075 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2076 clocks = <&cru MCLK_SAI3_2CH>, <&cru HCLK_SAI3_2CH>; 2077 clock-names = "mclk", "hclk"; 2078 dmas = <&dmac1 2>, <&dmac1 3>; 2079 dma-names = "tx", "rx"; 2080 power-domains = <&power RK3576_PD_AUDIO>; 2081 resets = <&cru SRST_M_SAI3_2CH>, <&cru SRST_H_SAI3_2CH>; 2082 reset-names = "m", "h"; 2083 pinctrl-names = "default"; 2084 pinctrl-0 = <&sai3m0_lrck 2085 &sai3m0_sclk 2086 &sai3m0_sdi 2087 &sai3m0_sdo>; 2088 #sound-dai-cells = <0>; 2089 sound-name-prefix = "SAI3"; 2090 status = "disabled"; 2091 }; 2092 2093 sai4: sai@2a640000 { 2094 compatible = "rockchip,rk3576-sai"; 2095 reg = <0x0 0x2a640000 0x0 0x1000>; 2096 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2097 clocks = <&cru MCLK_SAI4_2CH>, <&cru HCLK_SAI4_2CH>; 2098 clock-names = "mclk", "hclk"; 2099 dmas = <&dmac2 0>, <&dmac2 1>; 2100 dma-names = "tx", "rx"; 2101 power-domains = <&power RK3576_PD_AUDIO>; 2102 resets = <&cru SRST_M_SAI4_2CH>, <&cru SRST_H_SAI4_2CH>; 2103 reset-names = "m", "h"; 2104 pinctrl-names = "default"; 2105 pinctrl-0 = <&sai4m0_lrck 2106 &sai4m0_sclk 2107 &sai4m0_sdi 2108 &sai4m0_sdo>; 2109 #sound-dai-cells = <0>; 2110 sound-name-prefix = "SAI4"; 2111 status = "disabled"; 2112 }; 2113 2114 gic: interrupt-controller@2a701000 { 2115 compatible = "arm,gic-400"; 2116 reg = <0x0 0x2a701000 0 0x10000>, 2117 <0x0 0x2a702000 0 0x10000>, 2118 <0x0 0x2a704000 0 0x10000>, 2119 <0x0 0x2a706000 0 0x10000>; 2120 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2121 interrupt-controller; 2122 #interrupt-cells = <3>; 2123 #address-cells = <2>; 2124 #size-cells = <2>; 2125 }; 2126 2127 dmac0: dma-controller@2ab90000 { 2128 compatible = "arm,pl330", "arm,primecell"; 2129 reg = <0x0 0x2ab90000 0x0 0x4000>; 2130 arm,pl330-periph-burst; 2131 clocks = <&cru ACLK_DMAC0>; 2132 clock-names = "apb_pclk"; 2133 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2135 #dma-cells = <1>; 2136 }; 2137 2138 dmac1: dma-controller@2abb0000 { 2139 compatible = "arm,pl330", "arm,primecell"; 2140 reg = <0x0 0x2abb0000 0x0 0x4000>; 2141 arm,pl330-periph-burst; 2142 clocks = <&cru ACLK_DMAC1>; 2143 clock-names = "apb_pclk"; 2144 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 2146 #dma-cells = <1>; 2147 }; 2148 2149 dmac2: dma-controller@2abd0000 { 2150 compatible = "arm,pl330", "arm,primecell"; 2151 reg = <0x0 0x2abd0000 0x0 0x4000>; 2152 arm,pl330-periph-burst; 2153 clocks = <&cru ACLK_DMAC2>; 2154 clock-names = "apb_pclk"; 2155 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2157 #dma-cells = <1>; 2158 }; 2159 2160 i2c1: i2c@2ac40000 { 2161 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2162 reg = <0x0 0x2ac40000 0x0 0x1000>; 2163 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 2164 clock-names = "i2c", "pclk"; 2165 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 2166 pinctrl-names = "default"; 2167 pinctrl-0 = <&i2c1m0_xfer>; 2168 #address-cells = <1>; 2169 #size-cells = <0>; 2170 status = "disabled"; 2171 }; 2172 2173 i2c2: i2c@2ac50000 { 2174 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2175 reg = <0x0 0x2ac50000 0x0 0x1000>; 2176 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 2177 clock-names = "i2c", "pclk"; 2178 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 2179 pinctrl-names = "default"; 2180 pinctrl-0 = <&i2c2m0_xfer>; 2181 #address-cells = <1>; 2182 #size-cells = <0>; 2183 status = "disabled"; 2184 }; 2185 2186 i2c3: i2c@2ac60000 { 2187 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2188 reg = <0x0 0x2ac60000 0x0 0x1000>; 2189 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 2190 clock-names = "i2c", "pclk"; 2191 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 2192 pinctrl-names = "default"; 2193 pinctrl-0 = <&i2c3m0_xfer>; 2194 #address-cells = <1>; 2195 #size-cells = <0>; 2196 status = "disabled"; 2197 }; 2198 2199 i2c4: i2c@2ac70000 { 2200 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2201 reg = <0x0 0x2ac70000 0x0 0x1000>; 2202 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2203 clock-names = "i2c", "pclk"; 2204 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 2205 pinctrl-names = "default"; 2206 pinctrl-0 = <&i2c4m0_xfer>; 2207 #address-cells = <1>; 2208 #size-cells = <0>; 2209 status = "disabled"; 2210 }; 2211 2212 i2c5: i2c@2ac80000 { 2213 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2214 reg = <0x0 0x2ac80000 0x0 0x1000>; 2215 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2216 clock-names = "i2c", "pclk"; 2217 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 2218 pinctrl-names = "default"; 2219 pinctrl-0 = <&i2c5m0_xfer>; 2220 #address-cells = <1>; 2221 #size-cells = <0>; 2222 status = "disabled"; 2223 }; 2224 2225 i2c6: i2c@2ac90000 { 2226 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2227 reg = <0x0 0x2ac90000 0x0 0x1000>; 2228 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2229 clock-names = "i2c", "pclk"; 2230 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 2231 pinctrl-names = "default"; 2232 pinctrl-0 = <&i2c6m0_xfer>; 2233 #address-cells = <1>; 2234 #size-cells = <0>; 2235 status = "disabled"; 2236 }; 2237 2238 i2c7: i2c@2aca0000 { 2239 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2240 reg = <0x0 0x2aca0000 0x0 0x1000>; 2241 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2242 clock-names = "i2c", "pclk"; 2243 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2244 pinctrl-names = "default"; 2245 pinctrl-0 = <&i2c7m0_xfer>; 2246 #address-cells = <1>; 2247 #size-cells = <0>; 2248 status = "disabled"; 2249 }; 2250 2251 i2c8: i2c@2acb0000 { 2252 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2253 reg = <0x0 0x2acb0000 0x0 0x1000>; 2254 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2255 clock-names = "i2c", "pclk"; 2256 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2257 pinctrl-names = "default"; 2258 pinctrl-0 = <&i2c8m0_xfer>; 2259 #address-cells = <1>; 2260 #size-cells = <0>; 2261 status = "disabled"; 2262 }; 2263 2264 timer0: timer@2acc0000 { 2265 compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer"; 2266 reg = <0x0 0x2acc0000 0x0 0x20>; 2267 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_TIMER0>; 2268 clock-names = "pclk", "timer"; 2269 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2270 }; 2271 2272 wdt: watchdog@2ace0000 { 2273 compatible = "rockchip,rk3576-wdt", "snps,dw-wdt"; 2274 reg = <0x0 0x2ace0000 0x0 0x100>; 2275 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 2276 clock-names = "tclk", "pclk"; 2277 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 2278 }; 2279 2280 spi0: spi@2acf0000 { 2281 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2282 reg = <0x0 0x2acf0000 0x0 0x1000>; 2283 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 2284 clock-names = "spiclk", "apb_pclk"; 2285 dmas = <&dmac0 14>, <&dmac0 15>; 2286 dma-names = "tx", "rx"; 2287 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2288 num-cs = <2>; 2289 pinctrl-names = "default"; 2290 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; 2291 #address-cells = <1>; 2292 #size-cells = <0>; 2293 status = "disabled"; 2294 }; 2295 2296 spi1: spi@2ad00000 { 2297 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2298 reg = <0x0 0x2ad00000 0x0 0x1000>; 2299 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 2300 clock-names = "spiclk", "apb_pclk"; 2301 dmas = <&dmac0 16>, <&dmac0 17>; 2302 dma-names = "tx", "rx"; 2303 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 2304 num-cs = <2>; 2305 pinctrl-names = "default"; 2306 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; 2307 #address-cells = <1>; 2308 #size-cells = <0>; 2309 status = "disabled"; 2310 }; 2311 2312 spi2: spi@2ad10000 { 2313 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2314 reg = <0x0 0x2ad10000 0x0 0x1000>; 2315 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 2316 clock-names = "spiclk", "apb_pclk"; 2317 dmas = <&dmac1 15>, <&dmac1 16>; 2318 dma-names = "tx", "rx"; 2319 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2320 num-cs = <2>; 2321 pinctrl-names = "default"; 2322 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; 2323 #address-cells = <1>; 2324 #size-cells = <0>; 2325 status = "disabled"; 2326 }; 2327 2328 spi3: spi@2ad20000 { 2329 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2330 reg = <0x0 0x2ad20000 0x0 0x1000>; 2331 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 2332 clock-names = "spiclk", "apb_pclk"; 2333 dmas = <&dmac1 17>, <&dmac1 18>; 2334 dma-names = "tx", "rx"; 2335 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2336 num-cs = <2>; 2337 pinctrl-names = "default"; 2338 pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>; 2339 #address-cells = <1>; 2340 #size-cells = <0>; 2341 status = "disabled"; 2342 }; 2343 2344 spi4: spi@2ad30000 { 2345 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 2346 reg = <0x0 0x2ad30000 0x0 0x1000>; 2347 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2348 clock-names = "spiclk", "apb_pclk"; 2349 dmas = <&dmac2 12>, <&dmac2 13>; 2350 dma-names = "tx", "rx"; 2351 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 2352 num-cs = <2>; 2353 pinctrl-names = "default"; 2354 pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>; 2355 #address-cells = <1>; 2356 #size-cells = <0>; 2357 status = "disabled"; 2358 }; 2359 2360 uart0: serial@2ad40000 { 2361 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2362 reg = <0x0 0x2ad40000 0x0 0x100>; 2363 reg-shift = <2>; 2364 reg-io-width = <4>; 2365 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 2366 clock-names = "baudclk", "apb_pclk"; 2367 dmas = <&dmac0 6>, <&dmac0 7>; 2368 dma-names = "tx", "rx"; 2369 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 2370 pinctrl-0 = <&uart0m0_xfer>; 2371 pinctrl-names = "default"; 2372 status = "disabled"; 2373 }; 2374 2375 uart2: serial@2ad50000 { 2376 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2377 reg = <0x0 0x2ad50000 0x0 0x100>; 2378 reg-shift = <2>; 2379 reg-io-width = <4>; 2380 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 2381 clock-names = "baudclk", "apb_pclk"; 2382 dmas = <&dmac0 10>, <&dmac0 11>; 2383 dma-names = "tx", "rx"; 2384 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 2385 pinctrl-names = "default"; 2386 pinctrl-0 = <&uart2m0_xfer>; 2387 status = "disabled"; 2388 }; 2389 2390 uart3: serial@2ad60000 { 2391 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2392 reg = <0x0 0x2ad60000 0x0 0x100>; 2393 reg-shift = <2>; 2394 reg-io-width = <4>; 2395 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 2396 clock-names = "baudclk", "apb_pclk"; 2397 dmas = <&dmac0 12>, <&dmac0 13>; 2398 dma-names = "tx", "rx"; 2399 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 2400 pinctrl-0 = <&uart3m0_xfer>; 2401 pinctrl-names = "default"; 2402 status = "disabled"; 2403 }; 2404 2405 uart4: serial@2ad70000 { 2406 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2407 reg = <0x0 0x2ad70000 0x0 0x100>; 2408 reg-shift = <2>; 2409 reg-io-width = <4>; 2410 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 2411 clock-names = "baudclk", "apb_pclk"; 2412 dmas = <&dmac1 9>, <&dmac1 10>; 2413 dma-names = "tx", "rx"; 2414 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 2415 pinctrl-0 = <&uart4m0_xfer>; 2416 pinctrl-names = "default"; 2417 status = "disabled"; 2418 }; 2419 2420 uart5: serial@2ad80000 { 2421 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2422 reg = <0x0 0x2ad80000 0x0 0x100>; 2423 reg-shift = <2>; 2424 reg-io-width = <4>; 2425 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2426 clock-names = "baudclk", "apb_pclk"; 2427 dmas = <&dmac1 11>, <&dmac1 12>; 2428 dma-names = "tx", "rx"; 2429 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2430 pinctrl-0 = <&uart5m0_xfer>; 2431 pinctrl-names = "default"; 2432 status = "disabled"; 2433 }; 2434 2435 uart6: serial@2ad90000 { 2436 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2437 reg = <0x0 0x2ad90000 0x0 0x100>; 2438 reg-shift = <2>; 2439 reg-io-width = <4>; 2440 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2441 clock-names = "baudclk", "apb_pclk"; 2442 dmas = <&dmac1 13>, <&dmac1 14>; 2443 dma-names = "tx", "rx"; 2444 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2445 pinctrl-0 = <&uart6m0_xfer>; 2446 pinctrl-names = "default"; 2447 status = "disabled"; 2448 }; 2449 2450 uart7: serial@2ada0000 { 2451 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2452 reg = <0x0 0x2ada0000 0x0 0x100>; 2453 reg-shift = <2>; 2454 reg-io-width = <4>; 2455 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2456 clock-names = "baudclk", "apb_pclk"; 2457 dmas = <&dmac2 6>, <&dmac2 7>; 2458 dma-names = "tx", "rx"; 2459 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2460 pinctrl-0 = <&uart7m0_xfer>; 2461 pinctrl-names = "default"; 2462 status = "disabled"; 2463 }; 2464 2465 uart8: serial@2adb0000 { 2466 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2467 reg = <0x0 0x2adb0000 0x0 0x100>; 2468 reg-shift = <2>; 2469 reg-io-width = <4>; 2470 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2471 clock-names = "baudclk", "apb_pclk"; 2472 dmas = <&dmac2 8>, <&dmac2 9>; 2473 dma-names = "tx", "rx"; 2474 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 2475 pinctrl-0 = <&uart8m0_xfer>; 2476 pinctrl-names = "default"; 2477 status = "disabled"; 2478 }; 2479 2480 uart9: serial@2adc0000 { 2481 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2482 reg = <0x0 0x2adc0000 0x0 0x100>; 2483 reg-shift = <2>; 2484 reg-io-width = <4>; 2485 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2486 clock-names = "baudclk", "apb_pclk"; 2487 dmas = <&dmac2 10>, <&dmac2 11>; 2488 dma-names = "tx", "rx"; 2489 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 2490 pinctrl-0 = <&uart9m0_xfer>; 2491 pinctrl-names = "default"; 2492 status = "disabled"; 2493 }; 2494 2495 saradc: adc@2ae00000 { 2496 compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc"; 2497 reg = <0x0 0x2ae00000 0x0 0x10000>; 2498 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2499 clock-names = "saradc", "apb_pclk"; 2500 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 2501 resets = <&cru SRST_P_SARADC>; 2502 reset-names = "saradc-apb"; 2503 #io-channel-cells = <1>; 2504 status = "disabled"; 2505 }; 2506 2507 tsadc: tsadc@2ae70000 { 2508 compatible = "rockchip,rk3576-tsadc"; 2509 reg = <0x0 0x2ae70000 0x0 0x400>; 2510 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 2511 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2512 clock-names = "tsadc", "apb_pclk"; 2513 assigned-clocks = <&cru CLK_TSADC>; 2514 assigned-clock-rates = <2000000>; 2515 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 2516 reset-names = "tsadc-apb", "tsadc"; 2517 #thermal-sensor-cells = <1>; 2518 rockchip,hw-tshut-temp = <120000>; 2519 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 2520 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2521 #address-cells = <1>; 2522 #size-cells = <0>; 2523 2524 sensor@0 { 2525 reg = <0>; 2526 nvmem-cells = <&soc_tsadc_trim>; 2527 nvmem-cell-names = "trim"; 2528 }; 2529 sensor@1 { 2530 reg = <1>; 2531 nvmem-cells = <&bigcore_tsadc_trim>; 2532 nvmem-cell-names = "trim"; 2533 }; 2534 sensor@2 { 2535 reg = <2>; 2536 nvmem-cells = <&litcore_tsadc_trim>; 2537 nvmem-cell-names = "trim"; 2538 }; 2539 sensor@3 { 2540 reg = <3>; 2541 nvmem-cells = <&ddr_tsadc_trim>; 2542 nvmem-cell-names = "trim"; 2543 }; 2544 sensor@4 { 2545 reg = <4>; 2546 nvmem-cells = <&npu_tsadc_trim>; 2547 nvmem-cell-names = "trim"; 2548 }; 2549 sensor@5 { 2550 reg = <5>; 2551 nvmem-cells = <&gpu_tsadc_trim>; 2552 nvmem-cell-names = "trim"; 2553 }; 2554 }; 2555 2556 i2c9: i2c@2ae80000 { 2557 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 2558 reg = <0x0 0x2ae80000 0x0 0x1000>; 2559 clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>; 2560 clock-names = "i2c", "pclk"; 2561 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2562 pinctrl-names = "default"; 2563 pinctrl-0 = <&i2c9m0_xfer>; 2564 resets = <&cru SRST_I2C9>, <&cru SRST_P_I2C9>; 2565 reset-names = "i2c", "apb"; 2566 #address-cells = <1>; 2567 #size-cells = <0>; 2568 status = "disabled"; 2569 }; 2570 2571 uart10: serial@2afc0000 { 2572 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2573 reg = <0x0 0x2afc0000 0x0 0x100>; 2574 reg-shift = <2>; 2575 reg-io-width = <4>; 2576 clocks = <&cru SCLK_UART10>, <&cru PCLK_UART10>; 2577 clock-names = "baudclk", "apb_pclk"; 2578 dmas = <&dmac2 21>, <&dmac2 22>; 2579 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 2580 pinctrl-names = "default"; 2581 pinctrl-0 = <&uart10m0_xfer>; 2582 status = "disabled"; 2583 }; 2584 2585 uart11: serial@2afd0000 { 2586 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 2587 reg = <0x0 0x2afd0000 0x0 0x100>; 2588 reg-shift = <2>; 2589 reg-io-width = <4>; 2590 clocks = <&cru SCLK_UART11>, <&cru PCLK_UART11>; 2591 clock-names = "baudclk", "apb_pclk"; 2592 dmas = <&dmac2 23>, <&dmac2 24>; 2593 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 2594 pinctrl-names = "default"; 2595 pinctrl-0 = <&uart11m0_xfer>; 2596 status = "disabled"; 2597 }; 2598 2599 mipidcphy: phy@2b020000 { 2600 compatible = "rockchip,rk3576-mipi-dcphy"; 2601 reg = <0x0 0x2b020000 0x0 0x10000>; 2602 clocks = <&cru PCLK_MIPI_DCPHY>, 2603 <&cru CLK_PHY_REF_SRC>; 2604 clock-names = "pclk", "ref"; 2605 resets = <&cru SRST_M_MIPI_DCPHY>, 2606 <&cru SRST_P_MIPI_DCPHY>, 2607 <&cru SRST_P_DCPHY_GRF>, 2608 <&cru SRST_S_MIPI_DCPHY>; 2609 reset-names = "m_phy", "apb", "grf", "s_phy"; 2610 rockchip,grf = <&mipidcphy_grf>; 2611 #phy-cells = <1>; 2612 status = "disabled"; 2613 }; 2614 2615 combphy0_ps: phy@2b050000 { 2616 compatible = "rockchip,rk3576-naneng-combphy"; 2617 reg = <0x0 0x2b050000 0x0 0x100>; 2618 #phy-cells = <1>; 2619 clocks = <&cru CLK_REF_PCIE0_PHY>, 2620 <&cru PCLK_PCIE2_COMBOPHY0>, 2621 <&cru PCLK_PCIE0>; 2622 clock-names = "ref", "apb", "pipe"; 2623 assigned-clocks = <&cru CLK_REF_PCIE0_PHY>; 2624 assigned-clock-rates = <100000000>; 2625 resets = <&cru SRST_PCIE0_PIPE_PHY>, 2626 <&cru SRST_P_PCIE2_COMBOPHY0>; 2627 reset-names = "phy", "apb"; 2628 rockchip,pipe-grf = <&php_grf>; 2629 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 2630 status = "disabled"; 2631 }; 2632 2633 combphy1_psu: phy@2b060000 { 2634 compatible = "rockchip,rk3576-naneng-combphy"; 2635 reg = <0x0 0x2b060000 0x0 0x100>; 2636 #phy-cells = <1>; 2637 clocks = <&cru CLK_REF_PCIE1_PHY>, 2638 <&cru PCLK_PCIE2_COMBOPHY1>, 2639 <&cru PCLK_PCIE1>; 2640 clock-names = "ref", "apb", "pipe"; 2641 assigned-clocks = <&cru CLK_REF_PCIE1_PHY>; 2642 assigned-clock-rates = <100000000>; 2643 resets = <&cru SRST_PCIE1_PIPE_PHY>, 2644 <&cru SRST_P_PCIE2_COMBOPHY1>; 2645 reset-names = "phy", "apb"; 2646 rockchip,pipe-grf = <&php_grf>; 2647 rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 2648 status = "disabled"; 2649 }; 2650 2651 usbdp_phy: phy@2b010000 { 2652 compatible = "rockchip,rk3576-usbdp-phy"; 2653 reg = <0x0 0x2b010000 0x0 0x10000>; 2654 #phy-cells = <1>; 2655 clocks = <&cru CLK_PHY_REF_SRC >, 2656 <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>, 2657 <&cru PCLK_USBDPPHY>, 2658 <&u2phy0>; 2659 clock-names = "refclk", "immortal", "pclk", "utmi"; 2660 resets = <&cru SRST_USBDP_COMBO_PHY_INIT>, 2661 <&cru SRST_USBDP_COMBO_PHY_CMN>, 2662 <&cru SRST_USBDP_COMBO_PHY_LANE>, 2663 <&cru SRST_USBDP_COMBO_PHY_PCS>, 2664 <&cru SRST_P_USBDPPHY>; 2665 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 2666 rockchip,u2phy-grf = <&usb2phy_grf>; 2667 rockchip,usb-grf = <&usb_grf>; 2668 rockchip,usbdpphy-grf = <&usbdpphy_grf>; 2669 rockchip,vo-grf = <&vo1_grf>; 2670 status = "disabled"; 2671 }; 2672 2673 hdptxphy: hdmiphy@2b000000 { 2674 compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy"; 2675 reg = <0x0 0x2b000000 0x0 0x2000>; 2676 clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>; 2677 clock-names = "ref", "apb"; 2678 #clock-cells = <0>; 2679 resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, 2680 <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; 2681 reset-names = "apb", "init", "cmn", "lane"; 2682 rockchip,grf = <&hdptxphy_grf>; 2683 #phy-cells = <0>; 2684 status = "disabled"; 2685 }; 2686 2687 sram: sram@3ff88000 { 2688 compatible = "mmio-sram"; 2689 reg = <0x0 0x3ff88000 0x0 0x78000>; 2690 ranges = <0x0 0x0 0x3ff88000 0x78000>; 2691 #address-cells = <1>; 2692 #size-cells = <1>; 2693 2694 /* start address and size should be 4k align */ 2695 rkvdec_sram: rkvdec-sram@0 { 2696 reg = <0x0 0x78000>; 2697 }; 2698 }; 2699 2700 scmi_shmem: scmi-shmem@4010f000 { 2701 compatible = "arm,scmi-shmem"; 2702 reg = <0x0 0x4010f000 0x0 0x100>; 2703 }; 2704 }; 2705}; 2706 2707#include "rk3576-pinctrl.dtsi" 2708