1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3576-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rockchip,rk3576-power.h> 12#include <dt-bindings/reset/rockchip,rk3576-cru.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14 15/ { 16 compatible = "rockchip,rk3576"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 i2c9 = &i2c9; 33 serial0 = &uart0; 34 serial1 = &uart1; 35 serial2 = &uart2; 36 serial3 = &uart3; 37 serial4 = &uart4; 38 serial5 = &uart5; 39 serial6 = &uart6; 40 serial7 = &uart7; 41 serial8 = &uart8; 42 serial9 = &uart9; 43 serial10 = &uart10; 44 serial11 = &uart11; 45 spi0 = &spi0; 46 spi1 = &spi1; 47 spi2 = &spi2; 48 spi3 = &spi3; 49 spi4 = &spi4; 50 }; 51 52 xin32k: clock-xin32k { 53 compatible = "fixed-clock"; 54 clock-frequency = <32768>; 55 clock-output-names = "xin32k"; 56 #clock-cells = <0>; 57 }; 58 59 xin24m: clock-xin24m { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <24000000>; 63 clock-output-names = "xin24m"; 64 }; 65 66 spll: clock-spll { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <702000000>; 70 clock-output-names = "spll"; 71 }; 72 73 cpus { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 cpu-map { 78 cluster0 { 79 core0 { 80 cpu = <&cpu_l0>; 81 }; 82 core1 { 83 cpu = <&cpu_l1>; 84 }; 85 core2 { 86 cpu = <&cpu_l2>; 87 }; 88 core3 { 89 cpu = <&cpu_l3>; 90 }; 91 }; 92 cluster1 { 93 core0 { 94 cpu = <&cpu_b0>; 95 }; 96 core1 { 97 cpu = <&cpu_b1>; 98 }; 99 core2 { 100 cpu = <&cpu_b2>; 101 }; 102 core3 { 103 cpu = <&cpu_b3>; 104 }; 105 }; 106 }; 107 108 cpu_l0: cpu@0 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x0>; 112 enable-method = "psci"; 113 capacity-dmips-mhz = <485>; 114 clocks = <&scmi_clk ARMCLK_L>; 115 operating-points-v2 = <&cluster0_opp_table>; 116 #cooling-cells = <2>; 117 dynamic-power-coefficient = <120>; 118 cpu-idle-states = <&CPU_SLEEP>; 119 }; 120 121 cpu_l1: cpu@1 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a53"; 124 reg = <0x1>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <485>; 127 clocks = <&scmi_clk ARMCLK_L>; 128 operating-points-v2 = <&cluster0_opp_table>; 129 cpu-idle-states = <&CPU_SLEEP>; 130 }; 131 132 cpu_l2: cpu@2 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a53"; 135 reg = <0x2>; 136 enable-method = "psci"; 137 capacity-dmips-mhz = <485>; 138 clocks = <&scmi_clk ARMCLK_L>; 139 operating-points-v2 = <&cluster0_opp_table>; 140 cpu-idle-states = <&CPU_SLEEP>; 141 }; 142 143 cpu_l3: cpu@3 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a53"; 146 reg = <0x3>; 147 enable-method = "psci"; 148 capacity-dmips-mhz = <485>; 149 clocks = <&scmi_clk ARMCLK_L>; 150 operating-points-v2 = <&cluster0_opp_table>; 151 cpu-idle-states = <&CPU_SLEEP>; 152 }; 153 154 cpu_b0: cpu@100 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a72"; 157 reg = <0x100>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1024>; 160 clocks = <&scmi_clk ARMCLK_B>; 161 operating-points-v2 = <&cluster1_opp_table>; 162 #cooling-cells = <2>; 163 dynamic-power-coefficient = <320>; 164 cpu-idle-states = <&CPU_SLEEP>; 165 }; 166 167 cpu_b1: cpu@101 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a72"; 170 reg = <0x101>; 171 enable-method = "psci"; 172 capacity-dmips-mhz = <1024>; 173 clocks = <&scmi_clk ARMCLK_B>; 174 operating-points-v2 = <&cluster1_opp_table>; 175 cpu-idle-states = <&CPU_SLEEP>; 176 }; 177 178 cpu_b2: cpu@102 { 179 device_type = "cpu"; 180 compatible = "arm,cortex-a72"; 181 reg = <0x102>; 182 enable-method = "psci"; 183 capacity-dmips-mhz = <1024>; 184 clocks = <&scmi_clk ARMCLK_B>; 185 operating-points-v2 = <&cluster1_opp_table>; 186 cpu-idle-states = <&CPU_SLEEP>; 187 }; 188 189 cpu_b3: cpu@103 { 190 device_type = "cpu"; 191 compatible = "arm,cortex-a72"; 192 reg = <0x103>; 193 enable-method = "psci"; 194 capacity-dmips-mhz = <1024>; 195 clocks = <&scmi_clk ARMCLK_B>; 196 operating-points-v2 = <&cluster1_opp_table>; 197 cpu-idle-states = <&CPU_SLEEP>; 198 }; 199 200 idle-states { 201 entry-method = "psci"; 202 203 CPU_SLEEP: cpu-sleep { 204 compatible = "arm,idle-state"; 205 arm,psci-suspend-param = <0x0010000>; 206 entry-latency-us = <120>; 207 exit-latency-us = <250>; 208 min-residency-us = <900>; 209 local-timer-stop; 210 }; 211 }; 212 }; 213 214 cluster0_opp_table: opp-table-cluster0 { 215 compatible = "operating-points-v2"; 216 opp-shared; 217 218 opp-408000000 { 219 opp-hz = /bits/ 64 <408000000>; 220 opp-microvolt = <700000 700000 950000>; 221 clock-latency-ns = <40000>; 222 }; 223 224 opp-600000000 { 225 opp-hz = /bits/ 64 <600000000>; 226 opp-microvolt = <700000 700000 950000>; 227 clock-latency-ns = <40000>; 228 }; 229 230 opp-816000000 { 231 opp-hz = /bits/ 64 <816000000>; 232 opp-microvolt = <700000 700000 950000>; 233 clock-latency-ns = <40000>; 234 }; 235 236 opp-1008000000 { 237 opp-hz = /bits/ 64 <1008000000>; 238 opp-microvolt = <700000 700000 950000>; 239 clock-latency-ns = <40000>; 240 }; 241 242 opp-1200000000 { 243 opp-hz = /bits/ 64 <1200000000>; 244 opp-microvolt = <700000 700000 950000>; 245 clock-latency-ns = <40000>; 246 }; 247 248 opp-1416000000 { 249 opp-hz = /bits/ 64 <1416000000>; 250 opp-microvolt = <725000 725000 950000>; 251 clock-latency-ns = <40000>; 252 }; 253 254 opp-1608000000 { 255 opp-hz = /bits/ 64 <1608000000>; 256 opp-microvolt = <750000 750000 950000>; 257 clock-latency-ns = <40000>; 258 }; 259 260 opp-1800000000 { 261 opp-hz = /bits/ 64 <1800000000>; 262 opp-microvolt = <825000 825000 950000>; 263 clock-latency-ns = <40000>; 264 opp-suspend; 265 }; 266 267 opp-2016000000 { 268 opp-hz = /bits/ 64 <2016000000>; 269 opp-microvolt = <900000 900000 950000>; 270 clock-latency-ns = <40000>; 271 }; 272 273 opp-2208000000 { 274 opp-hz = /bits/ 64 <2208000000>; 275 opp-microvolt = <950000 950000 950000>; 276 clock-latency-ns = <40000>; 277 }; 278 }; 279 280 cluster1_opp_table: opp-table-cluster1 { 281 compatible = "operating-points-v2"; 282 opp-shared; 283 284 opp-408000000 { 285 opp-hz = /bits/ 64 <408000000>; 286 opp-microvolt = <700000 700000 950000>; 287 clock-latency-ns = <40000>; 288 opp-suspend; 289 }; 290 291 opp-600000000 { 292 opp-hz = /bits/ 64 <600000000>; 293 opp-microvolt = <700000 700000 950000>; 294 clock-latency-ns = <40000>; 295 }; 296 297 opp-816000000 { 298 opp-hz = /bits/ 64 <816000000>; 299 opp-microvolt = <700000 700000 950000>; 300 clock-latency-ns = <40000>; 301 }; 302 303 opp-1008000000 { 304 opp-hz = /bits/ 64 <1008000000>; 305 opp-microvolt = <700000 700000 950000>; 306 clock-latency-ns = <40000>; 307 }; 308 309 opp-1200000000 { 310 opp-hz = /bits/ 64 <1200000000>; 311 opp-microvolt = <700000 700000 950000>; 312 clock-latency-ns = <40000>; 313 }; 314 315 opp-1416000000 { 316 opp-hz = /bits/ 64 <1416000000>; 317 opp-microvolt = <712500 712500 950000>; 318 clock-latency-ns = <40000>; 319 }; 320 321 opp-1608000000 { 322 opp-hz = /bits/ 64 <1608000000>; 323 opp-microvolt = <737500 737500 950000>; 324 clock-latency-ns = <40000>; 325 }; 326 327 opp-1800000000 { 328 opp-hz = /bits/ 64 <1800000000>; 329 opp-microvolt = <800000 800000 950000>; 330 clock-latency-ns = <40000>; 331 }; 332 333 opp-2016000000 { 334 opp-hz = /bits/ 64 <2016000000>; 335 opp-microvolt = <862500 862500 950000>; 336 clock-latency-ns = <40000>; 337 }; 338 339 opp-2208000000 { 340 opp-hz = /bits/ 64 <2208000000>; 341 opp-microvolt = <925000 925000 950000>; 342 clock-latency-ns = <40000>; 343 }; 344 345 opp-2304000000 { 346 opp-hz = /bits/ 64 <2304000000>; 347 opp-microvolt = <950000 950000 950000>; 348 clock-latency-ns = <40000>; 349 }; 350 }; 351 352 gpu_opp_table: opp-table-gpu { 353 compatible = "operating-points-v2"; 354 355 opp-300000000 { 356 opp-hz = /bits/ 64 <300000000>; 357 opp-microvolt = <700000 700000 850000>; 358 }; 359 360 opp-400000000 { 361 opp-hz = /bits/ 64 <400000000>; 362 opp-microvolt = <700000 700000 850000>; 363 }; 364 365 opp-500000000 { 366 opp-hz = /bits/ 64 <500000000>; 367 opp-microvolt = <700000 700000 850000>; 368 }; 369 370 opp-600000000 { 371 opp-hz = /bits/ 64 <600000000>; 372 opp-microvolt = <700000 700000 850000>; 373 }; 374 375 opp-700000000 { 376 opp-hz = /bits/ 64 <700000000>; 377 opp-microvolt = <725000 725000 850000>; 378 }; 379 380 opp-800000000 { 381 opp-hz = /bits/ 64 <800000000>; 382 opp-microvolt = <775000 775000 850000>; 383 }; 384 385 opp-900000000 { 386 opp-hz = /bits/ 64 <900000000>; 387 opp-microvolt = <825000 825000 850000>; 388 }; 389 390 opp-950000000 { 391 opp-hz = /bits/ 64 <950000000>; 392 opp-microvolt = <850000 850000 850000>; 393 }; 394 }; 395 396 firmware { 397 scmi: scmi { 398 compatible = "arm,scmi-smc"; 399 arm,smc-id = <0x82000010>; 400 shmem = <&scmi_shmem>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 404 scmi_clk: protocol@14 { 405 reg = <0x14>; 406 #clock-cells = <1>; 407 }; 408 }; 409 }; 410 411 pmu_a53: pmu-a53 { 412 compatible = "arm,cortex-a53-pmu"; 413 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 417 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>; 418 }; 419 420 pmu_a72: pmu-a72 { 421 compatible = "arm,cortex-a72-pmu"; 422 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 426 interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; 427 }; 428 429 psci { 430 compatible = "arm,psci-1.0"; 431 method = "smc"; 432 }; 433 434 timer { 435 compatible = "arm,armv8-timer"; 436 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 437 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 438 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 439 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 440 }; 441 442 soc { 443 compatible = "simple-bus"; 444 #address-cells = <2>; 445 #size-cells = <2>; 446 ranges; 447 448 sys_grf: syscon@2600a000 { 449 compatible = "rockchip,rk3576-sys-grf", "syscon"; 450 reg = <0x0 0x2600a000 0x0 0x2000>; 451 }; 452 453 bigcore_grf: syscon@2600c000 { 454 compatible = "rockchip,rk3576-bigcore-grf", "syscon"; 455 reg = <0x0 0x2600c000 0x0 0x2000>; 456 }; 457 458 litcore_grf: syscon@2600e000 { 459 compatible = "rockchip,rk3576-litcore-grf", "syscon"; 460 reg = <0x0 0x2600e000 0x0 0x2000>; 461 }; 462 463 cci_grf: syscon@26010000 { 464 compatible = "rockchip,rk3576-cci-grf", "syscon"; 465 reg = <0x0 0x26010000 0x0 0x2000>; 466 }; 467 468 gpu_grf: syscon@26016000 { 469 compatible = "rockchip,rk3576-gpu-grf", "syscon"; 470 reg = <0x0 0x26016000 0x0 0x2000>; 471 }; 472 473 npu_grf: syscon@26018000 { 474 compatible = "rockchip,rk3576-npu-grf", "syscon"; 475 reg = <0x0 0x26018000 0x0 0x2000>; 476 }; 477 478 vo0_grf: syscon@2601a000 { 479 compatible = "rockchip,rk3576-vo0-grf", "syscon"; 480 reg = <0x0 0x2601a000 0x0 0x2000>; 481 }; 482 483 usb_grf: syscon@2601e000 { 484 compatible = "rockchip,rk3576-usb-grf", "syscon"; 485 reg = <0x0 0x2601e000 0x0 0x1000>; 486 }; 487 488 php_grf: syscon@26020000 { 489 compatible = "rockchip,rk3576-php-grf", "syscon"; 490 reg = <0x0 0x26020000 0x0 0x2000>; 491 }; 492 493 pmu0_grf: syscon@26024000 { 494 compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd"; 495 reg = <0x0 0x26024000 0x0 0x1000>; 496 }; 497 498 pmu1_grf: syscon@26026000 { 499 compatible = "rockchip,rk3576-pmu1-grf", "syscon"; 500 reg = <0x0 0x26026000 0x0 0x1000>; 501 }; 502 503 pipe_phy0_grf: syscon@26028000 { 504 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 505 reg = <0x0 0x26028000 0x0 0x2000>; 506 }; 507 508 pipe_phy1_grf: syscon@2602a000 { 509 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 510 reg = <0x0 0x2602a000 0x0 0x2000>; 511 }; 512 513 usbdpphy_grf: syscon@2602c000 { 514 compatible = "rockchip,rk3576-usbdpphy-grf", "syscon"; 515 reg = <0x0 0x2602c000 0x0 0x2000>; 516 }; 517 518 sdgmac_grf: syscon@26038000 { 519 compatible = "rockchip,rk3576-sdgmac-grf", "syscon"; 520 reg = <0x0 0x26038000 0x0 0x1000>; 521 }; 522 523 ioc_grf: syscon@26040000 { 524 compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd"; 525 reg = <0x0 0x26040000 0x0 0xc000>; 526 }; 527 528 cru: clock-controller@27200000 { 529 compatible = "rockchip,rk3576-cru"; 530 reg = <0x0 0x27200000 0x0 0x50000>; 531 #clock-cells = <1>; 532 #reset-cells = <1>; 533 534 assigned-clocks = 535 <&cru CLK_AUDIO_FRAC_1_SRC>, 536 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 537 <&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>, 538 <&cru CLK_UART_FRAC_1>, <&cru CLK_UART_FRAC_2>, 539 <&cru CLK_AUDIO_FRAC_0>, <&cru CLK_AUDIO_FRAC_1>, 540 <&cru CLK_CPLL_DIV2>, <&cru CLK_CPLL_DIV4>, 541 <&cru CLK_CPLL_DIV10>, <&cru FCLK_DDR_CM0_CORE>, 542 <&cru ACLK_PHP_ROOT>; 543 assigned-clock-parents = <&cru PLL_AUPLL>; 544 assigned-clock-rates = 545 <0>, 546 <1188000000>, <1000000000>, 547 <786432000>, <18432000>, 548 <96000000>, <128000000>, 549 <45158400>, <49152000>, 550 <500000000>, <250000000>, 551 <100000000>, <500000000>, 552 <250000000>; 553 }; 554 555 i2c0: i2c@27300000 { 556 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 557 reg = <0x0 0x27300000 0x0 0x1000>; 558 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 559 clock-names = "i2c", "pclk"; 560 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&i2c0m0_xfer>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 status = "disabled"; 566 }; 567 568 uart1: serial@27310000 { 569 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 570 reg = <0x0 0x27310000 0x0 0x100>; 571 reg-shift = <2>; 572 reg-io-width = <4>; 573 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 574 clock-names = "baudclk", "apb_pclk"; 575 dmas = <&dmac0 8>, <&dmac0 9>; 576 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 577 pinctrl-names = "default"; 578 pinctrl-0 = <&uart1m0_xfer>; 579 status = "disabled"; 580 }; 581 582 pmu: power-management@27380000 { 583 compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd"; 584 reg = <0x0 0x27380000 0x0 0x800>; 585 586 power: power-controller { 587 compatible = "rockchip,rk3576-power-controller"; 588 #power-domain-cells = <1>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 592 power-domain@RK3576_PD_NPU { 593 reg = <RK3576_PD_NPU>; 594 #power-domain-cells = <1>; 595 #address-cells = <1>; 596 #size-cells = <0>; 597 598 power-domain@RK3576_PD_NPUTOP { 599 reg = <RK3576_PD_NPUTOP>; 600 clocks = <&cru ACLK_RKNN0>, 601 <&cru ACLK_RKNN1>, 602 <&cru ACLK_RKNN_CBUF>, 603 <&cru CLK_RKNN_DSU0>, 604 <&cru HCLK_RKNN_CBUF>, 605 <&cru HCLK_RKNN_ROOT>, 606 <&cru HCLK_NPU_CM0_ROOT>, 607 <&cru PCLK_NPUTOP_ROOT>; 608 pm_qos = <&qos_npu_mcu>, 609 <&qos_npu_nsp0>, 610 <&qos_npu_nsp1>, 611 <&qos_npu_m0ro>, 612 <&qos_npu_m1ro>; 613 #power-domain-cells = <1>; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 617 power-domain@RK3576_PD_NPU0 { 618 reg = <RK3576_PD_NPU0>; 619 clocks = <&cru HCLK_RKNN_ROOT>, 620 <&cru ACLK_RKNN0>; 621 pm_qos = <&qos_npu_m0>; 622 #power-domain-cells = <0>; 623 }; 624 power-domain@RK3576_PD_NPU1 { 625 reg = <RK3576_PD_NPU1>; 626 clocks = <&cru HCLK_RKNN_ROOT>, 627 <&cru ACLK_RKNN1>; 628 pm_qos = <&qos_npu_m1>; 629 #power-domain-cells = <0>; 630 }; 631 }; 632 }; 633 634 power-domain@RK3576_PD_GPU { 635 reg = <RK3576_PD_GPU>; 636 clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>; 637 pm_qos = <&qos_gpu>; 638 #power-domain-cells = <0>; 639 }; 640 641 power-domain@RK3576_PD_NVM { 642 reg = <RK3576_PD_NVM>; 643 clocks = <&cru ACLK_EMMC>, <&cru HCLK_EMMC>; 644 pm_qos = <&qos_emmc>, 645 <&qos_fspi0>; 646 #power-domain-cells = <1>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 650 power-domain@RK3576_PD_SDGMAC { 651 reg = <RK3576_PD_SDGMAC>; 652 clocks = <&cru ACLK_HSGPIO>, 653 <&cru ACLK_GMAC0>, 654 <&cru ACLK_GMAC1>, 655 <&cru CCLK_SRC_SDIO>, 656 <&cru CCLK_SRC_SDMMC0>, 657 <&cru HCLK_HSGPIO>, 658 <&cru HCLK_SDIO>, 659 <&cru HCLK_SDMMC0>, 660 <&cru PCLK_SDGMAC_ROOT>; 661 pm_qos = <&qos_fspi1>, 662 <&qos_gmac0>, 663 <&qos_gmac1>, 664 <&qos_sdio>, 665 <&qos_sdmmc>, 666 <&qos_flexbus>; 667 #power-domain-cells = <0>; 668 }; 669 }; 670 671 power-domain@RK3576_PD_PHP { 672 reg = <RK3576_PD_PHP>; 673 clocks = <&cru ACLK_PHP_ROOT>, 674 <&cru PCLK_PHP_ROOT>, 675 <&cru ACLK_MMU0>, 676 <&cru ACLK_MMU1>; 677 pm_qos = <&qos_mmu0>, 678 <&qos_mmu1>; 679 #power-domain-cells = <1>; 680 #address-cells = <1>; 681 #size-cells = <0>; 682 683 power-domain@RK3576_PD_SUBPHP { 684 reg = <RK3576_PD_SUBPHP>; 685 #power-domain-cells = <0>; 686 }; 687 }; 688 689 power-domain@RK3576_PD_AUDIO { 690 reg = <RK3576_PD_AUDIO>; 691 #power-domain-cells = <0>; 692 }; 693 694 power-domain@RK3576_PD_VEPU1 { 695 reg = <RK3576_PD_VEPU1>; 696 clocks = <&cru ACLK_VEPU1>, 697 <&cru HCLK_VEPU1>; 698 pm_qos = <&qos_vepu1>; 699 #power-domain-cells = <0>; 700 }; 701 702 power-domain@RK3576_PD_VPU { 703 reg = <RK3576_PD_VPU>; 704 clocks = <&cru ACLK_EBC>, 705 <&cru HCLK_EBC>, 706 <&cru ACLK_JPEG>, 707 <&cru HCLK_JPEG>, 708 <&cru ACLK_RGA2E_0>, 709 <&cru HCLK_RGA2E_0>, 710 <&cru ACLK_RGA2E_1>, 711 <&cru HCLK_RGA2E_1>, 712 <&cru ACLK_VDPP>, 713 <&cru HCLK_VDPP>; 714 pm_qos = <&qos_ebc>, 715 <&qos_jpeg>, 716 <&qos_rga0>, 717 <&qos_rga1>, 718 <&qos_vdpp>; 719 #power-domain-cells = <0>; 720 }; 721 722 power-domain@RK3576_PD_VDEC { 723 reg = <RK3576_PD_VDEC>; 724 clocks = <&cru ACLK_RKVDEC_ROOT>, 725 <&cru HCLK_RKVDEC>; 726 pm_qos = <&qos_rkvdec>; 727 #power-domain-cells = <0>; 728 }; 729 730 power-domain@RK3576_PD_VI { 731 reg = <RK3576_PD_VI>; 732 clocks = <&cru ACLK_VICAP>, 733 <&cru HCLK_VICAP>, 734 <&cru DCLK_VICAP>, 735 <&cru ACLK_VI_ROOT>, 736 <&cru HCLK_VI_ROOT>, 737 <&cru PCLK_VI_ROOT>, 738 <&cru CLK_ISP_CORE>, 739 <&cru ACLK_ISP>, 740 <&cru HCLK_ISP>, 741 <&cru CLK_CORE_VPSS>, 742 <&cru ACLK_VPSS>, 743 <&cru HCLK_VPSS>; 744 pm_qos = <&qos_isp_mro>, 745 <&qos_isp_mwo>, 746 <&qos_vicap_m0>, 747 <&qos_vpss_mro>, 748 <&qos_vpss_mwo>; 749 #power-domain-cells = <1>; 750 #address-cells = <1>; 751 #size-cells = <0>; 752 753 power-domain@RK3576_PD_VEPU0 { 754 reg = <RK3576_PD_VEPU0>; 755 clocks = <&cru ACLK_VEPU0>, 756 <&cru HCLK_VEPU0>; 757 pm_qos = <&qos_vepu0>; 758 #power-domain-cells = <0>; 759 }; 760 }; 761 762 power-domain@RK3576_PD_VOP { 763 reg = <RK3576_PD_VOP>; 764 clocks = <&cru ACLK_VOP>, 765 <&cru HCLK_VOP>, 766 <&cru HCLK_VOP_ROOT>, 767 <&cru PCLK_VOP_ROOT>; 768 pm_qos = <&qos_vop_m0>, 769 <&qos_vop_m1ro>; 770 #power-domain-cells = <1>; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 774 power-domain@RK3576_PD_USB { 775 reg = <RK3576_PD_USB>; 776 clocks = <&cru PCLK_PHP_ROOT>, 777 <&cru ACLK_USB_ROOT>, 778 <&cru ACLK_MMU2>, 779 <&cru ACLK_SLV_MMU2>, 780 <&cru ACLK_UFS_SYS>; 781 pm_qos = <&qos_mmu2>, 782 <&qos_ufshc>; 783 #power-domain-cells = <0>; 784 }; 785 786 power-domain@RK3576_PD_VO0 { 787 reg = <RK3576_PD_VO0>; 788 clocks = <&cru ACLK_HDCP0>, 789 <&cru HCLK_HDCP0>, 790 <&cru ACLK_VO0_ROOT>, 791 <&cru PCLK_VO0_ROOT>, 792 <&cru HCLK_VOP_ROOT>; 793 pm_qos = <&qos_hdcp0>; 794 #power-domain-cells = <0>; 795 }; 796 797 power-domain@RK3576_PD_VO1 { 798 reg = <RK3576_PD_VO1>; 799 clocks = <&cru ACLK_HDCP1>, 800 <&cru HCLK_HDCP1>, 801 <&cru ACLK_VO1_ROOT>, 802 <&cru PCLK_VO1_ROOT>, 803 <&cru HCLK_VOP_ROOT>; 804 pm_qos = <&qos_hdcp1>; 805 #power-domain-cells = <0>; 806 }; 807 }; 808 }; 809 }; 810 811 gpu: gpu@27800000 { 812 compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; 813 reg = <0x0 0x27800000 0x0 0x200000>; 814 assigned-clocks = <&scmi_clk CLK_GPU>; 815 assigned-clock-rates = <198000000>; 816 clocks = <&cru CLK_GPU>; 817 clock-names = "core"; 818 dynamic-power-coefficient = <1625>; 819 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 822 interrupt-names = "job", "mmu", "gpu"; 823 operating-points-v2 = <&gpu_opp_table>; 824 power-domains = <&power RK3576_PD_GPU>; 825 #cooling-cells = <2>; 826 status = "disabled"; 827 }; 828 829 qos_hdcp1: qos@27f02000 { 830 compatible = "rockchip,rk3576-qos", "syscon"; 831 reg = <0x0 0x27f02000 0x0 0x20>; 832 }; 833 834 qos_fspi1: qos@27f04000 { 835 compatible = "rockchip,rk3576-qos", "syscon"; 836 reg = <0x0 0x27f04000 0x0 0x20>; 837 }; 838 839 qos_gmac0: qos@27f04080 { 840 compatible = "rockchip,rk3576-qos", "syscon"; 841 reg = <0x0 0x27f04080 0x0 0x20>; 842 }; 843 844 qos_gmac1: qos@27f04100 { 845 compatible = "rockchip,rk3576-qos", "syscon"; 846 reg = <0x0 0x27f04100 0x0 0x20>; 847 }; 848 849 qos_sdio: qos@27f04180 { 850 compatible = "rockchip,rk3576-qos", "syscon"; 851 reg = <0x0 0x27f04180 0x0 0x20>; 852 }; 853 854 qos_sdmmc: qos@27f04200 { 855 compatible = "rockchip,rk3576-qos", "syscon"; 856 reg = <0x0 0x27f04200 0x0 0x20>; 857 }; 858 859 qos_flexbus: qos@27f04280 { 860 compatible = "rockchip,rk3576-qos", "syscon"; 861 reg = <0x0 0x27f04280 0x0 0x20>; 862 }; 863 864 qos_gpu: qos@27f05000 { 865 compatible = "rockchip,rk3576-qos", "syscon"; 866 reg = <0x0 0x27f05000 0x0 0x20>; 867 }; 868 869 qos_vepu1: qos@27f06000 { 870 compatible = "rockchip,rk3576-qos", "syscon"; 871 reg = <0x0 0x27f06000 0x0 0x20>; 872 }; 873 874 qos_npu_mcu: qos@27f08000 { 875 compatible = "rockchip,rk3576-qos", "syscon"; 876 reg = <0x0 0x27f08000 0x0 0x20>; 877 }; 878 879 qos_npu_nsp0: qos@27f08080 { 880 compatible = "rockchip,rk3576-qos", "syscon"; 881 reg = <0x0 0x27f08080 0x0 0x20>; 882 }; 883 884 qos_npu_nsp1: qos@27f08100 { 885 compatible = "rockchip,rk3576-qos", "syscon"; 886 reg = <0x0 0x27f08100 0x0 0x20>; 887 }; 888 889 qos_emmc: qos@27f09000 { 890 compatible = "rockchip,rk3576-qos", "syscon"; 891 reg = <0x0 0x27f09000 0x0 0x20>; 892 }; 893 894 qos_fspi0: qos@27f09080 { 895 compatible = "rockchip,rk3576-qos", "syscon"; 896 reg = <0x0 0x27f09080 0x0 0x20>; 897 }; 898 899 qos_mmu0: qos@27f0a000 { 900 compatible = "rockchip,rk3576-qos", "syscon"; 901 reg = <0x0 0x27f0a000 0x0 0x20>; 902 }; 903 904 qos_mmu1: qos@27f0a080 { 905 compatible = "rockchip,rk3576-qos", "syscon"; 906 reg = <0x0 0x27f0a080 0x0 0x20>; 907 }; 908 909 qos_rkvdec: qos@27f0c000 { 910 compatible = "rockchip,rk3576-qos", "syscon"; 911 reg = <0x0 0x27f0c000 0x0 0x20>; 912 }; 913 914 qos_crypto: qos@27f0d000 { 915 compatible = "rockchip,rk3576-qos", "syscon"; 916 reg = <0x0 0x27f0d000 0x0 0x20>; 917 }; 918 919 qos_mmu2: qos@27f0e000 { 920 compatible = "rockchip,rk3576-qos", "syscon"; 921 reg = <0x0 0x27f0e000 0x0 0x20>; 922 }; 923 924 qos_ufshc: qos@27f0e080 { 925 compatible = "rockchip,rk3576-qos", "syscon"; 926 reg = <0x0 0x27f0e080 0x0 0x20>; 927 }; 928 929 qos_vepu0: qos@27f0f000 { 930 compatible = "rockchip,rk3576-qos", "syscon"; 931 reg = <0x0 0x27f0f000 0x0 0x20>; 932 }; 933 934 qos_isp_mro: qos@27f10000 { 935 compatible = "rockchip,rk3576-qos", "syscon"; 936 reg = <0x0 0x27f10000 0x0 0x20>; 937 }; 938 939 qos_isp_mwo: qos@27f10080 { 940 compatible = "rockchip,rk3576-qos", "syscon"; 941 reg = <0x0 0x27f10080 0x0 0x20>; 942 }; 943 944 qos_vicap_m0: qos@27f10100 { 945 compatible = "rockchip,rk3576-qos", "syscon"; 946 reg = <0x0 0x27f10100 0x0 0x20>; 947 }; 948 949 qos_vpss_mro: qos@27f10180 { 950 compatible = "rockchip,rk3576-qos", "syscon"; 951 reg = <0x0 0x27f10180 0x0 0x20>; 952 }; 953 954 qos_vpss_mwo: qos@27f10200 { 955 compatible = "rockchip,rk3576-qos", "syscon"; 956 reg = <0x0 0x27f10200 0x0 0x20>; 957 }; 958 959 qos_hdcp0: qos@27f11000 { 960 compatible = "rockchip,rk3576-qos", "syscon"; 961 reg = <0x0 0x27f11000 0x0 0x20>; 962 }; 963 964 qos_vop_m0: qos@27f12800 { 965 compatible = "rockchip,rk3576-qos", "syscon"; 966 reg = <0x0 0x27f12800 0x0 0x20>; 967 }; 968 969 qos_vop_m1ro: qos@27f12880 { 970 compatible = "rockchip,rk3576-qos", "syscon"; 971 reg = <0x0 0x27f12880 0x0 0x20>; 972 }; 973 974 qos_ebc: qos@27f13000 { 975 compatible = "rockchip,rk3576-qos", "syscon"; 976 reg = <0x0 0x27f13000 0x0 0x20>; 977 }; 978 979 qos_rga0: qos@27f13080 { 980 compatible = "rockchip,rk3576-qos", "syscon"; 981 reg = <0x0 0x27f13080 0x0 0x20>; 982 }; 983 984 qos_rga1: qos@27f13100 { 985 compatible = "rockchip,rk3576-qos", "syscon"; 986 reg = <0x0 0x27f13100 0x0 0x20>; 987 }; 988 989 qos_jpeg: qos@27f13180 { 990 compatible = "rockchip,rk3576-qos", "syscon"; 991 reg = <0x0 0x27f13180 0x0 0x20>; 992 }; 993 994 qos_vdpp: qos@27f13200 { 995 compatible = "rockchip,rk3576-qos", "syscon"; 996 reg = <0x0 0x27f13200 0x0 0x20>; 997 }; 998 999 qos_npu_m0: qos@27f20000 { 1000 compatible = "rockchip,rk3576-qos", "syscon"; 1001 reg = <0x0 0x27f20000 0x0 0x20>; 1002 }; 1003 1004 qos_npu_m1: qos@27f21000 { 1005 compatible = "rockchip,rk3576-qos", "syscon"; 1006 reg = <0x0 0x27f21000 0x0 0x20>; 1007 }; 1008 1009 qos_npu_m0ro: qos@27f22080 { 1010 compatible = "rockchip,rk3576-qos", "syscon"; 1011 reg = <0x0 0x27f22080 0x0 0x20>; 1012 }; 1013 1014 qos_npu_m1ro: qos@27f22100 { 1015 compatible = "rockchip,rk3576-qos", "syscon"; 1016 reg = <0x0 0x27f22100 0x0 0x20>; 1017 }; 1018 1019 gmac0: ethernet@2a220000 { 1020 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 1021 reg = <0x0 0x2a220000 0x0 0x10000>; 1022 clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>, 1023 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 1024 <&cru CLK_GMAC0_PTP_REF>; 1025 clock-names = "stmmaceth", "clk_mac_ref", 1026 "pclk_mac", "aclk_mac", 1027 "ptp_ref"; 1028 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1030 interrupt-names = "macirq", "eth_wake_irq"; 1031 power-domains = <&power RK3576_PD_SDGMAC>; 1032 resets = <&cru SRST_A_GMAC0>; 1033 reset-names = "stmmaceth"; 1034 rockchip,grf = <&sdgmac_grf>; 1035 rockchip,php-grf = <&ioc_grf>; 1036 snps,axi-config = <&gmac0_stmmac_axi_setup>; 1037 snps,mixed-burst; 1038 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 1039 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 1040 snps,tso; 1041 status = "disabled"; 1042 1043 mdio0: mdio { 1044 compatible = "snps,dwmac-mdio"; 1045 #address-cells = <0x1>; 1046 #size-cells = <0x0>; 1047 }; 1048 1049 gmac0_stmmac_axi_setup: stmmac-axi-config { 1050 snps,blen = <0 0 0 0 16 8 4>; 1051 snps,rd_osr_lmt = <8>; 1052 snps,wr_osr_lmt = <4>; 1053 }; 1054 1055 gmac0_mtl_rx_setup: rx-queues-config { 1056 snps,rx-queues-to-use = <1>; 1057 queue0 {}; 1058 }; 1059 1060 gmac0_mtl_tx_setup: tx-queues-config { 1061 snps,tx-queues-to-use = <1>; 1062 queue0 {}; 1063 }; 1064 }; 1065 1066 gmac1: ethernet@2a230000 { 1067 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 1068 reg = <0x0 0x2a230000 0x0 0x10000>; 1069 clocks = <&cru CLK_GMAC1_125M_SRC>, <&cru CLK_GMAC1_RMII_CRU>, 1070 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1071 <&cru CLK_GMAC1_PTP_REF>; 1072 clock-names = "stmmaceth", "clk_mac_ref", 1073 "pclk_mac", "aclk_mac", 1074 "ptp_ref"; 1075 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1077 interrupt-names = "macirq", "eth_wake_irq"; 1078 power-domains = <&power RK3576_PD_SDGMAC>; 1079 resets = <&cru SRST_A_GMAC1>; 1080 reset-names = "stmmaceth"; 1081 rockchip,grf = <&sdgmac_grf>; 1082 rockchip,php-grf = <&ioc_grf>; 1083 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1084 snps,mixed-burst; 1085 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1086 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1087 snps,tso; 1088 status = "disabled"; 1089 1090 mdio1: mdio { 1091 compatible = "snps,dwmac-mdio"; 1092 #address-cells = <0x1>; 1093 #size-cells = <0x0>; 1094 }; 1095 1096 gmac1_stmmac_axi_setup: stmmac-axi-config { 1097 snps,blen = <0 0 0 0 16 8 4>; 1098 snps,rd_osr_lmt = <8>; 1099 snps,wr_osr_lmt = <4>; 1100 }; 1101 1102 gmac1_mtl_rx_setup: rx-queues-config { 1103 snps,rx-queues-to-use = <1>; 1104 queue0 {}; 1105 }; 1106 1107 gmac1_mtl_tx_setup: tx-queues-config { 1108 snps,tx-queues-to-use = <1>; 1109 queue0 {}; 1110 }; 1111 }; 1112 1113 sdmmc: mmc@2a310000 { 1114 compatible = "rockchip,rk3576-dw-mshc"; 1115 reg = <0x0 0x2a310000 0x0 0x4000>; 1116 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; 1117 clock-names = "biu", "ciu"; 1118 fifo-depth = <0x100>; 1119 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 1120 max-frequency = <200000000>; 1121 pinctrl-names = "default"; 1122 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>; 1123 power-domains = <&power RK3576_PD_SDGMAC>; 1124 resets = <&cru SRST_H_SDMMC0>; 1125 reset-names = "reset"; 1126 status = "disabled"; 1127 }; 1128 1129 sdhci: mmc@2a330000 { 1130 compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc"; 1131 reg = <0x0 0x2a330000 0x0 0x10000>; 1132 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>; 1133 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1134 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 1135 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1136 <&cru TCLK_EMMC>; 1137 clock-names = "core", "bus", "axi", "block", "timer"; 1138 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 1139 max-frequency = <200000000>; 1140 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 1141 <&emmc_cmd>, <&emmc_strb>; 1142 pinctrl-names = "default"; 1143 power-domains = <&power RK3576_PD_NVM>; 1144 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1145 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1146 <&cru SRST_T_EMMC>; 1147 reset-names = "core", "bus", "axi", "block", "timer"; 1148 supports-cqe; 1149 status = "disabled"; 1150 }; 1151 1152 gic: interrupt-controller@2a701000 { 1153 compatible = "arm,gic-400"; 1154 reg = <0x0 0x2a701000 0 0x10000>, 1155 <0x0 0x2a702000 0 0x10000>, 1156 <0x0 0x2a704000 0 0x10000>, 1157 <0x0 0x2a706000 0 0x10000>; 1158 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1159 interrupt-controller; 1160 #interrupt-cells = <3>; 1161 #address-cells = <2>; 1162 #size-cells = <2>; 1163 }; 1164 1165 dmac0: dma-controller@2ab90000 { 1166 compatible = "arm,pl330", "arm,primecell"; 1167 reg = <0x0 0x2ab90000 0x0 0x4000>; 1168 arm,pl330-periph-burst; 1169 clocks = <&cru ACLK_DMAC0>; 1170 clock-names = "apb_pclk"; 1171 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1173 #dma-cells = <1>; 1174 }; 1175 1176 dmac1: dma-controller@2abb0000 { 1177 compatible = "arm,pl330", "arm,primecell"; 1178 reg = <0x0 0x2abb0000 0x0 0x4000>; 1179 arm,pl330-periph-burst; 1180 clocks = <&cru ACLK_DMAC1>; 1181 clock-names = "apb_pclk"; 1182 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1184 #dma-cells = <1>; 1185 }; 1186 1187 dmac2: dma-controller@2abd0000 { 1188 compatible = "arm,pl330", "arm,primecell"; 1189 reg = <0x0 0x2abd0000 0x0 0x4000>; 1190 arm,pl330-periph-burst; 1191 clocks = <&cru ACLK_DMAC2>; 1192 clock-names = "apb_pclk"; 1193 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1195 #dma-cells = <1>; 1196 }; 1197 1198 i2c1: i2c@2ac40000 { 1199 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1200 reg = <0x0 0x2ac40000 0x0 0x1000>; 1201 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1202 clock-names = "i2c", "pclk"; 1203 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1204 pinctrl-names = "default"; 1205 pinctrl-0 = <&i2c1m0_xfer>; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 status = "disabled"; 1209 }; 1210 1211 i2c2: i2c@2ac50000 { 1212 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1213 reg = <0x0 0x2ac50000 0x0 0x1000>; 1214 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1215 clock-names = "i2c", "pclk"; 1216 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1217 pinctrl-names = "default"; 1218 pinctrl-0 = <&i2c2m0_xfer>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 status = "disabled"; 1222 }; 1223 1224 i2c3: i2c@2ac60000 { 1225 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1226 reg = <0x0 0x2ac60000 0x0 0x1000>; 1227 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1228 clock-names = "i2c", "pclk"; 1229 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1230 pinctrl-names = "default"; 1231 pinctrl-0 = <&i2c3m0_xfer>; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 status = "disabled"; 1235 }; 1236 1237 i2c4: i2c@2ac70000 { 1238 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1239 reg = <0x0 0x2ac70000 0x0 0x1000>; 1240 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1241 clock-names = "i2c", "pclk"; 1242 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&i2c4m0_xfer>; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 status = "disabled"; 1248 }; 1249 1250 i2c5: i2c@2ac80000 { 1251 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1252 reg = <0x0 0x2ac80000 0x0 0x1000>; 1253 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1254 clock-names = "i2c", "pclk"; 1255 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1256 pinctrl-names = "default"; 1257 pinctrl-0 = <&i2c5m0_xfer>; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 status = "disabled"; 1261 }; 1262 1263 1264 i2c6: i2c@2ac90000 { 1265 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1266 reg = <0x0 0x2ac90000 0x0 0x1000>; 1267 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 1268 clock-names = "i2c", "pclk"; 1269 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1270 pinctrl-names = "default"; 1271 pinctrl-0 = <&i2c6m0_xfer>; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 status = "disabled"; 1275 }; 1276 1277 i2c7: i2c@2aca0000 { 1278 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1279 reg = <0x0 0x2aca0000 0x0 0x1000>; 1280 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 1281 clock-names = "i2c", "pclk"; 1282 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&i2c7m0_xfer>; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 status = "disabled"; 1288 }; 1289 1290 i2c8: i2c@2acb0000 { 1291 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1292 reg = <0x0 0x2acb0000 0x0 0x1000>; 1293 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 1294 clock-names = "i2c", "pclk"; 1295 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1296 pinctrl-names = "default"; 1297 pinctrl-0 = <&i2c8m0_xfer>; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 status = "disabled"; 1301 }; 1302 1303 timer0: timer@2acc0000 { 1304 compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer"; 1305 reg = <0x0 0x2acc0000 0x0 0x20>; 1306 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_TIMER0>; 1307 clock-names = "pclk", "timer"; 1308 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1309 }; 1310 1311 wdt: watchdog@2ace0000 { 1312 compatible = "rockchip,rk3576-wdt", "snps,dw-wdt"; 1313 reg = <0x0 0x2ace0000 0x0 0x100>; 1314 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 1315 clock-names = "tclk", "pclk"; 1316 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1317 status = "disabled"; 1318 }; 1319 1320 spi0: spi@2acf0000 { 1321 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 1322 reg = <0x0 0x2acf0000 0x0 0x1000>; 1323 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1324 clock-names = "spiclk", "apb_pclk"; 1325 dmas = <&dmac0 14>, <&dmac0 15>; 1326 dma-names = "tx", "rx"; 1327 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1328 num-cs = <2>; 1329 pinctrl-names = "default"; 1330 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; 1331 #address-cells = <1>; 1332 #size-cells = <0>; 1333 status = "disabled"; 1334 }; 1335 1336 spi1: spi@2ad00000 { 1337 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 1338 reg = <0x0 0x2ad00000 0x0 0x1000>; 1339 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1340 clock-names = "spiclk", "apb_pclk"; 1341 dmas = <&dmac0 16>, <&dmac0 17>; 1342 dma-names = "tx", "rx"; 1343 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1344 num-cs = <2>; 1345 pinctrl-names = "default"; 1346 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; 1347 #address-cells = <1>; 1348 #size-cells = <0>; 1349 status = "disabled"; 1350 }; 1351 1352 spi2: spi@2ad10000 { 1353 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 1354 reg = <0x0 0x2ad10000 0x0 0x1000>; 1355 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1356 clock-names = "spiclk", "apb_pclk"; 1357 dmas = <&dmac1 15>, <&dmac1 16>; 1358 dma-names = "tx", "rx"; 1359 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1360 num-cs = <2>; 1361 pinctrl-names = "default"; 1362 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; 1363 #address-cells = <1>; 1364 #size-cells = <0>; 1365 status = "disabled"; 1366 }; 1367 1368 spi3: spi@2ad20000 { 1369 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 1370 reg = <0x0 0x2ad20000 0x0 0x1000>; 1371 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1372 clock-names = "spiclk", "apb_pclk"; 1373 dmas = <&dmac1 17>, <&dmac1 18>; 1374 dma-names = "tx", "rx"; 1375 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1376 num-cs = <2>; 1377 pinctrl-names = "default"; 1378 pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>; 1379 #address-cells = <1>; 1380 #size-cells = <0>; 1381 status = "disabled"; 1382 }; 1383 1384 spi4: spi@2ad30000 { 1385 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 1386 reg = <0x0 0x2ad30000 0x0 0x1000>; 1387 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 1388 clock-names = "spiclk", "apb_pclk"; 1389 dmas = <&dmac2 12>, <&dmac2 13>; 1390 dma-names = "tx", "rx"; 1391 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1392 num-cs = <2>; 1393 pinctrl-names = "default"; 1394 pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>; 1395 #address-cells = <1>; 1396 #size-cells = <0>; 1397 status = "disabled"; 1398 }; 1399 1400 uart0: serial@2ad40000 { 1401 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1402 reg = <0x0 0x2ad40000 0x0 0x100>; 1403 reg-shift = <2>; 1404 reg-io-width = <4>; 1405 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 1406 clock-names = "baudclk", "apb_pclk"; 1407 dmas = <&dmac0 6>, <&dmac0 7>; 1408 dma-names = "tx", "rx"; 1409 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1410 pinctrl-0 = <&uart0m0_xfer>; 1411 pinctrl-names = "default"; 1412 status = "disabled"; 1413 }; 1414 1415 uart2: serial@2ad50000 { 1416 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1417 reg = <0x0 0x2ad50000 0x0 0x100>; 1418 reg-shift = <2>; 1419 reg-io-width = <4>; 1420 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1421 clock-names = "baudclk", "apb_pclk"; 1422 dmas = <&dmac0 10>, <&dmac0 11>; 1423 dma-names = "tx", "rx"; 1424 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1425 pinctrl-names = "default"; 1426 pinctrl-0 = <&uart2m0_xfer>; 1427 status = "disabled"; 1428 }; 1429 1430 uart3: serial@2ad60000 { 1431 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1432 reg = <0x0 0x2ad60000 0x0 0x100>; 1433 reg-shift = <2>; 1434 reg-io-width = <4>; 1435 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1436 clock-names = "baudclk", "apb_pclk"; 1437 dmas = <&dmac0 12>, <&dmac0 13>; 1438 dma-names = "tx", "rx"; 1439 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1440 pinctrl-0 = <&uart3m0_xfer>; 1441 pinctrl-names = "default"; 1442 status = "disabled"; 1443 }; 1444 1445 uart4: serial@2ad70000 { 1446 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1447 reg = <0x0 0x2ad70000 0x0 0x100>; 1448 reg-shift = <2>; 1449 reg-io-width = <4>; 1450 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1451 clock-names = "baudclk", "apb_pclk"; 1452 dmas = <&dmac1 9>, <&dmac1 10>; 1453 dma-names = "tx", "rx"; 1454 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1455 pinctrl-0 = <&uart4m0_xfer>; 1456 pinctrl-names = "default"; 1457 status = "disabled"; 1458 }; 1459 1460 uart5: serial@2ad80000 { 1461 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1462 reg = <0x0 0x2ad80000 0x0 0x100>; 1463 reg-shift = <2>; 1464 reg-io-width = <4>; 1465 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1466 clock-names = "baudclk", "apb_pclk"; 1467 dmas = <&dmac1 11>, <&dmac1 12>; 1468 dma-names = "tx", "rx"; 1469 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1470 pinctrl-0 = <&uart5m0_xfer>; 1471 pinctrl-names = "default"; 1472 status = "disabled"; 1473 }; 1474 1475 uart6: serial@2ad90000 { 1476 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1477 reg = <0x0 0x2ad90000 0x0 0x100>; 1478 reg-shift = <2>; 1479 reg-io-width = <4>; 1480 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1481 clock-names = "baudclk", "apb_pclk"; 1482 dmas = <&dmac1 13>, <&dmac1 14>; 1483 dma-names = "tx", "rx"; 1484 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1485 pinctrl-0 = <&uart6m0_xfer>; 1486 pinctrl-names = "default"; 1487 status = "disabled"; 1488 }; 1489 1490 uart7: serial@2ada0000 { 1491 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1492 reg = <0x0 0x2ada0000 0x0 0x100>; 1493 reg-shift = <2>; 1494 reg-io-width = <4>; 1495 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1496 clock-names = "baudclk", "apb_pclk"; 1497 dmas = <&dmac2 6>, <&dmac2 7>; 1498 dma-names = "tx", "rx"; 1499 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1500 pinctrl-0 = <&uart7m0_xfer>; 1501 pinctrl-names = "default"; 1502 status = "disabled"; 1503 }; 1504 1505 uart8: serial@2adb0000 { 1506 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1507 reg = <0x0 0x2adb0000 0x0 0x100>; 1508 reg-shift = <2>; 1509 reg-io-width = <4>; 1510 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1511 clock-names = "baudclk", "apb_pclk"; 1512 dmas = <&dmac2 8>, <&dmac2 9>; 1513 dma-names = "tx", "rx"; 1514 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1515 pinctrl-0 = <&uart8m0_xfer>; 1516 pinctrl-names = "default"; 1517 status = "disabled"; 1518 }; 1519 1520 uart9: serial@2adc0000 { 1521 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1522 reg = <0x0 0x2adc0000 0x0 0x100>; 1523 reg-shift = <2>; 1524 reg-io-width = <4>; 1525 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1526 clock-names = "baudclk", "apb_pclk"; 1527 dmas = <&dmac2 10>, <&dmac2 11>; 1528 dma-names = "tx", "rx"; 1529 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1530 pinctrl-0 = <&uart9m0_xfer>; 1531 pinctrl-names = "default"; 1532 status = "disabled"; 1533 }; 1534 1535 saradc: adc@2ae00000 { 1536 compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc"; 1537 reg = <0x0 0x2ae00000 0x0 0x10000>; 1538 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1539 clock-names = "saradc", "apb_pclk"; 1540 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1541 resets = <&cru SRST_P_SARADC>; 1542 reset-names = "saradc-apb"; 1543 #io-channel-cells = <1>; 1544 status = "disabled"; 1545 }; 1546 1547 i2c9: i2c@2ae80000 { 1548 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1549 reg = <0x0 0x2ae80000 0x0 0x1000>; 1550 clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>; 1551 clock-names = "i2c", "pclk"; 1552 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1553 pinctrl-names = "default"; 1554 pinctrl-0 = <&i2c9m0_xfer>; 1555 resets = <&cru SRST_I2C9>, <&cru SRST_P_I2C9>; 1556 reset-names = "i2c", "apb"; 1557 #address-cells = <1>; 1558 #size-cells = <0>; 1559 status = "disabled"; 1560 }; 1561 1562 uart10: serial@2afc0000 { 1563 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1564 reg = <0x0 0x2afc0000 0x0 0x100>; 1565 reg-shift = <2>; 1566 reg-io-width = <4>; 1567 clocks = <&cru SCLK_UART10>, <&cru PCLK_UART10>; 1568 clock-names = "baudclk", "apb_pclk"; 1569 dmas = <&dmac2 21>, <&dmac2 22>; 1570 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1571 pinctrl-names = "default"; 1572 pinctrl-0 = <&uart10m0_xfer>; 1573 status = "disabled"; 1574 }; 1575 1576 uart11: serial@2afd0000 { 1577 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1578 reg = <0x0 0x2afd0000 0x0 0x100>; 1579 reg-shift = <2>; 1580 reg-io-width = <4>; 1581 clocks = <&cru SCLK_UART11>, <&cru PCLK_UART11>; 1582 clock-names = "baudclk", "apb_pclk"; 1583 dmas = <&dmac2 23>, <&dmac2 24>; 1584 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1585 pinctrl-names = "default"; 1586 pinctrl-0 = <&uart11m0_xfer>; 1587 status = "disabled"; 1588 }; 1589 1590 sram: sram@3ff88000 { 1591 compatible = "mmio-sram"; 1592 reg = <0x0 0x3ff88000 0x0 0x78000>; 1593 ranges = <0x0 0x0 0x3ff88000 0x78000>; 1594 #address-cells = <1>; 1595 #size-cells = <1>; 1596 1597 /* start address and size should be 4k align */ 1598 rkvdec_sram: rkvdec-sram@0 { 1599 reg = <0x0 0x78000>; 1600 }; 1601 }; 1602 1603 scmi_shmem: scmi-shmem@4010f000 { 1604 compatible = "arm,scmi-shmem"; 1605 reg = <0x0 0x4010f000 0x0 0x100>; 1606 }; 1607 1608 pinctrl: pinctrl { 1609 compatible = "rockchip,rk3576-pinctrl"; 1610 rockchip,grf = <&ioc_grf>; 1611 #address-cells = <2>; 1612 #size-cells = <2>; 1613 ranges; 1614 1615 gpio0: gpio@27320000 { 1616 compatible = "rockchip,gpio-bank"; 1617 reg = <0x0 0x27320000 0x0 0x200>; 1618 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 1619 gpio-controller; 1620 gpio-ranges = <&pinctrl 0 0 32>; 1621 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1622 interrupt-controller; 1623 #gpio-cells = <2>; 1624 #interrupt-cells = <2>; 1625 }; 1626 1627 gpio1: gpio@2ae10000 { 1628 compatible = "rockchip,gpio-bank"; 1629 reg = <0x0 0x2ae10000 0x0 0x200>; 1630 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1631 gpio-controller; 1632 gpio-ranges = <&pinctrl 0 32 32>; 1633 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1634 interrupt-controller; 1635 #gpio-cells = <2>; 1636 #interrupt-cells = <2>; 1637 }; 1638 1639 gpio2: gpio@2ae20000 { 1640 compatible = "rockchip,gpio-bank"; 1641 reg = <0x0 0x2ae20000 0x0 0x200>; 1642 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1643 gpio-controller; 1644 gpio-ranges = <&pinctrl 0 64 32>; 1645 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1646 interrupt-controller; 1647 #gpio-cells = <2>; 1648 #interrupt-cells = <2>; 1649 }; 1650 1651 gpio3: gpio@2ae30000 { 1652 compatible = "rockchip,gpio-bank"; 1653 reg = <0x0 0x2ae30000 0x0 0x200>; 1654 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1655 gpio-controller; 1656 gpio-ranges = <&pinctrl 0 96 32>; 1657 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1658 interrupt-controller; 1659 #gpio-cells = <2>; 1660 #interrupt-cells = <2>; 1661 }; 1662 1663 gpio4: gpio@2ae40000 { 1664 compatible = "rockchip,gpio-bank"; 1665 reg = <0x0 0x2ae40000 0x0 0x200>; 1666 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1667 gpio-controller; 1668 gpio-ranges = <&pinctrl 0 128 32>; 1669 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1670 interrupt-controller; 1671 #gpio-cells = <2>; 1672 #interrupt-cells = <2>; 1673 }; 1674 }; 1675 }; 1676}; 1677 1678#include "rk3576-pinctrl.dtsi" 1679