xref: /linux/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi (revision 7f71507851fc7764b36a3221839607d3a45c2025)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/pinctrl/rockchip.h>
7#include "rockchip-pinconf.dtsi"
8
9/*
10 * This file is auto generated by pin2dts tool, please keep these code
11 * by adding changes at end of this file.
12 */
13&pinctrl {
14	aupll_clk {
15		/omit-if-no-ref/
16		aupll_clkm0_pins: aupll_clkm0-pins {
17			rockchip,pins =
18				/* aupll_clk_in_m0 */
19				<0 RK_PA0 3 &pcfg_pull_none>;
20		};
21
22		/omit-if-no-ref/
23		aupll_clkm1_pins: aupll_clkm1-pins {
24			rockchip,pins =
25				/* aupll_clk_in_m1 */
26				<0 RK_PB0 3 &pcfg_pull_none>;
27		};
28
29		/omit-if-no-ref/
30		aupll_clkm2_pins: aupll_clkm2-pins {
31			rockchip,pins =
32				/* aupll_clk_in_m2 */
33				<4 RK_PA2 3 &pcfg_pull_none>;
34		};
35	};
36
37	cam_clk0 {
38		/omit-if-no-ref/
39		cam_clk0m0_clk0: cam_clk0m0-clk0 {
40			rockchip,pins =
41				/* cam_clk0_out_m0 */
42				<3 RK_PD7 3 &pcfg_pull_none>;
43		};
44
45		/omit-if-no-ref/
46		cam_clk0m1_clk0: cam_clk0m1-clk0 {
47			rockchip,pins =
48				/* cam_clk0_out_m1 */
49				<2 RK_PD2 1 &pcfg_pull_none>;
50		};
51	};
52
53	cam_clk1 {
54		/omit-if-no-ref/
55		cam_clk1m0_clk1: cam_clk1m0-clk1 {
56			rockchip,pins =
57				/* cam_clk1_out_m0 */
58				<4 RK_PA0 3 &pcfg_pull_none>;
59		};
60
61		/omit-if-no-ref/
62		cam_clk1m1_clk1: cam_clk1m1-clk1 {
63			rockchip,pins =
64				/* cam_clk1_out_m1 */
65				<2 RK_PD6 1 &pcfg_pull_none>;
66		};
67	};
68
69	cam_clk2 {
70		/omit-if-no-ref/
71		cam_clk2m0_clk2: cam_clk2m0-clk2 {
72			rockchip,pins =
73				/* cam_clk2_out_m0 */
74				<4 RK_PA1 3 &pcfg_pull_none>;
75		};
76
77		/omit-if-no-ref/
78		cam_clk2m1_clk2: cam_clk2m1-clk2 {
79			rockchip,pins =
80				/* cam_clk2_out_m1 */
81				<2 RK_PD7 1 &pcfg_pull_none>;
82		};
83	};
84
85	can0 {
86		/omit-if-no-ref/
87		can0m0_pins: can0m0-pins {
88			rockchip,pins =
89				/* can0_rx_m0 */
90				<2 RK_PA0 13 &pcfg_pull_none>,
91				/* can0_tx_m0 */
92				<2 RK_PA1 13 &pcfg_pull_none>;
93		};
94
95		/omit-if-no-ref/
96		can0m1_pins: can0m1-pins {
97			rockchip,pins =
98				/* can0_rx_m1 */
99				<4 RK_PC3 12 &pcfg_pull_none>,
100				/* can0_tx_m1 */
101				<4 RK_PC2 12 &pcfg_pull_none>;
102		};
103
104		/omit-if-no-ref/
105		can0m2_pins: can0m2-pins {
106			rockchip,pins =
107				/* can0_rx_m2 */
108				<4 RK_PA6 13 &pcfg_pull_none>,
109				/* can0_tx_m2 */
110				<4 RK_PA4 13 &pcfg_pull_none>;
111		};
112
113		/omit-if-no-ref/
114		can0m3_pins: can0m3-pins {
115			rockchip,pins =
116				/* can0_rx_m3 */
117				<3 RK_PC1 12 &pcfg_pull_none>,
118				/* can0_tx_m3 */
119				<3 RK_PC4 12 &pcfg_pull_none>;
120		};
121	};
122
123	can1 {
124		/omit-if-no-ref/
125		can1m0_pins: can1m0-pins {
126			rockchip,pins =
127				/* can1_rx_m0 */
128				<2 RK_PA2 13 &pcfg_pull_none>,
129				/* can1_tx_m0 */
130				<2 RK_PA3 13 &pcfg_pull_none>;
131		};
132
133		/omit-if-no-ref/
134		can1m1_pins: can1m1-pins {
135			rockchip,pins =
136				/* can1_rx_m1 */
137				<4 RK_PC7 13 &pcfg_pull_none>,
138				/* can1_tx_m1 */
139				<4 RK_PC6 13 &pcfg_pull_none>;
140		};
141
142		/omit-if-no-ref/
143		can1m2_pins: can1m2-pins {
144			rockchip,pins =
145				/* can1_rx_m2 */
146				<4 RK_PB4 13 &pcfg_pull_none>,
147				/* can1_tx_m2 */
148				<4 RK_PB5 13 &pcfg_pull_none>;
149		};
150
151		/omit-if-no-ref/
152		can1m3_pins: can1m3-pins {
153			rockchip,pins =
154				/* can1_rx_m3 */
155				<3 RK_PA3 11 &pcfg_pull_none>,
156				/* can1_tx_m3 */
157				<3 RK_PA2 11 &pcfg_pull_none>;
158		};
159	};
160
161	clk0_32k {
162		/omit-if-no-ref/
163		clk0_32k_pins: clk0_32k-pins {
164			rockchip,pins =
165				/* clk0_32k_out */
166				<0 RK_PA2 10 &pcfg_pull_none>;
167		};
168	};
169
170	clk1_32k {
171		/omit-if-no-ref/
172		clk1_32k_pins: clk1_32k-pins {
173			rockchip,pins =
174				/* clk1_32k_out */
175				<1 RK_PD5 13 &pcfg_pull_none>;
176		};
177	};
178
179	clk_32k {
180		/omit-if-no-ref/
181		clk_32k_pins: clk_32k-pins {
182			rockchip,pins =
183				/* clk_32k_in */
184				<0 RK_PA2 9 &pcfg_pull_none>;
185		};
186	};
187
188	cpubig {
189		/omit-if-no-ref/
190		cpubig_pins: cpubig-pins {
191			rockchip,pins =
192				/* cpubig_avs */
193				<0 RK_PD2 11 &pcfg_pull_none>;
194		};
195	};
196
197	cpulit {
198		/omit-if-no-ref/
199		cpulit_pins: cpulit-pins {
200			rockchip,pins =
201				/* cpulit_avs */
202				<0 RK_PC0 11 &pcfg_pull_none>;
203		};
204	};
205
206	debug0_test {
207		/omit-if-no-ref/
208		debug0_test_pins: debug0_test-pins {
209			rockchip,pins =
210				/* debug0_test_out */
211				<1 RK_PC4 7 &pcfg_pull_none>;
212		};
213	};
214
215	debug1_test {
216		/omit-if-no-ref/
217		debug1_test_pins: debug1_test-pins {
218			rockchip,pins =
219				/* debug1_test_out */
220				<1 RK_PC5 7 &pcfg_pull_none>;
221		};
222	};
223
224	debug2_test {
225		/omit-if-no-ref/
226		debug2_test_pins: debug2_test-pins {
227			rockchip,pins =
228				/* debug2_test_out */
229				<1 RK_PC6 7 &pcfg_pull_none>;
230		};
231	};
232
233	debug3_test {
234		/omit-if-no-ref/
235		debug3_test_pins: debug3_test-pins {
236			rockchip,pins =
237				/* debug3_test_out */
238				<1 RK_PC7 7 &pcfg_pull_none>;
239		};
240	};
241
242	debug4_test {
243		/omit-if-no-ref/
244		debug4_test_pins: debug4_test-pins {
245			rockchip,pins =
246				/* debug4_test_out */
247				<1 RK_PD0 7 &pcfg_pull_none>;
248		};
249	};
250
251	debug5_test {
252		/omit-if-no-ref/
253		debug5_test_pins: debug5_test-pins {
254			rockchip,pins =
255				/* debug5_test_out */
256				<1 RK_PD1 7 &pcfg_pull_none>;
257		};
258	};
259
260	debug6_test {
261		/omit-if-no-ref/
262		debug6_test_pins: debug6_test-pins {
263			rockchip,pins =
264				/* debug6_test_out */
265				<1 RK_PD2 7 &pcfg_pull_none>;
266		};
267	};
268
269	debug7_test {
270		/omit-if-no-ref/
271		debug7_test_pins: debug7_test-pins {
272			rockchip,pins =
273				/* debug7_test_out */
274				<1 RK_PD3 7 &pcfg_pull_none>;
275		};
276	};
277
278	dp {
279		/omit-if-no-ref/
280		dpm0_pins: dpm0-pins {
281			rockchip,pins =
282				/* dp_hpdin_m0 */
283				<4 RK_PC4 10 &pcfg_pull_none>;
284		};
285
286		/omit-if-no-ref/
287		dpm1_pins: dpm1-pins {
288			rockchip,pins =
289				/* dp_hpdin_m1 */
290				<0 RK_PC5 9 &pcfg_pull_none>;
291		};
292	};
293
294	dsm_aud {
295		/omit-if-no-ref/
296		dsm_audm0_ln: dsm_audm0-ln {
297			rockchip,pins =
298				/* dsm_aud_ln_m0 */
299				<2 RK_PA1 3 &pcfg_pull_none>;
300		};
301
302		/omit-if-no-ref/
303		dsm_audm0_lp: dsm_audm0-lp {
304			rockchip,pins =
305				/* dsm_aud_lp_m0 */
306				<2 RK_PA0 3 &pcfg_pull_none>;
307		};
308
309		/omit-if-no-ref/
310		dsm_audm0_rn: dsm_audm0-rn {
311			rockchip,pins =
312				/* dsm_aud_rn_m0 */
313				<2 RK_PA3 3 &pcfg_pull_none>;
314		};
315
316		/omit-if-no-ref/
317		dsm_audm0_rp: dsm_audm0-rp {
318			rockchip,pins =
319				/* dsm_aud_rp_m0 */
320				<2 RK_PA2 3 &pcfg_pull_none>;
321		};
322
323		/omit-if-no-ref/
324		dsm_audm1_ln: dsm_audm1-ln {
325			rockchip,pins =
326				/* dsm_aud_ln_m1 */
327				<4 RK_PC1 1 &pcfg_pull_none>;
328		};
329
330		/omit-if-no-ref/
331		dsm_audm1_lp: dsm_audm1-lp {
332			rockchip,pins =
333				/* dsm_aud_lp_m1 */
334				<4 RK_PC0 1 &pcfg_pull_none>;
335		};
336
337		/omit-if-no-ref/
338		dsm_audm1_rn: dsm_audm1-rn {
339			rockchip,pins =
340				/* dsm_aud_rn_m1 */
341				<4 RK_PC3 1 &pcfg_pull_none>;
342		};
343
344		/omit-if-no-ref/
345		dsm_audm1_rp: dsm_audm1-rp {
346			rockchip,pins =
347				/* dsm_aud_rp_m1 */
348				<4 RK_PC2 1 &pcfg_pull_none>;
349		};
350	};
351
352	dsmc {
353		/omit-if-no-ref/
354		dsmc_clkn: dsmc-clkn {
355			rockchip,pins =
356				/* dsmc_clkn */
357				<3 RK_PD6 5 &pcfg_pull_none>;
358		};
359		/omit-if-no-ref/
360		dsmc_clkp: dsmc-clkp {
361			rockchip,pins =
362				/* dsmc_clkp */
363				<3 RK_PD5 5 &pcfg_pull_none>;
364		};
365		/omit-if-no-ref/
366		dsmc_csn0: dsmc-csn0 {
367			rockchip,pins =
368				/* dsmc_csn0 */
369				<3 RK_PD3 5 &pcfg_pull_none>;
370		};
371		/omit-if-no-ref/
372		dsmc_csn1: dsmc-csn1 {
373			rockchip,pins =
374				/* dsmc_csn1 */
375				<3 RK_PB0 5 &pcfg_pull_none>;
376		};
377		/omit-if-no-ref/
378		dsmc_csn2: dsmc-csn2 {
379			rockchip,pins =
380				/* dsmc_csn2 */
381				<3 RK_PD1 5 &pcfg_pull_none>;
382		};
383		/omit-if-no-ref/
384		dsmc_csn3: dsmc-csn3 {
385			rockchip,pins =
386				/* dsmc_csn3 */
387				<3 RK_PD2 5 &pcfg_pull_none>;
388		};
389		/omit-if-no-ref/
390		dsmc_data0: dsmc-data0 {
391			rockchip,pins =
392				/* dsmc_data0 */
393				<3 RK_PD4 5 &pcfg_pull_none>;
394		};
395		/omit-if-no-ref/
396		dsmc_data1: dsmc-data1 {
397			rockchip,pins =
398				/* dsmc_data1 */
399				<3 RK_PD0 5 &pcfg_pull_none>;
400		};
401		/omit-if-no-ref/
402		dsmc_data2: dsmc-data2 {
403			rockchip,pins =
404				/* dsmc_data2 */
405				<3 RK_PC7 5 &pcfg_pull_none>;
406		};
407		/omit-if-no-ref/
408		dsmc_data3: dsmc-data3 {
409			rockchip,pins =
410				/* dsmc_data3 */
411				<3 RK_PC6 5 &pcfg_pull_none>;
412		};
413		/omit-if-no-ref/
414		dsmc_data4: dsmc-data4 {
415			rockchip,pins =
416				/* dsmc_data4 */
417				<3 RK_PC5 5 &pcfg_pull_none>;
418		};
419		/omit-if-no-ref/
420		dsmc_data5: dsmc-data5 {
421			rockchip,pins =
422				/* dsmc_data5 */
423				<3 RK_PC4 5 &pcfg_pull_none>;
424		};
425		/omit-if-no-ref/
426		dsmc_data6: dsmc-data6 {
427			rockchip,pins =
428				/* dsmc_data6 */
429				<3 RK_PC1 5 &pcfg_pull_none>;
430		};
431		/omit-if-no-ref/
432		dsmc_data7: dsmc-data7 {
433			rockchip,pins =
434				/* dsmc_data7 */
435				<3 RK_PC0 5 &pcfg_pull_none>;
436		};
437		/omit-if-no-ref/
438		dsmc_data8: dsmc-data8 {
439			rockchip,pins =
440				/* dsmc_data8 */
441				<3 RK_PB5 5 &pcfg_pull_none>;
442		};
443		/omit-if-no-ref/
444		dsmc_data9: dsmc-data9 {
445			rockchip,pins =
446				/* dsmc_data9 */
447				<3 RK_PB4 5 &pcfg_pull_none>;
448		};
449		/omit-if-no-ref/
450		dsmc_data10: dsmc-data10 {
451			rockchip,pins =
452				/* dsmc_data10 */
453				<3 RK_PB3 5 &pcfg_pull_none>;
454		};
455		/omit-if-no-ref/
456		dsmc_data11: dsmc-data11 {
457			rockchip,pins =
458				/* dsmc_data11 */
459				<3 RK_PB2 5 &pcfg_pull_none>;
460		};
461		/omit-if-no-ref/
462		dsmc_data12: dsmc-data12 {
463			rockchip,pins =
464				/* dsmc_data12 */
465				<3 RK_PB1 5 &pcfg_pull_none>;
466		};
467		/omit-if-no-ref/
468		dsmc_data13: dsmc-data13 {
469			rockchip,pins =
470				/* dsmc_data13 */
471				<3 RK_PA7 5 &pcfg_pull_none>;
472		};
473		/omit-if-no-ref/
474		dsmc_data14: dsmc-data14 {
475			rockchip,pins =
476				/* dsmc_data14 */
477				<3 RK_PA6 5 &pcfg_pull_none>;
478		};
479		/omit-if-no-ref/
480		dsmc_data15: dsmc-data15 {
481			rockchip,pins =
482				/* dsmc_data15 */
483				<3 RK_PA5 5 &pcfg_pull_none>;
484		};
485		/omit-if-no-ref/
486		dsmc_dqs0: dsmc-dqs0 {
487			rockchip,pins =
488				/* dsmc_dqs0 */
489				<3 RK_PB7 5 &pcfg_pull_none>;
490		};
491		/omit-if-no-ref/
492		dsmc_dqs1: dsmc-dqs1 {
493			rockchip,pins =
494				/* dsmc_dqs1 */
495				<3 RK_PB6 5 &pcfg_pull_none>;
496		};
497		/omit-if-no-ref/
498		dsmc_int0: dsmc-int0 {
499			rockchip,pins =
500				/* dsmc_int0 */
501				<4 RK_PA0 5 &pcfg_pull_none>;
502		};
503		/omit-if-no-ref/
504		dsmc_int1: dsmc-int1 {
505			rockchip,pins =
506				/* dsmc_int1 */
507				<3 RK_PC2 5 &pcfg_pull_none>;
508		};
509		/omit-if-no-ref/
510		dsmc_int2: dsmc-int2 {
511			rockchip,pins =
512				/* dsmc_int2 */
513				<4 RK_PA1 5 &pcfg_pull_none>;
514		};
515		/omit-if-no-ref/
516		dsmc_int3: dsmc-int3 {
517			rockchip,pins =
518				/* dsmc_int3 */
519				<3 RK_PC3 5 &pcfg_pull_none>;
520		};
521		/omit-if-no-ref/
522		dsmc_rdyn: dsmc-rdyn {
523			rockchip,pins =
524				/* dsmc_rdyn */
525				<3 RK_PA4 5 &pcfg_pull_none>;
526		};
527		/omit-if-no-ref/
528		dsmc_resetn: dsmc-resetn {
529			rockchip,pins =
530				/* dsmc_resetn */
531				<3 RK_PD7 5 &pcfg_pull_none>;
532		};
533	};
534
535	dsmc_testclk {
536		/omit-if-no-ref/
537		dsmc_testclk_out: dsmc-testclk-out {
538			rockchip,pins =
539				/* dsmc_testclk_out */
540				<3 RK_PC2 7 &pcfg_pull_none>;
541		};
542	};
543
544	dsmc_testdata {
545		/omit-if-no-ref/
546		dsmc_testdata_out: dsmc-testdata-out {
547			rockchip,pins =
548				/* dsmc_testdata_out */
549				<3 RK_PC3 7 &pcfg_pull_none>;
550		};
551	};
552
553	edp_tx {
554		/omit-if-no-ref/
555		edp_txm0_pins: edp_txm0-pins {
556			rockchip,pins =
557				/* edp_tx_hpdin_m0 */
558				<4 RK_PC1 12 &pcfg_pull_none>;
559		};
560
561		/omit-if-no-ref/
562		edp_txm1_pins: edp_txm1-pins {
563			rockchip,pins =
564				/* edp_tx_hpdin_m1 */
565				<0 RK_PB6 10 &pcfg_pull_none>;
566		};
567	};
568
569	emmc {
570		/omit-if-no-ref/
571		emmc_rstnout: emmc-rstnout {
572			rockchip,pins =
573				/* emmc_rstn */
574				<1 RK_PB3 1 &pcfg_pull_none>;
575		};
576
577		/omit-if-no-ref/
578		emmc_bus8: emmc-bus8 {
579			rockchip,pins =
580				/* emmc_d0 */
581				<1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
582				/* emmc_d1 */
583				<1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
584				/* emmc_d2 */
585				<1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
586				/* emmc_d3 */
587				<1 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
588				/* emmc_d4 */
589				<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
590				/* emmc_d5 */
591				<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
592				/* emmc_d6 */
593				<1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
594				/* emmc_d7 */
595				<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
596		};
597
598		/omit-if-no-ref/
599		emmc_clk: emmc-clk {
600			rockchip,pins =
601				/* emmc_clk */
602				<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
603		};
604
605		/omit-if-no-ref/
606		emmc_cmd: emmc-cmd {
607			rockchip,pins =
608				/* emmc_cmd */
609				<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
610		};
611
612		/omit-if-no-ref/
613		emmc_strb: emmc-strb {
614			rockchip,pins =
615				/* emmc_strb */
616				<1 RK_PB2 1 &pcfg_pull_none>;
617		};
618	};
619
620	emmc_testclk {
621		/omit-if-no-ref/
622		emmc_testclk_test: emmc_testclk-test {
623			rockchip,pins =
624				/* emmc_testclk_out */
625				<1 RK_PB3 6 &pcfg_pull_none>;
626		};
627	};
628
629	emmc_testdata {
630		/omit-if-no-ref/
631		emmc_testdata_test: emmc_testdata-test {
632			rockchip,pins =
633				/* emmc_testdata_out */
634				<1 RK_PB7 5 &pcfg_pull_none>;
635		};
636	};
637
638	eth0 {
639		/omit-if-no-ref/
640		eth0m0_miim: eth0m0-miim {
641			rockchip,pins =
642				/* eth0_mdc_m0 */
643				<3 RK_PA6 3 &pcfg_pull_none>,
644				/* eth0_mdio_m0 */
645				<3 RK_PA5 3 &pcfg_pull_none>;
646		};
647
648		/omit-if-no-ref/
649		eth0m0_rx_bus2: eth0m0-rx_bus2 {
650			rockchip,pins =
651				/* eth0_rxctl_m0 */
652				<3 RK_PA7 3 &pcfg_pull_none>,
653				/* eth0_rxd0_m0 */
654				<3 RK_PB2 3 &pcfg_pull_none>,
655				/* eth0_rxd1_m0 */
656				<3 RK_PB1 3 &pcfg_pull_none>;
657		};
658
659		/omit-if-no-ref/
660		eth0m0_tx_bus2: eth0m0-tx_bus2 {
661			rockchip,pins =
662				/* eth0_txctl_m0 */
663				<3 RK_PB3 3 &pcfg_pull_none>,
664				/* eth0_txd0_m0 */
665				<3 RK_PB5 3 &pcfg_pull_none>,
666				/* eth0_txd1_m0 */
667				<3 RK_PB4 3 &pcfg_pull_none>;
668		};
669
670		/omit-if-no-ref/
671		eth0m0_rgmii_clk: eth0m0-rgmii_clk {
672			rockchip,pins =
673				/* eth0_rxclk_m0 */
674				<3 RK_PD1 3 &pcfg_pull_none>,
675				/* eth0_txclk_m0 */
676				<3 RK_PB6 3 &pcfg_pull_none>;
677		};
678
679		/omit-if-no-ref/
680		eth0m0_rgmii_bus: eth0m0-rgmii_bus {
681			rockchip,pins =
682				/* eth0_rxd2_m0 */
683				<3 RK_PD3 3 &pcfg_pull_none>,
684				/* eth0_rxd3_m0 */
685				<3 RK_PD2 3 &pcfg_pull_none>,
686				/* eth0_txd2_m0 */
687				<3 RK_PC3 3 &pcfg_pull_none>,
688				/* eth0_txd3_m0 */
689				<3 RK_PC2 3 &pcfg_pull_none>;
690		};
691
692		/omit-if-no-ref/
693		eth0m0_mclk: eth0m0-mclk {
694			rockchip,pins =
695				/* eth0m0_mclk */
696				<3 RK_PB0 3 &pcfg_pull_none>;
697		};
698		/omit-if-no-ref/
699		eth0m0_ppsclk: eth0m0-ppsclk {
700			rockchip,pins =
701				/* eth0m0_ppsclk */
702				<3 RK_PC0 3 &pcfg_pull_none>;
703		};
704		/omit-if-no-ref/
705		eth0m0_ppstrig: eth0m0-ppstrig {
706			rockchip,pins =
707				/* eth0m0_ppstrig */
708				<3 RK_PB7 3 &pcfg_pull_none>;
709		};
710
711		/omit-if-no-ref/
712		eth0m1_miim: eth0m1-miim {
713			rockchip,pins =
714				/* eth0_mdc_m1 */
715				<3 RK_PA1 3 &pcfg_pull_none>,
716				/* eth0_mdio_m1 */
717				<3 RK_PA0 3 &pcfg_pull_none>;
718		};
719
720		/omit-if-no-ref/
721		eth0m1_rx_bus2: eth0m1-rx_bus2 {
722			rockchip,pins =
723				/* eth0_rxctl_m1 */
724				<3 RK_PA2 3 &pcfg_pull_none>,
725				/* eth0_rxd0_m1 */
726				<2 RK_PA6 3 &pcfg_pull_none>,
727				/* eth0_rxd1_m1 */
728				<3 RK_PA3 3 &pcfg_pull_none>;
729		};
730
731		/omit-if-no-ref/
732		eth0m1_tx_bus2: eth0m1-tx_bus2 {
733			rockchip,pins =
734				/* eth0_txctl_m1 */
735				<2 RK_PA7 3 &pcfg_pull_none>,
736				/* eth0_txd0_m1 */
737				<2 RK_PB1 3 &pcfg_pull_none>,
738				/* eth0_txd1_m1 */
739				<2 RK_PB0 3 &pcfg_pull_none>;
740		};
741
742		/omit-if-no-ref/
743		eth0m1_rgmii_clk: eth0m1-rgmii_clk {
744			rockchip,pins =
745				/* eth0_rxclk_m1 */
746				<2 RK_PB5 3 &pcfg_pull_none>,
747				/* eth0_txclk_m1 */
748				<2 RK_PB3 3 &pcfg_pull_none>;
749		};
750
751		/omit-if-no-ref/
752		eth0m1_rgmii_bus: eth0m1-rgmii_bus {
753			rockchip,pins =
754				/* eth0_rxd2_m1 */
755				<2 RK_PB7 3 &pcfg_pull_none>,
756				/* eth0_rxd3_m1 */
757				<2 RK_PB6 3 &pcfg_pull_none>,
758				/* eth0_txd2_m1 */
759				<2 RK_PB4 3 &pcfg_pull_none>,
760				/* eth0_txd3_m1 */
761				<2 RK_PB2 3 &pcfg_pull_none>;
762		};
763
764		/omit-if-no-ref/
765		eth0m1_mclk: eth0m1-mclk {
766			rockchip,pins =
767				/* eth0m1_mclk */
768				<2 RK_PD6 3 &pcfg_pull_none>;
769		};
770		/omit-if-no-ref/
771		eth0m1_ppsclk: eth0m1-ppsclk {
772			rockchip,pins =
773				/* eth0m1_ppsclk */
774				<2 RK_PC1 3 &pcfg_pull_none>;
775		};
776		/omit-if-no-ref/
777		eth0m1_ppstrig: eth0m1-ppstrig {
778			rockchip,pins =
779				/* eth0m1_ppstrig */
780				<2 RK_PC2 3 &pcfg_pull_none>;
781		};
782	};
783
784	eth1 {
785		/omit-if-no-ref/
786		eth1m0_miim: eth1m0-miim {
787			rockchip,pins =
788				/* eth1_mdc_m0 */
789				<2 RK_PD4 2 &pcfg_pull_none>,
790				/* eth1_mdio_m0 */
791				<2 RK_PD5 2 &pcfg_pull_none>;
792		};
793
794		/omit-if-no-ref/
795		eth1m0_rx_bus2: eth1m0-rx_bus2 {
796			rockchip,pins =
797				/* eth1_rxctl_m0 */
798				<2 RK_PD3 2 &pcfg_pull_none>,
799				/* eth1_rxd0_m0 */
800				<2 RK_PD1 2 &pcfg_pull_none>,
801				/* eth1_rxd1_m0 */
802				<2 RK_PD2 2 &pcfg_pull_none>;
803		};
804
805		/omit-if-no-ref/
806		eth1m0_tx_bus2: eth1m0-tx_bus2 {
807			rockchip,pins =
808				/* eth1_txctl_m0 */
809				<2 RK_PD0 2 &pcfg_pull_none>,
810				/* eth1_txd0_m0 */
811				<2 RK_PC6 2 &pcfg_pull_none>,
812				/* eth1_txd1_m0 */
813				<2 RK_PC7 2 &pcfg_pull_none>;
814		};
815
816		/omit-if-no-ref/
817		eth1m0_rgmii_clk: eth1m0-rgmii_clk {
818			rockchip,pins =
819				/* eth1_rxclk_m0 */
820				<2 RK_PC2 2 &pcfg_pull_none>,
821				/* eth1_txclk_m0 */
822				<2 RK_PC5 2 &pcfg_pull_none>;
823		};
824
825		/omit-if-no-ref/
826		eth1m0_rgmii_bus: eth1m0-rgmii_bus {
827			rockchip,pins =
828				/* eth1_rxd2_m0 */
829				<2 RK_PC0 2 &pcfg_pull_none>,
830				/* eth1_rxd3_m0 */
831				<2 RK_PC1 2 &pcfg_pull_none>,
832				/* eth1_txd2_m0 */
833				<2 RK_PC3 2 &pcfg_pull_none>,
834				/* eth1_txd3_m0 */
835				<2 RK_PC4 2 &pcfg_pull_none>;
836		};
837
838		/omit-if-no-ref/
839		eth1m0_mclk: eth1m0-mclk {
840			rockchip,pins =
841				/* eth1m0_mclk */
842				<2 RK_PD7 2 &pcfg_pull_none>;
843		};
844		/omit-if-no-ref/
845		eth1m0_ppsclk: eth1m0-ppsclk {
846			rockchip,pins =
847				/* eth1m0_ppsclk */
848				<3 RK_PA2 2 &pcfg_pull_none>;
849		};
850		/omit-if-no-ref/
851		eth1m0_ppstrig: eth1m0-ppstrig {
852			rockchip,pins =
853				/* eth1m0_ppstrig */
854				<3 RK_PA1 2 &pcfg_pull_none>;
855		};
856
857		/omit-if-no-ref/
858		eth1m1_miim: eth1m1-miim {
859			rockchip,pins =
860				/* eth1_mdc_m1 */
861				<1 RK_PD2 1 &pcfg_pull_none>,
862				/* eth1_mdio_m1 */
863				<1 RK_PD3 1 &pcfg_pull_none>;
864		};
865
866		/omit-if-no-ref/
867		eth1m1_rx_bus2: eth1m1-rx_bus2 {
868			rockchip,pins =
869				/* eth1_rxctl_m1 */
870				<1 RK_PD1 1 &pcfg_pull_none>,
871				/* eth1_rxd0_m1 */
872				<1 RK_PC7 1 &pcfg_pull_none>,
873				/* eth1_rxd1_m1 */
874				<1 RK_PD0 1 &pcfg_pull_none>;
875		};
876
877		/omit-if-no-ref/
878		eth1m1_tx_bus2: eth1m1-tx_bus2 {
879			rockchip,pins =
880				/* eth1_txctl_m1 */
881				<1 RK_PC6 1 &pcfg_pull_none>,
882				/* eth1_txd0_m1 */
883				<1 RK_PC4 1 &pcfg_pull_none>,
884				/* eth1_txd1_m1 */
885				<1 RK_PC5 1 &pcfg_pull_none>;
886		};
887
888		/omit-if-no-ref/
889		eth1m1_rgmii_clk: eth1m1-rgmii_clk {
890			rockchip,pins =
891				/* eth1_rxclk_m1 */
892				<1 RK_PB6 1 &pcfg_pull_none>,
893				/* eth1_txclk_m1 */
894				<1 RK_PC1 1 &pcfg_pull_none>;
895		};
896
897		/omit-if-no-ref/
898		eth1m1_rgmii_bus: eth1m1-rgmii_bus {
899			rockchip,pins =
900				/* eth1_rxd2_m1 */
901				<1 RK_PB4 1 &pcfg_pull_none>,
902				/* eth1_rxd3_m1 */
903				<1 RK_PB5 1 &pcfg_pull_none>,
904				/* eth1_txd2_m1 */
905				<1 RK_PB7 1 &pcfg_pull_none>,
906				/* eth1_txd3_m1 */
907				<1 RK_PC0 1 &pcfg_pull_none>;
908		};
909
910		/omit-if-no-ref/
911		eth1m1_mclk: eth1m1-mclk {
912			rockchip,pins =
913				/* eth1m1_mclk */
914				<1 RK_PD4 1 &pcfg_pull_none>;
915		};
916		/omit-if-no-ref/
917		eth1m1_ppsclk: eth1m1-ppsclk {
918			rockchip,pins =
919				/* eth1m1_ppsclk */
920				<1 RK_PC2 1 &pcfg_pull_none>;
921		};
922		/omit-if-no-ref/
923		eth1m1_ppstrig: eth1m1-ppstrig {
924			rockchip,pins =
925				/* eth1m1_ppstrig */
926				<1 RK_PC3 1 &pcfg_pull_none>;
927		};
928	};
929
930	eth0_ptp {
931		/omit-if-no-ref/
932		eth0m0_ptp_refclk: eth0m0-ptp-refclk {
933			rockchip,pins =
934				/* eth0m0_ptp_refclk */
935				<3 RK_PC1 3 &pcfg_pull_none>;
936		};
937
938		/omit-if-no-ref/
939		eth0m1_ptp_refclk: eth0m1-ptp-refclk {
940			rockchip,pins =
941				/* eth0m1_ptp_refclk */
942				<2 RK_PC0 3 &pcfg_pull_none>;
943		};
944	};
945
946	eth0_testrxclk {
947		/omit-if-no-ref/
948		eth0_testrxclkm0_test: eth0_testrxclkm0-test {
949			rockchip,pins =
950				/* eth0_testrxclk_out_m0 */
951				<3 RK_PC7 3 &pcfg_pull_none>;
952		};
953
954		/omit-if-no-ref/
955		eth0_testrxclkm1_test: eth0_testrxclkm1-test {
956			rockchip,pins =
957				/* eth0_testrxclk_out_m1 */
958				<2 RK_PC5 6 &pcfg_pull_none>;
959		};
960	};
961
962	eth0_testrxd {
963		/omit-if-no-ref/
964		eth0_testrxdm0_test: eth0_testrxdm0-test {
965			rockchip,pins =
966				/* eth0_testrxd_out_m0 */
967				<3 RK_PD0 3 &pcfg_pull_none>;
968		};
969
970		/omit-if-no-ref/
971		eth0_testrxdm1_test: eth0_testrxdm1-test {
972			rockchip,pins =
973				/* eth0_testrxd_out_m1 */
974				<2 RK_PC4 6 &pcfg_pull_none>;
975		};
976	};
977
978	eth1_ptp {
979		/omit-if-no-ref/
980		eth1m0_ptp_refclk: eth1m0-ptp-refclk {
981			rockchip,pins =
982				/* eth1m0_ptp_refclk */
983				<3 RK_PA3 2 &pcfg_pull_none>;
984		};
985
986		/omit-if-no-ref/
987		eth1m1_ptp_refclk: eth1m1-ptp-refclk {
988			rockchip,pins =
989				/* eth1m1_ptp_refclk */
990				<2 RK_PB6 2 &pcfg_pull_none>;
991		};
992	};
993
994	eth1_testrxclk {
995		/omit-if-no-ref/
996		eth1_testrxclkm0_test: eth1_testrxclkm0-test {
997			rockchip,pins =
998				/* eth1_testrxclk_out_m0 */
999				<3 RK_PA1 6 &pcfg_pull_none>;
1000		};
1001
1002		/omit-if-no-ref/
1003		eth1_testrxclkm1_test: eth1_testrxclkm1-test {
1004			rockchip,pins =
1005				/* eth1_testrxclk_out_m1 */
1006				<1 RK_PC3 6 &pcfg_pull_none>;
1007		};
1008	};
1009
1010	eth1_testrxd {
1011		/omit-if-no-ref/
1012		eth1_testrxdm0_test: eth1_testrxdm0-test {
1013			rockchip,pins =
1014				/* eth1_testrxd_out_m0 */
1015				<3 RK_PA0 6 &pcfg_pull_none>;
1016		};
1017
1018		/omit-if-no-ref/
1019		eth1_testrxdm1_test: eth1_testrxdm1-test {
1020			rockchip,pins =
1021				/* eth1_testrxd_out_m1 */
1022				<1 RK_PC2 6 &pcfg_pull_none>;
1023		};
1024	};
1025
1026	eth_clk0_25m {
1027		/omit-if-no-ref/
1028		ethm0_clk0_25m_out: ethm0-clk0-25m-out {
1029			rockchip,pins =
1030				/* ethm0_clk0_25m_out */
1031				<3 RK_PA4 3 &pcfg_pull_none>;
1032		};
1033
1034		/omit-if-no-ref/
1035		ethm1_clk0_25m_out: ethm1-clk0-25m-out {
1036			rockchip,pins =
1037				/* ethm1_clk0_25m_out */
1038				<2 RK_PD7 3 &pcfg_pull_none>;
1039		};
1040	};
1041
1042	eth_clk1_25m {
1043		/omit-if-no-ref/
1044		ethm0_clk1_25m_out: ethm0-clk1-25m-out {
1045			rockchip,pins =
1046				/* ethm0_clk1_25m_out */
1047				<2 RK_PD6 2 &pcfg_pull_none>;
1048		};
1049
1050		/omit-if-no-ref/
1051		ethm1_clk1_25m_out: ethm1-clk1-25m-out {
1052			rockchip,pins =
1053				/* ethm1_clk1_25m_out */
1054				<1 RK_PD5 1 &pcfg_pull_none>;
1055		};
1056	};
1057
1058	flexbus0 {
1059		/omit-if-no-ref/
1060		flexbus0m0_csn: flexbus0m0-csn {
1061			rockchip,pins =
1062				/* flexbus0_csn_m0 */
1063				<3 RK_PA4 8 &pcfg_pull_none>;
1064		};
1065
1066		/omit-if-no-ref/
1067		flexbus0m0_d13: flexbus0m0-d13 {
1068			rockchip,pins =
1069				/* flexbus0_d13_m0 */
1070				<4 RK_PA0 6 &pcfg_pull_none>;
1071		};
1072
1073		/omit-if-no-ref/
1074		flexbus0m0_d14: flexbus0m0-d14 {
1075			rockchip,pins =
1076				/* flexbus0_d14_m0 */
1077				<4 RK_PA1 6 &pcfg_pull_none>;
1078		};
1079
1080		/omit-if-no-ref/
1081		flexbus0m0_d15: flexbus0m0-d15 {
1082			rockchip,pins =
1083				/* flexbus0_d15_m0 */
1084				<3 RK_PD7 6 &pcfg_pull_none>;
1085		};
1086
1087		/omit-if-no-ref/
1088		flexbus0m1_csn: flexbus0m1-csn {
1089			rockchip,pins =
1090				/* flexbus0_csn_m1 */
1091				<4 RK_PA1 8 &pcfg_pull_none>;
1092		};
1093
1094		/omit-if-no-ref/
1095		flexbus0m1_d13: flexbus0m1-d13 {
1096			rockchip,pins =
1097				/* flexbus0_d13_m1 */
1098				<4 RK_PA4 4 &pcfg_pull_none>;
1099		};
1100
1101		/omit-if-no-ref/
1102		flexbus0m1_d14: flexbus0m1-d14 {
1103			rockchip,pins =
1104				/* flexbus0_d14_m1 */
1105				<4 RK_PA6 4 &pcfg_pull_none>;
1106		};
1107
1108		/omit-if-no-ref/
1109		flexbus0m1_d15: flexbus0m1-d15 {
1110			rockchip,pins =
1111				/* flexbus0_d15_m1 */
1112				<4 RK_PB5 4 &pcfg_pull_none>;
1113		};
1114
1115		/omit-if-no-ref/
1116		flexbus0m2_csn: flexbus0m2-csn {
1117			rockchip,pins =
1118				/* flexbus0_csn_m2 */
1119				<3 RK_PC3 8 &pcfg_pull_none>;
1120		};
1121
1122		/omit-if-no-ref/
1123		flexbus0m3_csn: flexbus0m3-csn {
1124			rockchip,pins =
1125				/* flexbus0_csn_m3 */
1126				<3 RK_PD2 8 &pcfg_pull_none>;
1127		};
1128
1129		/omit-if-no-ref/
1130		flexbus0m4_csn: flexbus0m4-csn {
1131			rockchip,pins =
1132				/* flexbus0_csn_m4 */
1133				<4 RK_PB4 4 &pcfg_pull_none>;
1134		};
1135
1136		/omit-if-no-ref/
1137		flexbus0_clk: flexbus0-clk {
1138			rockchip,pins =
1139				/* flexbus0_clk */
1140				<3 RK_PB6 6 &pcfg_pull_none>;
1141		};
1142
1143		/omit-if-no-ref/
1144		flexbus0_d10: flexbus0-d10 {
1145			rockchip,pins =
1146				/* flexbus0_d10 */
1147				<3 RK_PC3 6 &pcfg_pull_none>;
1148		};
1149
1150		/omit-if-no-ref/
1151		flexbus0_d11: flexbus0-d11 {
1152			rockchip,pins =
1153				/* flexbus0_d11 */
1154				<3 RK_PD1 6 &pcfg_pull_none>;
1155		};
1156
1157		/omit-if-no-ref/
1158		flexbus0_d12: flexbus0-d12 {
1159			rockchip,pins =
1160				/* flexbus0_d12 */
1161				<3 RK_PD2 6 &pcfg_pull_none>;
1162		};
1163
1164		/omit-if-no-ref/
1165		flexbus0_d0: flexbus0-d0 {
1166			rockchip,pins =
1167				/* flexbus0_d0 */
1168				<3 RK_PB5 6 &pcfg_pull_none>;
1169		};
1170
1171		/omit-if-no-ref/
1172		flexbus0_d1: flexbus0-d1 {
1173			rockchip,pins =
1174				/* flexbus0_d1 */
1175				<3 RK_PB4 6 &pcfg_pull_none>;
1176		};
1177
1178		/omit-if-no-ref/
1179		flexbus0_d2: flexbus0-d2 {
1180			rockchip,pins =
1181				/* flexbus0_d2 */
1182				<3 RK_PB3 6 &pcfg_pull_none>;
1183		};
1184
1185		/omit-if-no-ref/
1186		flexbus0_d3: flexbus0-d3 {
1187			rockchip,pins =
1188				/* flexbus0_d3 */
1189				<3 RK_PB2 6 &pcfg_pull_none>;
1190		};
1191
1192		/omit-if-no-ref/
1193		flexbus0_d4: flexbus0-d4 {
1194			rockchip,pins =
1195				/* flexbus0_d4 */
1196				<3 RK_PB1 6 &pcfg_pull_none>;
1197		};
1198
1199		/omit-if-no-ref/
1200		flexbus0_d5: flexbus0-d5 {
1201			rockchip,pins =
1202				/* flexbus0_d5 */
1203				<3 RK_PA7 6 &pcfg_pull_none>;
1204		};
1205
1206		/omit-if-no-ref/
1207		flexbus0_d6: flexbus0-d6 {
1208			rockchip,pins =
1209				/* flexbus0_d6 */
1210				<3 RK_PA6 6 &pcfg_pull_none>;
1211		};
1212
1213		/omit-if-no-ref/
1214		flexbus0_d7: flexbus0-d7 {
1215			rockchip,pins =
1216				/* flexbus0_d7 */
1217				<3 RK_PA5 6 &pcfg_pull_none>;
1218		};
1219
1220		/omit-if-no-ref/
1221		flexbus0_d8: flexbus0-d8 {
1222			rockchip,pins =
1223				/* flexbus0_d8 */
1224				<3 RK_PB0 6 &pcfg_pull_none>;
1225		};
1226
1227		/omit-if-no-ref/
1228		flexbus0_d9: flexbus0-d9 {
1229			rockchip,pins =
1230				/* flexbus0_d9 */
1231				<3 RK_PC2 6 &pcfg_pull_none>;
1232		};
1233	};
1234
1235	flexbus1 {
1236		/omit-if-no-ref/
1237		flexbus1m0_csn: flexbus1m0-csn {
1238			rockchip,pins =
1239				/* flexbus1_csn_m0 */
1240				<3 RK_PB7 8 &pcfg_pull_none>;
1241		};
1242
1243		/omit-if-no-ref/
1244		flexbus1m0_d12: flexbus1m0-d12 {
1245			rockchip,pins =
1246				/* flexbus1_d12_m0 */
1247				<3 RK_PD7 7 &pcfg_pull_none>;
1248		};
1249
1250		/omit-if-no-ref/
1251		flexbus1m0_d13: flexbus1m0-d13 {
1252			rockchip,pins =
1253				/* flexbus1_d13_m0 */
1254				<4 RK_PA1 7 &pcfg_pull_none>;
1255		};
1256
1257		/omit-if-no-ref/
1258		flexbus1m0_d14: flexbus1m0-d14 {
1259			rockchip,pins =
1260				/* flexbus1_d14_m0 */
1261				<4 RK_PA0 7 &pcfg_pull_none>;
1262		};
1263
1264		/omit-if-no-ref/
1265		flexbus1m0_d15: flexbus1m0-d15 {
1266			rockchip,pins =
1267				/* flexbus1_d15_m0 */
1268				<3 RK_PD2 7 &pcfg_pull_none>;
1269		};
1270
1271		/omit-if-no-ref/
1272		flexbus1m1_csn: flexbus1m1-csn {
1273			rockchip,pins =
1274				/* flexbus1_csn_m1 */
1275				<3 RK_PD7 8 &pcfg_pull_none>;
1276		};
1277
1278		/omit-if-no-ref/
1279		flexbus1m1_d12: flexbus1m1-d12 {
1280			rockchip,pins =
1281				/* flexbus1_d12_m1 */
1282				<4 RK_PA5 4 &pcfg_pull_none>;
1283		};
1284
1285		/omit-if-no-ref/
1286		flexbus1m1_d13: flexbus1m1-d13 {
1287			rockchip,pins =
1288				/* flexbus1_d13_m1 */
1289				<4 RK_PB0 4 &pcfg_pull_none>;
1290		};
1291
1292		/omit-if-no-ref/
1293		flexbus1m1_d14: flexbus1m1-d14 {
1294			rockchip,pins =
1295				/* flexbus1_d14_m1 */
1296				<4 RK_PB1 4 &pcfg_pull_none>;
1297		};
1298
1299		/omit-if-no-ref/
1300		flexbus1m1_d15: flexbus1m1-d15 {
1301			rockchip,pins =
1302				/* flexbus1_d15_m1 */
1303				<4 RK_PB2 4 &pcfg_pull_none>;
1304		};
1305
1306		/omit-if-no-ref/
1307		flexbus1m2_csn: flexbus1m2-csn {
1308			rockchip,pins =
1309				/* flexbus1_csn_m2 */
1310				<3 RK_PD1 8 &pcfg_pull_none>;
1311		};
1312
1313		/omit-if-no-ref/
1314		flexbus1m3_csn: flexbus1m3-csn {
1315			rockchip,pins =
1316				/* flexbus1_csn_m3 */
1317				<4 RK_PA0 8 &pcfg_pull_none>;
1318		};
1319
1320		/omit-if-no-ref/
1321		flexbus1m4_csn: flexbus1m4-csn {
1322			rockchip,pins =
1323				/* flexbus1_csn_m4 */
1324				<4 RK_PA3 4 &pcfg_pull_none>;
1325		};
1326
1327		/omit-if-no-ref/
1328		flexbus1_clk: flexbus1-clk {
1329			rockchip,pins =
1330				/* flexbus1_clk */
1331				<3 RK_PD6 6 &pcfg_pull_none>;
1332		};
1333
1334		/omit-if-no-ref/
1335		flexbus1_d10: flexbus1-d10 {
1336			rockchip,pins =
1337				/* flexbus1_d10 */
1338				<3 RK_PB7 6 &pcfg_pull_none>;
1339		};
1340
1341		/omit-if-no-ref/
1342		flexbus1_d11: flexbus1-d11 {
1343			rockchip,pins =
1344				/* flexbus1_d11 */
1345				<3 RK_PA4 6 &pcfg_pull_none>;
1346		};
1347
1348		/omit-if-no-ref/
1349		flexbus1_d0: flexbus1-d0 {
1350			rockchip,pins =
1351				/* flexbus1_d0 */
1352				<3 RK_PD5 6 &pcfg_pull_none>;
1353		};
1354
1355		/omit-if-no-ref/
1356		flexbus1_d1: flexbus1-d1 {
1357			rockchip,pins =
1358				/* flexbus1_d1 */
1359				<3 RK_PD4 6 &pcfg_pull_none>;
1360		};
1361
1362		/omit-if-no-ref/
1363		flexbus1_d2: flexbus1-d2 {
1364			rockchip,pins =
1365				/* flexbus1_d2 */
1366				<3 RK_PD3 6 &pcfg_pull_none>;
1367		};
1368
1369		/omit-if-no-ref/
1370		flexbus1_d3: flexbus1-d3 {
1371			rockchip,pins =
1372				/* flexbus1_d3 */
1373				<3 RK_PD0 6 &pcfg_pull_none>;
1374		};
1375
1376		/omit-if-no-ref/
1377		flexbus1_d4: flexbus1-d4 {
1378			rockchip,pins =
1379				/* flexbus1_d4 */
1380				<3 RK_PC7 6 &pcfg_pull_none>;
1381		};
1382
1383		/omit-if-no-ref/
1384		flexbus1_d5: flexbus1-d5 {
1385			rockchip,pins =
1386				/* flexbus1_d5 */
1387				<3 RK_PC6 6 &pcfg_pull_none>;
1388		};
1389
1390		/omit-if-no-ref/
1391		flexbus1_d6: flexbus1-d6 {
1392			rockchip,pins =
1393				/* flexbus1_d6 */
1394				<3 RK_PC5 6 &pcfg_pull_none>;
1395		};
1396
1397		/omit-if-no-ref/
1398		flexbus1_d7: flexbus1-d7 {
1399			rockchip,pins =
1400				/* flexbus1_d7 */
1401				<3 RK_PC4 6 &pcfg_pull_none>;
1402		};
1403
1404		/omit-if-no-ref/
1405		flexbus1_d8: flexbus1-d8 {
1406			rockchip,pins =
1407				/* flexbus1_d8 */
1408				<3 RK_PC1 6 &pcfg_pull_none>;
1409		};
1410
1411		/omit-if-no-ref/
1412		flexbus1_d9: flexbus1-d9 {
1413			rockchip,pins =
1414				/* flexbus1_d9 */
1415				<3 RK_PC0 6 &pcfg_pull_none>;
1416		};
1417	};
1418
1419	flexbus0_testclk {
1420		/omit-if-no-ref/
1421		flexbus0_testclk_testclk: flexbus0_testclk-testclk {
1422			rockchip,pins =
1423				/* flexbus0_testclk_out */
1424				<2 RK_PA3 6 &pcfg_pull_none>;
1425		};
1426	};
1427
1428	flexbus0_testdata {
1429		/omit-if-no-ref/
1430		flexbus0_testdata_testdata: flexbus0_testdata-testdata {
1431			rockchip,pins =
1432				/* flexbus0_testdata_out */
1433				<2 RK_PA2 6 &pcfg_pull_none>;
1434		};
1435	};
1436
1437	flexbus1_testclk {
1438		/omit-if-no-ref/
1439		flexbus1_testclk_testclk: flexbus1_testclk-testclk {
1440			rockchip,pins =
1441				/* flexbus1_testclk_out */
1442				<2 RK_PA5 6 &pcfg_pull_none>;
1443		};
1444	};
1445
1446	flexbus1_testdata {
1447		/omit-if-no-ref/
1448		flexbus1_testdata_testdata: flexbus1_testdata-testdata {
1449			rockchip,pins =
1450				/* flexbus1_testdata_out */
1451				<2 RK_PA4 6 &pcfg_pull_none>;
1452		};
1453	};
1454
1455	fspi0 {
1456		/omit-if-no-ref/
1457		fspi0_pins: fspi0-pins {
1458			rockchip,pins =
1459				/* fspi0_clk */
1460				<1 RK_PB1 2 &pcfg_pull_none>,
1461				/* fspi0_d0 */
1462				<1 RK_PA0 2 &pcfg_pull_none>,
1463				/* fspi0_d1 */
1464				<1 RK_PA1 2 &pcfg_pull_none>,
1465				/* fspi0_d2 */
1466				<1 RK_PA2 2 &pcfg_pull_none>,
1467				/* fspi0_d3 */
1468				<1 RK_PA3 2 &pcfg_pull_none>,
1469				/* fspi0_d4 */
1470				<1 RK_PA4 2 &pcfg_pull_none>,
1471				/* fspi0_d5 */
1472				<1 RK_PA5 2 &pcfg_pull_none>,
1473				/* fspi0_d6 */
1474				<1 RK_PA6 2 &pcfg_pull_none>,
1475				/* fspi0_d7 */
1476				<1 RK_PA7 2 &pcfg_pull_none>,
1477				/* fspi0_dqs */
1478				<1 RK_PB2 2 &pcfg_pull_none>;
1479		};
1480
1481		/omit-if-no-ref/
1482		fspi0_csn0: fspi0-csn0 {
1483			rockchip,pins =
1484				/* fspi0_csn0 */
1485				<1 RK_PB3 2 &pcfg_pull_none>;
1486		};
1487		/omit-if-no-ref/
1488		fspi0_csn1: fspi0-csn1 {
1489			rockchip,pins =
1490				/* fspi0_csn1 */
1491				<1 RK_PB0 2 &pcfg_pull_none>;
1492		};
1493	};
1494
1495	fspi1 {
1496		/omit-if-no-ref/
1497		fspi1m0_pins: fspi1m0-pins {
1498			rockchip,pins =
1499				/* fspi1_clk_m0 */
1500				<2 RK_PA5 2 &pcfg_pull_none>,
1501				/* fspi1_d0_m0 */
1502				<2 RK_PA0 2 &pcfg_pull_none>,
1503				/* fspi1_d1_m0 */
1504				<2 RK_PA1 2 &pcfg_pull_none>,
1505				/* fspi1_d2_m0 */
1506				<2 RK_PA2 2 &pcfg_pull_none>,
1507				/* fspi1_d3_m0 */
1508				<2 RK_PA3 2 &pcfg_pull_none>;
1509		};
1510
1511		/omit-if-no-ref/
1512		fspi1m0_csn0: fspi1m0-csn0 {
1513			rockchip,pins =
1514				/* fspi1m0_csn0 */
1515				<2 RK_PA4 2 &pcfg_pull_none>;
1516		};
1517
1518		/omit-if-no-ref/
1519		fspi1m1_pins: fspi1m1-pins {
1520			rockchip,pins =
1521				/* fspi1_clk_m1 */
1522				<1 RK_PD5 3 &pcfg_pull_none>,
1523				/* fspi1_d0_m1 */
1524				<1 RK_PC4 3 &pcfg_pull_none>,
1525				/* fspi1_d1_m1 */
1526				<1 RK_PC5 3 &pcfg_pull_none>,
1527				/* fspi1_d2_m1 */
1528				<1 RK_PC6 3 &pcfg_pull_none>,
1529				/* fspi1_d3_m1 */
1530				<1 RK_PC7 3 &pcfg_pull_none>,
1531				/* fspi1_d4_m1 */
1532				<1 RK_PD0 3 &pcfg_pull_none>,
1533				/* fspi1_d5_m1 */
1534				<1 RK_PD1 3 &pcfg_pull_none>,
1535				/* fspi1_d6_m1 */
1536				<1 RK_PD2 3 &pcfg_pull_none>,
1537				/* fspi1_d7_m1 */
1538				<1 RK_PD3 3 &pcfg_pull_none>,
1539				/* fspi1_dqs_m1 */
1540				<1 RK_PD4 3 &pcfg_pull_none>;
1541		};
1542
1543		/omit-if-no-ref/
1544		fspi1m1_csn0: fspi1m1-csn0 {
1545			rockchip,pins =
1546				/* fspi1m1_csn0 */
1547				<1 RK_PC3 3 &pcfg_pull_none>;
1548		};
1549		/omit-if-no-ref/
1550		fspi1m1_csn1: fspi1m1-csn1 {
1551			rockchip,pins =
1552				/* fspi1m1_csn1 */
1553				<1 RK_PC2 3 &pcfg_pull_none>;
1554		};
1555	};
1556
1557	fspi0_testclk {
1558		/omit-if-no-ref/
1559		fspi0_testclk_test: fspi0_testclk-test {
1560			rockchip,pins =
1561				/* fspi0_testclk_out */
1562				<1 RK_PB0 6 &pcfg_pull_none>;
1563		};
1564	};
1565
1566	fspi0_testdata {
1567		/omit-if-no-ref/
1568		fspi0_testdata_test: fspi0_testdata-test {
1569			rockchip,pins =
1570				/* fspi0_testdata_out */
1571				<1 RK_PB7 6 &pcfg_pull_none>;
1572		};
1573	};
1574
1575	fspi1_testclk {
1576		/omit-if-no-ref/
1577		fspi1_testclkm1_test: fspi1_testclkm1-test {
1578			rockchip,pins =
1579				/* fspi1_testclk_out_m1 */
1580				<1 RK_PC1 7 &pcfg_pull_none>;
1581		};
1582	};
1583
1584	fspi1_testdata {
1585		/omit-if-no-ref/
1586		fspi1_testdatam1_test: fspi1_testdatam1-test {
1587			rockchip,pins =
1588				/* fspi1_testdata_out_m1 */
1589				<1 RK_PB7 7 &pcfg_pull_none>;
1590		};
1591	};
1592
1593	gpu {
1594		/omit-if-no-ref/
1595		gpu_pins: gpu-pins {
1596			rockchip,pins =
1597				/* gpu_avs */
1598				<0 RK_PD3 11 &pcfg_pull_none>;
1599		};
1600	};
1601
1602	hdmi_tx {
1603		/omit-if-no-ref/
1604		hdmi_txm0_pins: hdmi_txm0-pins {
1605			rockchip,pins =
1606				/* hdmi_tx_cec_m0 */
1607				<4 RK_PC0 9 &pcfg_pull_none>,
1608				/* hdmi_tx_hpdin_m0 */
1609				<4 RK_PC1 9 &pcfg_pull_none>;
1610		};
1611
1612		/omit-if-no-ref/
1613		hdmi_txm1_pins: hdmi_txm1-pins {
1614			rockchip,pins =
1615				/* hdmi_tx_cec_m1 */
1616				<0 RK_PC3 9 &pcfg_pull_none>,
1617				/* hdmi_tx_hpdin_m1 */
1618				<0 RK_PB6 9 &pcfg_pull_none>;
1619		};
1620
1621		/omit-if-no-ref/
1622		hdmi_tx_scl: hdmi-tx-scl {
1623			rockchip,pins =
1624				/* hdmi_tx_scl */
1625				<4 RK_PC2 9 &pcfg_pull_none>;
1626		};
1627		/omit-if-no-ref/
1628		hdmi_tx_sda: hdmi-tx-sda {
1629			rockchip,pins =
1630				/* hdmi_tx_sda */
1631				<4 RK_PC3 9 &pcfg_pull_none>;
1632		};
1633	};
1634
1635	i2c0 {
1636		/omit-if-no-ref/
1637		i2c0m0_xfer: i2c0m0-xfer {
1638			rockchip,pins =
1639				/* i2c0_scl_m0 */
1640				<0 RK_PB0 11 &pcfg_pull_none_smt>,
1641				/* i2c0_sda_m0 */
1642				<0 RK_PB1 11 &pcfg_pull_none_smt>;
1643		};
1644
1645		/omit-if-no-ref/
1646		i2c0m1_xfer: i2c0m1-xfer {
1647			rockchip,pins =
1648				/* i2c0_scl_m1 */
1649				<0 RK_PC1 9 &pcfg_pull_none_smt>,
1650				/* i2c0_sda_m1 */
1651				<0 RK_PC2 9 &pcfg_pull_none_smt>;
1652		};
1653	};
1654
1655	i2c1 {
1656		/omit-if-no-ref/
1657		i2c1m0_xfer: i2c1m0-xfer {
1658			rockchip,pins =
1659				/* i2c1_scl_m0 */
1660				<0 RK_PB2 11 &pcfg_pull_none_smt>,
1661				/* i2c1_sda_m0 */
1662				<0 RK_PB3 11 &pcfg_pull_none_smt>;
1663		};
1664
1665		/omit-if-no-ref/
1666		i2c1m1_xfer: i2c1m1-xfer {
1667			rockchip,pins =
1668				/* i2c1_scl_m1 */
1669				<0 RK_PB4 9 &pcfg_pull_none_smt>,
1670				/* i2c1_sda_m1 */
1671				<0 RK_PB5 9 &pcfg_pull_none_smt>;
1672		};
1673	};
1674
1675	i2c2 {
1676		/omit-if-no-ref/
1677		i2c2m0_xfer: i2c2m0-xfer {
1678			rockchip,pins =
1679				/* i2c2_scl_m0 */
1680				<0 RK_PB7 9 &pcfg_pull_none_smt>,
1681				/* i2c2_sda_m0 */
1682				<0 RK_PC0 9 &pcfg_pull_none_smt>;
1683		};
1684
1685		/omit-if-no-ref/
1686		i2c2m1_xfer: i2c2m1-xfer {
1687			rockchip,pins =
1688				/* i2c2_scl_m1 */
1689				<1 RK_PA0 10 &pcfg_pull_none_smt>,
1690				/* i2c2_sda_m1 */
1691				<1 RK_PA1 10 &pcfg_pull_none_smt>;
1692		};
1693
1694		/omit-if-no-ref/
1695		i2c2m2_xfer: i2c2m2-xfer {
1696			rockchip,pins =
1697				/* i2c2_scl_m2 */
1698				<4 RK_PA3 11 &pcfg_pull_none_smt>,
1699				/* i2c2_sda_m2 */
1700				<4 RK_PA5 11 &pcfg_pull_none_smt>;
1701		};
1702
1703		/omit-if-no-ref/
1704		i2c2m3_xfer: i2c2m3-xfer {
1705			rockchip,pins =
1706				/* i2c2_scl_m3 */
1707				<4 RK_PC2 11 &pcfg_pull_none_smt>,
1708				/* i2c2_sda_m3 */
1709				<4 RK_PC3 11 &pcfg_pull_none_smt>;
1710		};
1711	};
1712
1713	i2c3 {
1714		/omit-if-no-ref/
1715		i2c3m0_xfer: i2c3m0-xfer {
1716			rockchip,pins =
1717				/* i2c3_scl_m0 */
1718				<4 RK_PB5 11 &pcfg_pull_none_smt>,
1719				/* i2c3_sda_m0 */
1720				<4 RK_PB4 11 &pcfg_pull_none_smt>;
1721		};
1722
1723		/omit-if-no-ref/
1724		i2c3m1_xfer: i2c3m1-xfer {
1725			rockchip,pins =
1726				/* i2c3_scl_m1 */
1727				<0 RK_PC6 9 &pcfg_pull_none_smt>,
1728				/* i2c3_sda_m1 */
1729				<0 RK_PC7 9 &pcfg_pull_none_smt>;
1730		};
1731
1732		/omit-if-no-ref/
1733		i2c3m2_xfer: i2c3m2-xfer {
1734			rockchip,pins =
1735				/* i2c3_scl_m2 */
1736				<3 RK_PD4 11 &pcfg_pull_none_smt>,
1737				/* i2c3_sda_m2 */
1738				<3 RK_PD5 11 &pcfg_pull_none_smt>;
1739		};
1740
1741		/omit-if-no-ref/
1742		i2c3m3_xfer: i2c3m3-xfer {
1743			rockchip,pins =
1744				/* i2c3_scl_m3 */
1745				<4 RK_PC4 11 &pcfg_pull_none_smt>,
1746				/* i2c3_sda_m3 */
1747				<4 RK_PC5 11 &pcfg_pull_none_smt>;
1748		};
1749	};
1750
1751	i2c4 {
1752		/omit-if-no-ref/
1753		i2c4m0_xfer: i2c4m0-xfer {
1754			rockchip,pins =
1755				/* i2c4_scl_m0 */
1756				<0 RK_PD2 9 &pcfg_pull_none_smt>,
1757				/* i2c4_sda_m0 */
1758				<0 RK_PD3 9 &pcfg_pull_none_smt>;
1759		};
1760
1761		/omit-if-no-ref/
1762		i2c4m1_xfer: i2c4m1-xfer {
1763			rockchip,pins =
1764				/* i2c4_scl_m1 */
1765				<4 RK_PA4 11 &pcfg_pull_none_smt>,
1766				/* i2c4_sda_m1 */
1767				<4 RK_PA6 11 &pcfg_pull_none_smt>;
1768		};
1769
1770		/omit-if-no-ref/
1771		i2c4m2_xfer: i2c4m2-xfer {
1772			rockchip,pins =
1773				/* i2c4_scl_m2 */
1774				<2 RK_PA6 11 &pcfg_pull_none_smt>,
1775				/* i2c4_sda_m2 */
1776				<2 RK_PA7 11 &pcfg_pull_none_smt>;
1777		};
1778
1779		/omit-if-no-ref/
1780		i2c4m3_xfer: i2c4m3-xfer {
1781			rockchip,pins =
1782				/* i2c4_scl_m3 */
1783				<3 RK_PC0 11 &pcfg_pull_none_smt>,
1784				/* i2c4_sda_m3 */
1785				<3 RK_PB7 11 &pcfg_pull_none_smt>;
1786		};
1787	};
1788
1789	i2c5 {
1790		/omit-if-no-ref/
1791		i2c5m0_xfer: i2c5m0-xfer {
1792			rockchip,pins =
1793				/* i2c5_scl_m0 */
1794				<2 RK_PA5 11 &pcfg_pull_none_smt>,
1795				/* i2c5_sda_m0 */
1796				<2 RK_PA4 11 &pcfg_pull_none_smt>;
1797		};
1798
1799		/omit-if-no-ref/
1800		i2c5m1_xfer: i2c5m1-xfer {
1801			rockchip,pins =
1802				/* i2c5_scl_m1 */
1803				<1 RK_PD4 10 &pcfg_pull_none_smt>,
1804				/* i2c5_sda_m1 */
1805				<1 RK_PD5 10 &pcfg_pull_none_smt>;
1806		};
1807
1808		/omit-if-no-ref/
1809		i2c5m2_xfer: i2c5m2-xfer {
1810			rockchip,pins =
1811				/* i2c5_scl_m2 */
1812				<2 RK_PC6 11 &pcfg_pull_none_smt>,
1813				/* i2c5_sda_m2 */
1814				<2 RK_PC7 11 &pcfg_pull_none_smt>;
1815		};
1816
1817		/omit-if-no-ref/
1818		i2c5m3_xfer: i2c5m3-xfer {
1819			rockchip,pins =
1820				/* i2c5_scl_m3 */
1821				<3 RK_PC4 11 &pcfg_pull_none_smt>,
1822				/* i2c5_sda_m3 */
1823				<3 RK_PC1 11 &pcfg_pull_none_smt>;
1824		};
1825	};
1826
1827	i2c6 {
1828		/omit-if-no-ref/
1829		i2c6m0_xfer: i2c6m0-xfer {
1830			rockchip,pins =
1831				/* i2c6_scl_m0 */
1832				<0 RK_PA2 11 &pcfg_pull_none_smt>,
1833				/* i2c6_sda_m0 */
1834				<0 RK_PA5 11 &pcfg_pull_none_smt>;
1835		};
1836
1837		/omit-if-no-ref/
1838		i2c6m1_xfer: i2c6m1-xfer {
1839			rockchip,pins =
1840				/* i2c6_scl_m1 */
1841				<1 RK_PC2 10 &pcfg_pull_none_smt>,
1842				/* i2c6_sda_m1 */
1843				<1 RK_PC3 10 &pcfg_pull_none_smt>;
1844		};
1845
1846		/omit-if-no-ref/
1847		i2c6m2_xfer: i2c6m2-xfer {
1848			rockchip,pins =
1849				/* i2c6_scl_m2 */
1850				<2 RK_PD0 11 &pcfg_pull_none_smt>,
1851				/* i2c6_sda_m2 */
1852				<2 RK_PD1 11 &pcfg_pull_none_smt>;
1853		};
1854
1855		/omit-if-no-ref/
1856		i2c6m3_xfer: i2c6m3-xfer {
1857			rockchip,pins =
1858				/* i2c6_scl_m3 */
1859				<4 RK_PC6 11 &pcfg_pull_none_smt>,
1860				/* i2c6_sda_m3 */
1861				<4 RK_PC7 11 &pcfg_pull_none_smt>;
1862		};
1863	};
1864
1865	i2c7 {
1866		/omit-if-no-ref/
1867		i2c7m0_xfer: i2c7m0-xfer {
1868			rockchip,pins =
1869				/* i2c7_scl_m0 */
1870				<1 RK_PB0 10 &pcfg_pull_none_smt>,
1871				/* i2c7_sda_m0 */
1872				<1 RK_PB3 10 &pcfg_pull_none_smt>;
1873		};
1874
1875		/omit-if-no-ref/
1876		i2c7m1_xfer: i2c7m1-xfer {
1877			rockchip,pins =
1878				/* i2c7_scl_m1 */
1879				<3 RK_PA0 11 &pcfg_pull_none_smt>,
1880				/* i2c7_sda_m1 */
1881				<3 RK_PA1 11 &pcfg_pull_none_smt>;
1882		};
1883
1884		/omit-if-no-ref/
1885		i2c7m2_xfer: i2c7m2-xfer {
1886			rockchip,pins =
1887				/* i2c7_scl_m2 */
1888				<4 RK_PA0 11 &pcfg_pull_none_smt>,
1889				/* i2c7_sda_m2 */
1890				<4 RK_PA1 11 &pcfg_pull_none_smt>;
1891		};
1892
1893		/omit-if-no-ref/
1894		i2c7m3_xfer: i2c7m3-xfer {
1895			rockchip,pins =
1896				/* i2c7_scl_m3 */
1897				<4 RK_PC0 11 &pcfg_pull_none_smt>,
1898				/* i2c7_sda_m3 */
1899				<4 RK_PC1 11 &pcfg_pull_none_smt>;
1900		};
1901	};
1902
1903	i2c8 {
1904		/omit-if-no-ref/
1905		i2c8m0_xfer: i2c8m0-xfer {
1906			rockchip,pins =
1907				/* i2c8_scl_m0 */
1908				<2 RK_PA0 11 &pcfg_pull_none_smt>,
1909				/* i2c8_sda_m0 */
1910				<2 RK_PA1 11 &pcfg_pull_none_smt>;
1911		};
1912
1913		/omit-if-no-ref/
1914		i2c8m1_xfer: i2c8m1-xfer {
1915			rockchip,pins =
1916				/* i2c8_scl_m1 */
1917				<1 RK_PC6 10 &pcfg_pull_none_smt>,
1918				/* i2c8_sda_m1 */
1919				<1 RK_PC7 10 &pcfg_pull_none_smt>;
1920		};
1921
1922		/omit-if-no-ref/
1923		i2c8m2_xfer: i2c8m2-xfer {
1924			rockchip,pins =
1925				/* i2c8_scl_m2 */
1926				<2 RK_PB6 11 &pcfg_pull_none_smt>,
1927				/* i2c8_sda_m2 */
1928				<2 RK_PB7 11 &pcfg_pull_none_smt>;
1929		};
1930
1931		/omit-if-no-ref/
1932		i2c8m3_xfer: i2c8m3-xfer {
1933			rockchip,pins =
1934				/* i2c8_scl_m3 */
1935				<3 RK_PB3 11 &pcfg_pull_none_smt>,
1936				/* i2c8_sda_m3 */
1937				<3 RK_PB2 11 &pcfg_pull_none_smt>;
1938		};
1939	};
1940
1941	i2c9 {
1942		/omit-if-no-ref/
1943		i2c9m0_xfer: i2c9m0-xfer {
1944			rockchip,pins =
1945				/* i2c9_scl_m0 */
1946				<1 RK_PA5 10 &pcfg_pull_none_smt>,
1947				/* i2c9_sda_m0 */
1948				<1 RK_PA6 10 &pcfg_pull_none_smt>;
1949		};
1950
1951		/omit-if-no-ref/
1952		i2c9m1_xfer: i2c9m1-xfer {
1953			rockchip,pins =
1954				/* i2c9_scl_m1 */
1955				<1 RK_PB5 10 &pcfg_pull_none_smt>,
1956				/* i2c9_sda_m1 */
1957				<1 RK_PB4 10 &pcfg_pull_none_smt>;
1958		};
1959
1960		/omit-if-no-ref/
1961		i2c9m2_xfer: i2c9m2-xfer {
1962			rockchip,pins =
1963				/* i2c9_scl_m2 */
1964				<2 RK_PD5 11 &pcfg_pull_none_smt>,
1965				/* i2c9_sda_m2 */
1966				<2 RK_PD4 11 &pcfg_pull_none_smt>;
1967		};
1968
1969		/omit-if-no-ref/
1970		i2c9m3_xfer: i2c9m3-xfer {
1971			rockchip,pins =
1972				/* i2c9_scl_m3 */
1973				<3 RK_PC2 11 &pcfg_pull_none_smt>,
1974				/* i2c9_sda_m3 */
1975				<3 RK_PC3 11 &pcfg_pull_none_smt>;
1976		};
1977	};
1978
1979	i3c0 {
1980		/omit-if-no-ref/
1981		i3c0m0_xfer: i3c0m0-xfer {
1982			rockchip,pins =
1983				/* i3c0_scl_m0 */
1984				<0 RK_PC1 11 &pcfg_pull_none_smt>,
1985				/* i3c0_sda_m0 */
1986				<0 RK_PC2 11 &pcfg_pull_none_smt>;
1987		};
1988
1989		/omit-if-no-ref/
1990		i3c0m1_xfer: i3c0m1-xfer {
1991			rockchip,pins =
1992				/* i3c0_scl_m1 */
1993				<1 RK_PD2 10 &pcfg_pull_none_smt>,
1994				/* i3c0_sda_m1 */
1995				<1 RK_PD3 10 &pcfg_pull_none_smt>;
1996		};
1997	};
1998
1999	i3c1 {
2000		/omit-if-no-ref/
2001		i3c1m0_xfer: i3c1m0-xfer {
2002			rockchip,pins =
2003				/* i3c1_scl_m0 */
2004				<2 RK_PD2 12 &pcfg_pull_none_smt>,
2005				/* i3c1_sda_m0 */
2006				<2 RK_PD3 12 &pcfg_pull_none_smt>;
2007		};
2008
2009		/omit-if-no-ref/
2010		i3c1m1_xfer: i3c1m1-xfer {
2011			rockchip,pins =
2012				/* i3c1_scl_m1 */
2013				<2 RK_PA2 14 &pcfg_pull_none_smt>,
2014				/* i3c1_sda_m1 */
2015				<2 RK_PA3 14 &pcfg_pull_none_smt>;
2016		};
2017
2018		/omit-if-no-ref/
2019		i3c1m2_xfer: i3c1m2-xfer {
2020			rockchip,pins =
2021				/* i3c1_scl_m2 */
2022				<3 RK_PD3 11 &pcfg_pull_none_smt>,
2023				/* i3c1_sda_m2 */
2024				<3 RK_PD2 11 &pcfg_pull_none_smt>;
2025		};
2026	};
2027
2028	i3c0_sda {
2029		/omit-if-no-ref/
2030		i3c0_sdam0_pu: i3c0_sdam0-pu {
2031			rockchip,pins =
2032				/* i3c0_sda_pu_m0 */
2033				<0 RK_PC5 11 &pcfg_pull_none>;
2034		};
2035
2036		/omit-if-no-ref/
2037		i3c0_sdam1_pu: i3c0_sdam1-pu {
2038			rockchip,pins =
2039				/* i3c0_sda_pu_m1 */
2040				<1 RK_PD1 10 &pcfg_pull_none>;
2041		};
2042	};
2043
2044	i3c1_sda {
2045		/omit-if-no-ref/
2046		i3c1_sdam0_pu: i3c1_sdam0-pu {
2047			rockchip,pins =
2048				/* i3c1_sda_pu_m0 */
2049				<2 RK_PD6 12 &pcfg_pull_none>;
2050		};
2051
2052		/omit-if-no-ref/
2053		i3c1_sdam1_pu: i3c1_sdam1-pu {
2054			rockchip,pins =
2055				/* i3c1_sda_pu_m1 */
2056				<2 RK_PA5 14 &pcfg_pull_none>;
2057		};
2058
2059		/omit-if-no-ref/
2060		i3c1_sdam2_pu: i3c1_sdam2-pu {
2061			rockchip,pins =
2062				/* i3c1_sda_pu_m2 */
2063				<3 RK_PD1 11 &pcfg_pull_none>;
2064		};
2065	};
2066
2067	isp_flash {
2068		/omit-if-no-ref/
2069		isp_flashm0_pins: isp_flashm0-pins {
2070			rockchip,pins =
2071				/* isp_flash_trigout_m0 */
2072				<2 RK_PD5 1 &pcfg_pull_none>;
2073		};
2074
2075		/omit-if-no-ref/
2076		isp_flashm1_pins: isp_flashm1-pins {
2077			rockchip,pins =
2078				/* isp_flash_trigout_m1 */
2079				<4 RK_PC5 1 &pcfg_pull_none>;
2080		};
2081	};
2082
2083	isp_prelight {
2084		/omit-if-no-ref/
2085		isp_prelightm0_pins: isp_prelightm0-pins {
2086			rockchip,pins =
2087				/* isp_prelight_trig_m0 */
2088				<2 RK_PD4 1 &pcfg_pull_none>;
2089		};
2090
2091		/omit-if-no-ref/
2092		isp_prelightm1_pins: isp_prelightm1-pins {
2093			rockchip,pins =
2094				/* isp_prelight_trig_m1 */
2095				<4 RK_PC4 1 &pcfg_pull_none>;
2096		};
2097	};
2098
2099	jtag {
2100		/omit-if-no-ref/
2101		jtagm0_pins: jtagm0-pins {
2102			rockchip,pins =
2103				/* jtag_tck_m0 */
2104				<2 RK_PA2 9 &pcfg_pull_none>,
2105				/* jtag_tms_m0 */
2106				<2 RK_PA3 9 &pcfg_pull_none>;
2107		};
2108
2109		/omit-if-no-ref/
2110		jtagm1_pins: jtagm1-pins {
2111			rockchip,pins =
2112				/* jtag_tck_m1 */
2113				<0 RK_PD4 10 &pcfg_pull_none>,
2114				/* jtag_tms_m1 */
2115				<0 RK_PD5 10 &pcfg_pull_none>;
2116		};
2117	};
2118
2119	mipi {
2120		/omit-if-no-ref/
2121		mipim0_pins: mipim0-pins {
2122			rockchip,pins =
2123				/* mipi_te_m0 */
2124				<4 RK_PB2 11 &pcfg_pull_none>;
2125		};
2126
2127		/omit-if-no-ref/
2128		mipim1_pins: mipim1-pins {
2129			rockchip,pins =
2130				/* mipi_te_m1 */
2131				<3 RK_PA2 12 &pcfg_pull_none>;
2132		};
2133
2134		/omit-if-no-ref/
2135		mipim2_pins: mipim2-pins {
2136			rockchip,pins =
2137				/* mipi_te_m2 */
2138				<4 RK_PA0 12 &pcfg_pull_none>;
2139		};
2140
2141		/omit-if-no-ref/
2142		mipim3_pins: mipim3-pins {
2143			rockchip,pins =
2144				/* mipi_te_m3 */
2145				<1 RK_PB3 11 &pcfg_pull_none>;
2146		};
2147	};
2148
2149	npu {
2150		/omit-if-no-ref/
2151		npu_pins: npu-pins {
2152			rockchip,pins =
2153				/* npu_avs */
2154				<0 RK_PB7 11 &pcfg_pull_none>;
2155		};
2156	};
2157
2158	pcie0 {
2159		/omit-if-no-ref/
2160		pcie0m0_pins: pcie0m0-pins {
2161			rockchip,pins =
2162				/* pcie21_port0_clkreq_m0 */
2163				<2 RK_PB2 11 &pcfg_pull_up>;
2164		};
2165
2166		/omit-if-no-ref/
2167		pcie0m1_pins: pcie0m1-pins {
2168			rockchip,pins =
2169				/* pcie0_clkreq_m1 */
2170				<1 RK_PB6 12 &pcfg_pull_up>;
2171		};
2172
2173		/omit-if-no-ref/
2174		pcie0m2_pins: pcie0m2-pins {
2175			rockchip,pins =
2176				/* pcie0_clkreq_m2 */
2177				<4 RK_PB5 12 &pcfg_pull_up>;
2178		};
2179
2180		/omit-if-no-ref/
2181		pcie0m3_pins: pcie0m3-pins {
2182			rockchip,pins =
2183				/* pcie0_clkreq_m3 */
2184				<4 RK_PC6 9 &pcfg_pull_up>;
2185		};
2186
2187		/omit-if-no-ref/
2188		pcie0_buttonrst: pcie21-port0-buttonrst {
2189			rockchip,pins =
2190				/* pcie0_buttonrst */
2191				<1 RK_PC4 12 &pcfg_pull_none>;
2192		};
2193	};
2194
2195	pcie1 {
2196		/omit-if-no-ref/
2197		pcie1m0_pins: pcie1m0-pins {
2198			rockchip,pins =
2199				/* pcie1_clkreq_m0 */
2200				<2 RK_PB3 11 &pcfg_pull_up>;
2201		};
2202
2203		/omit-if-no-ref/
2204		pcie1m1_pins: pcie1m1-pins {
2205			rockchip,pins =
2206				/* pcie1_clkreq_m1 */
2207				<1 RK_PB4 12 &pcfg_pull_up>;
2208		};
2209
2210		/omit-if-no-ref/
2211		pcie1m2_pins: pcie1m2-pins {
2212			rockchip,pins =
2213				/* pcie1_clkreq_m2 */
2214				<4 RK_PA5 12 &pcfg_pull_up>;
2215		};
2216
2217		/omit-if-no-ref/
2218		pcie1m3_pins: pcie1m3-pins {
2219			rockchip,pins =
2220				/* pcie1_clkreq_m3 */
2221				<4 RK_PC1 10 &pcfg_pull_up>;
2222		};
2223
2224		/omit-if-no-ref/
2225		pcie1_buttonrst: pcie21-port1-buttonrst {
2226			rockchip,pins =
2227				/* pcie1_buttonrst */
2228				<1 RK_PC5 12 &pcfg_pull_none>;
2229		};
2230	};
2231
2232	pdm0 {
2233		/omit-if-no-ref/
2234		pdm0m0_clk0: pdm0m0-clk0 {
2235			rockchip,pins =
2236				/* pdm0_clk0_m0 */
2237				<0 RK_PC4 3 &pcfg_pull_none>;
2238		};
2239
2240		/omit-if-no-ref/
2241		pdm0m0_clk1: pdm0m0-clk1 {
2242			rockchip,pins =
2243				/* pdm0_clk1_m0 */
2244				<0 RK_PC3 3 &pcfg_pull_none>;
2245		};
2246
2247		/omit-if-no-ref/
2248		pdm0m0_sdi0: pdm0m0-sdi0 {
2249			rockchip,pins =
2250				/* pdm0_sdi0_m0 */
2251				<0 RK_PD0 3 &pcfg_pull_none>;
2252		};
2253
2254		/omit-if-no-ref/
2255		pdm0m0_sdi1: pdm0m0-sdi1 {
2256			rockchip,pins =
2257				/* pdm0_sdi1_m0 */
2258				<0 RK_PD1 3 &pcfg_pull_none>;
2259		};
2260
2261		/omit-if-no-ref/
2262		pdm0m0_sdi2: pdm0m0-sdi2 {
2263			rockchip,pins =
2264				/* pdm0_sdi2_m0 */
2265				<0 RK_PD2 3 &pcfg_pull_none>;
2266		};
2267
2268		/omit-if-no-ref/
2269		pdm0m0_sdi3: pdm0m0-sdi3 {
2270			rockchip,pins =
2271				/* pdm0_sdi3_m0 */
2272				<0 RK_PD3 3 &pcfg_pull_none>;
2273		};
2274
2275		/omit-if-no-ref/
2276		pdm0m1_clk0: pdm0m1-clk0 {
2277			rockchip,pins =
2278				/* pdm0_clk0_m1 */
2279				<1 RK_PB1 5 &pcfg_pull_none>;
2280		};
2281
2282		/omit-if-no-ref/
2283		pdm0m1_clk1: pdm0m1-clk1 {
2284			rockchip,pins =
2285				/* pdm0_clk1_m1 */
2286				<1 RK_PA6 5 &pcfg_pull_none>;
2287		};
2288
2289		/omit-if-no-ref/
2290		pdm0m1_sdi0: pdm0m1-sdi0 {
2291			rockchip,pins =
2292				/* pdm0_sdi0_m1 */
2293				<1 RK_PB2 5 &pcfg_pull_none>;
2294		};
2295
2296		/omit-if-no-ref/
2297		pdm0m1_sdi1: pdm0m1-sdi1 {
2298			rockchip,pins =
2299				/* pdm0_sdi1_m1 */
2300				<1 RK_PA3 5 &pcfg_pull_none>;
2301		};
2302
2303		/omit-if-no-ref/
2304		pdm0m1_sdi2: pdm0m1-sdi2 {
2305			rockchip,pins =
2306				/* pdm0_sdi2_m1 */
2307				<1 RK_PA5 5 &pcfg_pull_none>;
2308		};
2309
2310		/omit-if-no-ref/
2311		pdm0m1_sdi3: pdm0m1-sdi3 {
2312			rockchip,pins =
2313				/* pdm0_sdi3_m1 */
2314				<1 RK_PA2 5 &pcfg_pull_none>;
2315		};
2316
2317		/omit-if-no-ref/
2318		pdm0m2_clk0: pdm0m2-clk0 {
2319			rockchip,pins =
2320				/* pdm0_clk0_m2 */
2321				<1 RK_PC1 5 &pcfg_pull_none>;
2322		};
2323
2324		/omit-if-no-ref/
2325		pdm0m2_clk1: pdm0m2-clk1 {
2326			rockchip,pins =
2327				/* pdm0_clk1_m2 */
2328				<1 RK_PD5 5 &pcfg_pull_none>;
2329		};
2330
2331		/omit-if-no-ref/
2332		pdm0m2_sdi0: pdm0m2-sdi0 {
2333			rockchip,pins =
2334				/* pdm0_sdi0_m2 */
2335				<1 RK_PC6 5 &pcfg_pull_none>;
2336		};
2337
2338		/omit-if-no-ref/
2339		pdm0m2_sdi1: pdm0m2-sdi1 {
2340			rockchip,pins =
2341				/* pdm0_sdi1_m2 */
2342				<1 RK_PC7 5 &pcfg_pull_none>;
2343		};
2344
2345		/omit-if-no-ref/
2346		pdm0m2_sdi2: pdm0m2-sdi2 {
2347			rockchip,pins =
2348				/* pdm0_sdi2_m2 */
2349				<1 RK_PC0 5 &pcfg_pull_none>;
2350		};
2351
2352		/omit-if-no-ref/
2353		pdm0m2_sdi3: pdm0m2-sdi3 {
2354			rockchip,pins =
2355				/* pdm0_sdi3_m2 */
2356				<1 RK_PD4 5 &pcfg_pull_none>;
2357		};
2358
2359		/omit-if-no-ref/
2360		pdm0m3_clk0: pdm0m3-clk0 {
2361			rockchip,pins =
2362				/* pdm0_clk0_m3 */
2363				<2 RK_PB5 5 &pcfg_pull_none>;
2364		};
2365
2366		/omit-if-no-ref/
2367		pdm0m3_clk1: pdm0m3-clk1 {
2368			rockchip,pins =
2369				/* pdm0_clk1_m3 */
2370				<2 RK_PB3 5 &pcfg_pull_none>;
2371		};
2372
2373		/omit-if-no-ref/
2374		pdm0m3_sdi0: pdm0m3-sdi0 {
2375			rockchip,pins =
2376				/* pdm0_sdi0_m3 */
2377				<2 RK_PB4 5 &pcfg_pull_none>;
2378		};
2379
2380		/omit-if-no-ref/
2381		pdm0m3_sdi1: pdm0m3-sdi1 {
2382			rockchip,pins =
2383				/* pdm0_sdi1_m3 */
2384				<2 RK_PB2 5 &pcfg_pull_none>;
2385		};
2386
2387		/omit-if-no-ref/
2388		pdm0m3_sdi2: pdm0m3-sdi2 {
2389			rockchip,pins =
2390				/* pdm0_sdi2_m3 */
2391				<2 RK_PB1 5 &pcfg_pull_none>;
2392		};
2393
2394		/omit-if-no-ref/
2395		pdm0m3_sdi3: pdm0m3-sdi3 {
2396			rockchip,pins =
2397				/* pdm0_sdi3_m3 */
2398				<2 RK_PB0 5 &pcfg_pull_none>;
2399		};
2400	};
2401
2402	pdm1 {
2403		/omit-if-no-ref/
2404		pdm1m0_clk0: pdm1m0-clk0 {
2405			rockchip,pins =
2406				/* pdm1_clk0_m0 */
2407				<2 RK_PC5 5 &pcfg_pull_none>;
2408		};
2409
2410		/omit-if-no-ref/
2411		pdm1m0_clk1: pdm1m0-clk1 {
2412			rockchip,pins =
2413				/* pdm1_clk1_m0 */
2414				<2 RK_PC1 5 &pcfg_pull_none>;
2415		};
2416
2417		/omit-if-no-ref/
2418		pdm1m0_sdi0: pdm1m0-sdi0 {
2419			rockchip,pins =
2420				/* pdm1_sdi0_m0 */
2421				<2 RK_PC4 5 &pcfg_pull_none>;
2422		};
2423
2424		/omit-if-no-ref/
2425		pdm1m0_sdi1: pdm1m0-sdi1 {
2426			rockchip,pins =
2427				/* pdm1_sdi1_m0 */
2428				<2 RK_PC0 5 &pcfg_pull_none>;
2429		};
2430
2431		/omit-if-no-ref/
2432		pdm1m0_sdi2: pdm1m0-sdi2 {
2433			rockchip,pins =
2434				/* pdm1_sdi2_m0 */
2435				<2 RK_PC2 5 &pcfg_pull_none>;
2436		};
2437
2438		/omit-if-no-ref/
2439		pdm1m0_sdi3: pdm1m0-sdi3 {
2440			rockchip,pins =
2441				/* pdm1_sdi3_m0 */
2442				<2 RK_PC3 5 &pcfg_pull_none>;
2443		};
2444
2445		/omit-if-no-ref/
2446		pdm1m1_clk0: pdm1m1-clk0 {
2447			rockchip,pins =
2448				/* pdm1_clk0_m1 */
2449				<4 RK_PA6 3 &pcfg_pull_none>;
2450		};
2451
2452		/omit-if-no-ref/
2453		pdm1m1_clk1: pdm1m1-clk1 {
2454			rockchip,pins =
2455				/* pdm1_clk1_m1 */
2456				<4 RK_PB0 3 &pcfg_pull_none>;
2457		};
2458
2459		/omit-if-no-ref/
2460		pdm1m1_sdi0: pdm1m1-sdi0 {
2461			rockchip,pins =
2462				/* pdm1_sdi0_m1 */
2463				<4 RK_PB3 3 &pcfg_pull_none>;
2464		};
2465
2466		/omit-if-no-ref/
2467		pdm1m1_sdi1: pdm1m1-sdi1 {
2468			rockchip,pins =
2469				/* pdm1_sdi1_m1 */
2470				<4 RK_PB2 3 &pcfg_pull_none>;
2471		};
2472
2473		/omit-if-no-ref/
2474		pdm1m1_sdi2: pdm1m1-sdi2 {
2475			rockchip,pins =
2476				/* pdm1_sdi2_m1 */
2477				<4 RK_PB1 3 &pcfg_pull_none>;
2478		};
2479
2480		/omit-if-no-ref/
2481		pdm1m1_sdi3: pdm1m1-sdi3 {
2482			rockchip,pins =
2483				/* pdm1_sdi3_m1 */
2484				<4 RK_PA4 3 &pcfg_pull_none>;
2485		};
2486
2487		/omit-if-no-ref/
2488		pdm1m2_clk0: pdm1m2-clk0 {
2489			rockchip,pins =
2490				/* pdm1_clk0_m2 */
2491				<3 RK_PB1 4 &pcfg_pull_none>;
2492		};
2493
2494		/omit-if-no-ref/
2495		pdm1m2_clk1: pdm1m2-clk1 {
2496			rockchip,pins =
2497				/* pdm1_clk1_m2 */
2498				<3 RK_PA7 4 &pcfg_pull_none>;
2499		};
2500
2501		/omit-if-no-ref/
2502		pdm1m2_sdi0: pdm1m2-sdi0 {
2503			rockchip,pins =
2504				/* pdm1_sdi0_m2 */
2505				<3 RK_PB3 4 &pcfg_pull_none>;
2506		};
2507
2508		/omit-if-no-ref/
2509		pdm1m2_sdi1: pdm1m2-sdi1 {
2510			rockchip,pins =
2511				/* pdm1_sdi1_m2 */
2512				<3 RK_PB2 4 &pcfg_pull_none>;
2513		};
2514
2515		/omit-if-no-ref/
2516		pdm1m2_sdi2: pdm1m2-sdi2 {
2517			rockchip,pins =
2518				/* pdm1_sdi2_m2 */
2519				<3 RK_PA6 4 &pcfg_pull_none>;
2520		};
2521
2522		/omit-if-no-ref/
2523		pdm1m2_sdi3: pdm1m2-sdi3 {
2524			rockchip,pins =
2525				/* pdm1_sdi3_m2 */
2526				<3 RK_PA5 4 &pcfg_pull_none>;
2527		};
2528	};
2529
2530	pmu_debug_test {
2531		/omit-if-no-ref/
2532		pmu_debug_test_pins: pmu_debug_test-pins {
2533			rockchip,pins =
2534				/* pmu_debug_test_out */
2535				<0 RK_PB0 2 &pcfg_pull_none>;
2536		};
2537	};
2538
2539	pwm0 {
2540		/omit-if-no-ref/
2541		pwm0m0_ch0: pwm0m0-ch0 {
2542			rockchip,pins =
2543				/* pwm0_ch0_m0 */
2544				<0 RK_PC4 12 &pcfg_pull_none_drv_level_2>;
2545		};
2546
2547		/omit-if-no-ref/
2548		pwm0m0_ch1: pwm0m0-ch1 {
2549			rockchip,pins =
2550				/* pwm0_ch1_m0 */
2551				<0 RK_PC3 12 &pcfg_pull_none_drv_level_2>;
2552		};
2553
2554		/omit-if-no-ref/
2555		pwm0m1_ch0: pwm0m1-ch0 {
2556			rockchip,pins =
2557				/* pwm0_ch0_m1 */
2558				<1 RK_PC0 13 &pcfg_pull_none_drv_level_2>;
2559		};
2560
2561		/omit-if-no-ref/
2562		pwm0m1_ch1: pwm0m1-ch1 {
2563			rockchip,pins =
2564				/* pwm0_ch1_m1 */
2565				<4 RK_PC1 14 &pcfg_pull_none_drv_level_2>;
2566		};
2567
2568		/omit-if-no-ref/
2569		pwm0m2_ch0: pwm0m2-ch0 {
2570			rockchip,pins =
2571				/* pwm0_ch0_m2 */
2572				<2 RK_PC3 13 &pcfg_pull_none_drv_level_2>;
2573		};
2574
2575		/omit-if-no-ref/
2576		pwm0m2_ch1: pwm0m2-ch1 {
2577			rockchip,pins =
2578				/* pwm0_ch1_m2 */
2579				<2 RK_PC7 13 &pcfg_pull_none_drv_level_2>;
2580		};
2581
2582		/omit-if-no-ref/
2583		pwm0m3_ch0: pwm0m3-ch0 {
2584			rockchip,pins =
2585				/* pwm0_ch0_m3 */
2586				<3 RK_PB0 12 &pcfg_pull_none_drv_level_2>;
2587		};
2588
2589		/omit-if-no-ref/
2590		pwm0m3_ch1: pwm0m3-ch1 {
2591			rockchip,pins =
2592				/* pwm0_ch1_m3 */
2593				<3 RK_PB6 12 &pcfg_pull_none_drv_level_2>;
2594		};
2595	};
2596
2597	pwm1 {
2598		/omit-if-no-ref/
2599		pwm1m0_ch0: pwm1m0-ch0 {
2600			rockchip,pins =
2601				/* pwm1_ch0_m0 */
2602				<0 RK_PB4 12 &pcfg_pull_none>;
2603		};
2604
2605		/omit-if-no-ref/
2606		pwm1m0_ch1: pwm1m0-ch1 {
2607			rockchip,pins =
2608				/* pwm1_ch1_m0 */
2609				<0 RK_PB5 12 &pcfg_pull_none>;
2610		};
2611
2612		/omit-if-no-ref/
2613		pwm1m0_ch2: pwm1m0-ch2 {
2614			rockchip,pins =
2615				/* pwm1_ch2_m0 */
2616				<0 RK_PB6 12 &pcfg_pull_none>;
2617		};
2618
2619		/omit-if-no-ref/
2620		pwm1m0_ch3: pwm1m0-ch3 {
2621			rockchip,pins =
2622				/* pwm1_ch3_m0 */
2623				<0 RK_PC0 12 &pcfg_pull_none>;
2624		};
2625
2626		/omit-if-no-ref/
2627		pwm1m0_ch4: pwm1m0-ch4 {
2628			rockchip,pins =
2629				/* pwm1_ch4_m0 */
2630				<0 RK_PB7 12 &pcfg_pull_none>;
2631		};
2632
2633		/omit-if-no-ref/
2634		pwm1m0_ch5: pwm1m0-ch5 {
2635			rockchip,pins =
2636				/* pwm1_ch5_m0 */
2637				<0 RK_PD2 12 &pcfg_pull_none>;
2638		};
2639
2640		/omit-if-no-ref/
2641		pwm1m1_ch0: pwm1m1-ch0 {
2642			rockchip,pins =
2643				/* pwm1_ch0_m1 */
2644				<1 RK_PB4 13 &pcfg_pull_none>;
2645		};
2646
2647		/omit-if-no-ref/
2648		pwm1m1_ch1: pwm1m1-ch1 {
2649			rockchip,pins =
2650				/* pwm1_ch1_m1 */
2651				<1 RK_PB5 13 &pcfg_pull_none>;
2652		};
2653
2654		/omit-if-no-ref/
2655		pwm1m1_ch2: pwm1m1-ch2 {
2656			rockchip,pins =
2657				/* pwm1_ch2_m1 */
2658				<1 RK_PC2 13 &pcfg_pull_none>;
2659		};
2660
2661		/omit-if-no-ref/
2662		pwm1m1_ch3: pwm1m1-ch3 {
2663			rockchip,pins =
2664				/* pwm1_ch3_m1 */
2665				<1 RK_PD2 13 &pcfg_pull_none>;
2666		};
2667
2668		/omit-if-no-ref/
2669		pwm1m1_ch4: pwm1m1-ch4 {
2670			rockchip,pins =
2671				/* pwm1_ch4_m1 */
2672				<1 RK_PD3 13 &pcfg_pull_none>;
2673		};
2674
2675		/omit-if-no-ref/
2676		pwm1m1_ch5: pwm1m1-ch5 {
2677			rockchip,pins =
2678				/* pwm1_ch5_m1 */
2679				<4 RK_PC0 14 &pcfg_pull_none>;
2680		};
2681
2682		/omit-if-no-ref/
2683		pwm1m2_ch0: pwm1m2-ch0 {
2684			rockchip,pins =
2685				/* pwm1_ch0_m2 */
2686				<2 RK_PC0 13 &pcfg_pull_none>;
2687		};
2688
2689		/omit-if-no-ref/
2690		pwm1m2_ch1: pwm1m2-ch1 {
2691			rockchip,pins =
2692				/* pwm1_ch1_m2 */
2693				<2 RK_PC1 13 &pcfg_pull_none>;
2694		};
2695
2696		/omit-if-no-ref/
2697		pwm1m2_ch2: pwm1m2-ch2 {
2698			rockchip,pins =
2699				/* pwm1_ch2_m2 */
2700				<2 RK_PC2 13 &pcfg_pull_none>;
2701		};
2702
2703		/omit-if-no-ref/
2704		pwm1m2_ch3: pwm1m2-ch3 {
2705			rockchip,pins =
2706				/* pwm1_ch3_m2 */
2707				<2 RK_PC4 13 &pcfg_pull_none>;
2708		};
2709
2710		/omit-if-no-ref/
2711		pwm1m2_ch4: pwm1m2-ch4 {
2712			rockchip,pins =
2713				/* pwm1_ch4_m2 */
2714				<2 RK_PC5 13 &pcfg_pull_none>;
2715		};
2716
2717		/omit-if-no-ref/
2718		pwm1m2_ch5: pwm1m2-ch5 {
2719			rockchip,pins =
2720				/* pwm1_ch5_m2 */
2721				<2 RK_PC6 13 &pcfg_pull_none>;
2722		};
2723
2724		/omit-if-no-ref/
2725		pwm1m3_ch0: pwm1m3-ch0 {
2726			rockchip,pins =
2727				/* pwm1_ch0_m3 */
2728				<3 RK_PA4 12 &pcfg_pull_none>;
2729		};
2730
2731		/omit-if-no-ref/
2732		pwm1m3_ch1: pwm1m3-ch1 {
2733			rockchip,pins =
2734				/* pwm1_ch1_m3 */
2735				<3 RK_PA5 12 &pcfg_pull_none>;
2736		};
2737
2738		/omit-if-no-ref/
2739		pwm1m3_ch2: pwm1m3-ch2 {
2740			rockchip,pins =
2741				/* pwm1_ch2_m3 */
2742				<3 RK_PA6 12 &pcfg_pull_none>;
2743		};
2744
2745		/omit-if-no-ref/
2746		pwm1m3_ch3: pwm1m3-ch3 {
2747			rockchip,pins =
2748				/* pwm1_ch3_m3 */
2749				<3 RK_PB1 12 &pcfg_pull_none>;
2750		};
2751
2752		/omit-if-no-ref/
2753		pwm1m3_ch4: pwm1m3-ch4 {
2754			rockchip,pins =
2755				/* pwm1_ch4_m3 */
2756				<3 RK_PB4 12 &pcfg_pull_none>;
2757		};
2758
2759		/omit-if-no-ref/
2760		pwm1m3_ch5: pwm1m3-ch5 {
2761			rockchip,pins =
2762				/* pwm1_ch5_m3 */
2763				<3 RK_PB5 12 &pcfg_pull_none>;
2764		};
2765	};
2766
2767	pwm2 {
2768		/omit-if-no-ref/
2769		pwm2m0_ch0: pwm2m0-ch0 {
2770			rockchip,pins =
2771				/* pwm2_ch0_m0 */
2772				<0 RK_PD3 12 &pcfg_pull_none_drv_level_2>;
2773		};
2774
2775		/omit-if-no-ref/
2776		pwm2m0_ch1: pwm2m0-ch1 {
2777			rockchip,pins =
2778				/* pwm2_ch1_m0 */
2779				<1 RK_PB3 12 &pcfg_pull_none_drv_level_2>;
2780		};
2781
2782		/omit-if-no-ref/
2783		pwm2m0_ch2: pwm2m0-ch2 {
2784			rockchip,pins =
2785				/* pwm2_ch2_m0 */
2786				<2 RK_PA0 14 &pcfg_pull_none_drv_level_2>;
2787		};
2788
2789		/omit-if-no-ref/
2790		pwm2m0_ch3: pwm2m0-ch3 {
2791			rockchip,pins =
2792				/* pwm2_ch3_m0 */
2793				<2 RK_PA1 14 &pcfg_pull_none_drv_level_2>;
2794		};
2795
2796		/omit-if-no-ref/
2797		pwm2m0_ch4: pwm2m0-ch4 {
2798			rockchip,pins =
2799				/* pwm2_ch4_m0 */
2800				<2 RK_PA4 14 &pcfg_pull_none_drv_level_2>;
2801		};
2802
2803		/omit-if-no-ref/
2804		pwm2m0_ch5: pwm2m0-ch5 {
2805			rockchip,pins =
2806				/* pwm2_ch5_m0 */
2807				<4 RK_PA2 13 &pcfg_pull_none_drv_level_2>;
2808		};
2809
2810		/omit-if-no-ref/
2811		pwm2m0_ch6: pwm2m0-ch6 {
2812			rockchip,pins =
2813				/* pwm2_ch6_m0 */
2814				<4 RK_PA7 13 &pcfg_pull_none_drv_level_2>;
2815		};
2816
2817		/omit-if-no-ref/
2818		pwm2m0_ch7: pwm2m0-ch7 {
2819			rockchip,pins =
2820				/* pwm2_ch7_m0 */
2821				<4 RK_PB3 13 &pcfg_pull_none_drv_level_2>;
2822		};
2823
2824		/omit-if-no-ref/
2825		pwm2m1_ch0: pwm2m1-ch0 {
2826			rockchip,pins =
2827				/* pwm2_ch0_m1 */
2828				<4 RK_PC2 14 &pcfg_pull_none_drv_level_2>;
2829		};
2830
2831		/omit-if-no-ref/
2832		pwm2m1_ch1: pwm2m1-ch1 {
2833			rockchip,pins =
2834				/* pwm2_ch1_m1 */
2835				<4 RK_PC3 14 &pcfg_pull_none_drv_level_2>;
2836		};
2837
2838		/omit-if-no-ref/
2839		pwm2m1_ch2: pwm2m1-ch2 {
2840			rockchip,pins =
2841				/* pwm2_ch2_m1 */
2842				<4 RK_PC6 14 &pcfg_pull_none_drv_level_2>;
2843		};
2844
2845		/omit-if-no-ref/
2846		pwm2m1_ch3: pwm2m1-ch3 {
2847			rockchip,pins =
2848				/* pwm2_ch3_m1 */
2849				<4 RK_PC7 14 &pcfg_pull_none_drv_level_2>;
2850		};
2851
2852		/omit-if-no-ref/
2853		pwm2m1_ch4: pwm2m1-ch4 {
2854			rockchip,pins =
2855				/* pwm2_ch4_m1 */
2856				<4 RK_PA3 13 &pcfg_pull_none_drv_level_2>;
2857		};
2858
2859		/omit-if-no-ref/
2860		pwm2m1_ch5: pwm2m1-ch5 {
2861			rockchip,pins =
2862				/* pwm2_ch5_m1 */
2863				<4 RK_PC5 14 &pcfg_pull_none_drv_level_2>;
2864		};
2865
2866		/omit-if-no-ref/
2867		pwm2m1_ch6: pwm2m1-ch6 {
2868			rockchip,pins =
2869				/* pwm2_ch6_m1 */
2870				<4 RK_PC4 14 &pcfg_pull_none_drv_level_2>;
2871		};
2872
2873		/omit-if-no-ref/
2874		pwm2m1_ch7: pwm2m1-ch7 {
2875			rockchip,pins =
2876				/* pwm2_ch7_m1 */
2877				<1 RK_PB1 12 &pcfg_pull_none_drv_level_2>;
2878		};
2879
2880		/omit-if-no-ref/
2881		pwm2m2_ch0: pwm2m2-ch0 {
2882			rockchip,pins =
2883				/* pwm2_ch0_m2 */
2884				<2 RK_PD0 13 &pcfg_pull_none_drv_level_2>;
2885		};
2886
2887		/omit-if-no-ref/
2888		pwm2m2_ch1: pwm2m2-ch1 {
2889			rockchip,pins =
2890				/* pwm2_ch1_m2 */
2891				<2 RK_PD1 13 &pcfg_pull_none_drv_level_2>;
2892		};
2893
2894		/omit-if-no-ref/
2895		pwm2m2_ch2: pwm2m2-ch2 {
2896			rockchip,pins =
2897				/* pwm2_ch2_m2 */
2898				<2 RK_PD2 13 &pcfg_pull_none_drv_level_2>;
2899		};
2900
2901		/omit-if-no-ref/
2902		pwm2m2_ch3: pwm2m2-ch3 {
2903			rockchip,pins =
2904				/* pwm2_ch3_m2 */
2905				<2 RK_PD3 13 &pcfg_pull_none_drv_level_2>;
2906		};
2907
2908		/omit-if-no-ref/
2909		pwm2m2_ch4: pwm2m2-ch4 {
2910			rockchip,pins =
2911				/* pwm2_ch4_m2 */
2912				<2 RK_PD4 13 &pcfg_pull_none_drv_level_2>;
2913		};
2914
2915		/omit-if-no-ref/
2916		pwm2m2_ch5: pwm2m2-ch5 {
2917			rockchip,pins =
2918				/* pwm2_ch5_m2 */
2919				<2 RK_PD5 13 &pcfg_pull_none_drv_level_2>;
2920		};
2921
2922		/omit-if-no-ref/
2923		pwm2m2_ch6: pwm2m2-ch6 {
2924			rockchip,pins =
2925				/* pwm2_ch6_m2 */
2926				<2 RK_PD6 13 &pcfg_pull_none_drv_level_2>;
2927		};
2928
2929		/omit-if-no-ref/
2930		pwm2m2_ch7: pwm2m2-ch7 {
2931			rockchip,pins =
2932				/* pwm2_ch7_m2 */
2933				<2 RK_PD7 13 &pcfg_pull_none_drv_level_2>;
2934		};
2935
2936		/omit-if-no-ref/
2937		pwm2m3_ch0: pwm2m3-ch0 {
2938			rockchip,pins =
2939				/* pwm2_ch0_m3 */
2940				<3 RK_PC2 12 &pcfg_pull_none_drv_level_2>;
2941		};
2942
2943		/omit-if-no-ref/
2944		pwm2m3_ch1: pwm2m3-ch1 {
2945			rockchip,pins =
2946				/* pwm2_ch1_m3 */
2947				<3 RK_PC3 12 &pcfg_pull_none_drv_level_2>;
2948		};
2949
2950		/omit-if-no-ref/
2951		pwm2m3_ch2: pwm2m3-ch2 {
2952			rockchip,pins =
2953				/* pwm2_ch2_m3 */
2954				<3 RK_PC5 12 &pcfg_pull_none_drv_level_2>;
2955		};
2956
2957		/omit-if-no-ref/
2958		pwm2m3_ch3: pwm2m3-ch3 {
2959			rockchip,pins =
2960				/* pwm2_ch3_m3 */
2961				<3 RK_PD0 12 &pcfg_pull_none_drv_level_2>;
2962		};
2963
2964		/omit-if-no-ref/
2965		pwm2m3_ch4: pwm2m3-ch4 {
2966			rockchip,pins =
2967				/* pwm2_ch4_m3 */
2968				<3 RK_PD2 12 &pcfg_pull_none_drv_level_2>;
2969		};
2970
2971		/omit-if-no-ref/
2972		pwm2m3_ch5: pwm2m3-ch5 {
2973			rockchip,pins =
2974				/* pwm2_ch5_m3 */
2975				<3 RK_PD3 12 &pcfg_pull_none_drv_level_2>;
2976		};
2977
2978		/omit-if-no-ref/
2979		pwm2m3_ch6: pwm2m3-ch6 {
2980			rockchip,pins =
2981				/* pwm2_ch6_m3 */
2982				<3 RK_PD6 12 &pcfg_pull_none_drv_level_2>;
2983		};
2984
2985		/omit-if-no-ref/
2986		pwm2m3_ch7: pwm2m3-ch7 {
2987			rockchip,pins =
2988				/* pwm2_ch7_m3 */
2989				<3 RK_PD7 12 &pcfg_pull_none_drv_level_2>;
2990		};
2991	};
2992
2993	ref_clk0 {
2994		/omit-if-no-ref/
2995		ref_clk0_clk0: ref_clk0-clk0 {
2996			rockchip,pins =
2997				/* ref_clk0_out */
2998				<0 RK_PA0 1 &pcfg_pull_none>;
2999		};
3000	};
3001
3002	ref_clk1 {
3003		/omit-if-no-ref/
3004		ref_clk1_clk1: ref_clk1-clk1 {
3005			rockchip,pins =
3006				/* ref_clk1_out */
3007				<0 RK_PB4 1 &pcfg_pull_none>;
3008		};
3009	};
3010
3011	ref_clk2 {
3012		/omit-if-no-ref/
3013		ref_clk2_clk2: ref_clk2-clk2 {
3014			rockchip,pins =
3015				/* ref_clk2_out */
3016				<0 RK_PB5 1 &pcfg_pull_none>;
3017		};
3018	};
3019
3020	sai0 {
3021		/omit-if-no-ref/
3022		sai0m0_lrck: sai0m0-lrck {
3023			rockchip,pins =
3024				/* sai0_lrck_m0 */
3025				<2 RK_PB7 4 &pcfg_pull_none>;
3026		};
3027
3028		/omit-if-no-ref/
3029		sai0m0_mclk: sai0m0-mclk {
3030			rockchip,pins =
3031				/* sai0_mclk_m0 */
3032				<2 RK_PB5 4 &pcfg_pull_none>;
3033		};
3034
3035		/omit-if-no-ref/
3036		sai0m0_sclk: sai0m0-sclk {
3037			rockchip,pins =
3038				/* sai0_sclk_m0 */
3039				<2 RK_PB6 4 &pcfg_pull_none>;
3040		};
3041
3042		/omit-if-no-ref/
3043		sai0m0_sdi0: sai0m0-sdi0 {
3044			rockchip,pins =
3045				/* sai0_sdi0_m0 */
3046				<2 RK_PB0 4 &pcfg_pull_none>;
3047		};
3048
3049		/omit-if-no-ref/
3050		sai0m0_sdi1: sai0m0-sdi1 {
3051			rockchip,pins =
3052				/* sai0_sdi1_m0 */
3053				<2 RK_PB1 4 &pcfg_pull_none>;
3054		};
3055
3056		/omit-if-no-ref/
3057		sai0m0_sdi2: sai0m0-sdi2 {
3058			rockchip,pins =
3059				/* sai0_sdi2_m0 */
3060				<2 RK_PB2 4 &pcfg_pull_none>;
3061		};
3062
3063		/omit-if-no-ref/
3064		sai0m0_sdi3: sai0m0-sdi3 {
3065			rockchip,pins =
3066				/* sai0_sdi3_m0 */
3067				<2 RK_PB4 4 &pcfg_pull_none>;
3068		};
3069
3070		/omit-if-no-ref/
3071		sai0m0_sdo0: sai0m0-sdo0 {
3072			rockchip,pins =
3073				/* sai0_sdo0_m0 */
3074				<2 RK_PA6 4 &pcfg_pull_none>;
3075		};
3076
3077		/omit-if-no-ref/
3078		sai0m0_sdo1: sai0m0-sdo1 {
3079			rockchip,pins =
3080				/* sai0_sdo1_m0 */
3081				<2 RK_PA7 4 &pcfg_pull_none>;
3082		};
3083
3084		/omit-if-no-ref/
3085		sai0m0_sdo2: sai0m0-sdo2 {
3086			rockchip,pins =
3087				/* sai0_sdo2_m0 */
3088				<2 RK_PB3 4 &pcfg_pull_none>;
3089		};
3090
3091		/omit-if-no-ref/
3092		sai0m0_sdo3: sai0m0-sdo3 {
3093			rockchip,pins =
3094				/* sai0_sdo3_m0 */
3095				<2 RK_PD7 4 &pcfg_pull_none>;
3096		};
3097
3098		/omit-if-no-ref/
3099		sai0m1_lrck: sai0m1-lrck {
3100			rockchip,pins =
3101				/* sai0_lrck_m1 */
3102				<0 RK_PC7 1 &pcfg_pull_none>;
3103		};
3104
3105		/omit-if-no-ref/
3106		sai0m1_mclk: sai0m1-mclk {
3107			rockchip,pins =
3108				/* sai0_mclk_m1 */
3109				<0 RK_PC4 1 &pcfg_pull_none>;
3110		};
3111
3112		/omit-if-no-ref/
3113		sai0m1_sclk: sai0m1-sclk {
3114			rockchip,pins =
3115				/* sai0_sclk_m1 */
3116				<0 RK_PC6 1 &pcfg_pull_none>;
3117		};
3118
3119		/omit-if-no-ref/
3120		sai0m1_sdi0: sai0m1-sdi0 {
3121			rockchip,pins =
3122				/* sai0_sdi0_m1 */
3123				<0 RK_PD0 1 &pcfg_pull_none>;
3124		};
3125
3126		/omit-if-no-ref/
3127		sai0m1_sdi1: sai0m1-sdi1 {
3128			rockchip,pins =
3129				/* sai0_sdi1_m1 */
3130				<0 RK_PD1 1 &pcfg_pull_none>;
3131		};
3132
3133		/omit-if-no-ref/
3134		sai0m1_sdi2: sai0m1-sdi2 {
3135			rockchip,pins =
3136				/* sai0_sdi2_m1 */
3137				<0 RK_PD2 1 &pcfg_pull_none>;
3138		};
3139
3140		/omit-if-no-ref/
3141		sai0m1_sdi3: sai0m1-sdi3 {
3142			rockchip,pins =
3143				/* sai0_sdi3_m1 */
3144				<0 RK_PD3 1 &pcfg_pull_none>;
3145		};
3146
3147		/omit-if-no-ref/
3148		sai0m1_sdo0: sai0m1-sdo0 {
3149			rockchip,pins =
3150				/* sai0_sdo0_m1 */
3151				<0 RK_PC5 1 &pcfg_pull_none>;
3152		};
3153
3154		/omit-if-no-ref/
3155		sai0m1_sdo1: sai0m1-sdo1 {
3156			rockchip,pins =
3157				/* sai0_sdo1_m1 */
3158				<0 RK_PD3 2 &pcfg_pull_none>;
3159		};
3160
3161		/omit-if-no-ref/
3162		sai0m1_sdo2: sai0m1-sdo2 {
3163			rockchip,pins =
3164				/* sai0_sdo2_m1 */
3165				<0 RK_PD2 2 &pcfg_pull_none>;
3166		};
3167
3168		/omit-if-no-ref/
3169		sai0m1_sdo3: sai0m1-sdo3 {
3170			rockchip,pins =
3171				/* sai0_sdo3_m1 */
3172				<0 RK_PD1 2 &pcfg_pull_none>;
3173		};
3174
3175		/omit-if-no-ref/
3176		sai0m2_lrck: sai0m2-lrck {
3177			rockchip,pins =
3178				/* sai0_lrck_m2 */
3179				<1 RK_PA1 3 &pcfg_pull_none>;
3180		};
3181
3182		/omit-if-no-ref/
3183		sai0m2_mclk: sai0m2-mclk {
3184			rockchip,pins =
3185				/* sai0_mclk_m2 */
3186				<1 RK_PA4 3 &pcfg_pull_none>;
3187		};
3188
3189		/omit-if-no-ref/
3190		sai0m2_sclk: sai0m2-sclk {
3191			rockchip,pins =
3192				/* sai0_sclk_m2 */
3193				<1 RK_PA0 3 &pcfg_pull_none>;
3194		};
3195
3196		/omit-if-no-ref/
3197		sai0m2_sdi0: sai0m2-sdi0 {
3198			rockchip,pins =
3199				/* sai0_sdi0_m2 */
3200				<1 RK_PB2 3 &pcfg_pull_none>;
3201		};
3202
3203		/omit-if-no-ref/
3204		sai0m2_sdi1: sai0m2-sdi1 {
3205			rockchip,pins =
3206				/* sai0_sdi1_m2 */
3207				<1 RK_PB1 4 &pcfg_pull_none>;
3208		};
3209
3210		/omit-if-no-ref/
3211		sai0m2_sdi2: sai0m2-sdi2 {
3212			rockchip,pins =
3213				/* sai0_sdi2_m2 */
3214				<1 RK_PA3 4 &pcfg_pull_none>;
3215		};
3216
3217		/omit-if-no-ref/
3218		sai0m2_sdi3: sai0m2-sdi3 {
3219			rockchip,pins =
3220				/* sai0_sdi3_m2 */
3221				<1 RK_PA2 4 &pcfg_pull_none>;
3222		};
3223
3224		/omit-if-no-ref/
3225		sai0m2_sdo0: sai0m2-sdo0 {
3226			rockchip,pins =
3227				/* sai0_sdo0_m2 */
3228				<1 RK_PA7 3 &pcfg_pull_none>;
3229		};
3230
3231		/omit-if-no-ref/
3232		sai0m2_sdo1: sai0m2-sdo1 {
3233			rockchip,pins =
3234				/* sai0_sdo1_m2 */
3235				<1 RK_PA2 3 &pcfg_pull_none>;
3236		};
3237
3238		/omit-if-no-ref/
3239		sai0m2_sdo2: sai0m2-sdo2 {
3240			rockchip,pins =
3241				/* sai0_sdo2_m2 */
3242				<1 RK_PA3 3 &pcfg_pull_none>;
3243		};
3244
3245		/omit-if-no-ref/
3246		sai0m2_sdo3: sai0m2-sdo3 {
3247			rockchip,pins =
3248				/* sai0_sdo3_m2 */
3249				<1 RK_PB1 3 &pcfg_pull_none>;
3250		};
3251	};
3252
3253	sai1 {
3254		/omit-if-no-ref/
3255		sai1m0_lrck: sai1m0-lrck {
3256			rockchip,pins =
3257				/* sai1_lrck_m0 */
3258				<4 RK_PA5 1 &pcfg_pull_none>;
3259		};
3260
3261		/omit-if-no-ref/
3262		sai1m0_mclk: sai1m0-mclk {
3263			rockchip,pins =
3264				/* sai1_mclk_m0 */
3265				<4 RK_PA2 1 &pcfg_pull_none>;
3266		};
3267
3268		/omit-if-no-ref/
3269		sai1m0_sclk: sai1m0-sclk {
3270			rockchip,pins =
3271				/* sai1_sclk_m0 */
3272				<4 RK_PA3 1 &pcfg_pull_none>;
3273		};
3274
3275		/omit-if-no-ref/
3276		sai1m0_sdi0: sai1m0-sdi0 {
3277			rockchip,pins =
3278				/* sai1_sdi0_m0 */
3279				<4 RK_PB3 1 &pcfg_pull_none>;
3280		};
3281
3282		/omit-if-no-ref/
3283		sai1m0_sdi1: sai1m0-sdi1 {
3284			rockchip,pins =
3285				/* sai1_sdi1_m0 */
3286				<4 RK_PB2 2 &pcfg_pull_none>;
3287		};
3288
3289		/omit-if-no-ref/
3290		sai1m0_sdi2: sai1m0-sdi2 {
3291			rockchip,pins =
3292				/* sai1_sdi2_m0 */
3293				<4 RK_PB1 2 &pcfg_pull_none>;
3294		};
3295
3296		/omit-if-no-ref/
3297		sai1m0_sdi3: sai1m0-sdi3 {
3298			rockchip,pins =
3299				/* sai1_sdi3_m0 */
3300				<4 RK_PB0 2 &pcfg_pull_none>;
3301		};
3302
3303		/omit-if-no-ref/
3304		sai1m0_sdo0: sai1m0-sdo0 {
3305			rockchip,pins =
3306				/* sai1_sdo0_m0 */
3307				<4 RK_PA7 1 &pcfg_pull_none>;
3308		};
3309
3310		/omit-if-no-ref/
3311		sai1m0_sdo1: sai1m0-sdo1 {
3312			rockchip,pins =
3313				/* sai1_sdo1_m0 */
3314				<4 RK_PB0 1 &pcfg_pull_none>;
3315		};
3316
3317		/omit-if-no-ref/
3318		sai1m0_sdo2: sai1m0-sdo2 {
3319			rockchip,pins =
3320				/* sai1_sdo2_m0 */
3321				<4 RK_PB1 1 &pcfg_pull_none>;
3322		};
3323
3324		/omit-if-no-ref/
3325		sai1m0_sdo3: sai1m0-sdo3 {
3326			rockchip,pins =
3327				/* sai1_sdo3_m0 */
3328				<4 RK_PB2 1 &pcfg_pull_none>;
3329		};
3330
3331		/omit-if-no-ref/
3332		sai1m1_lrck: sai1m1-lrck {
3333			rockchip,pins =
3334				/* sai1_lrck_m1 */
3335				<3 RK_PC6 4 &pcfg_pull_none>;
3336		};
3337
3338		/omit-if-no-ref/
3339		sai1m1_mclk: sai1m1-mclk {
3340			rockchip,pins =
3341				/* sai1_mclk_m1 */
3342				<3 RK_PD0 4 &pcfg_pull_none>;
3343		};
3344
3345		/omit-if-no-ref/
3346		sai1m1_sclk: sai1m1-sclk {
3347			rockchip,pins =
3348				/* sai1_sclk_m1 */
3349				<3 RK_PC7 4 &pcfg_pull_none>;
3350		};
3351
3352		/omit-if-no-ref/
3353		sai1m1_sdi0: sai1m1-sdi0 {
3354			rockchip,pins =
3355				/* sai1_sdi0_m1 */
3356				<3 RK_PB7 4 &pcfg_pull_none>;
3357		};
3358
3359		/omit-if-no-ref/
3360		sai1m1_sdi1: sai1m1-sdi1 {
3361			rockchip,pins =
3362				/* sai1_sdi1_m1 */
3363				<3 RK_PD4 4 &pcfg_pull_none>;
3364		};
3365
3366		/omit-if-no-ref/
3367		sai1m1_sdi2: sai1m1-sdi2 {
3368			rockchip,pins =
3369				/* sai1_sdi2_m1 */
3370				<3 RK_PD5 4 &pcfg_pull_none>;
3371		};
3372
3373		/omit-if-no-ref/
3374		sai1m1_sdi3: sai1m1-sdi3 {
3375			rockchip,pins =
3376				/* sai1_sdi3_m1 */
3377				<3 RK_PD6 4 &pcfg_pull_none>;
3378		};
3379
3380		/omit-if-no-ref/
3381		sai1m1_sdo0: sai1m1-sdo0 {
3382			rockchip,pins =
3383				/* sai1_sdo0_m1 */
3384				<3 RK_PC5 4 &pcfg_pull_none>;
3385		};
3386
3387		/omit-if-no-ref/
3388		sai1m1_sdo1: sai1m1-sdo1 {
3389			rockchip,pins =
3390				/* sai1_sdo1_m1 */
3391				<3 RK_PC4 4 &pcfg_pull_none>;
3392		};
3393
3394		/omit-if-no-ref/
3395		sai1m1_sdo2: sai1m1-sdo2 {
3396			rockchip,pins =
3397				/* sai1_sdo2_m1 */
3398				<3 RK_PC1 4 &pcfg_pull_none>;
3399		};
3400
3401		/omit-if-no-ref/
3402		sai1m1_sdo3: sai1m1-sdo3 {
3403			rockchip,pins =
3404				/* sai1_sdo3_m1 */
3405				<3 RK_PC0 4 &pcfg_pull_none>;
3406		};
3407	};
3408
3409	sai2 {
3410		/omit-if-no-ref/
3411		sai2m0_lrck: sai2m0-lrck {
3412			rockchip,pins =
3413				/* sai2_lrck_m0 */
3414				<1 RK_PD2 4 &pcfg_pull_none>;
3415		};
3416
3417		/omit-if-no-ref/
3418		sai2m0_mclk: sai2m0-mclk {
3419			rockchip,pins =
3420				/* sai2_mclk_m0 */
3421				<1 RK_PD4 4 &pcfg_pull_none>;
3422		};
3423
3424		/omit-if-no-ref/
3425		sai2m0_sclk: sai2m0-sclk {
3426			rockchip,pins =
3427				/* sai2_sclk_m0 */
3428				<1 RK_PD1 4 &pcfg_pull_none>;
3429		};
3430
3431		/omit-if-no-ref/
3432		sai2m0_sdi: sai2m0-sdi {
3433			rockchip,pins =
3434				/* sai2m0_sdi */
3435				<1 RK_PD3 4 &pcfg_pull_none>;
3436		};
3437		/omit-if-no-ref/
3438		sai2m0_sdo: sai2m0-sdo {
3439			rockchip,pins =
3440				/* sai2m0_sdo */
3441				<1 RK_PD0 4 &pcfg_pull_none>;
3442		};
3443
3444		/omit-if-no-ref/
3445		sai2m1_lrck: sai2m1-lrck {
3446			rockchip,pins =
3447				/* sai2_lrck_m1 */
3448				<2 RK_PC3 4 &pcfg_pull_none>;
3449		};
3450
3451		/omit-if-no-ref/
3452		sai2m1_mclk: sai2m1-mclk {
3453			rockchip,pins =
3454				/* sai2_mclk_m1 */
3455				<2 RK_PC1 4 &pcfg_pull_none>;
3456		};
3457
3458		/omit-if-no-ref/
3459		sai2m1_sclk: sai2m1-sclk {
3460			rockchip,pins =
3461				/* sai2_sclk_m1 */
3462				<2 RK_PC2 4 &pcfg_pull_none>;
3463		};
3464
3465		/omit-if-no-ref/
3466		sai2m1_sdi: sai2m1-sdi {
3467			rockchip,pins =
3468				/* sai2m1_sdi */
3469				<2 RK_PC5 4 &pcfg_pull_none>;
3470		};
3471		/omit-if-no-ref/
3472		sai2m1_sdo: sai2m1-sdo {
3473			rockchip,pins =
3474				/* sai2m1_sdo */
3475				<2 RK_PC4 4 &pcfg_pull_none>;
3476		};
3477
3478		/omit-if-no-ref/
3479		sai2m2_lrck: sai2m2-lrck {
3480			rockchip,pins =
3481				/* sai2_lrck_m2 */
3482				<3 RK_PC3 4 &pcfg_pull_none>;
3483		};
3484
3485		/omit-if-no-ref/
3486		sai2m2_mclk: sai2m2-mclk {
3487			rockchip,pins =
3488				/* sai2_mclk_m2 */
3489				<3 RK_PD1 4 &pcfg_pull_none>;
3490		};
3491
3492		/omit-if-no-ref/
3493		sai2m2_sclk: sai2m2-sclk {
3494			rockchip,pins =
3495				/* sai2_sclk_m2 */
3496				<3 RK_PC2 4 &pcfg_pull_none>;
3497		};
3498
3499		/omit-if-no-ref/
3500		sai2m2_sdi: sai2m2-sdi {
3501			rockchip,pins =
3502				/* sai2m2_sdi */
3503				<3 RK_PD2 4 &pcfg_pull_none>;
3504		};
3505		/omit-if-no-ref/
3506		sai2m2_sdo: sai2m2-sdo {
3507			rockchip,pins =
3508				/* sai2m2_sdo */
3509				<3 RK_PD3 4 &pcfg_pull_none>;
3510		};
3511	};
3512
3513	sai3 {
3514		/omit-if-no-ref/
3515		sai3m0_lrck: sai3m0-lrck {
3516			rockchip,pins =
3517				/* sai3_lrck_m0 */
3518				<1 RK_PA6 4 &pcfg_pull_none>;
3519		};
3520
3521		/omit-if-no-ref/
3522		sai3m0_mclk: sai3m0-mclk {
3523			rockchip,pins =
3524				/* sai3_mclk_m0 */
3525				<1 RK_PA4 4 &pcfg_pull_none>;
3526		};
3527
3528		/omit-if-no-ref/
3529		sai3m0_sclk: sai3m0-sclk {
3530			rockchip,pins =
3531				/* sai3_sclk_m0 */
3532				<1 RK_PA5 4 &pcfg_pull_none>;
3533		};
3534
3535		/omit-if-no-ref/
3536		sai3m0_sdi: sai3m0-sdi {
3537			rockchip,pins =
3538				/* sai3m0_sdi */
3539				<1 RK_PA7 4 &pcfg_pull_none>;
3540		};
3541		/omit-if-no-ref/
3542		sai3m0_sdo: sai3m0-sdo {
3543			rockchip,pins =
3544				/* sai3m0_sdo */
3545				<1 RK_PB2 4 &pcfg_pull_none>;
3546		};
3547
3548		/omit-if-no-ref/
3549		sai3m1_lrck: sai3m1-lrck {
3550			rockchip,pins =
3551				/* sai3_lrck_m1 */
3552				<1 RK_PB5 4 &pcfg_pull_none>;
3553		};
3554
3555		/omit-if-no-ref/
3556		sai3m1_mclk: sai3m1-mclk {
3557			rockchip,pins =
3558				/* sai3_mclk_m1 */
3559				<1 RK_PC1 4 &pcfg_pull_none>;
3560		};
3561
3562		/omit-if-no-ref/
3563		sai3m1_sclk: sai3m1-sclk {
3564			rockchip,pins =
3565				/* sai3_sclk_m1 */
3566				<1 RK_PB4 4 &pcfg_pull_none>;
3567		};
3568
3569		/omit-if-no-ref/
3570		sai3m1_sdi: sai3m1-sdi {
3571			rockchip,pins =
3572				/* sai3m1_sdi */
3573				<1 RK_PB7 4 &pcfg_pull_none>;
3574		};
3575		/omit-if-no-ref/
3576		sai3m1_sdo: sai3m1-sdo {
3577			rockchip,pins =
3578				/* sai3m1_sdo */
3579				<1 RK_PB6 4 &pcfg_pull_none>;
3580		};
3581
3582		/omit-if-no-ref/
3583		sai3m2_lrck: sai3m2-lrck {
3584			rockchip,pins =
3585				/* sai3_lrck_m2 */
3586				<3 RK_PA1 4 &pcfg_pull_none>;
3587		};
3588
3589		/omit-if-no-ref/
3590		sai3m2_mclk: sai3m2-mclk {
3591			rockchip,pins =
3592				/* sai3_mclk_m2 */
3593				<2 RK_PD6 4 &pcfg_pull_none>;
3594		};
3595
3596		/omit-if-no-ref/
3597		sai3m2_sclk: sai3m2-sclk {
3598			rockchip,pins =
3599				/* sai3_sclk_m2 */
3600				<3 RK_PA0 4 &pcfg_pull_none>;
3601		};
3602
3603		/omit-if-no-ref/
3604		sai3m2_sdi: sai3m2-sdi {
3605			rockchip,pins =
3606				/* sai3m2_sdi */
3607				<3 RK_PA3 4 &pcfg_pull_none>;
3608		};
3609		/omit-if-no-ref/
3610		sai3m2_sdo: sai3m2-sdo {
3611			rockchip,pins =
3612				/* sai3m2_sdo */
3613				<3 RK_PA2 4 &pcfg_pull_none>;
3614		};
3615
3616		/omit-if-no-ref/
3617		sai3m3_lrck: sai3m3-lrck {
3618			rockchip,pins =
3619				/* sai3_lrck_m3 */
3620				<2 RK_PA2 4 &pcfg_pull_none>;
3621		};
3622
3623		/omit-if-no-ref/
3624		sai3m3_mclk: sai3m3-mclk {
3625			rockchip,pins =
3626				/* sai3_mclk_m3 */
3627				<2 RK_PA1 4 &pcfg_pull_none>;
3628		};
3629
3630		/omit-if-no-ref/
3631		sai3m3_sclk: sai3m3-sclk {
3632			rockchip,pins =
3633				/* sai3_sclk_m3 */
3634				<2 RK_PA5 4 &pcfg_pull_none>;
3635		};
3636
3637		/omit-if-no-ref/
3638		sai3m3_sdi: sai3m3-sdi {
3639			rockchip,pins =
3640				/* sai3m3_sdi */
3641				<2 RK_PA3 4 &pcfg_pull_none>;
3642		};
3643		/omit-if-no-ref/
3644		sai3m3_sdo: sai3m3-sdo {
3645			rockchip,pins =
3646				/* sai3m3_sdo */
3647				<2 RK_PA4 4 &pcfg_pull_none>;
3648		};
3649	};
3650
3651	sai4 {
3652		/omit-if-no-ref/
3653		sai4m0_lrck: sai4m0-lrck {
3654			rockchip,pins =
3655				/* sai4_lrck_m0 */
3656				<4 RK_PA6 2 &pcfg_pull_none>;
3657		};
3658
3659		/omit-if-no-ref/
3660		sai4m0_mclk: sai4m0-mclk {
3661			rockchip,pins =
3662				/* sai4_mclk_m0 */
3663				<4 RK_PA2 2 &pcfg_pull_none>;
3664		};
3665
3666		/omit-if-no-ref/
3667		sai4m0_sclk: sai4m0-sclk {
3668			rockchip,pins =
3669				/* sai4_sclk_m0 */
3670				<4 RK_PA4 2 &pcfg_pull_none>;
3671		};
3672
3673		/omit-if-no-ref/
3674		sai4m0_sdi: sai4m0-sdi {
3675			rockchip,pins =
3676				/* sai4m0_sdi */
3677				<4 RK_PA7 2 &pcfg_pull_none>;
3678		};
3679		/omit-if-no-ref/
3680		sai4m0_sdo: sai4m0-sdo {
3681			rockchip,pins =
3682				/* sai4m0_sdo */
3683				<4 RK_PB3 2 &pcfg_pull_none>;
3684		};
3685
3686		/omit-if-no-ref/
3687		sai4m1_lrck: sai4m1-lrck {
3688			rockchip,pins =
3689				/* sai4_lrck_m1 */
3690				<4 RK_PA0 4 &pcfg_pull_none>;
3691		};
3692
3693		/omit-if-no-ref/
3694		sai4m1_mclk: sai4m1-mclk {
3695			rockchip,pins =
3696				/* sai4_mclk_m1 */
3697				<3 RK_PB0 4 &pcfg_pull_none>;
3698		};
3699
3700		/omit-if-no-ref/
3701		sai4m1_sclk: sai4m1-sclk {
3702			rockchip,pins =
3703				/* sai4_sclk_m1 */
3704				<3 RK_PD7 4 &pcfg_pull_none>;
3705		};
3706
3707		/omit-if-no-ref/
3708		sai4m1_sdi: sai4m1-sdi {
3709			rockchip,pins =
3710				/* sai4m1_sdi */
3711				<3 RK_PA4 4 &pcfg_pull_none>;
3712		};
3713		/omit-if-no-ref/
3714		sai4m1_sdo: sai4m1-sdo {
3715			rockchip,pins =
3716				/* sai4m1_sdo */
3717				<4 RK_PA1 4 &pcfg_pull_none>;
3718		};
3719
3720		/omit-if-no-ref/
3721		sai4m2_lrck: sai4m2-lrck {
3722			rockchip,pins =
3723				/* sai4_lrck_m2 */
3724				<4 RK_PC4 2 &pcfg_pull_none>;
3725		};
3726
3727		/omit-if-no-ref/
3728		sai4m2_mclk: sai4m2-mclk {
3729			rockchip,pins =
3730				/* sai4_mclk_m2 */
3731				<4 RK_PC0 2 &pcfg_pull_none>;
3732		};
3733
3734		/omit-if-no-ref/
3735		sai4m2_sclk: sai4m2-sclk {
3736			rockchip,pins =
3737				/* sai4_sclk_m2 */
3738				<4 RK_PC7 2 &pcfg_pull_none>;
3739		};
3740
3741		/omit-if-no-ref/
3742		sai4m2_sdi: sai4m2-sdi {
3743			rockchip,pins =
3744				/* sai4m2_sdi */
3745				<4 RK_PC6 2 &pcfg_pull_none>;
3746		};
3747		/omit-if-no-ref/
3748		sai4m2_sdo: sai4m2-sdo {
3749			rockchip,pins =
3750				/* sai4m2_sdo */
3751				<4 RK_PC5 2 &pcfg_pull_none>;
3752		};
3753
3754		/omit-if-no-ref/
3755		sai4m3_lrck: sai4m3-lrck {
3756			rockchip,pins =
3757				/* sai4_lrck_m3 */
3758				<2 RK_PC7 4 &pcfg_pull_none>;
3759		};
3760
3761		/omit-if-no-ref/
3762		sai4m3_mclk: sai4m3-mclk {
3763			rockchip,pins =
3764				/* sai4_mclk_m3 */
3765				<2 RK_PD2 4 &pcfg_pull_none>;
3766		};
3767
3768		/omit-if-no-ref/
3769		sai4m3_sclk: sai4m3-sclk {
3770			rockchip,pins =
3771				/* sai4_sclk_m3 */
3772				<2 RK_PC6 4 &pcfg_pull_none>;
3773		};
3774
3775		/omit-if-no-ref/
3776		sai4m3_sdi: sai4m3-sdi {
3777			rockchip,pins =
3778				/* sai4m3_sdi */
3779				<2 RK_PD0 4 &pcfg_pull_none>;
3780		};
3781		/omit-if-no-ref/
3782		sai4m3_sdo: sai4m3-sdo {
3783			rockchip,pins =
3784				/* sai4m3_sdo */
3785				<2 RK_PD1 4 &pcfg_pull_none>;
3786		};
3787	};
3788
3789	sata30 {
3790		/omit-if-no-ref/
3791		sata30_sata: sata30-sata {
3792			rockchip,pins =
3793				/* sata30_cpdet */
3794				<1 RK_PC7 12 &pcfg_pull_none>,
3795				/* sata30_cppod */
3796				<1 RK_PC6 12 &pcfg_pull_none>,
3797				/* sata30_mpswit */
3798				<1 RK_PD5 12 &pcfg_pull_none>;
3799		};
3800	};
3801
3802	sata30_port0 {
3803		/omit-if-no-ref/
3804		sata30_port0m0_port0: sata30_port0m0-port0 {
3805			rockchip,pins =
3806				/* sata30_port0_actled_m0 */
3807				<2 RK_PB4 12 &pcfg_pull_none>;
3808		};
3809
3810		/omit-if-no-ref/
3811		sata30_port0m1_port0: sata30_port0m1-port0 {
3812			rockchip,pins =
3813				/* sata30_port0_actled_m1 */
3814				<4 RK_PC6 10 &pcfg_pull_none>;
3815		};
3816	};
3817
3818	sata30_port1 {
3819		/omit-if-no-ref/
3820		sata30_port1m0_port1: sata30_port1m0-port1 {
3821			rockchip,pins =
3822				/* sata30_port1_actled_m0 */
3823				<2 RK_PB5 12 &pcfg_pull_none>;
3824		};
3825
3826		/omit-if-no-ref/
3827		sata30_port1m1_port1: sata30_port1m1-port1 {
3828			rockchip,pins =
3829				/* sata30_port1_actled_m1 */
3830				<4 RK_PC5 10 &pcfg_pull_none>;
3831		};
3832	};
3833
3834	sdmmc0 {
3835		/omit-if-no-ref/
3836		sdmmc0_bus4: sdmmc0-bus4 {
3837			rockchip,pins =
3838				/* sdmmc0_d0 */
3839				<2 RK_PA0 1 &pcfg_pull_up_drv_level_3>,
3840				/* sdmmc0_d1 */
3841				<2 RK_PA1 1 &pcfg_pull_up_drv_level_3>,
3842				/* sdmmc0_d2 */
3843				<2 RK_PA2 1 &pcfg_pull_up_drv_level_3>,
3844				/* sdmmc0_d3 */
3845				<2 RK_PA3 1 &pcfg_pull_up_drv_level_3>;
3846		};
3847
3848		/omit-if-no-ref/
3849		sdmmc0_clk: sdmmc0-clk {
3850			rockchip,pins =
3851				/* sdmmc0_clk */
3852				<2 RK_PA5 1 &pcfg_pull_up_drv_level_3>;
3853		};
3854
3855		/omit-if-no-ref/
3856		sdmmc0_cmd: sdmmc0-cmd {
3857			rockchip,pins =
3858				/* sdmmc0_cmd */
3859				<2 RK_PA4 1 &pcfg_pull_up_drv_level_3>;
3860		};
3861
3862		/omit-if-no-ref/
3863		sdmmc0_det: sdmmc0-det {
3864			rockchip,pins =
3865				/* sdmmc0_detn */
3866				<0 RK_PA7 1 &pcfg_pull_up>;
3867		};
3868
3869		/omit-if-no-ref/
3870		sdmmc0_pwren: sdmmc0-pwren {
3871			rockchip,pins =
3872				/* sdmmc0_pwren */
3873				<0 RK_PB6 1 &pcfg_pull_none>;
3874		};
3875	};
3876
3877	sdmmc1 {
3878		/omit-if-no-ref/
3879		sdmmc1m0_bus4: sdmmc1m0-bus4 {
3880			rockchip,pins =
3881				/* sdmmc1_d0_m0 */
3882				<1 RK_PB4 2 &pcfg_pull_up_drv_level_2>,
3883				/* sdmmc1_d1_m0 */
3884				<1 RK_PB5 2 &pcfg_pull_up_drv_level_2>,
3885				/* sdmmc1_d2_m0 */
3886				<1 RK_PB6 2 &pcfg_pull_up_drv_level_2>,
3887				/* sdmmc1_d3_m0 */
3888				<1 RK_PB7 2 &pcfg_pull_up_drv_level_2>;
3889		};
3890
3891		/omit-if-no-ref/
3892		sdmmc1m0_clk: sdmmc1m0-clk {
3893			rockchip,pins =
3894				/* sdmmc1_clk_m0 */
3895				<1 RK_PC1 2 &pcfg_pull_up_drv_level_2>;
3896		};
3897
3898		/omit-if-no-ref/
3899		sdmmc1m0_cmd: sdmmc1m0-cmd {
3900			rockchip,pins =
3901				/* sdmmc1_cmd_m0 */
3902				<1 RK_PC0 2 &pcfg_pull_up_drv_level_2>;
3903		};
3904
3905		/omit-if-no-ref/
3906		sdmmc1m0_det: sdmmc1m0-det {
3907			rockchip,pins =
3908				/* sdmmc1_detn_m0 */
3909				<1 RK_PC3 2 &pcfg_pull_up>;
3910		};
3911
3912		/omit-if-no-ref/
3913		sdmmc1m0_pwren: sdmmc1m0-pwren {
3914			rockchip,pins =
3915				/* sdmmc1m0_pwren */
3916				<1 RK_PC2 2 &pcfg_pull_none>;
3917		};
3918
3919		/omit-if-no-ref/
3920		sdmmc1m1_bus4: sdmmc1m1-bus4 {
3921			rockchip,pins =
3922				/* sdmmc1_d0_m1 */
3923				<2 RK_PA6 2 &pcfg_pull_up_drv_level_2>,
3924				/* sdmmc1_d1_m1 */
3925				<2 RK_PA7 2 &pcfg_pull_up_drv_level_2>,
3926				/* sdmmc1_d2_m1 */
3927				<2 RK_PB0 2 &pcfg_pull_up_drv_level_2>,
3928				/* sdmmc1_d3_m1 */
3929				<2 RK_PB1 2 &pcfg_pull_up_drv_level_2>;
3930		};
3931
3932		/omit-if-no-ref/
3933		sdmmc1m1_clk: sdmmc1m1-clk {
3934			rockchip,pins =
3935				/* sdmmc1_clk_m1 */
3936				<2 RK_PB3 2 &pcfg_pull_up_drv_level_2>;
3937		};
3938
3939		/omit-if-no-ref/
3940		sdmmc1m1_cmd: sdmmc1m1-cmd {
3941			rockchip,pins =
3942				/* sdmmc1_cmd_m1 */
3943				<2 RK_PB2 2 &pcfg_pull_up_drv_level_2>;
3944		};
3945
3946		/omit-if-no-ref/
3947		sdmmc1m1_det: sdmmc1m1-det {
3948			rockchip,pins =
3949				/* sdmmc1_detn_m1 */
3950				<2 RK_PB5 2 &pcfg_pull_up>;
3951		};
3952
3953		/omit-if-no-ref/
3954		sdmmc1m1_pwren: sdmmc1m1-pwren {
3955			rockchip,pins =
3956				/* sdmmc1m1_pwren */
3957				<2 RK_PB4 2 &pcfg_pull_none>;
3958		};
3959
3960		/omit-if-no-ref/
3961		sdmmc1m2_det: sdmmc1m2-det {
3962			rockchip,pins =
3963				/* sdmmc1_detn_m2 */
3964				<0 RK_PB6 2 &pcfg_pull_up>;
3965		};
3966	};
3967
3968	sdmmc0_testclk {
3969		/omit-if-no-ref/
3970		sdmmc0_testclk_test: sdmmc0_testclk-test {
3971			rockchip,pins =
3972				/* sdmmc0_testclk_out */
3973				<1 RK_PC4 6 &pcfg_pull_none>;
3974		};
3975	};
3976
3977	sdmmc0_testdata {
3978		/omit-if-no-ref/
3979		sdmmc0_testdata_test: sdmmc0_testdata-test {
3980			rockchip,pins =
3981				/* sdmmc0_testdata_out */
3982				<1 RK_PC5 6 &pcfg_pull_none>;
3983		};
3984	};
3985
3986	sdmmc1_testclk {
3987		/omit-if-no-ref/
3988		sdmmc1_testclkm0_test: sdmmc1_testclkm0-test {
3989			rockchip,pins =
3990				/* sdmmc1_testclk_out_m0 */
3991				<1 RK_PC4 5 &pcfg_pull_none>;
3992		};
3993	};
3994
3995	sdmmc1_testdata {
3996		/omit-if-no-ref/
3997		sdmmc1_testdatam0_test: sdmmc1_testdatam0-test {
3998			rockchip,pins =
3999				/* sdmmc1_testdata_out_m0 */
4000				<1 RK_PC5 5 &pcfg_pull_none>;
4001		};
4002	};
4003
4004	spdif {
4005		/omit-if-no-ref/
4006		spdifm0_rx0: spdifm0-rx0 {
4007			rockchip,pins =
4008				/* spdif_rx0_m0 */
4009				<4 RK_PB4 1 &pcfg_pull_none>;
4010		};
4011
4012		/omit-if-no-ref/
4013		spdifm0_rx1: spdifm0-rx1 {
4014			rockchip,pins =
4015				/* spdif_rx1_m0 */
4016				<3 RK_PB4 4 &pcfg_pull_none>;
4017		};
4018
4019		/omit-if-no-ref/
4020		spdifm0_tx0: spdifm0-tx0 {
4021			rockchip,pins =
4022				/* spdif_tx0_m0 */
4023				<4 RK_PB5 1 &pcfg_pull_none>;
4024		};
4025
4026		/omit-if-no-ref/
4027		spdifm0_tx1: spdifm0-tx1 {
4028			rockchip,pins =
4029				/* spdif_tx1_m0 */
4030				<3 RK_PB5 4 &pcfg_pull_none>;
4031		};
4032
4033		/omit-if-no-ref/
4034		spdifm1_rx0: spdifm1-rx0 {
4035			rockchip,pins =
4036				/* spdif_rx0_m1 */
4037				<4 RK_PA0 2 &pcfg_pull_none>;
4038		};
4039
4040		/omit-if-no-ref/
4041		spdifm1_rx1: spdifm1-rx1 {
4042			rockchip,pins =
4043				/* spdif_rx1_m1 */
4044				<3 RK_PA2 5 &pcfg_pull_none>;
4045		};
4046
4047		/omit-if-no-ref/
4048		spdifm1_tx0: spdifm1-tx0 {
4049			rockchip,pins =
4050				/* spdif_tx0_m1 */
4051				<4 RK_PA1 2 &pcfg_pull_none>;
4052		};
4053
4054		/omit-if-no-ref/
4055		spdifm1_tx1: spdifm1-tx1 {
4056			rockchip,pins =
4057				/* spdif_tx1_m1 */
4058				<3 RK_PA3 5 &pcfg_pull_none>;
4059		};
4060
4061		/omit-if-no-ref/
4062		spdifm2_rx0: spdifm2-rx0 {
4063			rockchip,pins =
4064				/* spdif_rx0_m2 */
4065				<2 RK_PD6 5 &pcfg_pull_none>;
4066		};
4067
4068		/omit-if-no-ref/
4069		spdifm2_rx1: spdifm2-rx1 {
4070			rockchip,pins =
4071				/* spdif_rx1_m2 */
4072				<1 RK_PD4 6 &pcfg_pull_none>;
4073		};
4074
4075		/omit-if-no-ref/
4076		spdifm2_tx0: spdifm2-tx0 {
4077			rockchip,pins =
4078				/* spdif_tx0_m2 */
4079				<2 RK_PD7 5 &pcfg_pull_none>;
4080		};
4081
4082		/omit-if-no-ref/
4083		spdifm2_tx1: spdifm2-tx1 {
4084			rockchip,pins =
4085				/* spdif_tx1_m2 */
4086				<1 RK_PD5 6 &pcfg_pull_none>;
4087		};
4088	};
4089
4090	spi0 {
4091		/omit-if-no-ref/
4092		spi0m0_pins: spi0m0-pins {
4093			rockchip,pins =
4094				/* spi0_clk_m0 */
4095				<0 RK_PC7 11 &pcfg_pull_none>,
4096				/* spi0_miso_m0 */
4097				<0 RK_PD1 11 &pcfg_pull_none>,
4098				/* spi0_mosi_m0 */
4099				<0 RK_PD0 11 &pcfg_pull_none>;
4100		};
4101
4102		/omit-if-no-ref/
4103		spi0m0_csn0: spi0m0-csn0 {
4104			rockchip,pins =
4105				/* spi0m0_csn0 */
4106				<0 RK_PC6 11 &pcfg_pull_none>;
4107		};
4108		/omit-if-no-ref/
4109		spi0m0_csn1: spi0m0-csn1 {
4110			rockchip,pins =
4111				/* spi0m0_csn1 */
4112				<0 RK_PC3 11 &pcfg_pull_none>;
4113		};
4114
4115		/omit-if-no-ref/
4116		spi0m1_pins: spi0m1-pins {
4117			rockchip,pins =
4118				/* spi0_clk_m1 */
4119				<2 RK_PA5 12 &pcfg_pull_none>,
4120				/* spi0_miso_m1 */
4121				<2 RK_PA1 12 &pcfg_pull_none>,
4122				/* spi0_mosi_m1 */
4123				<2 RK_PA0 12 &pcfg_pull_none>;
4124		};
4125
4126		/omit-if-no-ref/
4127		spi0m1_csn0: spi0m1-csn0 {
4128			rockchip,pins =
4129				/* spi0m1_csn0 */
4130				<2 RK_PA4 12 &pcfg_pull_none>;
4131		};
4132		/omit-if-no-ref/
4133		spi0m1_csn1: spi0m1-csn1 {
4134			rockchip,pins =
4135				/* spi0m1_csn1 */
4136				<2 RK_PA2 12 &pcfg_pull_none>;
4137		};
4138
4139		/omit-if-no-ref/
4140		spi0m2_pins: spi0m2-pins {
4141			rockchip,pins =
4142				/* spi0_clk_m2 */
4143				<1 RK_PA7 9 &pcfg_pull_none>,
4144				/* spi0_miso_m2 */
4145				<1 RK_PA6 9 &pcfg_pull_none>,
4146				/* spi0_mosi_m2 */
4147				<1 RK_PA5 9 &pcfg_pull_none>;
4148		};
4149
4150		/omit-if-no-ref/
4151		spi0m2_csn0: spi0m2-csn0 {
4152			rockchip,pins =
4153				/* spi0m2_csn0 */
4154				<1 RK_PA4 9 &pcfg_pull_none>;
4155		};
4156		/omit-if-no-ref/
4157		spi0m2_csn1: spi0m2-csn1 {
4158			rockchip,pins =
4159				/* spi0m2_csn1 */
4160				<1 RK_PB2 9 &pcfg_pull_none>;
4161		};
4162	};
4163
4164	spi1 {
4165		/omit-if-no-ref/
4166		spi1m0_pins: spi1m0-pins {
4167			rockchip,pins =
4168				/* spi1_clk_m0 */
4169				<1 RK_PB4 11 &pcfg_pull_none>,
4170				/* spi1_miso_m0 */
4171				<1 RK_PB6 11 &pcfg_pull_none>,
4172				/* spi1_mosi_m0 */
4173				<1 RK_PB5 11 &pcfg_pull_none>;
4174		};
4175
4176		/omit-if-no-ref/
4177		spi1m0_csn0: spi1m0-csn0 {
4178			rockchip,pins =
4179				/* spi1m0_csn0 */
4180				<1 RK_PB7 11 &pcfg_pull_none>;
4181		};
4182		/omit-if-no-ref/
4183		spi1m0_csn1: spi1m0-csn1 {
4184			rockchip,pins =
4185				/* spi1m0_csn1 */
4186				<1 RK_PC0 11 &pcfg_pull_none>;
4187		};
4188
4189		/omit-if-no-ref/
4190		spi1m1_pins: spi1m1-pins {
4191			rockchip,pins =
4192				/* spi1_clk_m1 */
4193				<2 RK_PC5 10 &pcfg_pull_none>,
4194				/* spi1_miso_m1 */
4195				<2 RK_PC3 10 &pcfg_pull_none>,
4196				/* spi1_mosi_m1 */
4197				<2 RK_PC2 10 &pcfg_pull_none>;
4198		};
4199
4200		/omit-if-no-ref/
4201		spi1m1_csn0: spi1m1-csn0 {
4202			rockchip,pins =
4203				/* spi1m1_csn0 */
4204				<2 RK_PC4 10 &pcfg_pull_none>;
4205		};
4206		/omit-if-no-ref/
4207		spi1m1_csn1: spi1m1-csn1 {
4208			rockchip,pins =
4209				/* spi1m1_csn1 */
4210				<2 RK_PC1 10 &pcfg_pull_none>;
4211		};
4212
4213		/omit-if-no-ref/
4214		spi1m2_pins: spi1m2-pins {
4215			rockchip,pins =
4216				/* spi1_clk_m2 */
4217				<3 RK_PC7 10 &pcfg_pull_none>,
4218				/* spi1_miso_m2 */
4219				<3 RK_PC5 10 &pcfg_pull_none>,
4220				/* spi1_mosi_m2 */
4221				<3 RK_PC6 10 &pcfg_pull_none>;
4222		};
4223
4224		/omit-if-no-ref/
4225		spi1m2_csn0: spi1m2-csn0 {
4226			rockchip,pins =
4227				/* spi1m2_csn0 */
4228				<3 RK_PD0 10 &pcfg_pull_none>;
4229		};
4230		/omit-if-no-ref/
4231		spi1m2_csn1: spi1m2-csn1 {
4232			rockchip,pins =
4233				/* spi1m2_csn1 */
4234				<4 RK_PA0 10 &pcfg_pull_none>;
4235		};
4236	};
4237
4238	spi2 {
4239		/omit-if-no-ref/
4240		spi2m0_pins: spi2m0-pins {
4241			rockchip,pins =
4242				/* spi2_clk_m0 */
4243				<0 RK_PB2 9 &pcfg_pull_none>,
4244				/* spi2_miso_m0 */
4245				<0 RK_PB1 9 &pcfg_pull_none>,
4246				/* spi2_mosi_m0 */
4247				<0 RK_PB3 9 &pcfg_pull_none>;
4248		};
4249
4250		/omit-if-no-ref/
4251		spi2m0_csn0: spi2m0-csn0 {
4252			rockchip,pins =
4253				/* spi2m0_csn0 */
4254				<0 RK_PB0 9 &pcfg_pull_none>;
4255		};
4256		/omit-if-no-ref/
4257		spi2m0_csn1: spi2m0-csn1 {
4258			rockchip,pins =
4259				/* spi2m0_csn1 */
4260				<0 RK_PA7 9 &pcfg_pull_none>;
4261		};
4262
4263		/omit-if-no-ref/
4264		spi2m1_pins: spi2m1-pins {
4265			rockchip,pins =
4266				/* spi2_clk_m1 */
4267				<1 RK_PD5 11 &pcfg_pull_none>,
4268				/* spi2_miso_m1 */
4269				<1 RK_PC5 11 &pcfg_pull_none>,
4270				/* spi2_mosi_m1 */
4271				<1 RK_PC4 11 &pcfg_pull_none>;
4272		};
4273
4274		/omit-if-no-ref/
4275		spi2m1_csn0: spi2m1-csn0 {
4276			rockchip,pins =
4277				/* spi2m1_csn0 */
4278				<1 RK_PC3 11 &pcfg_pull_none>;
4279		};
4280		/omit-if-no-ref/
4281		spi2m1_csn1: spi2m1-csn1 {
4282			rockchip,pins =
4283				/* spi2m1_csn1 */
4284				<1 RK_PC2 11 &pcfg_pull_none>;
4285		};
4286
4287		/omit-if-no-ref/
4288		spi2m2_pins: spi2m2-pins {
4289			rockchip,pins =
4290				/* spi2_clk_m2 */
4291				<3 RK_PA4 10 &pcfg_pull_none>,
4292				/* spi2_miso_m2 */
4293				<3 RK_PC1 10 &pcfg_pull_none>,
4294				/* spi2_mosi_m2 */
4295				<3 RK_PB0 10 &pcfg_pull_none>;
4296		};
4297
4298		/omit-if-no-ref/
4299		spi2m2_csn0: spi2m2-csn0 {
4300			rockchip,pins =
4301				/* spi2m2_csn0 */
4302				<3 RK_PC4 10 &pcfg_pull_none>;
4303		};
4304		/omit-if-no-ref/
4305		spi2m2_csn1: spi2m2-csn1 {
4306			rockchip,pins =
4307				/* spi2m2_csn1 */
4308				<3 RK_PA5 10 &pcfg_pull_none>;
4309		};
4310	};
4311
4312	spi3 {
4313		/omit-if-no-ref/
4314		spi3m0_pins: spi3m0-pins {
4315			rockchip,pins =
4316				/* spi3_clk_m0 */
4317				<3 RK_PA0 10 &pcfg_pull_none>,
4318				/* spi3_miso_m0 */
4319				<3 RK_PA2 10 &pcfg_pull_none>,
4320				/* spi3_mosi_m0 */
4321				<3 RK_PA1 10 &pcfg_pull_none>;
4322		};
4323
4324		/omit-if-no-ref/
4325		spi3m0_csn0: spi3m0-csn0 {
4326			rockchip,pins =
4327				/* spi3m0_csn0 */
4328				<3 RK_PA3 10 &pcfg_pull_none>;
4329		};
4330		/omit-if-no-ref/
4331		spi3m0_csn1: spi3m0-csn1 {
4332			rockchip,pins =
4333				/* spi3m0_csn1 */
4334				<2 RK_PD7 10 &pcfg_pull_none>;
4335		};
4336
4337		/omit-if-no-ref/
4338		spi3m1_pins: spi3m1-pins {
4339			rockchip,pins =
4340				/* spi3_clk_m1 */
4341				<3 RK_PD4 10 &pcfg_pull_none>,
4342				/* spi3_miso_m1 */
4343				<3 RK_PD5 10 &pcfg_pull_none>,
4344				/* spi3_mosi_m1 */
4345				<3 RK_PD6 10 &pcfg_pull_none>;
4346		};
4347
4348		/omit-if-no-ref/
4349		spi3m1_csn0: spi3m1-csn0 {
4350			rockchip,pins =
4351				/* spi3m1_csn0 */
4352				<3 RK_PB6 10 &pcfg_pull_none>;
4353		};
4354		/omit-if-no-ref/
4355		spi3m1_csn1: spi3m1-csn1 {
4356			rockchip,pins =
4357				/* spi3m1_csn1 */
4358				<3 RK_PD7 10 &pcfg_pull_none>;
4359		};
4360
4361		/omit-if-no-ref/
4362		spi3m2_pins: spi3m2-pins {
4363			rockchip,pins =
4364				/* spi3_clk_m2 */
4365				<4 RK_PA7 9 &pcfg_pull_none>,
4366				/* spi3_miso_m2 */
4367				<4 RK_PA6 9 &pcfg_pull_none>,
4368				/* spi3_mosi_m2 */
4369				<4 RK_PA4 9 &pcfg_pull_none>;
4370		};
4371
4372		/omit-if-no-ref/
4373		spi3m2_csn0: spi3m2-csn0 {
4374			rockchip,pins =
4375				/* spi3m2_csn0 */
4376				<4 RK_PA3 9 &pcfg_pull_none>;
4377		};
4378		/omit-if-no-ref/
4379		spi3m2_csn1: spi3m2-csn1 {
4380			rockchip,pins =
4381				/* spi3m2_csn1 */
4382				<4 RK_PB3 10 &pcfg_pull_none>;
4383		};
4384	};
4385
4386	spi4 {
4387		/omit-if-no-ref/
4388		spi4m0_pins: spi4m0-pins {
4389			rockchip,pins =
4390				/* spi4_clk_m0 */
4391				<4 RK_PC7 12 &pcfg_pull_none>,
4392				/* spi4_miso_m0 */
4393				<4 RK_PC6 12 &pcfg_pull_none>,
4394				/* spi4_mosi_m0 */
4395				<4 RK_PC5 12 &pcfg_pull_none>;
4396		};
4397
4398		/omit-if-no-ref/
4399		spi4m0_csn0: spi4m0-csn0 {
4400			rockchip,pins =
4401				/* spi4m0_csn0 */
4402				<4 RK_PC4 12 &pcfg_pull_none>;
4403		};
4404		/omit-if-no-ref/
4405		spi4m0_csn1: spi4m0-csn1 {
4406			rockchip,pins =
4407				/* spi4m0_csn1 */
4408				<4 RK_PC0 12 &pcfg_pull_none>;
4409		};
4410
4411		/omit-if-no-ref/
4412		spi4m1_pins: spi4m1-pins {
4413			rockchip,pins =
4414				/* spi4_clk_m1 */
4415				<3 RK_PD1 10 &pcfg_pull_none>,
4416				/* spi4_miso_m1 */
4417				<3 RK_PC2 10 &pcfg_pull_none>,
4418				/* spi4_mosi_m1 */
4419				<3 RK_PC3 10 &pcfg_pull_none>;
4420		};
4421
4422		/omit-if-no-ref/
4423		spi4m1_csn0: spi4m1-csn0 {
4424			rockchip,pins =
4425				/* spi4m1_csn0 */
4426				<3 RK_PB1 10 &pcfg_pull_none>;
4427		};
4428		/omit-if-no-ref/
4429		spi4m1_csn1: spi4m1-csn1 {
4430			rockchip,pins =
4431				/* spi4m1_csn1 */
4432				<3 RK_PD2 10 &pcfg_pull_none>;
4433		};
4434
4435		/omit-if-no-ref/
4436		spi4m2_pins: spi4m2-pins {
4437			rockchip,pins =
4438				/* spi4_clk_m2 */
4439				<4 RK_PB0 9 &pcfg_pull_none>,
4440				/* spi4_miso_m2 */
4441				<4 RK_PB2 9 &pcfg_pull_none>,
4442				/* spi4_mosi_m2 */
4443				<4 RK_PB1 9 &pcfg_pull_none>;
4444		};
4445
4446		/omit-if-no-ref/
4447		spi4m2_csn0: spi4m2-csn0 {
4448			rockchip,pins =
4449				/* spi4m2_csn0 */
4450				<4 RK_PB3 9 &pcfg_pull_none>;
4451		};
4452		/omit-if-no-ref/
4453		spi4m2_csn1: spi4m2-csn1 {
4454			rockchip,pins =
4455				/* spi4m2_csn1 */
4456				<4 RK_PA5 9 &pcfg_pull_none>;
4457		};
4458
4459		/omit-if-no-ref/
4460		spi4m3_pins: spi4m3-pins {
4461			rockchip,pins =
4462				/* spi4_clk_m3 */
4463				<2 RK_PB3 10 &pcfg_pull_none>,
4464				/* spi4_miso_m3 */
4465				<2 RK_PB5 10 &pcfg_pull_none>,
4466				/* spi4_mosi_m3 */
4467				<2 RK_PB4 10 &pcfg_pull_none>;
4468		};
4469
4470		/omit-if-no-ref/
4471		spi4m3_csn0: spi4m3-csn0 {
4472			rockchip,pins =
4473				/* spi4m3_csn0 */
4474				<2 RK_PB2 10 &pcfg_pull_none>;
4475		};
4476		/omit-if-no-ref/
4477		spi4m3_csn1: spi4m3-csn1 {
4478			rockchip,pins =
4479				/* spi4m3_csn1 */
4480				<2 RK_PA6 10 &pcfg_pull_none>;
4481		};
4482	};
4483
4484	test_clk {
4485		/omit-if-no-ref/
4486		test_clk_pins: test_clk-pins {
4487			rockchip,pins =
4488				/* test_clk_out */
4489				<2 RK_PA5 5 &pcfg_pull_none>;
4490		};
4491	};
4492
4493	tsadc {
4494		/omit-if-no-ref/
4495		tsadcm0_pins: tsadcm0-pins {
4496			rockchip,pins =
4497				/* tsadc_ctrl_m0 */
4498				<0 RK_PA1 9 &pcfg_pull_none>;
4499		};
4500
4501		/omit-if-no-ref/
4502		tsadcm1_pins: tsadcm1-pins {
4503			rockchip,pins =
4504				/* tsadc_ctrl_m1 */
4505				<0 RK_PA3 10 &pcfg_pull_none>;
4506		};
4507	};
4508
4509	tsadc_ctrl {
4510		/omit-if-no-ref/
4511		tsadc_ctrl_pins: tsadc_ctrl-pins {
4512			rockchip,pins =
4513				/* tsadc_ctrl_org */
4514				<0 RK_PA1 10 &pcfg_pull_none>;
4515		};
4516	};
4517
4518	uart0 {
4519		/omit-if-no-ref/
4520		uart0m0_xfer: uart0m0-xfer {
4521			rockchip,pins =
4522				/* uart0_rx_m0 */
4523				<0 RK_PD5 9 &pcfg_pull_up>,
4524				/* uart0_tx_m0 */
4525				<0 RK_PD4 9 &pcfg_pull_up>;
4526		};
4527
4528		/omit-if-no-ref/
4529		uart0m1_xfer: uart0m1-xfer {
4530			rockchip,pins =
4531				/* uart0_rx_m1 */
4532				<2 RK_PA0 9 &pcfg_pull_up>,
4533				/* uart0_tx_m1 */
4534				<2 RK_PA1 9 &pcfg_pull_up>;
4535		};
4536	};
4537
4538	uart1 {
4539		/omit-if-no-ref/
4540		uart1m0_xfer: uart1m0-xfer {
4541			rockchip,pins =
4542				/* uart1_rx_m0 */
4543				<0 RK_PC0 10 &pcfg_pull_up>,
4544				/* uart1_tx_m0 */
4545				<0 RK_PB7 10 &pcfg_pull_up>;
4546		};
4547
4548		/omit-if-no-ref/
4549		uart1m0_ctsn: uart1m0-ctsn {
4550			rockchip,pins =
4551				/* uart1m0_ctsn */
4552				<0 RK_PD2 13 &pcfg_pull_none>;
4553		};
4554		/omit-if-no-ref/
4555		uart1m0_rtsn: uart1m0-rtsn {
4556			rockchip,pins =
4557				/* uart1m0_rtsn */
4558				<0 RK_PD3 13 &pcfg_pull_none>;
4559		};
4560
4561		/omit-if-no-ref/
4562		uart1m1_xfer: uart1m1-xfer {
4563			rockchip,pins =
4564				/* uart1_rx_m1 */
4565				<2 RK_PB1 9 &pcfg_pull_up>,
4566				/* uart1_tx_m1 */
4567				<2 RK_PB0 9 &pcfg_pull_up>;
4568		};
4569
4570		/omit-if-no-ref/
4571		uart1m1_ctsn: uart1m1-ctsn {
4572			rockchip,pins =
4573				/* uart1m1_ctsn */
4574				<2 RK_PB2 9 &pcfg_pull_none>;
4575		};
4576		/omit-if-no-ref/
4577		uart1m1_rtsn: uart1m1-rtsn {
4578			rockchip,pins =
4579				/* uart1m1_rtsn */
4580				<2 RK_PB3 9 &pcfg_pull_none>;
4581		};
4582
4583		/omit-if-no-ref/
4584		uart1m2_xfer: uart1m2-xfer {
4585			rockchip,pins =
4586				/* uart1_rx_m2 */
4587				<3 RK_PA6 9 &pcfg_pull_up>,
4588				/* uart1_tx_m2 */
4589				<3 RK_PA7 9 &pcfg_pull_up>;
4590		};
4591
4592		/omit-if-no-ref/
4593		uart1m2_ctsn: uart1m2-ctsn {
4594			rockchip,pins =
4595				/* uart1m2_ctsn */
4596				<3 RK_PA4 9 &pcfg_pull_none>;
4597		};
4598		/omit-if-no-ref/
4599		uart1m2_rtsn: uart1m2-rtsn {
4600			rockchip,pins =
4601				/* uart1m2_rtsn */
4602				<3 RK_PA5 9 &pcfg_pull_none>;
4603		};
4604	};
4605
4606	uart2 {
4607		/omit-if-no-ref/
4608		uart2m0_xfer: uart2m0-xfer {
4609			rockchip,pins =
4610				/* uart2_rx_m0 */
4611				<1 RK_PC7 9 &pcfg_pull_up>,
4612				/* uart2_tx_m0 */
4613				<1 RK_PC6 9 &pcfg_pull_up>;
4614		};
4615
4616		/omit-if-no-ref/
4617		uart2m0_ctsn: uart2m0-ctsn {
4618			rockchip,pins =
4619				/* uart2m0_ctsn */
4620				<1 RK_PC5 10 &pcfg_pull_none>;
4621		};
4622		/omit-if-no-ref/
4623		uart2m0_rtsn: uart2m0-rtsn {
4624			rockchip,pins =
4625				/* uart2m0_rtsn */
4626				<1 RK_PC4 10 &pcfg_pull_none>;
4627		};
4628
4629		/omit-if-no-ref/
4630		uart2m1_xfer: uart2m1-xfer {
4631			rockchip,pins =
4632				/* uart2_rx_m1 */
4633				<4 RK_PB4 10 &pcfg_pull_up>,
4634				/* uart2_tx_m1 */
4635				<4 RK_PB5 10 &pcfg_pull_up>;
4636		};
4637
4638		/omit-if-no-ref/
4639		uart2m1_ctsn: uart2m1-ctsn {
4640			rockchip,pins =
4641				/* uart2m1_ctsn */
4642				<4 RK_PB1 12 &pcfg_pull_none>;
4643		};
4644		/omit-if-no-ref/
4645		uart2m1_rtsn: uart2m1-rtsn {
4646			rockchip,pins =
4647				/* uart2m1_rtsn */
4648				<4 RK_PB0 12 &pcfg_pull_none>;
4649		};
4650
4651		/omit-if-no-ref/
4652		uart2m2_xfer: uart2m2-xfer {
4653			rockchip,pins =
4654				/* uart2_rx_m2 */
4655				<3 RK_PB7 9 &pcfg_pull_up>,
4656				/* uart2_tx_m2 */
4657				<3 RK_PC0 9 &pcfg_pull_up>;
4658		};
4659
4660		/omit-if-no-ref/
4661		uart2m2_ctsn: uart2m2-ctsn {
4662			rockchip,pins =
4663				/* uart2m2_ctsn */
4664				<3 RK_PD3 9 &pcfg_pull_none>;
4665		};
4666		/omit-if-no-ref/
4667		uart2m2_rtsn: uart2m2-rtsn {
4668			rockchip,pins =
4669				/* uart2m2_rtsn */
4670				<3 RK_PD2 9 &pcfg_pull_none>;
4671		};
4672	};
4673
4674	uart3 {
4675		/omit-if-no-ref/
4676		uart3m0_xfer: uart3m0-xfer {
4677			rockchip,pins =
4678				/* uart3_rx_m0 */
4679				<3 RK_PA1 9 &pcfg_pull_up>,
4680				/* uart3_tx_m0 */
4681				<3 RK_PA0 9 &pcfg_pull_up>;
4682		};
4683
4684		/omit-if-no-ref/
4685		uart3m0_ctsn: uart3m0-ctsn {
4686			rockchip,pins =
4687				/* uart3m0_ctsn */
4688				<3 RK_PA2 9 &pcfg_pull_none>;
4689		};
4690		/omit-if-no-ref/
4691		uart3m0_rtsn: uart3m0-rtsn {
4692			rockchip,pins =
4693				/* uart3m0_rtsn */
4694				<3 RK_PA3 9 &pcfg_pull_none>;
4695		};
4696
4697		/omit-if-no-ref/
4698		uart3m1_xfer: uart3m1-xfer {
4699			rockchip,pins =
4700				/* uart3_rx_m1 */
4701				<4 RK_PA1 9 &pcfg_pull_up>,
4702				/* uart3_tx_m1 */
4703				<4 RK_PA0 9 &pcfg_pull_up>;
4704		};
4705
4706		/omit-if-no-ref/
4707		uart3m1_ctsn: uart3m1-ctsn {
4708			rockchip,pins =
4709				/* uart3m1_ctsn */
4710				<3 RK_PB7 10 &pcfg_pull_none>;
4711		};
4712		/omit-if-no-ref/
4713		uart3m1_rtsn: uart3m1-rtsn {
4714			rockchip,pins =
4715				/* uart3m1_rtsn */
4716				<3 RK_PC0 10 &pcfg_pull_none>;
4717		};
4718
4719		/omit-if-no-ref/
4720		uart3m2_xfer: uart3m2-xfer {
4721			rockchip,pins =
4722				/* uart3_rx_m2 */
4723				<1 RK_PC1 9 &pcfg_pull_up>,
4724				/* uart3_tx_m2 */
4725				<1 RK_PC0 9 &pcfg_pull_up>;
4726		};
4727
4728		/omit-if-no-ref/
4729		uart3m2_ctsn: uart3m2-ctsn {
4730			rockchip,pins =
4731				/* uart3m2_ctsn */
4732				<1 RK_PB6 9 &pcfg_pull_none>;
4733		};
4734		/omit-if-no-ref/
4735		uart3m2_rtsn: uart3m2-rtsn {
4736			rockchip,pins =
4737				/* uart3m2_rtsn */
4738				<1 RK_PB7 9 &pcfg_pull_none>;
4739		};
4740	};
4741
4742	uart4 {
4743		/omit-if-no-ref/
4744		uart4m0_xfer: uart4m0-xfer {
4745			rockchip,pins =
4746				/* uart4_rx_m0 */
4747				<2 RK_PD1 9 &pcfg_pull_up>,
4748				/* uart4_tx_m0 */
4749				<2 RK_PD0 9 &pcfg_pull_up>;
4750		};
4751
4752		/omit-if-no-ref/
4753		uart4m0_ctsn: uart4m0-ctsn {
4754			rockchip,pins =
4755				/* uart4m0_ctsn */
4756				<2 RK_PC6 9 &pcfg_pull_none>;
4757		};
4758		/omit-if-no-ref/
4759		uart4m0_rtsn: uart4m0-rtsn {
4760			rockchip,pins =
4761				/* uart4m0_rtsn */
4762				<2 RK_PC7 9 &pcfg_pull_none>;
4763		};
4764
4765		/omit-if-no-ref/
4766		uart4m1_xfer: uart4m1-xfer {
4767			rockchip,pins =
4768				/* uart4_rx_m1 */
4769				<1 RK_PC5 9 &pcfg_pull_up>,
4770				/* uart4_tx_m1 */
4771				<1 RK_PC4 9 &pcfg_pull_up>;
4772		};
4773
4774		/omit-if-no-ref/
4775		uart4m1_ctsn: uart4m1-ctsn {
4776			rockchip,pins =
4777				/* uart4m1_ctsn */
4778				<1 RK_PC3 9 &pcfg_pull_none>;
4779		};
4780		/omit-if-no-ref/
4781		uart4m1_rtsn: uart4m1-rtsn {
4782			rockchip,pins =
4783				/* uart4m1_rtsn */
4784				<1 RK_PC2 9 &pcfg_pull_none>;
4785		};
4786
4787		/omit-if-no-ref/
4788		uart4m2_xfer: uart4m2-xfer {
4789			rockchip,pins =
4790				/* uart4_rx_m2 */
4791				<0 RK_PB5 10 &pcfg_pull_up>,
4792				/* uart4_tx_m2 */
4793				<0 RK_PB4 10 &pcfg_pull_up>;
4794		};
4795	};
4796
4797	uart5 {
4798		/omit-if-no-ref/
4799		uart5m0_xfer: uart5m0-xfer {
4800			rockchip,pins =
4801				/* uart5_rx_m0 */
4802				<3 RK_PD4 9 &pcfg_pull_up>,
4803				/* uart5_tx_m0 */
4804				<3 RK_PD5 9 &pcfg_pull_up>;
4805		};
4806
4807		/omit-if-no-ref/
4808		uart5m0_ctsn: uart5m0-ctsn {
4809			rockchip,pins =
4810				/* uart5m0_ctsn */
4811				<3 RK_PD6 9 &pcfg_pull_none>;
4812		};
4813		/omit-if-no-ref/
4814		uart5m0_rtsn: uart5m0-rtsn {
4815			rockchip,pins =
4816				/* uart5m0_rtsn */
4817				<3 RK_PD7 9 &pcfg_pull_none>;
4818		};
4819
4820		/omit-if-no-ref/
4821		uart5m1_xfer: uart5m1-xfer {
4822			rockchip,pins =
4823				/* uart5_rx_m1 */
4824				<4 RK_PB1 10 &pcfg_pull_up>,
4825				/* uart5_tx_m1 */
4826				<4 RK_PB0 10 &pcfg_pull_up>;
4827		};
4828
4829		/omit-if-no-ref/
4830		uart5m1_ctsn: uart5m1-ctsn {
4831			rockchip,pins =
4832				/* uart5m1_ctsn */
4833				<4 RK_PA5 10 &pcfg_pull_none>;
4834		};
4835		/omit-if-no-ref/
4836		uart5m1_rtsn: uart5m1-rtsn {
4837			rockchip,pins =
4838				/* uart5m1_rtsn */
4839				<4 RK_PA3 10 &pcfg_pull_none>;
4840		};
4841
4842		/omit-if-no-ref/
4843		uart5m2_xfer: uart5m2-xfer {
4844			rockchip,pins =
4845				/* uart5_rx_m2 */
4846				<2 RK_PA4 9 &pcfg_pull_up>,
4847				/* uart5_tx_m2 */
4848				<2 RK_PA5 9 &pcfg_pull_up>;
4849		};
4850
4851		/omit-if-no-ref/
4852		uart5m2_ctsn: uart5m2-ctsn {
4853			rockchip,pins =
4854				/* uart5m2_ctsn */
4855				<2 RK_PA3 10 &pcfg_pull_none>;
4856		};
4857		/omit-if-no-ref/
4858		uart5m2_rtsn: uart5m2-rtsn {
4859			rockchip,pins =
4860				/* uart5m2_rtsn */
4861				<2 RK_PA2 10 &pcfg_pull_none>;
4862		};
4863	};
4864
4865	uart6 {
4866		/omit-if-no-ref/
4867		uart6m0_xfer: uart6m0-xfer {
4868			rockchip,pins =
4869				/* uart6_rx_m0 */
4870				<4 RK_PA6 10 &pcfg_pull_up>,
4871				/* uart6_tx_m0 */
4872				<4 RK_PA4 10 &pcfg_pull_up>;
4873		};
4874
4875		/omit-if-no-ref/
4876		uart6m0_ctsn: uart6m0-ctsn {
4877			rockchip,pins =
4878				/* uart6m0_ctsn */
4879				<4 RK_PB1 11 &pcfg_pull_none>;
4880		};
4881		/omit-if-no-ref/
4882		uart6m0_rtsn: uart6m0-rtsn {
4883			rockchip,pins =
4884				/* uart6m0_rtsn */
4885				<4 RK_PB0 11 &pcfg_pull_none>;
4886		};
4887
4888		/omit-if-no-ref/
4889		uart6m1_xfer: uart6m1-xfer {
4890			rockchip,pins =
4891				/* uart6_rx_m1 */
4892				<2 RK_PD3 9 &pcfg_pull_up>,
4893				/* uart6_tx_m1 */
4894				<2 RK_PD2 9 &pcfg_pull_up>;
4895		};
4896
4897		/omit-if-no-ref/
4898		uart6m1_ctsn: uart6m1-ctsn {
4899			rockchip,pins =
4900				/* uart6m1_ctsn */
4901				<2 RK_PD5 9 &pcfg_pull_none>;
4902		};
4903		/omit-if-no-ref/
4904		uart6m1_rtsn: uart6m1-rtsn {
4905			rockchip,pins =
4906				/* uart6m1_rtsn */
4907				<2 RK_PD4 9 &pcfg_pull_none>;
4908		};
4909
4910		/omit-if-no-ref/
4911		uart6m2_xfer: uart6m2-xfer {
4912			rockchip,pins =
4913				/* uart6_rx_m2 */
4914				<1 RK_PB3 9 &pcfg_pull_up>,
4915				/* uart6_tx_m2 */
4916				<1 RK_PB0 9 &pcfg_pull_up>;
4917		};
4918
4919		/omit-if-no-ref/
4920		uart6m2_ctsn: uart6m2-ctsn {
4921			rockchip,pins =
4922				/* uart6m2_ctsn */
4923				<1 RK_PA3 10 &pcfg_pull_none>;
4924		};
4925		/omit-if-no-ref/
4926		uart6m2_rtsn: uart6m2-rtsn {
4927			rockchip,pins =
4928				/* uart6m2_rtsn */
4929				<1 RK_PA2 10 &pcfg_pull_none>;
4930		};
4931
4932		/omit-if-no-ref/
4933		uart6m3_xfer: uart6m3-xfer {
4934			rockchip,pins =
4935				/* uart6_rx_m3 */
4936				<4 RK_PC5 13 &pcfg_pull_up>,
4937				/* uart6_tx_m3 */
4938				<4 RK_PC4 13 &pcfg_pull_up>;
4939		};
4940	};
4941
4942	uart7 {
4943		/omit-if-no-ref/
4944		uart7m0_xfer: uart7m0-xfer {
4945			rockchip,pins =
4946				/* uart7_rx_m0 */
4947				<2 RK_PB7 9 &pcfg_pull_up>,
4948				/* uart7_tx_m0 */
4949				<2 RK_PB6 9 &pcfg_pull_up>;
4950		};
4951
4952		/omit-if-no-ref/
4953		uart7m0_ctsn: uart7m0-ctsn {
4954			rockchip,pins =
4955				/* uart7m0_ctsn */
4956				<2 RK_PB4 9 &pcfg_pull_none>;
4957		};
4958		/omit-if-no-ref/
4959		uart7m0_rtsn: uart7m0-rtsn {
4960			rockchip,pins =
4961				/* uart7m0_rtsn */
4962				<2 RK_PB5 9 &pcfg_pull_none>;
4963		};
4964
4965		/omit-if-no-ref/
4966		uart7m1_xfer: uart7m1-xfer {
4967			rockchip,pins =
4968				/* uart7_rx_m1 */
4969				<1 RK_PA3 9 &pcfg_pull_up>,
4970				/* uart7_tx_m1 */
4971				<1 RK_PA2 9 &pcfg_pull_up>;
4972		};
4973
4974		/omit-if-no-ref/
4975		uart7m1_ctsn: uart7m1-ctsn {
4976			rockchip,pins =
4977				/* uart7m1_ctsn */
4978				<1 RK_PA1 9 &pcfg_pull_none>;
4979		};
4980		/omit-if-no-ref/
4981		uart7m1_rtsn: uart7m1-rtsn {
4982			rockchip,pins =
4983				/* uart7m1_rtsn */
4984				<1 RK_PA0 9 &pcfg_pull_none>;
4985		};
4986
4987		/omit-if-no-ref/
4988		uart7m2_xfer: uart7m2-xfer {
4989			rockchip,pins =
4990				/* uart7_rx_m2 */
4991				<2 RK_PA0 10 &pcfg_pull_up>,
4992				/* uart7_tx_m2 */
4993				<2 RK_PA1 10 &pcfg_pull_up>;
4994		};
4995	};
4996
4997	uart8 {
4998		/omit-if-no-ref/
4999		uart8m0_xfer: uart8m0-xfer {
5000			rockchip,pins =
5001				/* uart8_rx_m0 */
5002				<3 RK_PC5 9 &pcfg_pull_up>,
5003				/* uart8_tx_m0 */
5004				<3 RK_PC6 9 &pcfg_pull_up>;
5005		};
5006
5007		/omit-if-no-ref/
5008		uart8m0_ctsn: uart8m0-ctsn {
5009			rockchip,pins =
5010				/* uart8m0_ctsn */
5011				<3 RK_PD0 9 &pcfg_pull_none>;
5012		};
5013		/omit-if-no-ref/
5014		uart8m0_rtsn: uart8m0-rtsn {
5015			rockchip,pins =
5016				/* uart8m0_rtsn */
5017				<3 RK_PC7 9 &pcfg_pull_none>;
5018		};
5019
5020		/omit-if-no-ref/
5021		uart8m1_xfer: uart8m1-xfer {
5022			rockchip,pins =
5023				/* uart8_rx_m1 */
5024				<2 RK_PA7 9 &pcfg_pull_up>,
5025				/* uart8_tx_m1 */
5026				<2 RK_PA6 9 &pcfg_pull_up>;
5027		};
5028
5029		/omit-if-no-ref/
5030		uart8m1_ctsn: uart8m1-ctsn {
5031			rockchip,pins =
5032				/* uart8m1_ctsn */
5033				<2 RK_PB7 10 &pcfg_pull_none>;
5034		};
5035		/omit-if-no-ref/
5036		uart8m1_rtsn: uart8m1-rtsn {
5037			rockchip,pins =
5038				/* uart8m1_rtsn */
5039				<2 RK_PB6 10 &pcfg_pull_none>;
5040		};
5041
5042		/omit-if-no-ref/
5043		uart8m2_xfer: uart8m2-xfer {
5044			rockchip,pins =
5045				/* uart8_rx_m2 */
5046				<0 RK_PC2 10 &pcfg_pull_up>,
5047				/* uart8_tx_m2 */
5048				<0 RK_PC1 10 &pcfg_pull_up>;
5049		};
5050	};
5051
5052	uart9 {
5053		/omit-if-no-ref/
5054		uart9m0_xfer: uart9m0-xfer {
5055			rockchip,pins =
5056				/* uart9_rx_m0 */
5057				<2 RK_PC0 9 &pcfg_pull_up>,
5058				/* uart9_tx_m0 */
5059				<2 RK_PC1 9 &pcfg_pull_up>;
5060		};
5061
5062		/omit-if-no-ref/
5063		uart9m0_ctsn: uart9m0-ctsn {
5064			rockchip,pins =
5065				/* uart9m0_ctsn */
5066				<2 RK_PD7 9 &pcfg_pull_none>;
5067		};
5068		/omit-if-no-ref/
5069		uart9m0_rtsn: uart9m0-rtsn {
5070			rockchip,pins =
5071				/* uart9m0_rtsn */
5072				<2 RK_PD6 9 &pcfg_pull_none>;
5073		};
5074
5075		/omit-if-no-ref/
5076		uart9m1_xfer: uart9m1-xfer {
5077			rockchip,pins =
5078				/* uart9_rx_m1 */
5079				<3 RK_PB2 9 &pcfg_pull_up>,
5080				/* uart9_tx_m1 */
5081				<3 RK_PB3 9 &pcfg_pull_up>;
5082		};
5083
5084		/omit-if-no-ref/
5085		uart9m1_ctsn: uart9m1-ctsn {
5086			rockchip,pins =
5087				/* uart9m1_ctsn */
5088				<3 RK_PB5 9 &pcfg_pull_none>;
5089		};
5090		/omit-if-no-ref/
5091		uart9m1_rtsn: uart9m1-rtsn {
5092			rockchip,pins =
5093				/* uart9m1_rtsn */
5094				<3 RK_PB4 9 &pcfg_pull_none>;
5095		};
5096
5097		/omit-if-no-ref/
5098		uart9m2_xfer: uart9m2-xfer {
5099			rockchip,pins =
5100				/* uart9_rx_m2 */
5101				<4 RK_PC3 13 &pcfg_pull_up>,
5102				/* uart9_tx_m2 */
5103				<4 RK_PC2 13 &pcfg_pull_up>;
5104		};
5105	};
5106
5107	uart10 {
5108		/omit-if-no-ref/
5109		uart10m0_xfer: uart10m0-xfer {
5110			rockchip,pins =
5111				/* uart10_rx_m0 */
5112				<3 RK_PB0 9 &pcfg_pull_up>,
5113				/* uart10_tx_m0 */
5114				<3 RK_PB1 9 &pcfg_pull_up>;
5115		};
5116
5117		/omit-if-no-ref/
5118		uart10m0_ctsn: uart10m0-ctsn {
5119			rockchip,pins =
5120				/* uart10m0_ctsn */
5121				<3 RK_PA6 10 &pcfg_pull_none>;
5122		};
5123		/omit-if-no-ref/
5124		uart10m0_rtsn: uart10m0-rtsn {
5125			rockchip,pins =
5126				/* uart10m0_rtsn */
5127				<3 RK_PA7 10 &pcfg_pull_none>;
5128		};
5129
5130		/omit-if-no-ref/
5131		uart10m1_xfer: uart10m1-xfer {
5132			rockchip,pins =
5133				/* uart10_rx_m1 */
5134				<1 RK_PD1 9 &pcfg_pull_up>,
5135				/* uart10_tx_m1 */
5136				<1 RK_PD0 9 &pcfg_pull_up>;
5137		};
5138
5139		/omit-if-no-ref/
5140		uart10m1_ctsn: uart10m1-ctsn {
5141			rockchip,pins =
5142				/* uart10m1_ctsn */
5143				<1 RK_PD5 9 &pcfg_pull_none>;
5144		};
5145		/omit-if-no-ref/
5146		uart10m1_rtsn: uart10m1-rtsn {
5147			rockchip,pins =
5148				/* uart10m1_rtsn */
5149				<1 RK_PD4 9 &pcfg_pull_none>;
5150		};
5151
5152		/omit-if-no-ref/
5153		uart10m2_xfer: uart10m2-xfer {
5154			rockchip,pins =
5155				/* uart10_rx_m2 */
5156				<0 RK_PC5 10 &pcfg_pull_up>,
5157				/* uart10_tx_m2 */
5158				<0 RK_PC4 10 &pcfg_pull_up>;
5159		};
5160	};
5161
5162	uart11 {
5163		/omit-if-no-ref/
5164		uart11m0_xfer: uart11m0-xfer {
5165			rockchip,pins =
5166				/* uart11_rx_m0 */
5167				<3 RK_PC1 9 &pcfg_pull_up>,
5168				/* uart11_tx_m0 */
5169				<3 RK_PC4 9 &pcfg_pull_up>;
5170		};
5171
5172		/omit-if-no-ref/
5173		uart11m0_ctsn: uart11m0-ctsn {
5174			rockchip,pins =
5175				/* uart11m0_ctsn */
5176				<3 RK_PC3 9 &pcfg_pull_none>;
5177		};
5178		/omit-if-no-ref/
5179		uart11m0_rtsn: uart11m0-rtsn {
5180			rockchip,pins =
5181				/* uart11m0_rtsn */
5182				<3 RK_PC2 9 &pcfg_pull_none>;
5183		};
5184
5185		/omit-if-no-ref/
5186		uart11m1_xfer: uart11m1-xfer {
5187			rockchip,pins =
5188				/* uart11_rx_m1 */
5189				<2 RK_PC5 9 &pcfg_pull_up>,
5190				/* uart11_tx_m1 */
5191				<2 RK_PC4 9 &pcfg_pull_up>;
5192		};
5193
5194		/omit-if-no-ref/
5195		uart11m1_ctsn: uart11m1-ctsn {
5196			rockchip,pins =
5197				/* uart11m1_ctsn */
5198				<2 RK_PC2 9 &pcfg_pull_none>;
5199		};
5200		/omit-if-no-ref/
5201		uart11m1_rtsn: uart11m1-rtsn {
5202			rockchip,pins =
5203				/* uart11m1_rtsn */
5204				<2 RK_PC3 9 &pcfg_pull_none>;
5205		};
5206
5207		/omit-if-no-ref/
5208		uart11m2_xfer: uart11m2-xfer {
5209			rockchip,pins =
5210				/* uart11_rx_m2 */
5211				<4 RK_PC1 13 &pcfg_pull_up>,
5212				/* uart11_tx_m2 */
5213				<4 RK_PC0 13 &pcfg_pull_up>;
5214		};
5215	};
5216
5217	ufs {
5218		/omit-if-no-ref/
5219		ufs_refclk: ufs-refclk {
5220			rockchip,pins =
5221				/* ufs_refclk */
5222				<4 RK_PD1 1 &pcfg_pull_none>;
5223		};
5224
5225		/omit-if-no-ref/
5226		ufs_rst: ufs-rst {
5227			rockchip,pins =
5228				/* ufs_rstn */
5229				<4 RK_PD0 1 &pcfg_pull_none>;
5230		};
5231	};
5232
5233	ufs_testdata0 {
5234		/omit-if-no-ref/
5235		ufs_testdata0_test: ufs_testdata0-test {
5236			rockchip,pins =
5237				/* ufs_testdata0_out */
5238				<4 RK_PC4 4 &pcfg_pull_none>;
5239		};
5240	};
5241
5242	ufs_testdata1 {
5243		/omit-if-no-ref/
5244		ufs_testdata1_test: ufs_testdata1-test {
5245			rockchip,pins =
5246				/* ufs_testdata1_out */
5247				<4 RK_PC5 4 &pcfg_pull_none>;
5248		};
5249	};
5250
5251	ufs_testdata2 {
5252		/omit-if-no-ref/
5253		ufs_testdata2_test: ufs_testdata2-test {
5254			rockchip,pins =
5255				/* ufs_testdata2_out */
5256				<4 RK_PC6 4 &pcfg_pull_none>;
5257		};
5258	};
5259
5260	ufs_testdata3 {
5261		/omit-if-no-ref/
5262		ufs_testdata3_test: ufs_testdata3-test {
5263			rockchip,pins =
5264				/* ufs_testdata3_out */
5265				<4 RK_PC7 4 &pcfg_pull_none>;
5266		};
5267	};
5268
5269	vi_cif {
5270		/omit-if-no-ref/
5271		vi_cif_pins: vi_cif-pins {
5272			rockchip,pins =
5273				/* vi_cif_clki */
5274				<3 RK_PA3 1 &pcfg_pull_none>,
5275				/* vi_cif_clko */
5276				<3 RK_PA2 1 &pcfg_pull_none>,
5277				/* vi_cif_d0 */
5278				<2 RK_PC5 1 &pcfg_pull_none>,
5279				/* vi_cif_d1 */
5280				<2 RK_PC4 1 &pcfg_pull_none>,
5281				/* vi_cif_d2 */
5282				<2 RK_PC3 1 &pcfg_pull_none>,
5283				/* vi_cif_d3 */
5284				<2 RK_PC2 1 &pcfg_pull_none>,
5285				/* vi_cif_d4 */
5286				<2 RK_PC1 1 &pcfg_pull_none>,
5287				/* vi_cif_d5 */
5288				<2 RK_PC0 1 &pcfg_pull_none>,
5289				/* vi_cif_d6 */
5290				<2 RK_PB7 1 &pcfg_pull_none>,
5291				/* vi_cif_d7 */
5292				<2 RK_PB6 1 &pcfg_pull_none>,
5293				/* vi_cif_d8 */
5294				<2 RK_PB5 1 &pcfg_pull_none>,
5295				/* vi_cif_d9 */
5296				<2 RK_PB4 1 &pcfg_pull_none>,
5297				/* vi_cif_d10 */
5298				<2 RK_PB3 1 &pcfg_pull_none>,
5299				/* vi_cif_d11 */
5300				<2 RK_PB2 1 &pcfg_pull_none>,
5301				/* vi_cif_d12 */
5302				<2 RK_PB1 1 &pcfg_pull_none>,
5303				/* vi_cif_d13 */
5304				<2 RK_PB0 1 &pcfg_pull_none>,
5305				/* vi_cif_d14 */
5306				<2 RK_PA7 1 &pcfg_pull_none>,
5307				/* vi_cif_d15 */
5308				<2 RK_PA6 1 &pcfg_pull_none>,
5309				/* vi_cif_href */
5310				<3 RK_PA0 1 &pcfg_pull_none>,
5311				/* vi_cif_vsync */
5312				<3 RK_PA1 1 &pcfg_pull_none>;
5313		};
5314	};
5315
5316	vo_lcdc {
5317		/omit-if-no-ref/
5318		vo_lcdc_pins: vo_lcdc-pins {
5319			rockchip,pins =
5320				/* vo_lcdc_clk */
5321				<3 RK_PD7 1 &pcfg_pull_none>,
5322				/* vo_lcdc_d0 */
5323				<3 RK_PD3 1 &pcfg_pull_none>,
5324				/* vo_lcdc_d1 */
5325				<3 RK_PD2 1 &pcfg_pull_none>,
5326				/* vo_lcdc_d2 */
5327				<3 RK_PD1 1 &pcfg_pull_none>,
5328				/* vo_lcdc_d3 */
5329				<3 RK_PD0 1 &pcfg_pull_none>,
5330				/* vo_lcdc_d4 */
5331				<3 RK_PC7 1 &pcfg_pull_none>,
5332				/* vo_lcdc_d5 */
5333				<3 RK_PC6 1 &pcfg_pull_none>,
5334				/* vo_lcdc_d6 */
5335				<3 RK_PC5 1 &pcfg_pull_none>,
5336				/* vo_lcdc_d7 */
5337				<3 RK_PC4 1 &pcfg_pull_none>,
5338				/* vo_lcdc_d8 */
5339				<3 RK_PC3 1 &pcfg_pull_none>,
5340				/* vo_lcdc_d9 */
5341				<3 RK_PC2 1 &pcfg_pull_none>,
5342				/* vo_lcdc_d10 */
5343				<3 RK_PC1 1 &pcfg_pull_none>,
5344				/* vo_lcdc_d11 */
5345				<3 RK_PC0 1 &pcfg_pull_none>,
5346				/* vo_lcdc_d12 */
5347				<3 RK_PB7 1 &pcfg_pull_none>,
5348				/* vo_lcdc_d13 */
5349				<3 RK_PB6 1 &pcfg_pull_none>,
5350				/* vo_lcdc_d14 */
5351				<3 RK_PB5 1 &pcfg_pull_none>,
5352				/* vo_lcdc_d15 */
5353				<3 RK_PB4 1 &pcfg_pull_none>,
5354				/* vo_lcdc_d16 */
5355				<3 RK_PB3 1 &pcfg_pull_none>,
5356				/* vo_lcdc_d17 */
5357				<3 RK_PB2 1 &pcfg_pull_none>,
5358				/* vo_lcdc_d18 */
5359				<3 RK_PB1 1 &pcfg_pull_none>,
5360				/* vo_lcdc_d19 */
5361				<3 RK_PB0 1 &pcfg_pull_none>,
5362				/* vo_lcdc_d20 */
5363				<3 RK_PA7 1 &pcfg_pull_none>,
5364				/* vo_lcdc_d21 */
5365				<3 RK_PA6 1 &pcfg_pull_none>,
5366				/* vo_lcdc_d22 */
5367				<3 RK_PA5 1 &pcfg_pull_none>,
5368				/* vo_lcdc_d23 */
5369				<3 RK_PA4 1 &pcfg_pull_none>,
5370				/* vo_lcdc_den */
5371				<3 RK_PD4 1 &pcfg_pull_none>,
5372				/* vo_lcdc_hsync */
5373				<3 RK_PD5 1 &pcfg_pull_none>,
5374				/* vo_lcdc_vsync */
5375				<3 RK_PD6 1 &pcfg_pull_none>;
5376		};
5377	};
5378
5379	vo_post {
5380		/omit-if-no-ref/
5381		vo_post_pins: vo_post-pins {
5382			rockchip,pins =
5383				/* vo_post_empty */
5384				<4 RK_PA1 1 &pcfg_pull_none>;
5385		};
5386	};
5387
5388	vp0_sync {
5389		/omit-if-no-ref/
5390		vp0_sync_pins: vp0_sync-pins {
5391			rockchip,pins =
5392				/* vp0_sync_out */
5393				<4 RK_PC5 3 &pcfg_pull_none>;
5394		};
5395	};
5396
5397	vp1_sync {
5398		/omit-if-no-ref/
5399		vp1_sync_pins: vp1_sync-pins {
5400			rockchip,pins =
5401				/* vp1_sync_out */
5402				<4 RK_PC6 3 &pcfg_pull_none>;
5403		};
5404	};
5405
5406	vp2_sync {
5407		/omit-if-no-ref/
5408		vp2_sync_pins: vp2_sync-pins {
5409			rockchip,pins =
5410				/* vp2_sync_out */
5411				<4 RK_PC7 3 &pcfg_pull_none>;
5412		};
5413	};
5414};
5415
5416/*
5417 * This part is edited handly.
5418 */
5419&pinctrl {
5420	pmic {
5421		/omit-if-no-ref/
5422		pmic_pins: pmic-pins {
5423			rockchip,pins =
5424				/* pmic_int */
5425				<0 RK_PA6 9 &pcfg_pull_up>,
5426				/* pmic_sleep */
5427				<0 RK_PA4 9 &pcfg_pull_none>;
5428		};
5429	};
5430
5431	vo {
5432		/omit-if-no-ref/
5433		bt1120_pins: bt1120-pins {
5434			rockchip,pins =
5435				/* vo_lcdc_clk */
5436				<3 RK_PD7 1 &pcfg_pull_none>,
5437				/* vo_lcdc_d3 */
5438				<3 RK_PD0 1 &pcfg_pull_none>,
5439				/* vo_lcdc_d4 */
5440				<3 RK_PC7 1 &pcfg_pull_none>,
5441				/* vo_lcdc_d5 */
5442				<3 RK_PC6 1 &pcfg_pull_none>,
5443				/* vo_lcdc_d6 */
5444				<3 RK_PC5 1 &pcfg_pull_none>,
5445				/* vo_lcdc_d7 */
5446				<3 RK_PC4 1 &pcfg_pull_none>,
5447				/* vo_lcdc_d10 */
5448				<3 RK_PC1 1 &pcfg_pull_none>,
5449				/* vo_lcdc_d11 */
5450				<3 RK_PC0 1 &pcfg_pull_none>,
5451				/* vo_lcdc_d12 */
5452				<3 RK_PB7 1 &pcfg_pull_none>,
5453				/* vo_lcdc_d13 */
5454				<3 RK_PB6 1 &pcfg_pull_none>,
5455				/* vo_lcdc_d14 */
5456				<3 RK_PB5 1 &pcfg_pull_none>,
5457				/* vo_lcdc_d15 */
5458				<3 RK_PB4 1 &pcfg_pull_none>,
5459				/* vo_lcdc_d19 */
5460				<3 RK_PB0 1 &pcfg_pull_none>,
5461				/* vo_lcdc_d20 */
5462				<3 RK_PA7 1 &pcfg_pull_none>,
5463				/* vo_lcdc_d21 */
5464				<3 RK_PA6 1 &pcfg_pull_none>,
5465				/* vo_lcdc_d22 */
5466				<3 RK_PA5 1 &pcfg_pull_none>,
5467				/* vo_lcdc_d23 */
5468				<3 RK_PA4 1 &pcfg_pull_none>;
5469		};
5470
5471		/omit-if-no-ref/
5472		bt656_pins: bt656-pins {
5473			rockchip,pins =
5474				/* vo_lcdc_clk */
5475				<3 RK_PD7 1 &pcfg_pull_none>,
5476				/* vo_lcdc_d3 */
5477				<3 RK_PD0 1 &pcfg_pull_none>,
5478				/* vo_lcdc_d4 */
5479				<3 RK_PC7 1 &pcfg_pull_none>,
5480				/* vo_lcdc_d5 */
5481				<3 RK_PC6 1 &pcfg_pull_none>,
5482				/* vo_lcdc_d6 */
5483				<3 RK_PC5 1 &pcfg_pull_none>,
5484				/* vo_lcdc_d7 */
5485				<3 RK_PC4 1 &pcfg_pull_none>,
5486				/* vo_lcdc_d10 */
5487				<3 RK_PC1 1 &pcfg_pull_none>,
5488				/* vo_lcdc_d11 */
5489				<3 RK_PC0 1 &pcfg_pull_none>,
5490				/* vo_lcdc_d12 */
5491				<3 RK_PB7 1 &pcfg_pull_none>;
5492		};
5493
5494		/omit-if-no-ref/
5495		rgb3x8_pins_m0: rgb3x8-pins-m0 {
5496			rockchip,pins =
5497				/* vo_lcdc_clk */
5498				<3 RK_PD7 1 &pcfg_pull_none>,
5499				/* vo_lcdc_d3 */
5500				<3 RK_PD0 1 &pcfg_pull_none>,
5501				/* vo_lcdc_d4 */
5502				<3 RK_PC7 1 &pcfg_pull_none>,
5503				/* vo_lcdc_d5 */
5504				<3 RK_PC6 1 &pcfg_pull_none>,
5505				/* vo_lcdc_d6 */
5506				<3 RK_PC5 1 &pcfg_pull_none>,
5507				/* vo_lcdc_d7 */
5508				<3 RK_PC4 1 &pcfg_pull_none>,
5509				/* vo_lcdc_d10 */
5510				<3 RK_PC1 1 &pcfg_pull_none>,
5511				/* vo_lcdc_d11 */
5512				<3 RK_PC0 1 &pcfg_pull_none>,
5513				/* vo_lcdc_d12 */
5514				<3 RK_PB7 1 &pcfg_pull_none>,
5515				/* vo_lcdc_den */
5516				<3 RK_PD4 1 &pcfg_pull_none>,
5517				/* vo_lcdc_hsync */
5518				<3 RK_PD5 1 &pcfg_pull_none>,
5519				/* vo_lcdc_vsync */
5520				<3 RK_PD6 1 &pcfg_pull_none>;
5521		};
5522
5523		/omit-if-no-ref/
5524		rgb3x8_pins_m1: rgb3x8-pins-m1 {
5525			rockchip,pins =
5526				/* vo_lcdc_clk */
5527				<3 RK_PD7 1 &pcfg_pull_none>,
5528				/* vo_lcdc_d13 */
5529				<3 RK_PB6 1 &pcfg_pull_none>,
5530				/* vo_lcdc_d14 */
5531				<3 RK_PB5 1 &pcfg_pull_none>,
5532				/* vo_lcdc_d15 */
5533				<3 RK_PB4 1 &pcfg_pull_none>,
5534				/* vo_lcdc_d19 */
5535				<3 RK_PB0 1 &pcfg_pull_none>,
5536				/* vo_lcdc_d20 */
5537				<3 RK_PA7 1 &pcfg_pull_none>,
5538				/* vo_lcdc_d21 */
5539				<3 RK_PA6 1 &pcfg_pull_none>,
5540				/* vo_lcdc_d22 */
5541				<3 RK_PA5 1 &pcfg_pull_none>,
5542				/* vo_lcdc_d23 */
5543				<3 RK_PA4 1 &pcfg_pull_none>,
5544				/* vo_lcdc_den */
5545				<3 RK_PD4 1 &pcfg_pull_none>,
5546				/* vo_lcdc_hsync */
5547				<3 RK_PD5 1 &pcfg_pull_none>,
5548				/* vo_lcdc_vsync */
5549				<3 RK_PD6 1 &pcfg_pull_none>;
5550		};
5551
5552		/omit-if-no-ref/
5553		rgb565_pins: rgb565-pins {
5554			rockchip,pins =
5555				/* vo_lcdc_clk */
5556				<3 RK_PD7 1 &pcfg_pull_none>,
5557				/* vo_lcdc_d3 */
5558				<3 RK_PD0 1 &pcfg_pull_none>,
5559				/* vo_lcdc_d4 */
5560				<3 RK_PC7 1 &pcfg_pull_none>,
5561				/* vo_lcdc_d5 */
5562				<3 RK_PC6 1 &pcfg_pull_none>,
5563				/* vo_lcdc_d6 */
5564				<3 RK_PC5 1 &pcfg_pull_none>,
5565				/* vo_lcdc_d7 */
5566				<3 RK_PC4 1 &pcfg_pull_none>,
5567				/* vo_lcdc_d10 */
5568				<3 RK_PC1 1 &pcfg_pull_none>,
5569				/* vo_lcdc_d11 */
5570				<3 RK_PC0 1 &pcfg_pull_none>,
5571				/* vo_lcdc_d12 */
5572				<3 RK_PB7 1 &pcfg_pull_none>,
5573				/* vo_lcdc_d13 */
5574				<3 RK_PB6 1 &pcfg_pull_none>,
5575				/* vo_lcdc_d14 */
5576				<3 RK_PB5 1 &pcfg_pull_none>,
5577				/* vo_lcdc_d15 */
5578				<3 RK_PB4 1 &pcfg_pull_none>,
5579				/* vo_lcdc_d19 */
5580				<3 RK_PB0 1 &pcfg_pull_none>,
5581				/* vo_lcdc_d20 */
5582				<3 RK_PA7 1 &pcfg_pull_none>,
5583				/* vo_lcdc_d21 */
5584				<3 RK_PA6 1 &pcfg_pull_none>,
5585				/* vo_lcdc_d22 */
5586				<3 RK_PA5 1 &pcfg_pull_none>,
5587				/* vo_lcdc_d23 */
5588				<3 RK_PA4 1 &pcfg_pull_none>,
5589				/* vo_lcdc_den */
5590				<3 RK_PD4 1 &pcfg_pull_none>,
5591				/* vo_lcdc_hsync */
5592				<3 RK_PD5 1 &pcfg_pull_none>,
5593				/* vo_lcdc_vsync */
5594				<3 RK_PD6 1 &pcfg_pull_none>;
5595		};
5596
5597		/omit-if-no-ref/
5598		rgb666_pins: rgb666-pins {
5599			rockchip,pins =
5600				/* vo_lcdc_clk */
5601				<3 RK_PD7 1 &pcfg_pull_none>,
5602				/* vo_lcdc_d2 */
5603				<3 RK_PD1 1 &pcfg_pull_none>,
5604				/* vo_lcdc_d3 */
5605				<3 RK_PD0 1 &pcfg_pull_none>,
5606				/* vo_lcdc_d4 */
5607				<3 RK_PC7 1 &pcfg_pull_none>,
5608				/* vo_lcdc_d5 */
5609				<3 RK_PC6 1 &pcfg_pull_none>,
5610				/* vo_lcdc_d6 */
5611				<3 RK_PC5 1 &pcfg_pull_none>,
5612				/* vo_lcdc_d7 */
5613				<3 RK_PC4 1 &pcfg_pull_none>,
5614				/* vo_lcdc_d10 */
5615				<3 RK_PC1 1 &pcfg_pull_none>,
5616				/* vo_lcdc_d11 */
5617				<3 RK_PC0 1 &pcfg_pull_none>,
5618				/* vo_lcdc_d12 */
5619				<3 RK_PB7 1 &pcfg_pull_none>,
5620				/* vo_lcdc_d13 */
5621				<3 RK_PB6 1 &pcfg_pull_none>,
5622				/* vo_lcdc_d14 */
5623				<3 RK_PB5 1 &pcfg_pull_none>,
5624				/* vo_lcdc_d15 */
5625				<3 RK_PB4 1 &pcfg_pull_none>,
5626				/* vo_lcdc_d18 */
5627				<3 RK_PB1 1 &pcfg_pull_none>,
5628				/* vo_lcdc_d19 */
5629				<3 RK_PB0 1 &pcfg_pull_none>,
5630				/* vo_lcdc_d20 */
5631				<3 RK_PA7 1 &pcfg_pull_none>,
5632				/* vo_lcdc_d21 */
5633				<3 RK_PA6 1 &pcfg_pull_none>,
5634				/* vo_lcdc_d22 */
5635				<3 RK_PA5 1 &pcfg_pull_none>,
5636				/* vo_lcdc_d23 */
5637				<3 RK_PA4 1 &pcfg_pull_none>,
5638				/* vo_lcdc_den */
5639				<3 RK_PD4 1 &pcfg_pull_none>,
5640				/* vo_lcdc_hsync */
5641				<3 RK_PD5 1 &pcfg_pull_none>,
5642				/* vo_lcdc_vsync */
5643				<3 RK_PD6 1 &pcfg_pull_none>;
5644		};
5645
5646		/omit-if-no-ref/
5647		rgb888_pins: rgb888-pins {
5648			rockchip,pins =
5649				/* vo_lcdc_clk */
5650				<3 RK_PD7 1 &pcfg_pull_none>,
5651				/* vo_lcdc_d0 */
5652				<3 RK_PD3 1 &pcfg_pull_none>,
5653				/* vo_lcdc_d1 */
5654				<3 RK_PD2 1 &pcfg_pull_none>,
5655				/* vo_lcdc_d2 */
5656				<3 RK_PD1 1 &pcfg_pull_none>,
5657				/* vo_lcdc_d3 */
5658				<3 RK_PD0 1 &pcfg_pull_none>,
5659				/* vo_lcdc_d4 */
5660				<3 RK_PC7 1 &pcfg_pull_none>,
5661				/* vo_lcdc_d5 */
5662				<3 RK_PC6 1 &pcfg_pull_none>,
5663				/* vo_lcdc_d6 */
5664				<3 RK_PC5 1 &pcfg_pull_none>,
5665				/* vo_lcdc_d7 */
5666				<3 RK_PC4 1 &pcfg_pull_none>,
5667				/* vo_lcdc_d8 */
5668				<3 RK_PC3 1 &pcfg_pull_none>,
5669				/* vo_lcdc_d9 */
5670				<3 RK_PC2 1 &pcfg_pull_none>,
5671				/* vo_lcdc_d10 */
5672				<3 RK_PC1 1 &pcfg_pull_none>,
5673				/* vo_lcdc_d11 */
5674				<3 RK_PC0 1 &pcfg_pull_none>,
5675				/* vo_lcdc_d12 */
5676				<3 RK_PB7 1 &pcfg_pull_none>,
5677				/* vo_lcdc_d13 */
5678				<3 RK_PB6 1 &pcfg_pull_none>,
5679				/* vo_lcdc_d14 */
5680				<3 RK_PB5 1 &pcfg_pull_none>,
5681				/* vo_lcdc_d15 */
5682				<3 RK_PB4 1 &pcfg_pull_none>,
5683				/* vo_lcdc_d16 */
5684				<3 RK_PB3 1 &pcfg_pull_none>,
5685				/* vo_lcdc_d17 */
5686				<3 RK_PB2 1 &pcfg_pull_none>,
5687				/* vo_lcdc_d18 */
5688				<3 RK_PB1 1 &pcfg_pull_none>,
5689				/* vo_lcdc_d19 */
5690				<3 RK_PB0 1 &pcfg_pull_none>,
5691				/* vo_lcdc_d20 */
5692				<3 RK_PA7 1 &pcfg_pull_none>,
5693				/* vo_lcdc_d21 */
5694				<3 RK_PA6 1 &pcfg_pull_none>,
5695				/* vo_lcdc_d22 */
5696				<3 RK_PA5 1 &pcfg_pull_none>,
5697				/* vo_lcdc_d23 */
5698				<3 RK_PA4 1 &pcfg_pull_none>,
5699				/* vo_lcdc_den */
5700				<3 RK_PD4 1 &pcfg_pull_none>,
5701				/* vo_lcdc_hsync */
5702				<3 RK_PD5 1 &pcfg_pull_none>,
5703				/* vo_lcdc_vsync */
5704				<3 RK_PD6 1 &pcfg_pull_none>;
5705		};
5706	};
5707
5708	vo_ebc {
5709		/omit-if-no-ref/
5710		vo_ebc_pins: vo_ebc-pins {
5711			rockchip,pins =
5712				/* vo_ebc_gdclk */
5713				<3 RK_PD5 2 &pcfg_pull_none>,
5714				/* vo_ebc_gdoe */
5715				<3 RK_PA6 2 &pcfg_pull_none>,
5716				/* vo_ebc_gdsp */
5717				<3 RK_PA5 2 &pcfg_pull_none>,
5718				/* vo_ebc_sdce0 */
5719				<3 RK_PB3 2 &pcfg_pull_none>,
5720				/* vo_ebc_sdclk */
5721				<3 RK_PD6 2 &pcfg_pull_none>,
5722				/* vo_ebc_sddo0 */
5723				<3 RK_PD3 2 &pcfg_pull_none>,
5724				/* vo_ebc_sddo1 */
5725				<3 RK_PD2 2 &pcfg_pull_none>,
5726				/* vo_ebc_sddo2 */
5727				<3 RK_PD1 2 &pcfg_pull_none>,
5728				/* vo_ebc_sddo3 */
5729				<3 RK_PD0 2 &pcfg_pull_none>,
5730				/* vo_ebc_sddo4 */
5731				<3 RK_PC7 2 &pcfg_pull_none>,
5732				/* vo_ebc_sddo5 */
5733				<3 RK_PC6 2 &pcfg_pull_none>,
5734				/* vo_ebc_sddo6 */
5735				<3 RK_PC5 2 &pcfg_pull_none>,
5736				/* vo_ebc_sddo7 */
5737				<3 RK_PC4 2 &pcfg_pull_none>,
5738				/* vo_ebc_sddo8 */
5739				<3 RK_PC3 2 &pcfg_pull_none>,
5740				/* vo_ebc_sddo9 */
5741				<3 RK_PC2 2 &pcfg_pull_none>,
5742				/* vo_ebc_sddo10 */
5743				<3 RK_PC1 2 &pcfg_pull_none>,
5744				/* vo_ebc_sddo11 */
5745				<3 RK_PC0 2 &pcfg_pull_none>,
5746				/* vo_ebc_sddo12 */
5747				<3 RK_PB7 2 &pcfg_pull_none>,
5748				/* vo_ebc_sddo13 */
5749				<3 RK_PB6 2 &pcfg_pull_none>,
5750				/* vo_ebc_sddo14 */
5751				<3 RK_PB5 2 &pcfg_pull_none>,
5752				/* vo_ebc_sddo15 */
5753				<3 RK_PB4 2 &pcfg_pull_none>,
5754				/* vo_ebc_sdle */
5755				<3 RK_PD4 2 &pcfg_pull_none>,
5756				/* vo_ebc_sdoe */
5757				<3 RK_PD7 2 &pcfg_pull_none>;
5758		};
5759
5760		/omit-if-no-ref/
5761		vo_ebc_extern: vo_ebc-extern {
5762			rockchip,pins =
5763				/* vo_ebc_sdce1 */
5764				<3 RK_PB2 2 &pcfg_pull_none>,
5765				/* vo_ebc_sdce2 */
5766				<3 RK_PB1 2 &pcfg_pull_none>,
5767				/* vo_ebc_sdce3 */
5768				<3 RK_PB0 2 &pcfg_pull_none>,
5769				/* vo_ebc_sdshr */
5770				<3 RK_PA4 2 &pcfg_pull_none>,
5771				/* vo_ebc_vcom */
5772				<3 RK_PA7 2 &pcfg_pull_none>;
5773		};
5774	};
5775};
5776