1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3568-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 gpio0 = &gpio0; 22 gpio1 = &gpio1; 23 gpio2 = &gpio2; 24 gpio3 = &gpio3; 25 gpio4 = &gpio4; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 serial6 = &uart6; 39 serial7 = &uart7; 40 serial8 = &uart8; 41 serial9 = &uart9; 42 spi0 = &spi0; 43 spi1 = &spi1; 44 spi2 = &spi2; 45 spi3 = &spi3; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x0 0x0>; 56 clocks = <&scmi_clk 0>; 57 #cooling-cells = <2>; 58 enable-method = "psci"; 59 operating-points-v2 = <&cpu0_opp_table>; 60 }; 61 62 cpu1: cpu@100 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a55"; 65 reg = <0x0 0x100>; 66 #cooling-cells = <2>; 67 enable-method = "psci"; 68 operating-points-v2 = <&cpu0_opp_table>; 69 }; 70 71 cpu2: cpu@200 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x0 0x200>; 75 #cooling-cells = <2>; 76 enable-method = "psci"; 77 operating-points-v2 = <&cpu0_opp_table>; 78 }; 79 80 cpu3: cpu@300 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x0 0x300>; 84 #cooling-cells = <2>; 85 enable-method = "psci"; 86 operating-points-v2 = <&cpu0_opp_table>; 87 }; 88 }; 89 90 cpu0_opp_table: opp-table-0 { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 94 opp-408000000 { 95 opp-hz = /bits/ 64 <408000000>; 96 opp-microvolt = <900000 900000 1150000>; 97 clock-latency-ns = <40000>; 98 }; 99 100 opp-600000000 { 101 opp-hz = /bits/ 64 <600000000>; 102 opp-microvolt = <900000 900000 1150000>; 103 }; 104 105 opp-816000000 { 106 opp-hz = /bits/ 64 <816000000>; 107 opp-microvolt = <900000 900000 1150000>; 108 opp-suspend; 109 }; 110 111 opp-1104000000 { 112 opp-hz = /bits/ 64 <1104000000>; 113 opp-microvolt = <900000 900000 1150000>; 114 }; 115 116 opp-1416000000 { 117 opp-hz = /bits/ 64 <1416000000>; 118 opp-microvolt = <900000 900000 1150000>; 119 }; 120 121 opp-1608000000 { 122 opp-hz = /bits/ 64 <1608000000>; 123 opp-microvolt = <975000 975000 1150000>; 124 }; 125 126 opp-1800000000 { 127 opp-hz = /bits/ 64 <1800000000>; 128 opp-microvolt = <1050000 1050000 1150000>; 129 }; 130 }; 131 132 display_subsystem: display-subsystem { 133 compatible = "rockchip,display-subsystem"; 134 ports = <&vop_out>; 135 }; 136 137 firmware { 138 scmi: scmi { 139 compatible = "arm,scmi-smc"; 140 arm,smc-id = <0x82000010>; 141 shmem = <&scmi_shmem>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 145 scmi_clk: protocol@14 { 146 reg = <0x14>; 147 #clock-cells = <1>; 148 }; 149 }; 150 }; 151 152 gpu_opp_table: opp-table-1 { 153 compatible = "operating-points-v2"; 154 155 opp-200000000 { 156 opp-hz = /bits/ 64 <200000000>; 157 opp-microvolt = <825000>; 158 }; 159 160 opp-300000000 { 161 opp-hz = /bits/ 64 <300000000>; 162 opp-microvolt = <825000>; 163 }; 164 165 opp-400000000 { 166 opp-hz = /bits/ 64 <400000000>; 167 opp-microvolt = <825000>; 168 }; 169 170 opp-600000000 { 171 opp-hz = /bits/ 64 <600000000>; 172 opp-microvolt = <825000>; 173 }; 174 175 opp-700000000 { 176 opp-hz = /bits/ 64 <700000000>; 177 opp-microvolt = <900000>; 178 }; 179 180 opp-800000000 { 181 opp-hz = /bits/ 64 <800000000>; 182 opp-microvolt = <1000000>; 183 }; 184 }; 185 186 hdmi_sound: hdmi-sound { 187 compatible = "simple-audio-card"; 188 simple-audio-card,name = "HDMI"; 189 simple-audio-card,format = "i2s"; 190 simple-audio-card,mclk-fs = <256>; 191 status = "disabled"; 192 193 simple-audio-card,codec { 194 sound-dai = <&hdmi>; 195 }; 196 197 simple-audio-card,cpu { 198 sound-dai = <&i2s0_8ch>; 199 }; 200 }; 201 202 pmu { 203 compatible = "arm,cortex-a55-pmu"; 204 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 208 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 209 }; 210 211 psci { 212 compatible = "arm,psci-1.0"; 213 method = "smc"; 214 }; 215 216 timer { 217 compatible = "arm,armv8-timer"; 218 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 222 arm,no-tick-in-suspend; 223 }; 224 225 xin24m: xin24m { 226 compatible = "fixed-clock"; 227 clock-frequency = <24000000>; 228 clock-output-names = "xin24m"; 229 #clock-cells = <0>; 230 }; 231 232 xin32k: xin32k { 233 compatible = "fixed-clock"; 234 clock-frequency = <32768>; 235 clock-output-names = "xin32k"; 236 pinctrl-0 = <&clk32k_out0>; 237 pinctrl-names = "default"; 238 #clock-cells = <0>; 239 }; 240 241 sram@10f000 { 242 compatible = "mmio-sram"; 243 reg = <0x0 0x0010f000 0x0 0x100>; 244 #address-cells = <1>; 245 #size-cells = <1>; 246 ranges = <0 0x0 0x0010f000 0x100>; 247 248 scmi_shmem: sram@0 { 249 compatible = "arm,scmi-shmem"; 250 reg = <0x0 0x100>; 251 }; 252 }; 253 254 sata1: sata@fc400000 { 255 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 256 reg = <0 0xfc400000 0 0x1000>; 257 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, 258 <&cru CLK_SATA1_RXOOB>; 259 clock-names = "sata", "pmalive", "rxoob"; 260 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 261 phys = <&combphy1 PHY_TYPE_SATA>; 262 phy-names = "sata-phy"; 263 ports-implemented = <0x1>; 264 power-domains = <&power RK3568_PD_PIPE>; 265 status = "disabled"; 266 }; 267 268 sata2: sata@fc800000 { 269 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 270 reg = <0 0xfc800000 0 0x1000>; 271 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, 272 <&cru CLK_SATA2_RXOOB>; 273 clock-names = "sata", "pmalive", "rxoob"; 274 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 275 phys = <&combphy2 PHY_TYPE_SATA>; 276 phy-names = "sata-phy"; 277 ports-implemented = <0x1>; 278 power-domains = <&power RK3568_PD_PIPE>; 279 status = "disabled"; 280 }; 281 282 usb_host0_xhci: usb@fcc00000 { 283 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 284 reg = <0x0 0xfcc00000 0x0 0x400000>; 285 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 287 <&cru ACLK_USB3OTG0>; 288 clock-names = "ref_clk", "suspend_clk", 289 "bus_clk"; 290 dr_mode = "otg"; 291 phy_type = "utmi_wide"; 292 power-domains = <&power RK3568_PD_PIPE>; 293 resets = <&cru SRST_USB3OTG0>; 294 snps,dis_u2_susphy_quirk; 295 status = "disabled"; 296 }; 297 298 usb_host1_xhci: usb@fd000000 { 299 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 300 reg = <0x0 0xfd000000 0x0 0x400000>; 301 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 303 <&cru ACLK_USB3OTG1>; 304 clock-names = "ref_clk", "suspend_clk", 305 "bus_clk"; 306 dr_mode = "host"; 307 phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; 308 phy-names = "usb2-phy", "usb3-phy"; 309 phy_type = "utmi_wide"; 310 power-domains = <&power RK3568_PD_PIPE>; 311 resets = <&cru SRST_USB3OTG1>; 312 snps,dis_u2_susphy_quirk; 313 status = "disabled"; 314 }; 315 316 gic: interrupt-controller@fd400000 { 317 compatible = "arm,gic-v3"; 318 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 319 <0x0 0xfd460000 0 0x80000>; /* GICR */ 320 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 321 interrupt-controller; 322 #interrupt-cells = <3>; 323 mbi-alias = <0x0 0xfd410000>; 324 mbi-ranges = <296 24>; 325 msi-controller; 326 }; 327 328 usb_host0_ehci: usb@fd800000 { 329 compatible = "generic-ehci"; 330 reg = <0x0 0xfd800000 0x0 0x40000>; 331 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 333 <&cru PCLK_USB>; 334 phys = <&usb2phy1_otg>; 335 phy-names = "usb"; 336 status = "disabled"; 337 }; 338 339 usb_host0_ohci: usb@fd840000 { 340 compatible = "generic-ohci"; 341 reg = <0x0 0xfd840000 0x0 0x40000>; 342 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 344 <&cru PCLK_USB>; 345 phys = <&usb2phy1_otg>; 346 phy-names = "usb"; 347 status = "disabled"; 348 }; 349 350 usb_host1_ehci: usb@fd880000 { 351 compatible = "generic-ehci"; 352 reg = <0x0 0xfd880000 0x0 0x40000>; 353 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 355 <&cru PCLK_USB>; 356 phys = <&usb2phy1_host>; 357 phy-names = "usb"; 358 status = "disabled"; 359 }; 360 361 usb_host1_ohci: usb@fd8c0000 { 362 compatible = "generic-ohci"; 363 reg = <0x0 0xfd8c0000 0x0 0x40000>; 364 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 366 <&cru PCLK_USB>; 367 phys = <&usb2phy1_host>; 368 phy-names = "usb"; 369 status = "disabled"; 370 }; 371 372 pmugrf: syscon@fdc20000 { 373 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 374 reg = <0x0 0xfdc20000 0x0 0x10000>; 375 376 pmu_io_domains: io-domains { 377 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 378 status = "disabled"; 379 }; 380 }; 381 382 pipegrf: syscon@fdc50000 { 383 reg = <0x0 0xfdc50000 0x0 0x1000>; 384 }; 385 386 grf: syscon@fdc60000 { 387 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 388 reg = <0x0 0xfdc60000 0x0 0x10000>; 389 }; 390 391 pipe_phy_grf1: syscon@fdc80000 { 392 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 393 reg = <0x0 0xfdc80000 0x0 0x1000>; 394 }; 395 396 pipe_phy_grf2: syscon@fdc90000 { 397 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 398 reg = <0x0 0xfdc90000 0x0 0x1000>; 399 }; 400 401 usb2phy0_grf: syscon@fdca0000 { 402 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 403 reg = <0x0 0xfdca0000 0x0 0x8000>; 404 }; 405 406 usb2phy1_grf: syscon@fdca8000 { 407 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 408 reg = <0x0 0xfdca8000 0x0 0x8000>; 409 }; 410 411 pmucru: clock-controller@fdd00000 { 412 compatible = "rockchip,rk3568-pmucru"; 413 reg = <0x0 0xfdd00000 0x0 0x1000>; 414 #clock-cells = <1>; 415 #reset-cells = <1>; 416 }; 417 418 cru: clock-controller@fdd20000 { 419 compatible = "rockchip,rk3568-cru"; 420 reg = <0x0 0xfdd20000 0x0 0x1000>; 421 clocks = <&xin24m>; 422 clock-names = "xin24m"; 423 #clock-cells = <1>; 424 #reset-cells = <1>; 425 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; 426 assigned-clock-rates = <32768>, <1200000000>, <200000000>; 427 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; 428 rockchip,grf = <&grf>; 429 }; 430 431 i2c0: i2c@fdd40000 { 432 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 433 reg = <0x0 0xfdd40000 0x0 0x1000>; 434 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 436 clock-names = "i2c", "pclk"; 437 pinctrl-0 = <&i2c0_xfer>; 438 pinctrl-names = "default"; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 status = "disabled"; 442 }; 443 444 uart0: serial@fdd50000 { 445 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 446 reg = <0x0 0xfdd50000 0x0 0x100>; 447 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 449 clock-names = "baudclk", "apb_pclk"; 450 dmas = <&dmac0 0>, <&dmac0 1>; 451 pinctrl-0 = <&uart0_xfer>; 452 pinctrl-names = "default"; 453 reg-io-width = <4>; 454 reg-shift = <2>; 455 status = "disabled"; 456 }; 457 458 pwm0: pwm@fdd70000 { 459 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 460 reg = <0x0 0xfdd70000 0x0 0x10>; 461 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 462 clock-names = "pwm", "pclk"; 463 pinctrl-0 = <&pwm0m0_pins>; 464 pinctrl-names = "default"; 465 #pwm-cells = <3>; 466 status = "disabled"; 467 }; 468 469 pwm1: pwm@fdd70010 { 470 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 471 reg = <0x0 0xfdd70010 0x0 0x10>; 472 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 473 clock-names = "pwm", "pclk"; 474 pinctrl-0 = <&pwm1m0_pins>; 475 pinctrl-names = "default"; 476 #pwm-cells = <3>; 477 status = "disabled"; 478 }; 479 480 pwm2: pwm@fdd70020 { 481 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 482 reg = <0x0 0xfdd70020 0x0 0x10>; 483 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 484 clock-names = "pwm", "pclk"; 485 pinctrl-0 = <&pwm2m0_pins>; 486 pinctrl-names = "default"; 487 #pwm-cells = <3>; 488 status = "disabled"; 489 }; 490 491 pwm3: pwm@fdd70030 { 492 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 493 reg = <0x0 0xfdd70030 0x0 0x10>; 494 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 495 clock-names = "pwm", "pclk"; 496 pinctrl-0 = <&pwm3_pins>; 497 pinctrl-names = "default"; 498 #pwm-cells = <3>; 499 status = "disabled"; 500 }; 501 502 pmu: power-management@fdd90000 { 503 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 504 reg = <0x0 0xfdd90000 0x0 0x1000>; 505 506 power: power-controller { 507 compatible = "rockchip,rk3568-power-controller"; 508 #power-domain-cells = <1>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 512 /* These power domains are grouped by VD_GPU */ 513 power-domain@RK3568_PD_GPU { 514 reg = <RK3568_PD_GPU>; 515 clocks = <&cru ACLK_GPU_PRE>, 516 <&cru PCLK_GPU_PRE>; 517 pm_qos = <&qos_gpu>; 518 #power-domain-cells = <0>; 519 }; 520 521 /* These power domains are grouped by VD_LOGIC */ 522 power-domain@RK3568_PD_VI { 523 reg = <RK3568_PD_VI>; 524 clocks = <&cru HCLK_VI>, 525 <&cru PCLK_VI>; 526 pm_qos = <&qos_isp>, 527 <&qos_vicap0>, 528 <&qos_vicap1>; 529 #power-domain-cells = <0>; 530 }; 531 532 power-domain@RK3568_PD_VO { 533 reg = <RK3568_PD_VO>; 534 clocks = <&cru HCLK_VO>, 535 <&cru PCLK_VO>, 536 <&cru ACLK_VOP_PRE>; 537 pm_qos = <&qos_hdcp>, 538 <&qos_vop_m0>, 539 <&qos_vop_m1>; 540 #power-domain-cells = <0>; 541 }; 542 543 power-domain@RK3568_PD_RGA { 544 reg = <RK3568_PD_RGA>; 545 clocks = <&cru HCLK_RGA_PRE>, 546 <&cru PCLK_RGA_PRE>; 547 pm_qos = <&qos_ebc>, 548 <&qos_iep>, 549 <&qos_jpeg_dec>, 550 <&qos_jpeg_enc>, 551 <&qos_rga_rd>, 552 <&qos_rga_wr>; 553 #power-domain-cells = <0>; 554 }; 555 556 power-domain@RK3568_PD_VPU { 557 reg = <RK3568_PD_VPU>; 558 clocks = <&cru HCLK_VPU_PRE>; 559 pm_qos = <&qos_vpu>; 560 #power-domain-cells = <0>; 561 }; 562 563 power-domain@RK3568_PD_RKVDEC { 564 clocks = <&cru HCLK_RKVDEC_PRE>; 565 reg = <RK3568_PD_RKVDEC>; 566 pm_qos = <&qos_rkvdec>; 567 #power-domain-cells = <0>; 568 }; 569 570 power-domain@RK3568_PD_RKVENC { 571 reg = <RK3568_PD_RKVENC>; 572 clocks = <&cru HCLK_RKVENC_PRE>; 573 pm_qos = <&qos_rkvenc_rd_m0>, 574 <&qos_rkvenc_rd_m1>, 575 <&qos_rkvenc_wr_m0>; 576 #power-domain-cells = <0>; 577 }; 578 }; 579 }; 580 581 gpu: gpu@fde60000 { 582 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; 583 reg = <0x0 0xfde60000 0x0 0x4000>; 584 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 587 interrupt-names = "job", "mmu", "gpu"; 588 clocks = <&scmi_clk 1>, <&cru CLK_GPU>; 589 clock-names = "gpu", "bus"; 590 #cooling-cells = <2>; 591 operating-points-v2 = <&gpu_opp_table>; 592 power-domains = <&power RK3568_PD_GPU>; 593 status = "disabled"; 594 }; 595 596 vpu: video-codec@fdea0400 { 597 compatible = "rockchip,rk3568-vpu"; 598 reg = <0x0 0xfdea0000 0x0 0x800>; 599 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 601 clock-names = "aclk", "hclk"; 602 iommus = <&vdpu_mmu>; 603 power-domains = <&power RK3568_PD_VPU>; 604 }; 605 606 vdpu_mmu: iommu@fdea0800 { 607 compatible = "rockchip,rk3568-iommu"; 608 reg = <0x0 0xfdea0800 0x0 0x40>; 609 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 610 clock-names = "aclk", "iface"; 611 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 612 power-domains = <&power RK3568_PD_VPU>; 613 #iommu-cells = <0>; 614 }; 615 616 vepu: video-codec@fdee0000 { 617 compatible = "rockchip,rk3568-vepu"; 618 reg = <0x0 0xfdee0000 0x0 0x800>; 619 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 621 clock-names = "aclk", "hclk"; 622 iommus = <&vepu_mmu>; 623 power-domains = <&power RK3568_PD_RGA>; 624 }; 625 626 vepu_mmu: iommu@fdee0800 { 627 compatible = "rockchip,rk3568-iommu"; 628 reg = <0x0 0xfdee0800 0x0 0x40>; 629 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 631 clock-names = "aclk", "iface"; 632 power-domains = <&power RK3568_PD_RGA>; 633 #iommu-cells = <0>; 634 }; 635 636 sdmmc2: mmc@fe000000 { 637 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 638 reg = <0x0 0xfe000000 0x0 0x4000>; 639 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 641 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 642 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 643 fifo-depth = <0x100>; 644 max-frequency = <150000000>; 645 resets = <&cru SRST_SDMMC2>; 646 reset-names = "reset"; 647 status = "disabled"; 648 }; 649 650 gmac1: ethernet@fe010000 { 651 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 652 reg = <0x0 0xfe010000 0x0 0x10000>; 653 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 655 interrupt-names = "macirq", "eth_wake_irq"; 656 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 657 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 658 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 659 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 660 clock-names = "stmmaceth", "mac_clk_rx", 661 "mac_clk_tx", "clk_mac_refout", 662 "aclk_mac", "pclk_mac", 663 "clk_mac_speed", "ptp_ref"; 664 resets = <&cru SRST_A_GMAC1>; 665 reset-names = "stmmaceth"; 666 rockchip,grf = <&grf>; 667 snps,axi-config = <&gmac1_stmmac_axi_setup>; 668 snps,mixed-burst; 669 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 670 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 671 snps,tso; 672 status = "disabled"; 673 674 mdio1: mdio { 675 compatible = "snps,dwmac-mdio"; 676 #address-cells = <0x1>; 677 #size-cells = <0x0>; 678 }; 679 680 gmac1_stmmac_axi_setup: stmmac-axi-config { 681 snps,blen = <0 0 0 0 16 8 4>; 682 snps,rd_osr_lmt = <8>; 683 snps,wr_osr_lmt = <4>; 684 }; 685 686 gmac1_mtl_rx_setup: rx-queues-config { 687 snps,rx-queues-to-use = <1>; 688 queue0 {}; 689 }; 690 691 gmac1_mtl_tx_setup: tx-queues-config { 692 snps,tx-queues-to-use = <1>; 693 queue0 {}; 694 }; 695 }; 696 697 vop: vop@fe040000 { 698 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; 699 reg-names = "vop", "gamma-lut"; 700 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, 702 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; 703 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; 704 iommus = <&vop_mmu>; 705 power-domains = <&power RK3568_PD_VO>; 706 rockchip,grf = <&grf>; 707 status = "disabled"; 708 709 vop_out: ports { 710 #address-cells = <1>; 711 #size-cells = <0>; 712 713 vp0: port@0 { 714 reg = <0>; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 }; 718 719 vp1: port@1 { 720 reg = <1>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 }; 724 725 vp2: port@2 { 726 reg = <2>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 }; 730 }; 731 }; 732 733 vop_mmu: iommu@fe043e00 { 734 compatible = "rockchip,rk3568-iommu"; 735 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; 736 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 738 clock-names = "aclk", "iface"; 739 #iommu-cells = <0>; 740 status = "disabled"; 741 }; 742 743 dsi0: dsi@fe060000 { 744 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 745 reg = <0x00 0xfe060000 0x00 0x10000>; 746 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 747 clock-names = "pclk"; 748 clocks = <&cru PCLK_DSITX_0>; 749 phy-names = "dphy"; 750 phys = <&dsi_dphy0>; 751 power-domains = <&power RK3568_PD_VO>; 752 reset-names = "apb"; 753 resets = <&cru SRST_P_DSITX_0>; 754 rockchip,grf = <&grf>; 755 status = "disabled"; 756 757 ports { 758 #address-cells = <1>; 759 #size-cells = <0>; 760 761 dsi0_in: port@0 { 762 reg = <0>; 763 }; 764 765 dsi0_out: port@1 { 766 reg = <1>; 767 }; 768 }; 769 }; 770 771 dsi1: dsi@fe070000 { 772 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 773 reg = <0x0 0xfe070000 0x0 0x10000>; 774 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 775 clock-names = "pclk"; 776 clocks = <&cru PCLK_DSITX_1>; 777 phy-names = "dphy"; 778 phys = <&dsi_dphy1>; 779 power-domains = <&power RK3568_PD_VO>; 780 reset-names = "apb"; 781 resets = <&cru SRST_P_DSITX_1>; 782 rockchip,grf = <&grf>; 783 status = "disabled"; 784 785 ports { 786 #address-cells = <1>; 787 #size-cells = <0>; 788 789 dsi1_in: port@0 { 790 reg = <0>; 791 }; 792 793 dsi1_out: port@1 { 794 reg = <1>; 795 }; 796 }; 797 }; 798 799 hdmi: hdmi@fe0a0000 { 800 compatible = "rockchip,rk3568-dw-hdmi"; 801 reg = <0x0 0xfe0a0000 0x0 0x20000>; 802 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&cru PCLK_HDMI_HOST>, 804 <&cru CLK_HDMI_SFR>, 805 <&cru CLK_HDMI_CEC>, 806 <&pmucru CLK_HDMI_REF>, 807 <&cru HCLK_VO>; 808 clock-names = "iahb", "isfr", "cec", "ref"; 809 pinctrl-names = "default"; 810 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; 811 power-domains = <&power RK3568_PD_VO>; 812 reg-io-width = <4>; 813 rockchip,grf = <&grf>; 814 #sound-dai-cells = <0>; 815 status = "disabled"; 816 817 ports { 818 #address-cells = <1>; 819 #size-cells = <0>; 820 821 hdmi_in: port@0 { 822 reg = <0>; 823 }; 824 825 hdmi_out: port@1 { 826 reg = <1>; 827 }; 828 }; 829 }; 830 831 qos_gpu: qos@fe128000 { 832 compatible = "rockchip,rk3568-qos", "syscon"; 833 reg = <0x0 0xfe128000 0x0 0x20>; 834 }; 835 836 qos_rkvenc_rd_m0: qos@fe138080 { 837 compatible = "rockchip,rk3568-qos", "syscon"; 838 reg = <0x0 0xfe138080 0x0 0x20>; 839 }; 840 841 qos_rkvenc_rd_m1: qos@fe138100 { 842 compatible = "rockchip,rk3568-qos", "syscon"; 843 reg = <0x0 0xfe138100 0x0 0x20>; 844 }; 845 846 qos_rkvenc_wr_m0: qos@fe138180 { 847 compatible = "rockchip,rk3568-qos", "syscon"; 848 reg = <0x0 0xfe138180 0x0 0x20>; 849 }; 850 851 qos_isp: qos@fe148000 { 852 compatible = "rockchip,rk3568-qos", "syscon"; 853 reg = <0x0 0xfe148000 0x0 0x20>; 854 }; 855 856 qos_vicap0: qos@fe148080 { 857 compatible = "rockchip,rk3568-qos", "syscon"; 858 reg = <0x0 0xfe148080 0x0 0x20>; 859 }; 860 861 qos_vicap1: qos@fe148100 { 862 compatible = "rockchip,rk3568-qos", "syscon"; 863 reg = <0x0 0xfe148100 0x0 0x20>; 864 }; 865 866 qos_vpu: qos@fe150000 { 867 compatible = "rockchip,rk3568-qos", "syscon"; 868 reg = <0x0 0xfe150000 0x0 0x20>; 869 }; 870 871 qos_ebc: qos@fe158000 { 872 compatible = "rockchip,rk3568-qos", "syscon"; 873 reg = <0x0 0xfe158000 0x0 0x20>; 874 }; 875 876 qos_iep: qos@fe158100 { 877 compatible = "rockchip,rk3568-qos", "syscon"; 878 reg = <0x0 0xfe158100 0x0 0x20>; 879 }; 880 881 qos_jpeg_dec: qos@fe158180 { 882 compatible = "rockchip,rk3568-qos", "syscon"; 883 reg = <0x0 0xfe158180 0x0 0x20>; 884 }; 885 886 qos_jpeg_enc: qos@fe158200 { 887 compatible = "rockchip,rk3568-qos", "syscon"; 888 reg = <0x0 0xfe158200 0x0 0x20>; 889 }; 890 891 qos_rga_rd: qos@fe158280 { 892 compatible = "rockchip,rk3568-qos", "syscon"; 893 reg = <0x0 0xfe158280 0x0 0x20>; 894 }; 895 896 qos_rga_wr: qos@fe158300 { 897 compatible = "rockchip,rk3568-qos", "syscon"; 898 reg = <0x0 0xfe158300 0x0 0x20>; 899 }; 900 901 qos_npu: qos@fe180000 { 902 compatible = "rockchip,rk3568-qos", "syscon"; 903 reg = <0x0 0xfe180000 0x0 0x20>; 904 }; 905 906 qos_pcie2x1: qos@fe190000 { 907 compatible = "rockchip,rk3568-qos", "syscon"; 908 reg = <0x0 0xfe190000 0x0 0x20>; 909 }; 910 911 qos_sata1: qos@fe190280 { 912 compatible = "rockchip,rk3568-qos", "syscon"; 913 reg = <0x0 0xfe190280 0x0 0x20>; 914 }; 915 916 qos_sata2: qos@fe190300 { 917 compatible = "rockchip,rk3568-qos", "syscon"; 918 reg = <0x0 0xfe190300 0x0 0x20>; 919 }; 920 921 qos_usb3_0: qos@fe190380 { 922 compatible = "rockchip,rk3568-qos", "syscon"; 923 reg = <0x0 0xfe190380 0x0 0x20>; 924 }; 925 926 qos_usb3_1: qos@fe190400 { 927 compatible = "rockchip,rk3568-qos", "syscon"; 928 reg = <0x0 0xfe190400 0x0 0x20>; 929 }; 930 931 qos_rkvdec: qos@fe198000 { 932 compatible = "rockchip,rk3568-qos", "syscon"; 933 reg = <0x0 0xfe198000 0x0 0x20>; 934 }; 935 936 qos_hdcp: qos@fe1a8000 { 937 compatible = "rockchip,rk3568-qos", "syscon"; 938 reg = <0x0 0xfe1a8000 0x0 0x20>; 939 }; 940 941 qos_vop_m0: qos@fe1a8080 { 942 compatible = "rockchip,rk3568-qos", "syscon"; 943 reg = <0x0 0xfe1a8080 0x0 0x20>; 944 }; 945 946 qos_vop_m1: qos@fe1a8100 { 947 compatible = "rockchip,rk3568-qos", "syscon"; 948 reg = <0x0 0xfe1a8100 0x0 0x20>; 949 }; 950 951 pcie2x1: pcie@fe260000 { 952 compatible = "rockchip,rk3568-pcie"; 953 reg = <0x3 0xc0000000 0x0 0x00400000>, 954 <0x0 0xfe260000 0x0 0x00010000>, 955 <0x3 0x3f000000 0x0 0x01000000>; 956 reg-names = "dbi", "apb", "config"; 957 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 962 interrupt-names = "sys", "pmc", "msi", "legacy", "err"; 963 bus-range = <0x0 0xf>; 964 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 965 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, 966 <&cru CLK_PCIE20_AUX_NDFT>; 967 clock-names = "aclk_mst", "aclk_slv", 968 "aclk_dbi", "pclk", "aux"; 969 device_type = "pci"; 970 #interrupt-cells = <1>; 971 interrupt-map-mask = <0 0 0 7>; 972 interrupt-map = <0 0 0 1 &pcie_intc 0>, 973 <0 0 0 2 &pcie_intc 1>, 974 <0 0 0 3 &pcie_intc 2>, 975 <0 0 0 4 &pcie_intc 3>; 976 linux,pci-domain = <0>; 977 num-ib-windows = <6>; 978 num-ob-windows = <2>; 979 max-link-speed = <2>; 980 msi-map = <0x0 &gic 0x0 0x1000>; 981 num-lanes = <1>; 982 phys = <&combphy2 PHY_TYPE_PCIE>; 983 phy-names = "pcie-phy"; 984 power-domains = <&power RK3568_PD_PIPE>; 985 ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 986 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; 987 resets = <&cru SRST_PCIE20_POWERUP>; 988 reset-names = "pipe"; 989 #address-cells = <3>; 990 #size-cells = <2>; 991 status = "disabled"; 992 993 pcie_intc: legacy-interrupt-controller { 994 #address-cells = <0>; 995 #interrupt-cells = <1>; 996 interrupt-controller; 997 interrupt-parent = <&gic>; 998 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 999 }; 1000 }; 1001 1002 sdmmc0: mmc@fe2b0000 { 1003 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 1004 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1005 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 1007 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 1008 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1009 fifo-depth = <0x100>; 1010 max-frequency = <150000000>; 1011 resets = <&cru SRST_SDMMC0>; 1012 reset-names = "reset"; 1013 status = "disabled"; 1014 }; 1015 1016 sdmmc1: mmc@fe2c0000 { 1017 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 1018 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1019 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 1021 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 1022 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1023 fifo-depth = <0x100>; 1024 max-frequency = <150000000>; 1025 resets = <&cru SRST_SDMMC1>; 1026 reset-names = "reset"; 1027 status = "disabled"; 1028 }; 1029 1030 sfc: spi@fe300000 { 1031 compatible = "rockchip,sfc"; 1032 reg = <0x0 0xfe300000 0x0 0x4000>; 1033 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1034 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1035 clock-names = "clk_sfc", "hclk_sfc"; 1036 pinctrl-0 = <&fspi_pins>; 1037 pinctrl-names = "default"; 1038 status = "disabled"; 1039 }; 1040 1041 sdhci: mmc@fe310000 { 1042 compatible = "rockchip,rk3568-dwcmshc"; 1043 reg = <0x0 0xfe310000 0x0 0x10000>; 1044 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1045 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 1046 assigned-clock-rates = <200000000>, <24000000>; 1047 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1048 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1049 <&cru TCLK_EMMC>; 1050 clock-names = "core", "bus", "axi", "block", "timer"; 1051 status = "disabled"; 1052 }; 1053 1054 i2s0_8ch: i2s@fe400000 { 1055 compatible = "rockchip,rk3568-i2s-tdm"; 1056 reg = <0x0 0xfe400000 0x0 0x1000>; 1057 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1058 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1059 assigned-clock-rates = <1188000000>, <1188000000>; 1060 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1061 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1062 dmas = <&dmac1 0>; 1063 dma-names = "tx"; 1064 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1065 reset-names = "tx-m", "rx-m"; 1066 rockchip,grf = <&grf>; 1067 #sound-dai-cells = <0>; 1068 status = "disabled"; 1069 }; 1070 1071 i2s1_8ch: i2s@fe410000 { 1072 compatible = "rockchip,rk3568-i2s-tdm"; 1073 reg = <0x0 0xfe410000 0x0 0x1000>; 1074 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1075 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; 1076 assigned-clock-rates = <1188000000>, <1188000000>; 1077 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, 1078 <&cru HCLK_I2S1_8CH>; 1079 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1080 dmas = <&dmac1 3>, <&dmac1 2>; 1081 dma-names = "rx", "tx"; 1082 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1083 reset-names = "tx-m", "rx-m"; 1084 rockchip,grf = <&grf>; 1085 pinctrl-names = "default"; 1086 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx 1087 &i2s1m0_lrcktx &i2s1m0_lrckrx 1088 &i2s1m0_sdi0 &i2s1m0_sdi1 1089 &i2s1m0_sdi2 &i2s1m0_sdi3 1090 &i2s1m0_sdo0 &i2s1m0_sdo1 1091 &i2s1m0_sdo2 &i2s1m0_sdo3>; 1092 #sound-dai-cells = <0>; 1093 status = "disabled"; 1094 }; 1095 1096 i2s2_2ch: i2s@fe420000 { 1097 compatible = "rockchip,rk3568-i2s-tdm"; 1098 reg = <0x0 0xfe420000 0x0 0x1000>; 1099 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1100 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1101 assigned-clock-rates = <1188000000>; 1102 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1103 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1104 dmas = <&dmac1 4>, <&dmac1 5>; 1105 dma-names = "tx", "rx"; 1106 resets = <&cru SRST_M_I2S2_2CH>; 1107 reset-names = "m"; 1108 rockchip,grf = <&grf>; 1109 pinctrl-names = "default"; 1110 pinctrl-0 = <&i2s2m0_sclktx 1111 &i2s2m0_lrcktx 1112 &i2s2m0_sdi 1113 &i2s2m0_sdo>; 1114 #sound-dai-cells = <0>; 1115 status = "disabled"; 1116 }; 1117 1118 i2s3_2ch: i2s@fe430000 { 1119 compatible = "rockchip,rk3568-i2s-tdm"; 1120 reg = <0x0 0xfe430000 0x0 0x1000>; 1121 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1122 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, 1123 <&cru HCLK_I2S3_2CH>; 1124 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1125 dmas = <&dmac1 6>, <&dmac1 7>; 1126 dma-names = "tx", "rx"; 1127 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; 1128 reset-names = "tx-m", "rx-m"; 1129 rockchip,grf = <&grf>; 1130 #sound-dai-cells = <0>; 1131 status = "disabled"; 1132 }; 1133 1134 pdm: pdm@fe440000 { 1135 compatible = "rockchip,rk3568-pdm"; 1136 reg = <0x0 0xfe440000 0x0 0x1000>; 1137 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1138 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1139 clock-names = "pdm_clk", "pdm_hclk"; 1140 dmas = <&dmac1 9>; 1141 dma-names = "rx"; 1142 pinctrl-0 = <&pdmm0_clk 1143 &pdmm0_clk1 1144 &pdmm0_sdi0 1145 &pdmm0_sdi1 1146 &pdmm0_sdi2 1147 &pdmm0_sdi3>; 1148 pinctrl-names = "default"; 1149 resets = <&cru SRST_M_PDM>; 1150 reset-names = "pdm-m"; 1151 #sound-dai-cells = <0>; 1152 status = "disabled"; 1153 }; 1154 1155 spdif: spdif@fe460000 { 1156 compatible = "rockchip,rk3568-spdif"; 1157 reg = <0x0 0xfe460000 0x0 0x1000>; 1158 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1159 clock-names = "mclk", "hclk"; 1160 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 1161 dmas = <&dmac1 1>; 1162 dma-names = "tx"; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&spdifm0_tx>; 1165 #sound-dai-cells = <0>; 1166 status = "disabled"; 1167 }; 1168 1169 dmac0: dma-controller@fe530000 { 1170 compatible = "arm,pl330", "arm,primecell"; 1171 reg = <0x0 0xfe530000 0x0 0x4000>; 1172 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1174 arm,pl330-periph-burst; 1175 clocks = <&cru ACLK_BUS>; 1176 clock-names = "apb_pclk"; 1177 #dma-cells = <1>; 1178 }; 1179 1180 dmac1: dma-controller@fe550000 { 1181 compatible = "arm,pl330", "arm,primecell"; 1182 reg = <0x0 0xfe550000 0x0 0x4000>; 1183 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1185 arm,pl330-periph-burst; 1186 clocks = <&cru ACLK_BUS>; 1187 clock-names = "apb_pclk"; 1188 #dma-cells = <1>; 1189 }; 1190 1191 i2c1: i2c@fe5a0000 { 1192 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1193 reg = <0x0 0xfe5a0000 0x0 0x1000>; 1194 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1195 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1196 clock-names = "i2c", "pclk"; 1197 pinctrl-0 = <&i2c1_xfer>; 1198 pinctrl-names = "default"; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 status = "disabled"; 1202 }; 1203 1204 i2c2: i2c@fe5b0000 { 1205 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1206 reg = <0x0 0xfe5b0000 0x0 0x1000>; 1207 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1208 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1209 clock-names = "i2c", "pclk"; 1210 pinctrl-0 = <&i2c2m0_xfer>; 1211 pinctrl-names = "default"; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 status = "disabled"; 1215 }; 1216 1217 i2c3: i2c@fe5c0000 { 1218 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1219 reg = <0x0 0xfe5c0000 0x0 0x1000>; 1220 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1221 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1222 clock-names = "i2c", "pclk"; 1223 pinctrl-0 = <&i2c3m0_xfer>; 1224 pinctrl-names = "default"; 1225 #address-cells = <1>; 1226 #size-cells = <0>; 1227 status = "disabled"; 1228 }; 1229 1230 i2c4: i2c@fe5d0000 { 1231 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1232 reg = <0x0 0xfe5d0000 0x0 0x1000>; 1233 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1234 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1235 clock-names = "i2c", "pclk"; 1236 pinctrl-0 = <&i2c4m0_xfer>; 1237 pinctrl-names = "default"; 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 status = "disabled"; 1241 }; 1242 1243 i2c5: i2c@fe5e0000 { 1244 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1245 reg = <0x0 0xfe5e0000 0x0 0x1000>; 1246 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1247 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1248 clock-names = "i2c", "pclk"; 1249 pinctrl-0 = <&i2c5m0_xfer>; 1250 pinctrl-names = "default"; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 status = "disabled"; 1254 }; 1255 1256 wdt: watchdog@fe600000 { 1257 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; 1258 reg = <0x0 0xfe600000 0x0 0x100>; 1259 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 1260 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 1261 clock-names = "tclk", "pclk"; 1262 }; 1263 1264 spi0: spi@fe610000 { 1265 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1266 reg = <0x0 0xfe610000 0x0 0x1000>; 1267 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1268 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1269 clock-names = "spiclk", "apb_pclk"; 1270 dmas = <&dmac0 20>, <&dmac0 21>; 1271 dma-names = "tx", "rx"; 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 status = "disabled"; 1277 }; 1278 1279 spi1: spi@fe620000 { 1280 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1281 reg = <0x0 0xfe620000 0x0 0x1000>; 1282 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1284 clock-names = "spiclk", "apb_pclk"; 1285 dmas = <&dmac0 22>, <&dmac0 23>; 1286 dma-names = "tx", "rx"; 1287 pinctrl-names = "default"; 1288 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 1289 #address-cells = <1>; 1290 #size-cells = <0>; 1291 status = "disabled"; 1292 }; 1293 1294 spi2: spi@fe630000 { 1295 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1296 reg = <0x0 0xfe630000 0x0 0x1000>; 1297 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1298 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1299 clock-names = "spiclk", "apb_pclk"; 1300 dmas = <&dmac0 24>, <&dmac0 25>; 1301 dma-names = "tx", "rx"; 1302 pinctrl-names = "default"; 1303 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 status = "disabled"; 1307 }; 1308 1309 spi3: spi@fe640000 { 1310 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1311 reg = <0x0 0xfe640000 0x0 0x1000>; 1312 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1313 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1314 clock-names = "spiclk", "apb_pclk"; 1315 dmas = <&dmac0 26>, <&dmac0 27>; 1316 dma-names = "tx", "rx"; 1317 pinctrl-names = "default"; 1318 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; 1319 #address-cells = <1>; 1320 #size-cells = <0>; 1321 status = "disabled"; 1322 }; 1323 1324 uart1: serial@fe650000 { 1325 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1326 reg = <0x0 0xfe650000 0x0 0x100>; 1327 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1328 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1329 clock-names = "baudclk", "apb_pclk"; 1330 dmas = <&dmac0 2>, <&dmac0 3>; 1331 pinctrl-0 = <&uart1m0_xfer>; 1332 pinctrl-names = "default"; 1333 reg-io-width = <4>; 1334 reg-shift = <2>; 1335 status = "disabled"; 1336 }; 1337 1338 uart2: serial@fe660000 { 1339 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1340 reg = <0x0 0xfe660000 0x0 0x100>; 1341 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1342 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1343 clock-names = "baudclk", "apb_pclk"; 1344 dmas = <&dmac0 4>, <&dmac0 5>; 1345 pinctrl-0 = <&uart2m0_xfer>; 1346 pinctrl-names = "default"; 1347 reg-io-width = <4>; 1348 reg-shift = <2>; 1349 status = "disabled"; 1350 }; 1351 1352 uart3: serial@fe670000 { 1353 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1354 reg = <0x0 0xfe670000 0x0 0x100>; 1355 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1356 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1357 clock-names = "baudclk", "apb_pclk"; 1358 dmas = <&dmac0 6>, <&dmac0 7>; 1359 pinctrl-0 = <&uart3m0_xfer>; 1360 pinctrl-names = "default"; 1361 reg-io-width = <4>; 1362 reg-shift = <2>; 1363 status = "disabled"; 1364 }; 1365 1366 uart4: serial@fe680000 { 1367 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1368 reg = <0x0 0xfe680000 0x0 0x100>; 1369 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1370 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1371 clock-names = "baudclk", "apb_pclk"; 1372 dmas = <&dmac0 8>, <&dmac0 9>; 1373 pinctrl-0 = <&uart4m0_xfer>; 1374 pinctrl-names = "default"; 1375 reg-io-width = <4>; 1376 reg-shift = <2>; 1377 status = "disabled"; 1378 }; 1379 1380 uart5: serial@fe690000 { 1381 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1382 reg = <0x0 0xfe690000 0x0 0x100>; 1383 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1384 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1385 clock-names = "baudclk", "apb_pclk"; 1386 dmas = <&dmac0 10>, <&dmac0 11>; 1387 pinctrl-0 = <&uart5m0_xfer>; 1388 pinctrl-names = "default"; 1389 reg-io-width = <4>; 1390 reg-shift = <2>; 1391 status = "disabled"; 1392 }; 1393 1394 uart6: serial@fe6a0000 { 1395 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1396 reg = <0x0 0xfe6a0000 0x0 0x100>; 1397 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1398 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1399 clock-names = "baudclk", "apb_pclk"; 1400 dmas = <&dmac0 12>, <&dmac0 13>; 1401 pinctrl-0 = <&uart6m0_xfer>; 1402 pinctrl-names = "default"; 1403 reg-io-width = <4>; 1404 reg-shift = <2>; 1405 status = "disabled"; 1406 }; 1407 1408 uart7: serial@fe6b0000 { 1409 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1410 reg = <0x0 0xfe6b0000 0x0 0x100>; 1411 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1412 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1413 clock-names = "baudclk", "apb_pclk"; 1414 dmas = <&dmac0 14>, <&dmac0 15>; 1415 pinctrl-0 = <&uart7m0_xfer>; 1416 pinctrl-names = "default"; 1417 reg-io-width = <4>; 1418 reg-shift = <2>; 1419 status = "disabled"; 1420 }; 1421 1422 uart8: serial@fe6c0000 { 1423 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1424 reg = <0x0 0xfe6c0000 0x0 0x100>; 1425 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1426 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1427 clock-names = "baudclk", "apb_pclk"; 1428 dmas = <&dmac0 16>, <&dmac0 17>; 1429 pinctrl-0 = <&uart8m0_xfer>; 1430 pinctrl-names = "default"; 1431 reg-io-width = <4>; 1432 reg-shift = <2>; 1433 status = "disabled"; 1434 }; 1435 1436 uart9: serial@fe6d0000 { 1437 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1438 reg = <0x0 0xfe6d0000 0x0 0x100>; 1439 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1440 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1441 clock-names = "baudclk", "apb_pclk"; 1442 dmas = <&dmac0 18>, <&dmac0 19>; 1443 pinctrl-0 = <&uart9m0_xfer>; 1444 pinctrl-names = "default"; 1445 reg-io-width = <4>; 1446 reg-shift = <2>; 1447 status = "disabled"; 1448 }; 1449 1450 thermal_zones: thermal-zones { 1451 cpu_thermal: cpu-thermal { 1452 polling-delay-passive = <100>; 1453 polling-delay = <1000>; 1454 1455 thermal-sensors = <&tsadc 0>; 1456 1457 trips { 1458 cpu_alert0: cpu_alert0 { 1459 temperature = <70000>; 1460 hysteresis = <2000>; 1461 type = "passive"; 1462 }; 1463 cpu_alert1: cpu_alert1 { 1464 temperature = <75000>; 1465 hysteresis = <2000>; 1466 type = "passive"; 1467 }; 1468 cpu_crit: cpu_crit { 1469 temperature = <95000>; 1470 hysteresis = <2000>; 1471 type = "critical"; 1472 }; 1473 }; 1474 1475 cooling-maps { 1476 map0 { 1477 trip = <&cpu_alert0>; 1478 cooling-device = 1479 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1480 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1481 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1482 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1483 }; 1484 }; 1485 }; 1486 1487 gpu_thermal: gpu-thermal { 1488 polling-delay-passive = <20>; /* milliseconds */ 1489 polling-delay = <1000>; /* milliseconds */ 1490 1491 thermal-sensors = <&tsadc 1>; 1492 1493 trips { 1494 gpu_threshold: gpu-threshold { 1495 temperature = <70000>; 1496 hysteresis = <2000>; 1497 type = "passive"; 1498 }; 1499 gpu_target: gpu-target { 1500 temperature = <75000>; 1501 hysteresis = <2000>; 1502 type = "passive"; 1503 }; 1504 gpu_crit: gpu-crit { 1505 temperature = <95000>; 1506 hysteresis = <2000>; 1507 type = "critical"; 1508 }; 1509 }; 1510 1511 cooling-maps { 1512 map0 { 1513 trip = <&gpu_target>; 1514 cooling-device = 1515 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1516 }; 1517 }; 1518 }; 1519 }; 1520 1521 tsadc: tsadc@fe710000 { 1522 compatible = "rockchip,rk3568-tsadc"; 1523 reg = <0x0 0xfe710000 0x0 0x100>; 1524 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1525 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 1526 assigned-clock-rates = <17000000>, <700000>; 1527 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 1528 clock-names = "tsadc", "apb_pclk"; 1529 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, 1530 <&cru SRST_TSADCPHY>; 1531 rockchip,grf = <&grf>; 1532 rockchip,hw-tshut-temp = <95000>; 1533 pinctrl-names = "init", "default", "sleep"; 1534 pinctrl-0 = <&tsadc_pin>; 1535 pinctrl-1 = <&tsadc_shutorg>; 1536 pinctrl-2 = <&tsadc_pin>; 1537 #thermal-sensor-cells = <1>; 1538 status = "disabled"; 1539 }; 1540 1541 saradc: saradc@fe720000 { 1542 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 1543 reg = <0x0 0xfe720000 0x0 0x100>; 1544 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1545 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1546 clock-names = "saradc", "apb_pclk"; 1547 resets = <&cru SRST_P_SARADC>; 1548 reset-names = "saradc-apb"; 1549 #io-channel-cells = <1>; 1550 status = "disabled"; 1551 }; 1552 1553 pwm4: pwm@fe6e0000 { 1554 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1555 reg = <0x0 0xfe6e0000 0x0 0x10>; 1556 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1557 clock-names = "pwm", "pclk"; 1558 pinctrl-0 = <&pwm4_pins>; 1559 pinctrl-names = "default"; 1560 #pwm-cells = <3>; 1561 status = "disabled"; 1562 }; 1563 1564 pwm5: pwm@fe6e0010 { 1565 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1566 reg = <0x0 0xfe6e0010 0x0 0x10>; 1567 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1568 clock-names = "pwm", "pclk"; 1569 pinctrl-0 = <&pwm5_pins>; 1570 pinctrl-names = "default"; 1571 #pwm-cells = <3>; 1572 status = "disabled"; 1573 }; 1574 1575 pwm6: pwm@fe6e0020 { 1576 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1577 reg = <0x0 0xfe6e0020 0x0 0x10>; 1578 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1579 clock-names = "pwm", "pclk"; 1580 pinctrl-0 = <&pwm6_pins>; 1581 pinctrl-names = "default"; 1582 #pwm-cells = <3>; 1583 status = "disabled"; 1584 }; 1585 1586 pwm7: pwm@fe6e0030 { 1587 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1588 reg = <0x0 0xfe6e0030 0x0 0x10>; 1589 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1590 clock-names = "pwm", "pclk"; 1591 pinctrl-0 = <&pwm7_pins>; 1592 pinctrl-names = "default"; 1593 #pwm-cells = <3>; 1594 status = "disabled"; 1595 }; 1596 1597 pwm8: pwm@fe6f0000 { 1598 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1599 reg = <0x0 0xfe6f0000 0x0 0x10>; 1600 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1601 clock-names = "pwm", "pclk"; 1602 pinctrl-0 = <&pwm8m0_pins>; 1603 pinctrl-names = "default"; 1604 #pwm-cells = <3>; 1605 status = "disabled"; 1606 }; 1607 1608 pwm9: pwm@fe6f0010 { 1609 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1610 reg = <0x0 0xfe6f0010 0x0 0x10>; 1611 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1612 clock-names = "pwm", "pclk"; 1613 pinctrl-0 = <&pwm9m0_pins>; 1614 pinctrl-names = "default"; 1615 #pwm-cells = <3>; 1616 status = "disabled"; 1617 }; 1618 1619 pwm10: pwm@fe6f0020 { 1620 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1621 reg = <0x0 0xfe6f0020 0x0 0x10>; 1622 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1623 clock-names = "pwm", "pclk"; 1624 pinctrl-0 = <&pwm10m0_pins>; 1625 pinctrl-names = "default"; 1626 #pwm-cells = <3>; 1627 status = "disabled"; 1628 }; 1629 1630 pwm11: pwm@fe6f0030 { 1631 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1632 reg = <0x0 0xfe6f0030 0x0 0x10>; 1633 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1634 clock-names = "pwm", "pclk"; 1635 pinctrl-0 = <&pwm11m0_pins>; 1636 pinctrl-names = "default"; 1637 #pwm-cells = <3>; 1638 status = "disabled"; 1639 }; 1640 1641 pwm12: pwm@fe700000 { 1642 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1643 reg = <0x0 0xfe700000 0x0 0x10>; 1644 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1645 clock-names = "pwm", "pclk"; 1646 pinctrl-0 = <&pwm12m0_pins>; 1647 pinctrl-names = "default"; 1648 #pwm-cells = <3>; 1649 status = "disabled"; 1650 }; 1651 1652 pwm13: pwm@fe700010 { 1653 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1654 reg = <0x0 0xfe700010 0x0 0x10>; 1655 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1656 clock-names = "pwm", "pclk"; 1657 pinctrl-0 = <&pwm13m0_pins>; 1658 pinctrl-names = "default"; 1659 #pwm-cells = <3>; 1660 status = "disabled"; 1661 }; 1662 1663 pwm14: pwm@fe700020 { 1664 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1665 reg = <0x0 0xfe700020 0x0 0x10>; 1666 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1667 clock-names = "pwm", "pclk"; 1668 pinctrl-0 = <&pwm14m0_pins>; 1669 pinctrl-names = "default"; 1670 #pwm-cells = <3>; 1671 status = "disabled"; 1672 }; 1673 1674 pwm15: pwm@fe700030 { 1675 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1676 reg = <0x0 0xfe700030 0x0 0x10>; 1677 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1678 clock-names = "pwm", "pclk"; 1679 pinctrl-0 = <&pwm15m0_pins>; 1680 pinctrl-names = "default"; 1681 #pwm-cells = <3>; 1682 status = "disabled"; 1683 }; 1684 1685 combphy1: phy@fe830000 { 1686 compatible = "rockchip,rk3568-naneng-combphy"; 1687 reg = <0x0 0xfe830000 0x0 0x100>; 1688 clocks = <&pmucru CLK_PCIEPHY1_REF>, 1689 <&cru PCLK_PIPEPHY1>, 1690 <&cru PCLK_PIPE>; 1691 clock-names = "ref", "apb", "pipe"; 1692 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; 1693 assigned-clock-rates = <100000000>; 1694 resets = <&cru SRST_PIPEPHY1>; 1695 rockchip,pipe-grf = <&pipegrf>; 1696 rockchip,pipe-phy-grf = <&pipe_phy_grf1>; 1697 #phy-cells = <1>; 1698 status = "disabled"; 1699 }; 1700 1701 combphy2: phy@fe840000 { 1702 compatible = "rockchip,rk3568-naneng-combphy"; 1703 reg = <0x0 0xfe840000 0x0 0x100>; 1704 clocks = <&pmucru CLK_PCIEPHY2_REF>, 1705 <&cru PCLK_PIPEPHY2>, 1706 <&cru PCLK_PIPE>; 1707 clock-names = "ref", "apb", "pipe"; 1708 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; 1709 assigned-clock-rates = <100000000>; 1710 resets = <&cru SRST_PIPEPHY2>; 1711 rockchip,pipe-grf = <&pipegrf>; 1712 rockchip,pipe-phy-grf = <&pipe_phy_grf2>; 1713 #phy-cells = <1>; 1714 status = "disabled"; 1715 }; 1716 1717 csi_dphy: phy@fe870000 { 1718 compatible = "rockchip,rk3568-csi-dphy"; 1719 reg = <0x0 0xfe870000 0x0 0x10000>; 1720 clocks = <&cru PCLK_MIPICSIPHY>; 1721 clock-names = "pclk"; 1722 #phy-cells = <0>; 1723 resets = <&cru SRST_P_MIPICSIPHY>; 1724 reset-names = "apb"; 1725 rockchip,grf = <&grf>; 1726 status = "disabled"; 1727 }; 1728 1729 dsi_dphy0: mipi-dphy@fe850000 { 1730 compatible = "rockchip,rk3568-dsi-dphy"; 1731 reg = <0x0 0xfe850000 0x0 0x10000>; 1732 clock-names = "ref", "pclk"; 1733 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; 1734 #phy-cells = <0>; 1735 power-domains = <&power RK3568_PD_VO>; 1736 reset-names = "apb"; 1737 resets = <&cru SRST_P_MIPIDSIPHY0>; 1738 status = "disabled"; 1739 }; 1740 1741 dsi_dphy1: mipi-dphy@fe860000 { 1742 compatible = "rockchip,rk3568-dsi-dphy"; 1743 reg = <0x0 0xfe860000 0x0 0x10000>; 1744 clock-names = "ref", "pclk"; 1745 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; 1746 #phy-cells = <0>; 1747 power-domains = <&power RK3568_PD_VO>; 1748 reset-names = "apb"; 1749 resets = <&cru SRST_P_MIPIDSIPHY1>; 1750 status = "disabled"; 1751 }; 1752 1753 usb2phy0: usb2phy@fe8a0000 { 1754 compatible = "rockchip,rk3568-usb2phy"; 1755 reg = <0x0 0xfe8a0000 0x0 0x10000>; 1756 clocks = <&pmucru CLK_USBPHY0_REF>; 1757 clock-names = "phyclk"; 1758 clock-output-names = "clk_usbphy0_480m"; 1759 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1760 rockchip,usbgrf = <&usb2phy0_grf>; 1761 #clock-cells = <0>; 1762 status = "disabled"; 1763 1764 usb2phy0_host: host-port { 1765 #phy-cells = <0>; 1766 status = "disabled"; 1767 }; 1768 1769 usb2phy0_otg: otg-port { 1770 #phy-cells = <0>; 1771 status = "disabled"; 1772 }; 1773 }; 1774 1775 usb2phy1: usb2phy@fe8b0000 { 1776 compatible = "rockchip,rk3568-usb2phy"; 1777 reg = <0x0 0xfe8b0000 0x0 0x10000>; 1778 clocks = <&pmucru CLK_USBPHY1_REF>; 1779 clock-names = "phyclk"; 1780 clock-output-names = "clk_usbphy1_480m"; 1781 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1782 rockchip,usbgrf = <&usb2phy1_grf>; 1783 #clock-cells = <0>; 1784 status = "disabled"; 1785 1786 usb2phy1_host: host-port { 1787 #phy-cells = <0>; 1788 status = "disabled"; 1789 }; 1790 1791 usb2phy1_otg: otg-port { 1792 #phy-cells = <0>; 1793 status = "disabled"; 1794 }; 1795 }; 1796 1797 pinctrl: pinctrl { 1798 compatible = "rockchip,rk3568-pinctrl"; 1799 rockchip,grf = <&grf>; 1800 rockchip,pmu = <&pmugrf>; 1801 #address-cells = <2>; 1802 #size-cells = <2>; 1803 ranges; 1804 1805 gpio0: gpio@fdd60000 { 1806 compatible = "rockchip,gpio-bank"; 1807 reg = <0x0 0xfdd60000 0x0 0x100>; 1808 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1809 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 1810 gpio-controller; 1811 gpio-ranges = <&pinctrl 0 0 32>; 1812 #gpio-cells = <2>; 1813 interrupt-controller; 1814 #interrupt-cells = <2>; 1815 }; 1816 1817 gpio1: gpio@fe740000 { 1818 compatible = "rockchip,gpio-bank"; 1819 reg = <0x0 0xfe740000 0x0 0x100>; 1820 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1821 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1822 gpio-controller; 1823 gpio-ranges = <&pinctrl 0 32 32>; 1824 #gpio-cells = <2>; 1825 interrupt-controller; 1826 #interrupt-cells = <2>; 1827 }; 1828 1829 gpio2: gpio@fe750000 { 1830 compatible = "rockchip,gpio-bank"; 1831 reg = <0x0 0xfe750000 0x0 0x100>; 1832 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1833 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1834 gpio-controller; 1835 gpio-ranges = <&pinctrl 0 64 32>; 1836 #gpio-cells = <2>; 1837 interrupt-controller; 1838 #interrupt-cells = <2>; 1839 }; 1840 1841 gpio3: gpio@fe760000 { 1842 compatible = "rockchip,gpio-bank"; 1843 reg = <0x0 0xfe760000 0x0 0x100>; 1844 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1845 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1846 gpio-controller; 1847 gpio-ranges = <&pinctrl 0 96 32>; 1848 #gpio-cells = <2>; 1849 interrupt-controller; 1850 #interrupt-cells = <2>; 1851 }; 1852 1853 gpio4: gpio@fe770000 { 1854 compatible = "rockchip,gpio-bank"; 1855 reg = <0x0 0xfe770000 0x0 0x100>; 1856 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1857 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1858 gpio-controller; 1859 gpio-ranges = <&pinctrl 0 128 32>; 1860 #gpio-cells = <2>; 1861 interrupt-controller; 1862 #interrupt-cells = <2>; 1863 }; 1864 }; 1865}; 1866 1867#include "rk3568-pinctrl.dtsi" 1868