1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3568-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 gpio0 = &gpio0; 22 gpio1 = &gpio1; 23 gpio2 = &gpio2; 24 gpio3 = &gpio3; 25 gpio4 = &gpio4; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 serial6 = &uart6; 39 serial7 = &uart7; 40 serial8 = &uart8; 41 serial9 = &uart9; 42 spi0 = &spi0; 43 spi1 = &spi1; 44 spi2 = &spi2; 45 spi3 = &spi3; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x0 0x0>; 56 clocks = <&scmi_clk 0>; 57 #cooling-cells = <2>; 58 enable-method = "psci"; 59 operating-points-v2 = <&cpu0_opp_table>; 60 i-cache-size = <0x8000>; 61 i-cache-line-size = <64>; 62 i-cache-sets = <128>; 63 d-cache-size = <0x8000>; 64 d-cache-line-size = <64>; 65 d-cache-sets = <128>; 66 next-level-cache = <&l3_cache>; 67 }; 68 69 cpu1: cpu@100 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a55"; 72 reg = <0x0 0x100>; 73 #cooling-cells = <2>; 74 enable-method = "psci"; 75 operating-points-v2 = <&cpu0_opp_table>; 76 i-cache-size = <0x8000>; 77 i-cache-line-size = <64>; 78 i-cache-sets = <128>; 79 d-cache-size = <0x8000>; 80 d-cache-line-size = <64>; 81 d-cache-sets = <128>; 82 next-level-cache = <&l3_cache>; 83 }; 84 85 cpu2: cpu@200 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a55"; 88 reg = <0x0 0x200>; 89 #cooling-cells = <2>; 90 enable-method = "psci"; 91 operating-points-v2 = <&cpu0_opp_table>; 92 i-cache-size = <0x8000>; 93 i-cache-line-size = <64>; 94 i-cache-sets = <128>; 95 d-cache-size = <0x8000>; 96 d-cache-line-size = <64>; 97 d-cache-sets = <128>; 98 next-level-cache = <&l3_cache>; 99 }; 100 101 cpu3: cpu@300 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a55"; 104 reg = <0x0 0x300>; 105 #cooling-cells = <2>; 106 enable-method = "psci"; 107 operating-points-v2 = <&cpu0_opp_table>; 108 i-cache-size = <0x8000>; 109 i-cache-line-size = <64>; 110 i-cache-sets = <128>; 111 d-cache-size = <0x8000>; 112 d-cache-line-size = <64>; 113 d-cache-sets = <128>; 114 next-level-cache = <&l3_cache>; 115 }; 116 }; 117 118 /* 119 * There are no private per-core L2 caches, but only the 120 * L3 cache that appears to the CPU cores as L2 caches 121 */ 122 l3_cache: l3-cache { 123 compatible = "cache"; 124 cache-level = <2>; 125 cache-unified; 126 cache-size = <0x80000>; 127 cache-line-size = <64>; 128 cache-sets = <512>; 129 }; 130 131 cpu0_opp_table: opp-table-0 { 132 compatible = "operating-points-v2"; 133 opp-shared; 134 135 opp-408000000 { 136 opp-hz = /bits/ 64 <408000000>; 137 opp-microvolt = <900000 900000 1150000>; 138 clock-latency-ns = <40000>; 139 }; 140 141 opp-600000000 { 142 opp-hz = /bits/ 64 <600000000>; 143 opp-microvolt = <900000 900000 1150000>; 144 }; 145 146 opp-816000000 { 147 opp-hz = /bits/ 64 <816000000>; 148 opp-microvolt = <900000 900000 1150000>; 149 opp-suspend; 150 }; 151 152 opp-1104000000 { 153 opp-hz = /bits/ 64 <1104000000>; 154 opp-microvolt = <900000 900000 1150000>; 155 }; 156 157 opp-1416000000 { 158 opp-hz = /bits/ 64 <1416000000>; 159 opp-microvolt = <900000 900000 1150000>; 160 }; 161 162 opp-1608000000 { 163 opp-hz = /bits/ 64 <1608000000>; 164 opp-microvolt = <975000 975000 1150000>; 165 }; 166 167 opp-1800000000 { 168 opp-hz = /bits/ 64 <1800000000>; 169 opp-microvolt = <1050000 1050000 1150000>; 170 }; 171 }; 172 173 display_subsystem: display-subsystem { 174 compatible = "rockchip,display-subsystem"; 175 ports = <&vop_out>; 176 }; 177 178 firmware { 179 scmi: scmi { 180 compatible = "arm,scmi-smc"; 181 arm,smc-id = <0x82000010>; 182 shmem = <&scmi_shmem>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 186 scmi_clk: protocol@14 { 187 reg = <0x14>; 188 #clock-cells = <1>; 189 }; 190 }; 191 }; 192 193 gpu_opp_table: opp-table-1 { 194 compatible = "operating-points-v2"; 195 196 opp-200000000 { 197 opp-hz = /bits/ 64 <200000000>; 198 opp-microvolt = <850000 850000 1000000>; 199 }; 200 201 opp-300000000 { 202 opp-hz = /bits/ 64 <300000000>; 203 opp-microvolt = <850000 850000 1000000>; 204 }; 205 206 opp-400000000 { 207 opp-hz = /bits/ 64 <400000000>; 208 opp-microvolt = <850000 850000 1000000>; 209 }; 210 211 opp-600000000 { 212 opp-hz = /bits/ 64 <600000000>; 213 opp-microvolt = <900000 900000 1000000>; 214 }; 215 216 opp-700000000 { 217 opp-hz = /bits/ 64 <700000000>; 218 opp-microvolt = <950000 950000 1000000>; 219 }; 220 221 opp-800000000 { 222 opp-hz = /bits/ 64 <800000000>; 223 opp-microvolt = <1000000 1000000 1000000>; 224 }; 225 }; 226 227 hdmi_sound: hdmi-sound { 228 compatible = "simple-audio-card"; 229 simple-audio-card,name = "HDMI"; 230 simple-audio-card,format = "i2s"; 231 simple-audio-card,mclk-fs = <256>; 232 status = "disabled"; 233 234 simple-audio-card,codec { 235 sound-dai = <&hdmi>; 236 }; 237 238 simple-audio-card,cpu { 239 sound-dai = <&i2s0_8ch>; 240 }; 241 }; 242 243 pmu { 244 compatible = "arm,cortex-a55-pmu"; 245 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 249 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 250 }; 251 252 psci { 253 compatible = "arm,psci-1.0"; 254 method = "smc"; 255 }; 256 257 timer { 258 compatible = "arm,armv8-timer"; 259 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 263 arm,no-tick-in-suspend; 264 }; 265 266 xin24m: xin24m { 267 compatible = "fixed-clock"; 268 clock-frequency = <24000000>; 269 clock-output-names = "xin24m"; 270 #clock-cells = <0>; 271 }; 272 273 xin32k: xin32k { 274 compatible = "fixed-clock"; 275 clock-frequency = <32768>; 276 clock-output-names = "xin32k"; 277 pinctrl-0 = <&clk32k_out0>; 278 pinctrl-names = "default"; 279 #clock-cells = <0>; 280 }; 281 282 sram@10f000 { 283 compatible = "mmio-sram"; 284 reg = <0x0 0x0010f000 0x0 0x100>; 285 #address-cells = <1>; 286 #size-cells = <1>; 287 ranges = <0 0x0 0x0010f000 0x100>; 288 289 scmi_shmem: sram@0 { 290 compatible = "arm,scmi-shmem"; 291 reg = <0x0 0x100>; 292 }; 293 }; 294 295 sata1: sata@fc400000 { 296 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 297 reg = <0 0xfc400000 0 0x1000>; 298 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, 299 <&cru CLK_SATA1_RXOOB>; 300 clock-names = "sata", "pmalive", "rxoob"; 301 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 302 phys = <&combphy1 PHY_TYPE_SATA>; 303 phy-names = "sata-phy"; 304 ports-implemented = <0x1>; 305 power-domains = <&power RK3568_PD_PIPE>; 306 status = "disabled"; 307 }; 308 309 sata2: sata@fc800000 { 310 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 311 reg = <0 0xfc800000 0 0x1000>; 312 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, 313 <&cru CLK_SATA2_RXOOB>; 314 clock-names = "sata", "pmalive", "rxoob"; 315 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 316 phys = <&combphy2 PHY_TYPE_SATA>; 317 phy-names = "sata-phy"; 318 ports-implemented = <0x1>; 319 power-domains = <&power RK3568_PD_PIPE>; 320 status = "disabled"; 321 }; 322 323 usb_host0_xhci: usb@fcc00000 { 324 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 325 reg = <0x0 0xfcc00000 0x0 0x400000>; 326 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 328 <&cru ACLK_USB3OTG0>; 329 clock-names = "ref_clk", "suspend_clk", 330 "bus_clk"; 331 dr_mode = "otg"; 332 phy_type = "utmi_wide"; 333 power-domains = <&power RK3568_PD_PIPE>; 334 resets = <&cru SRST_USB3OTG0>; 335 snps,dis_u2_susphy_quirk; 336 status = "disabled"; 337 }; 338 339 usb_host1_xhci: usb@fd000000 { 340 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 341 reg = <0x0 0xfd000000 0x0 0x400000>; 342 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 344 <&cru ACLK_USB3OTG1>; 345 clock-names = "ref_clk", "suspend_clk", 346 "bus_clk"; 347 dr_mode = "host"; 348 phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; 349 phy-names = "usb2-phy", "usb3-phy"; 350 phy_type = "utmi_wide"; 351 power-domains = <&power RK3568_PD_PIPE>; 352 resets = <&cru SRST_USB3OTG1>; 353 snps,dis_u2_susphy_quirk; 354 status = "disabled"; 355 }; 356 357 gic: interrupt-controller@fd400000 { 358 compatible = "arm,gic-v3"; 359 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 360 <0x0 0xfd460000 0 0x80000>; /* GICR */ 361 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 362 interrupt-controller; 363 #interrupt-cells = <3>; 364 mbi-alias = <0x0 0xfd410000>; 365 mbi-ranges = <296 24>; 366 msi-controller; 367 }; 368 369 usb_host0_ehci: usb@fd800000 { 370 compatible = "generic-ehci"; 371 reg = <0x0 0xfd800000 0x0 0x40000>; 372 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 374 <&cru PCLK_USB>; 375 phys = <&usb2phy1_otg>; 376 phy-names = "usb"; 377 status = "disabled"; 378 }; 379 380 usb_host0_ohci: usb@fd840000 { 381 compatible = "generic-ohci"; 382 reg = <0x0 0xfd840000 0x0 0x40000>; 383 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 385 <&cru PCLK_USB>; 386 phys = <&usb2phy1_otg>; 387 phy-names = "usb"; 388 status = "disabled"; 389 }; 390 391 usb_host1_ehci: usb@fd880000 { 392 compatible = "generic-ehci"; 393 reg = <0x0 0xfd880000 0x0 0x40000>; 394 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 396 <&cru PCLK_USB>; 397 phys = <&usb2phy1_host>; 398 phy-names = "usb"; 399 status = "disabled"; 400 }; 401 402 usb_host1_ohci: usb@fd8c0000 { 403 compatible = "generic-ohci"; 404 reg = <0x0 0xfd8c0000 0x0 0x40000>; 405 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 407 <&cru PCLK_USB>; 408 phys = <&usb2phy1_host>; 409 phy-names = "usb"; 410 status = "disabled"; 411 }; 412 413 pmugrf: syscon@fdc20000 { 414 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 415 reg = <0x0 0xfdc20000 0x0 0x10000>; 416 417 pmu_io_domains: io-domains { 418 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 419 status = "disabled"; 420 }; 421 }; 422 423 pipegrf: syscon@fdc50000 { 424 reg = <0x0 0xfdc50000 0x0 0x1000>; 425 }; 426 427 grf: syscon@fdc60000 { 428 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 429 reg = <0x0 0xfdc60000 0x0 0x10000>; 430 }; 431 432 pipe_phy_grf1: syscon@fdc80000 { 433 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 434 reg = <0x0 0xfdc80000 0x0 0x1000>; 435 }; 436 437 pipe_phy_grf2: syscon@fdc90000 { 438 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 439 reg = <0x0 0xfdc90000 0x0 0x1000>; 440 }; 441 442 usb2phy0_grf: syscon@fdca0000 { 443 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 444 reg = <0x0 0xfdca0000 0x0 0x8000>; 445 }; 446 447 usb2phy1_grf: syscon@fdca8000 { 448 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 449 reg = <0x0 0xfdca8000 0x0 0x8000>; 450 }; 451 452 pmucru: clock-controller@fdd00000 { 453 compatible = "rockchip,rk3568-pmucru"; 454 reg = <0x0 0xfdd00000 0x0 0x1000>; 455 #clock-cells = <1>; 456 #reset-cells = <1>; 457 }; 458 459 cru: clock-controller@fdd20000 { 460 compatible = "rockchip,rk3568-cru"; 461 reg = <0x0 0xfdd20000 0x0 0x1000>; 462 clocks = <&xin24m>; 463 clock-names = "xin24m"; 464 #clock-cells = <1>; 465 #reset-cells = <1>; 466 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; 467 assigned-clock-rates = <32768>, <1200000000>, <200000000>; 468 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; 469 rockchip,grf = <&grf>; 470 }; 471 472 i2c0: i2c@fdd40000 { 473 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 474 reg = <0x0 0xfdd40000 0x0 0x1000>; 475 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 477 clock-names = "i2c", "pclk"; 478 pinctrl-0 = <&i2c0_xfer>; 479 pinctrl-names = "default"; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 status = "disabled"; 483 }; 484 485 uart0: serial@fdd50000 { 486 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 487 reg = <0x0 0xfdd50000 0x0 0x100>; 488 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 490 clock-names = "baudclk", "apb_pclk"; 491 dmas = <&dmac0 0>, <&dmac0 1>; 492 pinctrl-0 = <&uart0_xfer>; 493 pinctrl-names = "default"; 494 reg-io-width = <4>; 495 reg-shift = <2>; 496 status = "disabled"; 497 }; 498 499 pwm0: pwm@fdd70000 { 500 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 501 reg = <0x0 0xfdd70000 0x0 0x10>; 502 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 503 clock-names = "pwm", "pclk"; 504 pinctrl-0 = <&pwm0m0_pins>; 505 pinctrl-names = "default"; 506 #pwm-cells = <3>; 507 status = "disabled"; 508 }; 509 510 pwm1: pwm@fdd70010 { 511 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 512 reg = <0x0 0xfdd70010 0x0 0x10>; 513 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 514 clock-names = "pwm", "pclk"; 515 pinctrl-0 = <&pwm1m0_pins>; 516 pinctrl-names = "default"; 517 #pwm-cells = <3>; 518 status = "disabled"; 519 }; 520 521 pwm2: pwm@fdd70020 { 522 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 523 reg = <0x0 0xfdd70020 0x0 0x10>; 524 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 525 clock-names = "pwm", "pclk"; 526 pinctrl-0 = <&pwm2m0_pins>; 527 pinctrl-names = "default"; 528 #pwm-cells = <3>; 529 status = "disabled"; 530 }; 531 532 pwm3: pwm@fdd70030 { 533 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 534 reg = <0x0 0xfdd70030 0x0 0x10>; 535 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 536 clock-names = "pwm", "pclk"; 537 pinctrl-0 = <&pwm3_pins>; 538 pinctrl-names = "default"; 539 #pwm-cells = <3>; 540 status = "disabled"; 541 }; 542 543 pmu: power-management@fdd90000 { 544 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 545 reg = <0x0 0xfdd90000 0x0 0x1000>; 546 547 power: power-controller { 548 compatible = "rockchip,rk3568-power-controller"; 549 #power-domain-cells = <1>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 553 /* These power domains are grouped by VD_GPU */ 554 power-domain@RK3568_PD_GPU { 555 reg = <RK3568_PD_GPU>; 556 clocks = <&cru ACLK_GPU_PRE>, 557 <&cru PCLK_GPU_PRE>; 558 pm_qos = <&qos_gpu>; 559 #power-domain-cells = <0>; 560 }; 561 562 /* These power domains are grouped by VD_LOGIC */ 563 power-domain@RK3568_PD_VI { 564 reg = <RK3568_PD_VI>; 565 clocks = <&cru HCLK_VI>, 566 <&cru PCLK_VI>; 567 pm_qos = <&qos_isp>, 568 <&qos_vicap0>, 569 <&qos_vicap1>; 570 #power-domain-cells = <0>; 571 }; 572 573 power-domain@RK3568_PD_VO { 574 reg = <RK3568_PD_VO>; 575 clocks = <&cru HCLK_VO>, 576 <&cru PCLK_VO>, 577 <&cru ACLK_VOP_PRE>; 578 pm_qos = <&qos_hdcp>, 579 <&qos_vop_m0>, 580 <&qos_vop_m1>; 581 #power-domain-cells = <0>; 582 }; 583 584 power-domain@RK3568_PD_RGA { 585 reg = <RK3568_PD_RGA>; 586 clocks = <&cru HCLK_RGA_PRE>, 587 <&cru PCLK_RGA_PRE>; 588 pm_qos = <&qos_ebc>, 589 <&qos_iep>, 590 <&qos_jpeg_dec>, 591 <&qos_jpeg_enc>, 592 <&qos_rga_rd>, 593 <&qos_rga_wr>; 594 #power-domain-cells = <0>; 595 }; 596 597 power-domain@RK3568_PD_VPU { 598 reg = <RK3568_PD_VPU>; 599 clocks = <&cru HCLK_VPU_PRE>; 600 pm_qos = <&qos_vpu>; 601 #power-domain-cells = <0>; 602 }; 603 604 power-domain@RK3568_PD_RKVDEC { 605 clocks = <&cru HCLK_RKVDEC_PRE>; 606 reg = <RK3568_PD_RKVDEC>; 607 pm_qos = <&qos_rkvdec>; 608 #power-domain-cells = <0>; 609 }; 610 611 power-domain@RK3568_PD_RKVENC { 612 reg = <RK3568_PD_RKVENC>; 613 clocks = <&cru HCLK_RKVENC_PRE>; 614 pm_qos = <&qos_rkvenc_rd_m0>, 615 <&qos_rkvenc_rd_m1>, 616 <&qos_rkvenc_wr_m0>; 617 #power-domain-cells = <0>; 618 }; 619 }; 620 }; 621 622 gpu: gpu@fde60000 { 623 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; 624 reg = <0x0 0xfde60000 0x0 0x4000>; 625 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 628 interrupt-names = "job", "mmu", "gpu"; 629 clocks = <&scmi_clk 1>, <&cru CLK_GPU>; 630 clock-names = "gpu", "bus"; 631 #cooling-cells = <2>; 632 operating-points-v2 = <&gpu_opp_table>; 633 power-domains = <&power RK3568_PD_GPU>; 634 status = "disabled"; 635 }; 636 637 vpu: video-codec@fdea0400 { 638 compatible = "rockchip,rk3568-vpu"; 639 reg = <0x0 0xfdea0000 0x0 0x800>; 640 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 641 interrupt-names = "vdpu"; 642 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 643 clock-names = "aclk", "hclk"; 644 iommus = <&vdpu_mmu>; 645 power-domains = <&power RK3568_PD_VPU>; 646 }; 647 648 vdpu_mmu: iommu@fdea0800 { 649 compatible = "rockchip,rk3568-iommu"; 650 reg = <0x0 0xfdea0800 0x0 0x40>; 651 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 652 clock-names = "aclk", "iface"; 653 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 654 power-domains = <&power RK3568_PD_VPU>; 655 #iommu-cells = <0>; 656 }; 657 658 rga: rga@fdeb0000 { 659 compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; 660 reg = <0x0 0xfdeb0000 0x0 0x180>; 661 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; 663 clock-names = "aclk", "hclk", "sclk"; 664 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 665 reset-names = "core", "axi", "ahb"; 666 power-domains = <&power RK3568_PD_RGA>; 667 }; 668 669 vepu: video-codec@fdee0000 { 670 compatible = "rockchip,rk3568-vepu"; 671 reg = <0x0 0xfdee0000 0x0 0x800>; 672 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 674 clock-names = "aclk", "hclk"; 675 iommus = <&vepu_mmu>; 676 power-domains = <&power RK3568_PD_RGA>; 677 }; 678 679 vepu_mmu: iommu@fdee0800 { 680 compatible = "rockchip,rk3568-iommu"; 681 reg = <0x0 0xfdee0800 0x0 0x40>; 682 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 684 clock-names = "aclk", "iface"; 685 power-domains = <&power RK3568_PD_RGA>; 686 #iommu-cells = <0>; 687 }; 688 689 sdmmc2: mmc@fe000000 { 690 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 691 reg = <0x0 0xfe000000 0x0 0x4000>; 692 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 694 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 695 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 696 fifo-depth = <0x100>; 697 max-frequency = <150000000>; 698 resets = <&cru SRST_SDMMC2>; 699 reset-names = "reset"; 700 status = "disabled"; 701 }; 702 703 gmac1: ethernet@fe010000 { 704 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 705 reg = <0x0 0xfe010000 0x0 0x10000>; 706 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 708 interrupt-names = "macirq", "eth_wake_irq"; 709 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 710 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 711 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 712 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 713 clock-names = "stmmaceth", "mac_clk_rx", 714 "mac_clk_tx", "clk_mac_refout", 715 "aclk_mac", "pclk_mac", 716 "clk_mac_speed", "ptp_ref"; 717 resets = <&cru SRST_A_GMAC1>; 718 reset-names = "stmmaceth"; 719 rockchip,grf = <&grf>; 720 snps,axi-config = <&gmac1_stmmac_axi_setup>; 721 snps,mixed-burst; 722 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 723 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 724 snps,tso; 725 status = "disabled"; 726 727 mdio1: mdio { 728 compatible = "snps,dwmac-mdio"; 729 #address-cells = <0x1>; 730 #size-cells = <0x0>; 731 }; 732 733 gmac1_stmmac_axi_setup: stmmac-axi-config { 734 snps,blen = <0 0 0 0 16 8 4>; 735 snps,rd_osr_lmt = <8>; 736 snps,wr_osr_lmt = <4>; 737 }; 738 739 gmac1_mtl_rx_setup: rx-queues-config { 740 snps,rx-queues-to-use = <1>; 741 queue0 {}; 742 }; 743 744 gmac1_mtl_tx_setup: tx-queues-config { 745 snps,tx-queues-to-use = <1>; 746 queue0 {}; 747 }; 748 }; 749 750 vop: vop@fe040000 { 751 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; 752 reg-names = "vop", "gamma-lut"; 753 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, 755 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; 756 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; 757 iommus = <&vop_mmu>; 758 power-domains = <&power RK3568_PD_VO>; 759 rockchip,grf = <&grf>; 760 status = "disabled"; 761 762 vop_out: ports { 763 #address-cells = <1>; 764 #size-cells = <0>; 765 766 vp0: port@0 { 767 reg = <0>; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 }; 771 772 vp1: port@1 { 773 reg = <1>; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 }; 777 778 vp2: port@2 { 779 reg = <2>; 780 #address-cells = <1>; 781 #size-cells = <0>; 782 }; 783 }; 784 }; 785 786 vop_mmu: iommu@fe043e00 { 787 compatible = "rockchip,rk3568-iommu"; 788 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; 789 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 791 clock-names = "aclk", "iface"; 792 #iommu-cells = <0>; 793 power-domains = <&power RK3568_PD_VO>; 794 status = "disabled"; 795 }; 796 797 dsi0: dsi@fe060000 { 798 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 799 reg = <0x00 0xfe060000 0x00 0x10000>; 800 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 801 clock-names = "pclk"; 802 clocks = <&cru PCLK_DSITX_0>; 803 phy-names = "dphy"; 804 phys = <&dsi_dphy0>; 805 power-domains = <&power RK3568_PD_VO>; 806 reset-names = "apb"; 807 resets = <&cru SRST_P_DSITX_0>; 808 rockchip,grf = <&grf>; 809 status = "disabled"; 810 811 ports { 812 #address-cells = <1>; 813 #size-cells = <0>; 814 815 dsi0_in: port@0 { 816 reg = <0>; 817 }; 818 819 dsi0_out: port@1 { 820 reg = <1>; 821 }; 822 }; 823 }; 824 825 dsi1: dsi@fe070000 { 826 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 827 reg = <0x0 0xfe070000 0x0 0x10000>; 828 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 829 clock-names = "pclk"; 830 clocks = <&cru PCLK_DSITX_1>; 831 phy-names = "dphy"; 832 phys = <&dsi_dphy1>; 833 power-domains = <&power RK3568_PD_VO>; 834 reset-names = "apb"; 835 resets = <&cru SRST_P_DSITX_1>; 836 rockchip,grf = <&grf>; 837 status = "disabled"; 838 839 ports { 840 #address-cells = <1>; 841 #size-cells = <0>; 842 843 dsi1_in: port@0 { 844 reg = <0>; 845 }; 846 847 dsi1_out: port@1 { 848 reg = <1>; 849 }; 850 }; 851 }; 852 853 hdmi: hdmi@fe0a0000 { 854 compatible = "rockchip,rk3568-dw-hdmi"; 855 reg = <0x0 0xfe0a0000 0x0 0x20000>; 856 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&cru PCLK_HDMI_HOST>, 858 <&cru CLK_HDMI_SFR>, 859 <&cru CLK_HDMI_CEC>, 860 <&pmucru CLK_HDMI_REF>, 861 <&cru HCLK_VO>; 862 clock-names = "iahb", "isfr", "cec", "ref"; 863 pinctrl-names = "default"; 864 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; 865 power-domains = <&power RK3568_PD_VO>; 866 reg-io-width = <4>; 867 rockchip,grf = <&grf>; 868 #sound-dai-cells = <0>; 869 status = "disabled"; 870 871 ports { 872 #address-cells = <1>; 873 #size-cells = <0>; 874 875 hdmi_in: port@0 { 876 reg = <0>; 877 }; 878 879 hdmi_out: port@1 { 880 reg = <1>; 881 }; 882 }; 883 }; 884 885 qos_gpu: qos@fe128000 { 886 compatible = "rockchip,rk3568-qos", "syscon"; 887 reg = <0x0 0xfe128000 0x0 0x20>; 888 }; 889 890 qos_rkvenc_rd_m0: qos@fe138080 { 891 compatible = "rockchip,rk3568-qos", "syscon"; 892 reg = <0x0 0xfe138080 0x0 0x20>; 893 }; 894 895 qos_rkvenc_rd_m1: qos@fe138100 { 896 compatible = "rockchip,rk3568-qos", "syscon"; 897 reg = <0x0 0xfe138100 0x0 0x20>; 898 }; 899 900 qos_rkvenc_wr_m0: qos@fe138180 { 901 compatible = "rockchip,rk3568-qos", "syscon"; 902 reg = <0x0 0xfe138180 0x0 0x20>; 903 }; 904 905 qos_isp: qos@fe148000 { 906 compatible = "rockchip,rk3568-qos", "syscon"; 907 reg = <0x0 0xfe148000 0x0 0x20>; 908 }; 909 910 qos_vicap0: qos@fe148080 { 911 compatible = "rockchip,rk3568-qos", "syscon"; 912 reg = <0x0 0xfe148080 0x0 0x20>; 913 }; 914 915 qos_vicap1: qos@fe148100 { 916 compatible = "rockchip,rk3568-qos", "syscon"; 917 reg = <0x0 0xfe148100 0x0 0x20>; 918 }; 919 920 qos_vpu: qos@fe150000 { 921 compatible = "rockchip,rk3568-qos", "syscon"; 922 reg = <0x0 0xfe150000 0x0 0x20>; 923 }; 924 925 qos_ebc: qos@fe158000 { 926 compatible = "rockchip,rk3568-qos", "syscon"; 927 reg = <0x0 0xfe158000 0x0 0x20>; 928 }; 929 930 qos_iep: qos@fe158100 { 931 compatible = "rockchip,rk3568-qos", "syscon"; 932 reg = <0x0 0xfe158100 0x0 0x20>; 933 }; 934 935 qos_jpeg_dec: qos@fe158180 { 936 compatible = "rockchip,rk3568-qos", "syscon"; 937 reg = <0x0 0xfe158180 0x0 0x20>; 938 }; 939 940 qos_jpeg_enc: qos@fe158200 { 941 compatible = "rockchip,rk3568-qos", "syscon"; 942 reg = <0x0 0xfe158200 0x0 0x20>; 943 }; 944 945 qos_rga_rd: qos@fe158280 { 946 compatible = "rockchip,rk3568-qos", "syscon"; 947 reg = <0x0 0xfe158280 0x0 0x20>; 948 }; 949 950 qos_rga_wr: qos@fe158300 { 951 compatible = "rockchip,rk3568-qos", "syscon"; 952 reg = <0x0 0xfe158300 0x0 0x20>; 953 }; 954 955 qos_npu: qos@fe180000 { 956 compatible = "rockchip,rk3568-qos", "syscon"; 957 reg = <0x0 0xfe180000 0x0 0x20>; 958 }; 959 960 qos_pcie2x1: qos@fe190000 { 961 compatible = "rockchip,rk3568-qos", "syscon"; 962 reg = <0x0 0xfe190000 0x0 0x20>; 963 }; 964 965 qos_sata1: qos@fe190280 { 966 compatible = "rockchip,rk3568-qos", "syscon"; 967 reg = <0x0 0xfe190280 0x0 0x20>; 968 }; 969 970 qos_sata2: qos@fe190300 { 971 compatible = "rockchip,rk3568-qos", "syscon"; 972 reg = <0x0 0xfe190300 0x0 0x20>; 973 }; 974 975 qos_usb3_0: qos@fe190380 { 976 compatible = "rockchip,rk3568-qos", "syscon"; 977 reg = <0x0 0xfe190380 0x0 0x20>; 978 }; 979 980 qos_usb3_1: qos@fe190400 { 981 compatible = "rockchip,rk3568-qos", "syscon"; 982 reg = <0x0 0xfe190400 0x0 0x20>; 983 }; 984 985 qos_rkvdec: qos@fe198000 { 986 compatible = "rockchip,rk3568-qos", "syscon"; 987 reg = <0x0 0xfe198000 0x0 0x20>; 988 }; 989 990 qos_hdcp: qos@fe1a8000 { 991 compatible = "rockchip,rk3568-qos", "syscon"; 992 reg = <0x0 0xfe1a8000 0x0 0x20>; 993 }; 994 995 qos_vop_m0: qos@fe1a8080 { 996 compatible = "rockchip,rk3568-qos", "syscon"; 997 reg = <0x0 0xfe1a8080 0x0 0x20>; 998 }; 999 1000 qos_vop_m1: qos@fe1a8100 { 1001 compatible = "rockchip,rk3568-qos", "syscon"; 1002 reg = <0x0 0xfe1a8100 0x0 0x20>; 1003 }; 1004 1005 dfi: dfi@fe230000 { 1006 compatible = "rockchip,rk3568-dfi"; 1007 reg = <0x00 0xfe230000 0x00 0x400>; 1008 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1009 rockchip,pmu = <&pmugrf>; 1010 }; 1011 1012 pcie2x1: pcie@fe260000 { 1013 compatible = "rockchip,rk3568-pcie"; 1014 reg = <0x3 0xc0000000 0x0 0x00400000>, 1015 <0x0 0xfe260000 0x0 0x00010000>, 1016 <0x0 0xf4000000 0x0 0x00100000>; 1017 reg-names = "dbi", "apb", "config"; 1018 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1023 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1024 bus-range = <0x0 0xf>; 1025 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 1026 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, 1027 <&cru CLK_PCIE20_AUX_NDFT>; 1028 clock-names = "aclk_mst", "aclk_slv", 1029 "aclk_dbi", "pclk", "aux"; 1030 device_type = "pci"; 1031 #interrupt-cells = <1>; 1032 interrupt-map-mask = <0 0 0 7>; 1033 interrupt-map = <0 0 0 1 &pcie_intc 0>, 1034 <0 0 0 2 &pcie_intc 1>, 1035 <0 0 0 3 &pcie_intc 2>, 1036 <0 0 0 4 &pcie_intc 3>; 1037 linux,pci-domain = <0>; 1038 num-ib-windows = <6>; 1039 num-ob-windows = <2>; 1040 max-link-speed = <2>; 1041 msi-map = <0x0 &gic 0x0 0x1000>; 1042 num-lanes = <1>; 1043 phys = <&combphy2 PHY_TYPE_PCIE>; 1044 phy-names = "pcie-phy"; 1045 power-domains = <&power RK3568_PD_PIPE>; 1046 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 1047 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, 1048 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; 1049 resets = <&cru SRST_PCIE20_POWERUP>; 1050 reset-names = "pipe"; 1051 #address-cells = <3>; 1052 #size-cells = <2>; 1053 status = "disabled"; 1054 1055 pcie_intc: legacy-interrupt-controller { 1056 #address-cells = <0>; 1057 #interrupt-cells = <1>; 1058 interrupt-controller; 1059 interrupt-parent = <&gic>; 1060 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 1061 }; 1062 }; 1063 1064 sdmmc0: mmc@fe2b0000 { 1065 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 1066 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1067 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 1069 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 1070 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1071 fifo-depth = <0x100>; 1072 max-frequency = <150000000>; 1073 resets = <&cru SRST_SDMMC0>; 1074 reset-names = "reset"; 1075 status = "disabled"; 1076 }; 1077 1078 sdmmc1: mmc@fe2c0000 { 1079 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 1080 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1081 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1082 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 1083 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 1084 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1085 fifo-depth = <0x100>; 1086 max-frequency = <150000000>; 1087 resets = <&cru SRST_SDMMC1>; 1088 reset-names = "reset"; 1089 status = "disabled"; 1090 }; 1091 1092 sfc: spi@fe300000 { 1093 compatible = "rockchip,sfc"; 1094 reg = <0x0 0xfe300000 0x0 0x4000>; 1095 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1097 clock-names = "clk_sfc", "hclk_sfc"; 1098 pinctrl-0 = <&fspi_pins>; 1099 pinctrl-names = "default"; 1100 status = "disabled"; 1101 }; 1102 1103 sdhci: mmc@fe310000 { 1104 compatible = "rockchip,rk3568-dwcmshc"; 1105 reg = <0x0 0xfe310000 0x0 0x10000>; 1106 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1107 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 1108 assigned-clock-rates = <200000000>, <24000000>; 1109 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1110 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1111 <&cru TCLK_EMMC>; 1112 clock-names = "core", "bus", "axi", "block", "timer"; 1113 status = "disabled"; 1114 }; 1115 1116 i2s0_8ch: i2s@fe400000 { 1117 compatible = "rockchip,rk3568-i2s-tdm"; 1118 reg = <0x0 0xfe400000 0x0 0x1000>; 1119 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1120 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1121 assigned-clock-rates = <1188000000>, <1188000000>; 1122 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1123 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1124 dmas = <&dmac1 0>; 1125 dma-names = "tx"; 1126 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1127 reset-names = "tx-m", "rx-m"; 1128 rockchip,grf = <&grf>; 1129 #sound-dai-cells = <0>; 1130 status = "disabled"; 1131 }; 1132 1133 i2s1_8ch: i2s@fe410000 { 1134 compatible = "rockchip,rk3568-i2s-tdm"; 1135 reg = <0x0 0xfe410000 0x0 0x1000>; 1136 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1137 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; 1138 assigned-clock-rates = <1188000000>, <1188000000>; 1139 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, 1140 <&cru HCLK_I2S1_8CH>; 1141 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1142 dmas = <&dmac1 3>, <&dmac1 2>; 1143 dma-names = "rx", "tx"; 1144 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1145 reset-names = "tx-m", "rx-m"; 1146 rockchip,grf = <&grf>; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx 1149 &i2s1m0_lrcktx &i2s1m0_lrckrx 1150 &i2s1m0_sdi0 &i2s1m0_sdi1 1151 &i2s1m0_sdi2 &i2s1m0_sdi3 1152 &i2s1m0_sdo0 &i2s1m0_sdo1 1153 &i2s1m0_sdo2 &i2s1m0_sdo3>; 1154 #sound-dai-cells = <0>; 1155 status = "disabled"; 1156 }; 1157 1158 i2s2_2ch: i2s@fe420000 { 1159 compatible = "rockchip,rk3568-i2s-tdm"; 1160 reg = <0x0 0xfe420000 0x0 0x1000>; 1161 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1162 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1163 assigned-clock-rates = <1188000000>; 1164 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1165 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1166 dmas = <&dmac1 4>, <&dmac1 5>; 1167 dma-names = "tx", "rx"; 1168 resets = <&cru SRST_M_I2S2_2CH>; 1169 reset-names = "tx-m"; 1170 rockchip,grf = <&grf>; 1171 pinctrl-names = "default"; 1172 pinctrl-0 = <&i2s2m0_sclktx 1173 &i2s2m0_lrcktx 1174 &i2s2m0_sdi 1175 &i2s2m0_sdo>; 1176 #sound-dai-cells = <0>; 1177 status = "disabled"; 1178 }; 1179 1180 i2s3_2ch: i2s@fe430000 { 1181 compatible = "rockchip,rk3568-i2s-tdm"; 1182 reg = <0x0 0xfe430000 0x0 0x1000>; 1183 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1184 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, 1185 <&cru HCLK_I2S3_2CH>; 1186 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1187 dmas = <&dmac1 6>, <&dmac1 7>; 1188 dma-names = "tx", "rx"; 1189 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; 1190 reset-names = "tx-m", "rx-m"; 1191 rockchip,grf = <&grf>; 1192 #sound-dai-cells = <0>; 1193 status = "disabled"; 1194 }; 1195 1196 pdm: pdm@fe440000 { 1197 compatible = "rockchip,rk3568-pdm"; 1198 reg = <0x0 0xfe440000 0x0 0x1000>; 1199 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1200 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1201 clock-names = "pdm_clk", "pdm_hclk"; 1202 dmas = <&dmac1 9>; 1203 dma-names = "rx"; 1204 pinctrl-0 = <&pdmm0_clk 1205 &pdmm0_clk1 1206 &pdmm0_sdi0 1207 &pdmm0_sdi1 1208 &pdmm0_sdi2 1209 &pdmm0_sdi3>; 1210 pinctrl-names = "default"; 1211 resets = <&cru SRST_M_PDM>; 1212 reset-names = "pdm-m"; 1213 #sound-dai-cells = <0>; 1214 status = "disabled"; 1215 }; 1216 1217 spdif: spdif@fe460000 { 1218 compatible = "rockchip,rk3568-spdif"; 1219 reg = <0x0 0xfe460000 0x0 0x1000>; 1220 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1221 clock-names = "mclk", "hclk"; 1222 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 1223 dmas = <&dmac1 1>; 1224 dma-names = "tx"; 1225 pinctrl-names = "default"; 1226 pinctrl-0 = <&spdifm0_tx>; 1227 #sound-dai-cells = <0>; 1228 status = "disabled"; 1229 }; 1230 1231 dmac0: dma-controller@fe530000 { 1232 compatible = "arm,pl330", "arm,primecell"; 1233 reg = <0x0 0xfe530000 0x0 0x4000>; 1234 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1236 arm,pl330-periph-burst; 1237 clocks = <&cru ACLK_BUS>; 1238 clock-names = "apb_pclk"; 1239 #dma-cells = <1>; 1240 }; 1241 1242 dmac1: dma-controller@fe550000 { 1243 compatible = "arm,pl330", "arm,primecell"; 1244 reg = <0x0 0xfe550000 0x0 0x4000>; 1245 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1247 arm,pl330-periph-burst; 1248 clocks = <&cru ACLK_BUS>; 1249 clock-names = "apb_pclk"; 1250 #dma-cells = <1>; 1251 }; 1252 1253 i2c1: i2c@fe5a0000 { 1254 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1255 reg = <0x0 0xfe5a0000 0x0 0x1000>; 1256 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1258 clock-names = "i2c", "pclk"; 1259 pinctrl-0 = <&i2c1_xfer>; 1260 pinctrl-names = "default"; 1261 #address-cells = <1>; 1262 #size-cells = <0>; 1263 status = "disabled"; 1264 }; 1265 1266 i2c2: i2c@fe5b0000 { 1267 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1268 reg = <0x0 0xfe5b0000 0x0 0x1000>; 1269 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1270 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1271 clock-names = "i2c", "pclk"; 1272 pinctrl-0 = <&i2c2m0_xfer>; 1273 pinctrl-names = "default"; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 status = "disabled"; 1277 }; 1278 1279 i2c3: i2c@fe5c0000 { 1280 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1281 reg = <0x0 0xfe5c0000 0x0 0x1000>; 1282 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1284 clock-names = "i2c", "pclk"; 1285 pinctrl-0 = <&i2c3m0_xfer>; 1286 pinctrl-names = "default"; 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 status = "disabled"; 1290 }; 1291 1292 i2c4: i2c@fe5d0000 { 1293 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1294 reg = <0x0 0xfe5d0000 0x0 0x1000>; 1295 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1296 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1297 clock-names = "i2c", "pclk"; 1298 pinctrl-0 = <&i2c4m0_xfer>; 1299 pinctrl-names = "default"; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 status = "disabled"; 1303 }; 1304 1305 i2c5: i2c@fe5e0000 { 1306 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1307 reg = <0x0 0xfe5e0000 0x0 0x1000>; 1308 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1309 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1310 clock-names = "i2c", "pclk"; 1311 pinctrl-0 = <&i2c5m0_xfer>; 1312 pinctrl-names = "default"; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 status = "disabled"; 1316 }; 1317 1318 wdt: watchdog@fe600000 { 1319 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; 1320 reg = <0x0 0xfe600000 0x0 0x100>; 1321 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 1322 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 1323 clock-names = "tclk", "pclk"; 1324 }; 1325 1326 spi0: spi@fe610000 { 1327 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1328 reg = <0x0 0xfe610000 0x0 0x1000>; 1329 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1330 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1331 clock-names = "spiclk", "apb_pclk"; 1332 dmas = <&dmac0 20>, <&dmac0 21>; 1333 dma-names = "tx", "rx"; 1334 pinctrl-names = "default"; 1335 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 status = "disabled"; 1339 }; 1340 1341 spi1: spi@fe620000 { 1342 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1343 reg = <0x0 0xfe620000 0x0 0x1000>; 1344 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1345 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1346 clock-names = "spiclk", "apb_pclk"; 1347 dmas = <&dmac0 22>, <&dmac0 23>; 1348 dma-names = "tx", "rx"; 1349 pinctrl-names = "default"; 1350 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 1351 #address-cells = <1>; 1352 #size-cells = <0>; 1353 status = "disabled"; 1354 }; 1355 1356 spi2: spi@fe630000 { 1357 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1358 reg = <0x0 0xfe630000 0x0 0x1000>; 1359 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1360 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1361 clock-names = "spiclk", "apb_pclk"; 1362 dmas = <&dmac0 24>, <&dmac0 25>; 1363 dma-names = "tx", "rx"; 1364 pinctrl-names = "default"; 1365 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 1366 #address-cells = <1>; 1367 #size-cells = <0>; 1368 status = "disabled"; 1369 }; 1370 1371 spi3: spi@fe640000 { 1372 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1373 reg = <0x0 0xfe640000 0x0 0x1000>; 1374 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1375 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1376 clock-names = "spiclk", "apb_pclk"; 1377 dmas = <&dmac0 26>, <&dmac0 27>; 1378 dma-names = "tx", "rx"; 1379 pinctrl-names = "default"; 1380 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 status = "disabled"; 1384 }; 1385 1386 uart1: serial@fe650000 { 1387 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1388 reg = <0x0 0xfe650000 0x0 0x100>; 1389 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1390 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1391 clock-names = "baudclk", "apb_pclk"; 1392 dmas = <&dmac0 2>, <&dmac0 3>; 1393 pinctrl-0 = <&uart1m0_xfer>; 1394 pinctrl-names = "default"; 1395 reg-io-width = <4>; 1396 reg-shift = <2>; 1397 status = "disabled"; 1398 }; 1399 1400 uart2: serial@fe660000 { 1401 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1402 reg = <0x0 0xfe660000 0x0 0x100>; 1403 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1404 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1405 clock-names = "baudclk", "apb_pclk"; 1406 dmas = <&dmac0 4>, <&dmac0 5>; 1407 pinctrl-0 = <&uart2m0_xfer>; 1408 pinctrl-names = "default"; 1409 reg-io-width = <4>; 1410 reg-shift = <2>; 1411 status = "disabled"; 1412 }; 1413 1414 uart3: serial@fe670000 { 1415 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1416 reg = <0x0 0xfe670000 0x0 0x100>; 1417 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1418 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1419 clock-names = "baudclk", "apb_pclk"; 1420 dmas = <&dmac0 6>, <&dmac0 7>; 1421 pinctrl-0 = <&uart3m0_xfer>; 1422 pinctrl-names = "default"; 1423 reg-io-width = <4>; 1424 reg-shift = <2>; 1425 status = "disabled"; 1426 }; 1427 1428 uart4: serial@fe680000 { 1429 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1430 reg = <0x0 0xfe680000 0x0 0x100>; 1431 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1432 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1433 clock-names = "baudclk", "apb_pclk"; 1434 dmas = <&dmac0 8>, <&dmac0 9>; 1435 pinctrl-0 = <&uart4m0_xfer>; 1436 pinctrl-names = "default"; 1437 reg-io-width = <4>; 1438 reg-shift = <2>; 1439 status = "disabled"; 1440 }; 1441 1442 uart5: serial@fe690000 { 1443 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1444 reg = <0x0 0xfe690000 0x0 0x100>; 1445 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1446 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1447 clock-names = "baudclk", "apb_pclk"; 1448 dmas = <&dmac0 10>, <&dmac0 11>; 1449 pinctrl-0 = <&uart5m0_xfer>; 1450 pinctrl-names = "default"; 1451 reg-io-width = <4>; 1452 reg-shift = <2>; 1453 status = "disabled"; 1454 }; 1455 1456 uart6: serial@fe6a0000 { 1457 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1458 reg = <0x0 0xfe6a0000 0x0 0x100>; 1459 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1460 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1461 clock-names = "baudclk", "apb_pclk"; 1462 dmas = <&dmac0 12>, <&dmac0 13>; 1463 pinctrl-0 = <&uart6m0_xfer>; 1464 pinctrl-names = "default"; 1465 reg-io-width = <4>; 1466 reg-shift = <2>; 1467 status = "disabled"; 1468 }; 1469 1470 uart7: serial@fe6b0000 { 1471 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1472 reg = <0x0 0xfe6b0000 0x0 0x100>; 1473 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1474 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1475 clock-names = "baudclk", "apb_pclk"; 1476 dmas = <&dmac0 14>, <&dmac0 15>; 1477 pinctrl-0 = <&uart7m0_xfer>; 1478 pinctrl-names = "default"; 1479 reg-io-width = <4>; 1480 reg-shift = <2>; 1481 status = "disabled"; 1482 }; 1483 1484 uart8: serial@fe6c0000 { 1485 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1486 reg = <0x0 0xfe6c0000 0x0 0x100>; 1487 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1488 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1489 clock-names = "baudclk", "apb_pclk"; 1490 dmas = <&dmac0 16>, <&dmac0 17>; 1491 pinctrl-0 = <&uart8m0_xfer>; 1492 pinctrl-names = "default"; 1493 reg-io-width = <4>; 1494 reg-shift = <2>; 1495 status = "disabled"; 1496 }; 1497 1498 uart9: serial@fe6d0000 { 1499 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1500 reg = <0x0 0xfe6d0000 0x0 0x100>; 1501 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1502 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1503 clock-names = "baudclk", "apb_pclk"; 1504 dmas = <&dmac0 18>, <&dmac0 19>; 1505 pinctrl-0 = <&uart9m0_xfer>; 1506 pinctrl-names = "default"; 1507 reg-io-width = <4>; 1508 reg-shift = <2>; 1509 status = "disabled"; 1510 }; 1511 1512 thermal_zones: thermal-zones { 1513 cpu_thermal: cpu-thermal { 1514 polling-delay-passive = <100>; 1515 polling-delay = <1000>; 1516 1517 thermal-sensors = <&tsadc 0>; 1518 1519 trips { 1520 cpu_alert0: cpu_alert0 { 1521 temperature = <70000>; 1522 hysteresis = <2000>; 1523 type = "passive"; 1524 }; 1525 cpu_alert1: cpu_alert1 { 1526 temperature = <75000>; 1527 hysteresis = <2000>; 1528 type = "passive"; 1529 }; 1530 cpu_crit: cpu_crit { 1531 temperature = <95000>; 1532 hysteresis = <2000>; 1533 type = "critical"; 1534 }; 1535 }; 1536 1537 cooling-maps { 1538 map0 { 1539 trip = <&cpu_alert0>; 1540 cooling-device = 1541 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1542 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1543 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1544 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1545 }; 1546 }; 1547 }; 1548 1549 gpu_thermal: gpu-thermal { 1550 polling-delay-passive = <20>; /* milliseconds */ 1551 polling-delay = <1000>; /* milliseconds */ 1552 1553 thermal-sensors = <&tsadc 1>; 1554 1555 trips { 1556 gpu_threshold: gpu-threshold { 1557 temperature = <70000>; 1558 hysteresis = <2000>; 1559 type = "passive"; 1560 }; 1561 gpu_target: gpu-target { 1562 temperature = <75000>; 1563 hysteresis = <2000>; 1564 type = "passive"; 1565 }; 1566 gpu_crit: gpu-crit { 1567 temperature = <95000>; 1568 hysteresis = <2000>; 1569 type = "critical"; 1570 }; 1571 }; 1572 1573 cooling-maps { 1574 map0 { 1575 trip = <&gpu_target>; 1576 cooling-device = 1577 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1578 }; 1579 }; 1580 }; 1581 }; 1582 1583 tsadc: tsadc@fe710000 { 1584 compatible = "rockchip,rk3568-tsadc"; 1585 reg = <0x0 0xfe710000 0x0 0x100>; 1586 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1587 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 1588 assigned-clock-rates = <17000000>, <700000>; 1589 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 1590 clock-names = "tsadc", "apb_pclk"; 1591 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, 1592 <&cru SRST_TSADCPHY>; 1593 rockchip,grf = <&grf>; 1594 rockchip,hw-tshut-temp = <95000>; 1595 pinctrl-names = "init", "default", "sleep"; 1596 pinctrl-0 = <&tsadc_pin>; 1597 pinctrl-1 = <&tsadc_shutorg>; 1598 pinctrl-2 = <&tsadc_pin>; 1599 #thermal-sensor-cells = <1>; 1600 status = "disabled"; 1601 }; 1602 1603 saradc: saradc@fe720000 { 1604 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 1605 reg = <0x0 0xfe720000 0x0 0x100>; 1606 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1607 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1608 clock-names = "saradc", "apb_pclk"; 1609 resets = <&cru SRST_P_SARADC>; 1610 reset-names = "saradc-apb"; 1611 #io-channel-cells = <1>; 1612 status = "disabled"; 1613 }; 1614 1615 pwm4: pwm@fe6e0000 { 1616 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1617 reg = <0x0 0xfe6e0000 0x0 0x10>; 1618 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1619 clock-names = "pwm", "pclk"; 1620 pinctrl-0 = <&pwm4_pins>; 1621 pinctrl-names = "default"; 1622 #pwm-cells = <3>; 1623 status = "disabled"; 1624 }; 1625 1626 pwm5: pwm@fe6e0010 { 1627 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1628 reg = <0x0 0xfe6e0010 0x0 0x10>; 1629 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1630 clock-names = "pwm", "pclk"; 1631 pinctrl-0 = <&pwm5_pins>; 1632 pinctrl-names = "default"; 1633 #pwm-cells = <3>; 1634 status = "disabled"; 1635 }; 1636 1637 pwm6: pwm@fe6e0020 { 1638 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1639 reg = <0x0 0xfe6e0020 0x0 0x10>; 1640 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1641 clock-names = "pwm", "pclk"; 1642 pinctrl-0 = <&pwm6_pins>; 1643 pinctrl-names = "default"; 1644 #pwm-cells = <3>; 1645 status = "disabled"; 1646 }; 1647 1648 pwm7: pwm@fe6e0030 { 1649 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1650 reg = <0x0 0xfe6e0030 0x0 0x10>; 1651 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1652 clock-names = "pwm", "pclk"; 1653 pinctrl-0 = <&pwm7_pins>; 1654 pinctrl-names = "default"; 1655 #pwm-cells = <3>; 1656 status = "disabled"; 1657 }; 1658 1659 pwm8: pwm@fe6f0000 { 1660 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1661 reg = <0x0 0xfe6f0000 0x0 0x10>; 1662 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1663 clock-names = "pwm", "pclk"; 1664 pinctrl-0 = <&pwm8m0_pins>; 1665 pinctrl-names = "default"; 1666 #pwm-cells = <3>; 1667 status = "disabled"; 1668 }; 1669 1670 pwm9: pwm@fe6f0010 { 1671 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1672 reg = <0x0 0xfe6f0010 0x0 0x10>; 1673 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1674 clock-names = "pwm", "pclk"; 1675 pinctrl-0 = <&pwm9m0_pins>; 1676 pinctrl-names = "default"; 1677 #pwm-cells = <3>; 1678 status = "disabled"; 1679 }; 1680 1681 pwm10: pwm@fe6f0020 { 1682 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1683 reg = <0x0 0xfe6f0020 0x0 0x10>; 1684 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1685 clock-names = "pwm", "pclk"; 1686 pinctrl-0 = <&pwm10m0_pins>; 1687 pinctrl-names = "default"; 1688 #pwm-cells = <3>; 1689 status = "disabled"; 1690 }; 1691 1692 pwm11: pwm@fe6f0030 { 1693 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1694 reg = <0x0 0xfe6f0030 0x0 0x10>; 1695 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1696 clock-names = "pwm", "pclk"; 1697 pinctrl-0 = <&pwm11m0_pins>; 1698 pinctrl-names = "default"; 1699 #pwm-cells = <3>; 1700 status = "disabled"; 1701 }; 1702 1703 pwm12: pwm@fe700000 { 1704 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1705 reg = <0x0 0xfe700000 0x0 0x10>; 1706 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1707 clock-names = "pwm", "pclk"; 1708 pinctrl-0 = <&pwm12m0_pins>; 1709 pinctrl-names = "default"; 1710 #pwm-cells = <3>; 1711 status = "disabled"; 1712 }; 1713 1714 pwm13: pwm@fe700010 { 1715 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1716 reg = <0x0 0xfe700010 0x0 0x10>; 1717 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1718 clock-names = "pwm", "pclk"; 1719 pinctrl-0 = <&pwm13m0_pins>; 1720 pinctrl-names = "default"; 1721 #pwm-cells = <3>; 1722 status = "disabled"; 1723 }; 1724 1725 pwm14: pwm@fe700020 { 1726 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1727 reg = <0x0 0xfe700020 0x0 0x10>; 1728 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1729 clock-names = "pwm", "pclk"; 1730 pinctrl-0 = <&pwm14m0_pins>; 1731 pinctrl-names = "default"; 1732 #pwm-cells = <3>; 1733 status = "disabled"; 1734 }; 1735 1736 pwm15: pwm@fe700030 { 1737 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1738 reg = <0x0 0xfe700030 0x0 0x10>; 1739 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1740 clock-names = "pwm", "pclk"; 1741 pinctrl-0 = <&pwm15m0_pins>; 1742 pinctrl-names = "default"; 1743 #pwm-cells = <3>; 1744 status = "disabled"; 1745 }; 1746 1747 combphy1: phy@fe830000 { 1748 compatible = "rockchip,rk3568-naneng-combphy"; 1749 reg = <0x0 0xfe830000 0x0 0x100>; 1750 clocks = <&pmucru CLK_PCIEPHY1_REF>, 1751 <&cru PCLK_PIPEPHY1>, 1752 <&cru PCLK_PIPE>; 1753 clock-names = "ref", "apb", "pipe"; 1754 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; 1755 assigned-clock-rates = <100000000>; 1756 resets = <&cru SRST_PIPEPHY1>; 1757 rockchip,pipe-grf = <&pipegrf>; 1758 rockchip,pipe-phy-grf = <&pipe_phy_grf1>; 1759 #phy-cells = <1>; 1760 status = "disabled"; 1761 }; 1762 1763 combphy2: phy@fe840000 { 1764 compatible = "rockchip,rk3568-naneng-combphy"; 1765 reg = <0x0 0xfe840000 0x0 0x100>; 1766 clocks = <&pmucru CLK_PCIEPHY2_REF>, 1767 <&cru PCLK_PIPEPHY2>, 1768 <&cru PCLK_PIPE>; 1769 clock-names = "ref", "apb", "pipe"; 1770 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; 1771 assigned-clock-rates = <100000000>; 1772 resets = <&cru SRST_PIPEPHY2>; 1773 rockchip,pipe-grf = <&pipegrf>; 1774 rockchip,pipe-phy-grf = <&pipe_phy_grf2>; 1775 #phy-cells = <1>; 1776 status = "disabled"; 1777 }; 1778 1779 csi_dphy: phy@fe870000 { 1780 compatible = "rockchip,rk3568-csi-dphy"; 1781 reg = <0x0 0xfe870000 0x0 0x10000>; 1782 clocks = <&cru PCLK_MIPICSIPHY>; 1783 clock-names = "pclk"; 1784 #phy-cells = <0>; 1785 resets = <&cru SRST_P_MIPICSIPHY>; 1786 reset-names = "apb"; 1787 rockchip,grf = <&grf>; 1788 status = "disabled"; 1789 }; 1790 1791 dsi_dphy0: mipi-dphy@fe850000 { 1792 compatible = "rockchip,rk3568-dsi-dphy"; 1793 reg = <0x0 0xfe850000 0x0 0x10000>; 1794 clock-names = "ref", "pclk"; 1795 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; 1796 #phy-cells = <0>; 1797 power-domains = <&power RK3568_PD_VO>; 1798 reset-names = "apb"; 1799 resets = <&cru SRST_P_MIPIDSIPHY0>; 1800 status = "disabled"; 1801 }; 1802 1803 dsi_dphy1: mipi-dphy@fe860000 { 1804 compatible = "rockchip,rk3568-dsi-dphy"; 1805 reg = <0x0 0xfe860000 0x0 0x10000>; 1806 clock-names = "ref", "pclk"; 1807 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; 1808 #phy-cells = <0>; 1809 power-domains = <&power RK3568_PD_VO>; 1810 reset-names = "apb"; 1811 resets = <&cru SRST_P_MIPIDSIPHY1>; 1812 status = "disabled"; 1813 }; 1814 1815 usb2phy0: usb2phy@fe8a0000 { 1816 compatible = "rockchip,rk3568-usb2phy"; 1817 reg = <0x0 0xfe8a0000 0x0 0x10000>; 1818 clocks = <&pmucru CLK_USBPHY0_REF>; 1819 clock-names = "phyclk"; 1820 clock-output-names = "clk_usbphy0_480m"; 1821 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1822 rockchip,usbgrf = <&usb2phy0_grf>; 1823 #clock-cells = <0>; 1824 status = "disabled"; 1825 1826 usb2phy0_host: host-port { 1827 #phy-cells = <0>; 1828 status = "disabled"; 1829 }; 1830 1831 usb2phy0_otg: otg-port { 1832 #phy-cells = <0>; 1833 status = "disabled"; 1834 }; 1835 }; 1836 1837 usb2phy1: usb2phy@fe8b0000 { 1838 compatible = "rockchip,rk3568-usb2phy"; 1839 reg = <0x0 0xfe8b0000 0x0 0x10000>; 1840 clocks = <&pmucru CLK_USBPHY1_REF>; 1841 clock-names = "phyclk"; 1842 clock-output-names = "clk_usbphy1_480m"; 1843 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1844 rockchip,usbgrf = <&usb2phy1_grf>; 1845 #clock-cells = <0>; 1846 status = "disabled"; 1847 1848 usb2phy1_host: host-port { 1849 #phy-cells = <0>; 1850 status = "disabled"; 1851 }; 1852 1853 usb2phy1_otg: otg-port { 1854 #phy-cells = <0>; 1855 status = "disabled"; 1856 }; 1857 }; 1858 1859 pinctrl: pinctrl { 1860 compatible = "rockchip,rk3568-pinctrl"; 1861 rockchip,grf = <&grf>; 1862 rockchip,pmu = <&pmugrf>; 1863 #address-cells = <2>; 1864 #size-cells = <2>; 1865 ranges; 1866 1867 gpio0: gpio@fdd60000 { 1868 compatible = "rockchip,gpio-bank"; 1869 reg = <0x0 0xfdd60000 0x0 0x100>; 1870 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1871 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 1872 gpio-controller; 1873 gpio-ranges = <&pinctrl 0 0 32>; 1874 #gpio-cells = <2>; 1875 interrupt-controller; 1876 #interrupt-cells = <2>; 1877 }; 1878 1879 gpio1: gpio@fe740000 { 1880 compatible = "rockchip,gpio-bank"; 1881 reg = <0x0 0xfe740000 0x0 0x100>; 1882 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1883 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1884 gpio-controller; 1885 gpio-ranges = <&pinctrl 0 32 32>; 1886 #gpio-cells = <2>; 1887 interrupt-controller; 1888 #interrupt-cells = <2>; 1889 }; 1890 1891 gpio2: gpio@fe750000 { 1892 compatible = "rockchip,gpio-bank"; 1893 reg = <0x0 0xfe750000 0x0 0x100>; 1894 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1895 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1896 gpio-controller; 1897 gpio-ranges = <&pinctrl 0 64 32>; 1898 #gpio-cells = <2>; 1899 interrupt-controller; 1900 #interrupt-cells = <2>; 1901 }; 1902 1903 gpio3: gpio@fe760000 { 1904 compatible = "rockchip,gpio-bank"; 1905 reg = <0x0 0xfe760000 0x0 0x100>; 1906 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1907 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1908 gpio-controller; 1909 gpio-ranges = <&pinctrl 0 96 32>; 1910 #gpio-cells = <2>; 1911 interrupt-controller; 1912 #interrupt-cells = <2>; 1913 }; 1914 1915 gpio4: gpio@fe770000 { 1916 compatible = "rockchip,gpio-bank"; 1917 reg = <0x0 0xfe770000 0x0 0x100>; 1918 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1919 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1920 gpio-controller; 1921 gpio-ranges = <&pinctrl 0 128 32>; 1922 #gpio-cells = <2>; 1923 interrupt-controller; 1924 #interrupt-cells = <2>; 1925 }; 1926 }; 1927}; 1928 1929#include "rk3568-pinctrl.dtsi" 1930