1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3568-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 gpio0 = &gpio0; 22 gpio1 = &gpio1; 23 gpio2 = &gpio2; 24 gpio3 = &gpio3; 25 gpio4 = &gpio4; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 serial6 = &uart6; 39 serial7 = &uart7; 40 serial8 = &uart8; 41 serial9 = &uart9; 42 spi0 = &spi0; 43 spi1 = &spi1; 44 spi2 = &spi2; 45 spi3 = &spi3; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x0 0x0>; 56 clocks = <&scmi_clk 0>; 57 #cooling-cells = <2>; 58 enable-method = "psci"; 59 operating-points-v2 = <&cpu0_opp_table>; 60 i-cache-size = <0x8000>; 61 i-cache-line-size = <64>; 62 i-cache-sets = <128>; 63 d-cache-size = <0x8000>; 64 d-cache-line-size = <64>; 65 d-cache-sets = <128>; 66 next-level-cache = <&l3_cache>; 67 }; 68 69 cpu1: cpu@100 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a55"; 72 reg = <0x0 0x100>; 73 #cooling-cells = <2>; 74 enable-method = "psci"; 75 operating-points-v2 = <&cpu0_opp_table>; 76 i-cache-size = <0x8000>; 77 i-cache-line-size = <64>; 78 i-cache-sets = <128>; 79 d-cache-size = <0x8000>; 80 d-cache-line-size = <64>; 81 d-cache-sets = <128>; 82 next-level-cache = <&l3_cache>; 83 }; 84 85 cpu2: cpu@200 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a55"; 88 reg = <0x0 0x200>; 89 #cooling-cells = <2>; 90 enable-method = "psci"; 91 operating-points-v2 = <&cpu0_opp_table>; 92 i-cache-size = <0x8000>; 93 i-cache-line-size = <64>; 94 i-cache-sets = <128>; 95 d-cache-size = <0x8000>; 96 d-cache-line-size = <64>; 97 d-cache-sets = <128>; 98 next-level-cache = <&l3_cache>; 99 }; 100 101 cpu3: cpu@300 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a55"; 104 reg = <0x0 0x300>; 105 #cooling-cells = <2>; 106 enable-method = "psci"; 107 operating-points-v2 = <&cpu0_opp_table>; 108 i-cache-size = <0x8000>; 109 i-cache-line-size = <64>; 110 i-cache-sets = <128>; 111 d-cache-size = <0x8000>; 112 d-cache-line-size = <64>; 113 d-cache-sets = <128>; 114 next-level-cache = <&l3_cache>; 115 }; 116 }; 117 118 /* 119 * There are no private per-core L2 caches, but only the 120 * L3 cache that appears to the CPU cores as L2 caches 121 */ 122 l3_cache: l3-cache { 123 compatible = "cache"; 124 cache-level = <2>; 125 cache-unified; 126 cache-size = <0x80000>; 127 cache-line-size = <64>; 128 cache-sets = <512>; 129 }; 130 131 cpu0_opp_table: opp-table-0 { 132 compatible = "operating-points-v2"; 133 opp-shared; 134 135 opp-408000000 { 136 opp-hz = /bits/ 64 <408000000>; 137 opp-microvolt = <900000 900000 1150000>; 138 clock-latency-ns = <40000>; 139 }; 140 141 opp-600000000 { 142 opp-hz = /bits/ 64 <600000000>; 143 opp-microvolt = <900000 900000 1150000>; 144 }; 145 146 opp-816000000 { 147 opp-hz = /bits/ 64 <816000000>; 148 opp-microvolt = <900000 900000 1150000>; 149 opp-suspend; 150 }; 151 152 opp-1104000000 { 153 opp-hz = /bits/ 64 <1104000000>; 154 opp-microvolt = <900000 900000 1150000>; 155 }; 156 157 opp-1416000000 { 158 opp-hz = /bits/ 64 <1416000000>; 159 opp-microvolt = <900000 900000 1150000>; 160 }; 161 162 opp-1608000000 { 163 opp-hz = /bits/ 64 <1608000000>; 164 opp-microvolt = <975000 975000 1150000>; 165 }; 166 167 opp-1800000000 { 168 opp-hz = /bits/ 64 <1800000000>; 169 opp-microvolt = <1050000 1050000 1150000>; 170 }; 171 }; 172 173 display_subsystem: display-subsystem { 174 compatible = "rockchip,display-subsystem"; 175 ports = <&vop_out>; 176 }; 177 178 firmware { 179 scmi: scmi { 180 compatible = "arm,scmi-smc"; 181 arm,smc-id = <0x82000010>; 182 shmem = <&scmi_shmem>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 186 scmi_clk: protocol@14 { 187 reg = <0x14>; 188 #clock-cells = <1>; 189 }; 190 }; 191 }; 192 193 gpu_opp_table: opp-table-1 { 194 compatible = "operating-points-v2"; 195 196 opp-200000000 { 197 opp-hz = /bits/ 64 <200000000>; 198 opp-microvolt = <850000 850000 1000000>; 199 }; 200 201 opp-300000000 { 202 opp-hz = /bits/ 64 <300000000>; 203 opp-microvolt = <850000 850000 1000000>; 204 }; 205 206 opp-400000000 { 207 opp-hz = /bits/ 64 <400000000>; 208 opp-microvolt = <850000 850000 1000000>; 209 }; 210 211 opp-600000000 { 212 opp-hz = /bits/ 64 <600000000>; 213 opp-microvolt = <900000 900000 1000000>; 214 }; 215 216 opp-700000000 { 217 opp-hz = /bits/ 64 <700000000>; 218 opp-microvolt = <950000 950000 1000000>; 219 }; 220 221 opp-800000000 { 222 opp-hz = /bits/ 64 <800000000>; 223 opp-microvolt = <1000000 1000000 1000000>; 224 }; 225 }; 226 227 hdmi_sound: hdmi-sound { 228 compatible = "simple-audio-card"; 229 simple-audio-card,name = "HDMI"; 230 simple-audio-card,format = "i2s"; 231 simple-audio-card,mclk-fs = <256>; 232 status = "disabled"; 233 234 simple-audio-card,codec { 235 sound-dai = <&hdmi>; 236 }; 237 238 simple-audio-card,cpu { 239 sound-dai = <&i2s0_8ch>; 240 }; 241 }; 242 243 pmu { 244 compatible = "arm,cortex-a55-pmu"; 245 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 249 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 250 }; 251 252 psci { 253 compatible = "arm,psci-1.0"; 254 method = "smc"; 255 }; 256 257 timer { 258 compatible = "arm,armv8-timer"; 259 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 263 arm,no-tick-in-suspend; 264 }; 265 266 xin24m: xin24m { 267 compatible = "fixed-clock"; 268 clock-frequency = <24000000>; 269 clock-output-names = "xin24m"; 270 #clock-cells = <0>; 271 }; 272 273 xin32k: xin32k { 274 compatible = "fixed-clock"; 275 clock-frequency = <32768>; 276 clock-output-names = "xin32k"; 277 pinctrl-0 = <&clk32k_out0>; 278 pinctrl-names = "default"; 279 #clock-cells = <0>; 280 }; 281 282 sram@10f000 { 283 compatible = "mmio-sram"; 284 reg = <0x0 0x0010f000 0x0 0x100>; 285 #address-cells = <1>; 286 #size-cells = <1>; 287 ranges = <0 0x0 0x0010f000 0x100>; 288 289 scmi_shmem: sram@0 { 290 compatible = "arm,scmi-shmem"; 291 reg = <0x0 0x100>; 292 }; 293 }; 294 295 sata1: sata@fc400000 { 296 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 297 reg = <0 0xfc400000 0 0x1000>; 298 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, 299 <&cru CLK_SATA1_RXOOB>; 300 clock-names = "sata", "pmalive", "rxoob"; 301 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 302 phys = <&combphy1 PHY_TYPE_SATA>; 303 phy-names = "sata-phy"; 304 ports-implemented = <0x1>; 305 power-domains = <&power RK3568_PD_PIPE>; 306 status = "disabled"; 307 }; 308 309 sata2: sata@fc800000 { 310 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 311 reg = <0 0xfc800000 0 0x1000>; 312 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, 313 <&cru CLK_SATA2_RXOOB>; 314 clock-names = "sata", "pmalive", "rxoob"; 315 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 316 phys = <&combphy2 PHY_TYPE_SATA>; 317 phy-names = "sata-phy"; 318 ports-implemented = <0x1>; 319 power-domains = <&power RK3568_PD_PIPE>; 320 status = "disabled"; 321 }; 322 323 usb_host0_xhci: usb@fcc00000 { 324 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 325 reg = <0x0 0xfcc00000 0x0 0x400000>; 326 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 328 <&cru ACLK_USB3OTG0>; 329 clock-names = "ref_clk", "suspend_clk", 330 "bus_clk"; 331 dr_mode = "otg"; 332 phy_type = "utmi_wide"; 333 power-domains = <&power RK3568_PD_PIPE>; 334 resets = <&cru SRST_USB3OTG0>; 335 snps,dis_u2_susphy_quirk; 336 status = "disabled"; 337 }; 338 339 usb_host1_xhci: usb@fd000000 { 340 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 341 reg = <0x0 0xfd000000 0x0 0x400000>; 342 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 344 <&cru ACLK_USB3OTG1>; 345 clock-names = "ref_clk", "suspend_clk", 346 "bus_clk"; 347 dr_mode = "host"; 348 phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; 349 phy-names = "usb2-phy", "usb3-phy"; 350 phy_type = "utmi_wide"; 351 power-domains = <&power RK3568_PD_PIPE>; 352 resets = <&cru SRST_USB3OTG1>; 353 snps,dis_u2_susphy_quirk; 354 status = "disabled"; 355 }; 356 357 gic: interrupt-controller@fd400000 { 358 compatible = "arm,gic-v3"; 359 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 360 <0x0 0xfd460000 0 0x80000>; /* GICR */ 361 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 362 interrupt-controller; 363 #interrupt-cells = <3>; 364 mbi-alias = <0x0 0xfd410000>; 365 mbi-ranges = <296 24>; 366 msi-controller; 367 }; 368 369 usb_host0_ehci: usb@fd800000 { 370 compatible = "generic-ehci"; 371 reg = <0x0 0xfd800000 0x0 0x40000>; 372 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 374 <&cru PCLK_USB>; 375 phys = <&usb2phy1_otg>; 376 phy-names = "usb"; 377 status = "disabled"; 378 }; 379 380 usb_host0_ohci: usb@fd840000 { 381 compatible = "generic-ohci"; 382 reg = <0x0 0xfd840000 0x0 0x40000>; 383 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 385 <&cru PCLK_USB>; 386 phys = <&usb2phy1_otg>; 387 phy-names = "usb"; 388 status = "disabled"; 389 }; 390 391 usb_host1_ehci: usb@fd880000 { 392 compatible = "generic-ehci"; 393 reg = <0x0 0xfd880000 0x0 0x40000>; 394 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 396 <&cru PCLK_USB>; 397 phys = <&usb2phy1_host>; 398 phy-names = "usb"; 399 status = "disabled"; 400 }; 401 402 usb_host1_ohci: usb@fd8c0000 { 403 compatible = "generic-ohci"; 404 reg = <0x0 0xfd8c0000 0x0 0x40000>; 405 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 407 <&cru PCLK_USB>; 408 phys = <&usb2phy1_host>; 409 phy-names = "usb"; 410 status = "disabled"; 411 }; 412 413 pmugrf: syscon@fdc20000 { 414 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 415 reg = <0x0 0xfdc20000 0x0 0x10000>; 416 417 pmu_io_domains: io-domains { 418 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 419 status = "disabled"; 420 }; 421 }; 422 423 pipegrf: syscon@fdc50000 { 424 reg = <0x0 0xfdc50000 0x0 0x1000>; 425 }; 426 427 grf: syscon@fdc60000 { 428 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 429 reg = <0x0 0xfdc60000 0x0 0x10000>; 430 }; 431 432 pipe_phy_grf1: syscon@fdc80000 { 433 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 434 reg = <0x0 0xfdc80000 0x0 0x1000>; 435 }; 436 437 pipe_phy_grf2: syscon@fdc90000 { 438 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 439 reg = <0x0 0xfdc90000 0x0 0x1000>; 440 }; 441 442 usb2phy0_grf: syscon@fdca0000 { 443 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 444 reg = <0x0 0xfdca0000 0x0 0x8000>; 445 }; 446 447 usb2phy1_grf: syscon@fdca8000 { 448 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 449 reg = <0x0 0xfdca8000 0x0 0x8000>; 450 }; 451 452 pmucru: clock-controller@fdd00000 { 453 compatible = "rockchip,rk3568-pmucru"; 454 reg = <0x0 0xfdd00000 0x0 0x1000>; 455 #clock-cells = <1>; 456 #reset-cells = <1>; 457 }; 458 459 cru: clock-controller@fdd20000 { 460 compatible = "rockchip,rk3568-cru"; 461 reg = <0x0 0xfdd20000 0x0 0x1000>; 462 clocks = <&xin24m>; 463 clock-names = "xin24m"; 464 #clock-cells = <1>; 465 #reset-cells = <1>; 466 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; 467 assigned-clock-rates = <32768>, <1200000000>, <200000000>; 468 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; 469 rockchip,grf = <&grf>; 470 }; 471 472 i2c0: i2c@fdd40000 { 473 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 474 reg = <0x0 0xfdd40000 0x0 0x1000>; 475 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 477 clock-names = "i2c", "pclk"; 478 pinctrl-0 = <&i2c0_xfer>; 479 pinctrl-names = "default"; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 status = "disabled"; 483 }; 484 485 uart0: serial@fdd50000 { 486 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 487 reg = <0x0 0xfdd50000 0x0 0x100>; 488 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 490 clock-names = "baudclk", "apb_pclk"; 491 dmas = <&dmac0 0>, <&dmac0 1>; 492 pinctrl-0 = <&uart0_xfer>; 493 pinctrl-names = "default"; 494 reg-io-width = <4>; 495 reg-shift = <2>; 496 status = "disabled"; 497 }; 498 499 pwm0: pwm@fdd70000 { 500 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 501 reg = <0x0 0xfdd70000 0x0 0x10>; 502 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 503 clock-names = "pwm", "pclk"; 504 pinctrl-0 = <&pwm0m0_pins>; 505 pinctrl-names = "default"; 506 #pwm-cells = <3>; 507 status = "disabled"; 508 }; 509 510 pwm1: pwm@fdd70010 { 511 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 512 reg = <0x0 0xfdd70010 0x0 0x10>; 513 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 514 clock-names = "pwm", "pclk"; 515 pinctrl-0 = <&pwm1m0_pins>; 516 pinctrl-names = "default"; 517 #pwm-cells = <3>; 518 status = "disabled"; 519 }; 520 521 pwm2: pwm@fdd70020 { 522 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 523 reg = <0x0 0xfdd70020 0x0 0x10>; 524 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 525 clock-names = "pwm", "pclk"; 526 pinctrl-0 = <&pwm2m0_pins>; 527 pinctrl-names = "default"; 528 #pwm-cells = <3>; 529 status = "disabled"; 530 }; 531 532 pwm3: pwm@fdd70030 { 533 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 534 reg = <0x0 0xfdd70030 0x0 0x10>; 535 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 536 clock-names = "pwm", "pclk"; 537 pinctrl-0 = <&pwm3_pins>; 538 pinctrl-names = "default"; 539 #pwm-cells = <3>; 540 status = "disabled"; 541 }; 542 543 pmu: power-management@fdd90000 { 544 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 545 reg = <0x0 0xfdd90000 0x0 0x1000>; 546 547 power: power-controller { 548 compatible = "rockchip,rk3568-power-controller"; 549 #power-domain-cells = <1>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 553 /* These power domains are grouped by VD_GPU */ 554 power-domain@RK3568_PD_GPU { 555 reg = <RK3568_PD_GPU>; 556 clocks = <&cru ACLK_GPU_PRE>, 557 <&cru PCLK_GPU_PRE>; 558 pm_qos = <&qos_gpu>; 559 #power-domain-cells = <0>; 560 }; 561 562 /* These power domains are grouped by VD_LOGIC */ 563 power-domain@RK3568_PD_VI { 564 reg = <RK3568_PD_VI>; 565 clocks = <&cru HCLK_VI>, 566 <&cru PCLK_VI>; 567 pm_qos = <&qos_isp>, 568 <&qos_vicap0>, 569 <&qos_vicap1>; 570 #power-domain-cells = <0>; 571 }; 572 573 power-domain@RK3568_PD_VO { 574 reg = <RK3568_PD_VO>; 575 clocks = <&cru HCLK_VO>, 576 <&cru PCLK_VO>, 577 <&cru ACLK_VOP_PRE>; 578 pm_qos = <&qos_hdcp>, 579 <&qos_vop_m0>, 580 <&qos_vop_m1>; 581 #power-domain-cells = <0>; 582 }; 583 584 power-domain@RK3568_PD_RGA { 585 reg = <RK3568_PD_RGA>; 586 clocks = <&cru HCLK_RGA_PRE>, 587 <&cru PCLK_RGA_PRE>; 588 pm_qos = <&qos_ebc>, 589 <&qos_iep>, 590 <&qos_jpeg_dec>, 591 <&qos_jpeg_enc>, 592 <&qos_rga_rd>, 593 <&qos_rga_wr>; 594 #power-domain-cells = <0>; 595 }; 596 597 power-domain@RK3568_PD_VPU { 598 reg = <RK3568_PD_VPU>; 599 clocks = <&cru HCLK_VPU_PRE>; 600 pm_qos = <&qos_vpu>; 601 #power-domain-cells = <0>; 602 }; 603 604 power-domain@RK3568_PD_RKVDEC { 605 clocks = <&cru HCLK_RKVDEC_PRE>; 606 reg = <RK3568_PD_RKVDEC>; 607 pm_qos = <&qos_rkvdec>; 608 #power-domain-cells = <0>; 609 }; 610 611 power-domain@RK3568_PD_RKVENC { 612 reg = <RK3568_PD_RKVENC>; 613 clocks = <&cru HCLK_RKVENC_PRE>; 614 pm_qos = <&qos_rkvenc_rd_m0>, 615 <&qos_rkvenc_rd_m1>, 616 <&qos_rkvenc_wr_m0>; 617 #power-domain-cells = <0>; 618 }; 619 }; 620 }; 621 622 gpu: gpu@fde60000 { 623 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; 624 reg = <0x0 0xfde60000 0x0 0x4000>; 625 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 628 interrupt-names = "job", "mmu", "gpu"; 629 clocks = <&scmi_clk 1>, <&cru CLK_GPU>; 630 clock-names = "gpu", "bus"; 631 #cooling-cells = <2>; 632 operating-points-v2 = <&gpu_opp_table>; 633 power-domains = <&power RK3568_PD_GPU>; 634 status = "disabled"; 635 }; 636 637 vpu: video-codec@fdea0400 { 638 compatible = "rockchip,rk3568-vpu"; 639 reg = <0x0 0xfdea0000 0x0 0x800>; 640 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 641 interrupt-names = "vdpu"; 642 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 643 clock-names = "aclk", "hclk"; 644 iommus = <&vdpu_mmu>; 645 power-domains = <&power RK3568_PD_VPU>; 646 }; 647 648 vdpu_mmu: iommu@fdea0800 { 649 compatible = "rockchip,rk3568-iommu"; 650 reg = <0x0 0xfdea0800 0x0 0x40>; 651 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 652 clock-names = "aclk", "iface"; 653 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 654 power-domains = <&power RK3568_PD_VPU>; 655 #iommu-cells = <0>; 656 }; 657 658 rga: rga@fdeb0000 { 659 compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; 660 reg = <0x0 0xfdeb0000 0x0 0x180>; 661 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; 663 clock-names = "aclk", "hclk", "sclk"; 664 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 665 reset-names = "core", "axi", "ahb"; 666 power-domains = <&power RK3568_PD_RGA>; 667 }; 668 669 vepu: video-codec@fdee0000 { 670 compatible = "rockchip,rk3568-vepu"; 671 reg = <0x0 0xfdee0000 0x0 0x800>; 672 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 674 clock-names = "aclk", "hclk"; 675 iommus = <&vepu_mmu>; 676 power-domains = <&power RK3568_PD_RGA>; 677 }; 678 679 vepu_mmu: iommu@fdee0800 { 680 compatible = "rockchip,rk3568-iommu"; 681 reg = <0x0 0xfdee0800 0x0 0x40>; 682 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 684 clock-names = "aclk", "iface"; 685 power-domains = <&power RK3568_PD_RGA>; 686 #iommu-cells = <0>; 687 }; 688 689 sdmmc2: mmc@fe000000 { 690 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 691 reg = <0x0 0xfe000000 0x0 0x4000>; 692 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 694 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 695 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 696 fifo-depth = <0x100>; 697 max-frequency = <150000000>; 698 resets = <&cru SRST_SDMMC2>; 699 reset-names = "reset"; 700 status = "disabled"; 701 }; 702 703 gmac1: ethernet@fe010000 { 704 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 705 reg = <0x0 0xfe010000 0x0 0x10000>; 706 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 708 interrupt-names = "macirq", "eth_wake_irq"; 709 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 710 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 711 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 712 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 713 clock-names = "stmmaceth", "mac_clk_rx", 714 "mac_clk_tx", "clk_mac_refout", 715 "aclk_mac", "pclk_mac", 716 "clk_mac_speed", "ptp_ref"; 717 resets = <&cru SRST_A_GMAC1>; 718 reset-names = "stmmaceth"; 719 rockchip,grf = <&grf>; 720 snps,axi-config = <&gmac1_stmmac_axi_setup>; 721 snps,mixed-burst; 722 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 723 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 724 snps,tso; 725 status = "disabled"; 726 727 mdio1: mdio { 728 compatible = "snps,dwmac-mdio"; 729 #address-cells = <0x1>; 730 #size-cells = <0x0>; 731 }; 732 733 gmac1_stmmac_axi_setup: stmmac-axi-config { 734 snps,blen = <0 0 0 0 16 8 4>; 735 snps,rd_osr_lmt = <8>; 736 snps,wr_osr_lmt = <4>; 737 }; 738 739 gmac1_mtl_rx_setup: rx-queues-config { 740 snps,rx-queues-to-use = <1>; 741 queue0 {}; 742 }; 743 744 gmac1_mtl_tx_setup: tx-queues-config { 745 snps,tx-queues-to-use = <1>; 746 queue0 {}; 747 }; 748 }; 749 750 vop: vop@fe040000 { 751 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; 752 reg-names = "vop", "gamma-lut"; 753 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, 755 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; 756 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; 757 iommus = <&vop_mmu>; 758 power-domains = <&power RK3568_PD_VO>; 759 rockchip,grf = <&grf>; 760 status = "disabled"; 761 762 vop_out: ports { 763 #address-cells = <1>; 764 #size-cells = <0>; 765 766 vp0: port@0 { 767 reg = <0>; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 }; 771 772 vp1: port@1 { 773 reg = <1>; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 }; 777 778 vp2: port@2 { 779 reg = <2>; 780 #address-cells = <1>; 781 #size-cells = <0>; 782 }; 783 }; 784 }; 785 786 vop_mmu: iommu@fe043e00 { 787 compatible = "rockchip,rk3568-iommu"; 788 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; 789 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 791 clock-names = "aclk", "iface"; 792 #iommu-cells = <0>; 793 power-domains = <&power RK3568_PD_VO>; 794 status = "disabled"; 795 }; 796 797 dsi0: dsi@fe060000 { 798 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 799 reg = <0x00 0xfe060000 0x00 0x10000>; 800 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 801 clock-names = "pclk"; 802 clocks = <&cru PCLK_DSITX_0>; 803 phy-names = "dphy"; 804 phys = <&dsi_dphy0>; 805 power-domains = <&power RK3568_PD_VO>; 806 reset-names = "apb"; 807 resets = <&cru SRST_P_DSITX_0>; 808 rockchip,grf = <&grf>; 809 status = "disabled"; 810 811 ports { 812 #address-cells = <1>; 813 #size-cells = <0>; 814 815 dsi0_in: port@0 { 816 reg = <0>; 817 }; 818 819 dsi0_out: port@1 { 820 reg = <1>; 821 }; 822 }; 823 }; 824 825 dsi1: dsi@fe070000 { 826 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 827 reg = <0x0 0xfe070000 0x0 0x10000>; 828 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 829 clock-names = "pclk"; 830 clocks = <&cru PCLK_DSITX_1>; 831 phy-names = "dphy"; 832 phys = <&dsi_dphy1>; 833 power-domains = <&power RK3568_PD_VO>; 834 reset-names = "apb"; 835 resets = <&cru SRST_P_DSITX_1>; 836 rockchip,grf = <&grf>; 837 status = "disabled"; 838 839 ports { 840 #address-cells = <1>; 841 #size-cells = <0>; 842 843 dsi1_in: port@0 { 844 reg = <0>; 845 }; 846 847 dsi1_out: port@1 { 848 reg = <1>; 849 }; 850 }; 851 }; 852 853 hdmi: hdmi@fe0a0000 { 854 compatible = "rockchip,rk3568-dw-hdmi"; 855 reg = <0x0 0xfe0a0000 0x0 0x20000>; 856 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&cru PCLK_HDMI_HOST>, 858 <&cru CLK_HDMI_SFR>, 859 <&cru CLK_HDMI_CEC>, 860 <&pmucru CLK_HDMI_REF>, 861 <&cru HCLK_VO>; 862 clock-names = "iahb", "isfr", "cec", "ref"; 863 pinctrl-names = "default"; 864 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; 865 power-domains = <&power RK3568_PD_VO>; 866 reg-io-width = <4>; 867 rockchip,grf = <&grf>; 868 #sound-dai-cells = <0>; 869 status = "disabled"; 870 871 ports { 872 #address-cells = <1>; 873 #size-cells = <0>; 874 875 hdmi_in: port@0 { 876 reg = <0>; 877 }; 878 879 hdmi_out: port@1 { 880 reg = <1>; 881 }; 882 }; 883 }; 884 885 qos_gpu: qos@fe128000 { 886 compatible = "rockchip,rk3568-qos", "syscon"; 887 reg = <0x0 0xfe128000 0x0 0x20>; 888 }; 889 890 qos_rkvenc_rd_m0: qos@fe138080 { 891 compatible = "rockchip,rk3568-qos", "syscon"; 892 reg = <0x0 0xfe138080 0x0 0x20>; 893 }; 894 895 qos_rkvenc_rd_m1: qos@fe138100 { 896 compatible = "rockchip,rk3568-qos", "syscon"; 897 reg = <0x0 0xfe138100 0x0 0x20>; 898 }; 899 900 qos_rkvenc_wr_m0: qos@fe138180 { 901 compatible = "rockchip,rk3568-qos", "syscon"; 902 reg = <0x0 0xfe138180 0x0 0x20>; 903 }; 904 905 qos_isp: qos@fe148000 { 906 compatible = "rockchip,rk3568-qos", "syscon"; 907 reg = <0x0 0xfe148000 0x0 0x20>; 908 }; 909 910 qos_vicap0: qos@fe148080 { 911 compatible = "rockchip,rk3568-qos", "syscon"; 912 reg = <0x0 0xfe148080 0x0 0x20>; 913 }; 914 915 qos_vicap1: qos@fe148100 { 916 compatible = "rockchip,rk3568-qos", "syscon"; 917 reg = <0x0 0xfe148100 0x0 0x20>; 918 }; 919 920 qos_vpu: qos@fe150000 { 921 compatible = "rockchip,rk3568-qos", "syscon"; 922 reg = <0x0 0xfe150000 0x0 0x20>; 923 }; 924 925 qos_ebc: qos@fe158000 { 926 compatible = "rockchip,rk3568-qos", "syscon"; 927 reg = <0x0 0xfe158000 0x0 0x20>; 928 }; 929 930 qos_iep: qos@fe158100 { 931 compatible = "rockchip,rk3568-qos", "syscon"; 932 reg = <0x0 0xfe158100 0x0 0x20>; 933 }; 934 935 qos_jpeg_dec: qos@fe158180 { 936 compatible = "rockchip,rk3568-qos", "syscon"; 937 reg = <0x0 0xfe158180 0x0 0x20>; 938 }; 939 940 qos_jpeg_enc: qos@fe158200 { 941 compatible = "rockchip,rk3568-qos", "syscon"; 942 reg = <0x0 0xfe158200 0x0 0x20>; 943 }; 944 945 qos_rga_rd: qos@fe158280 { 946 compatible = "rockchip,rk3568-qos", "syscon"; 947 reg = <0x0 0xfe158280 0x0 0x20>; 948 }; 949 950 qos_rga_wr: qos@fe158300 { 951 compatible = "rockchip,rk3568-qos", "syscon"; 952 reg = <0x0 0xfe158300 0x0 0x20>; 953 }; 954 955 qos_npu: qos@fe180000 { 956 compatible = "rockchip,rk3568-qos", "syscon"; 957 reg = <0x0 0xfe180000 0x0 0x20>; 958 }; 959 960 qos_pcie2x1: qos@fe190000 { 961 compatible = "rockchip,rk3568-qos", "syscon"; 962 reg = <0x0 0xfe190000 0x0 0x20>; 963 }; 964 965 qos_sata1: qos@fe190280 { 966 compatible = "rockchip,rk3568-qos", "syscon"; 967 reg = <0x0 0xfe190280 0x0 0x20>; 968 }; 969 970 qos_sata2: qos@fe190300 { 971 compatible = "rockchip,rk3568-qos", "syscon"; 972 reg = <0x0 0xfe190300 0x0 0x20>; 973 }; 974 975 qos_usb3_0: qos@fe190380 { 976 compatible = "rockchip,rk3568-qos", "syscon"; 977 reg = <0x0 0xfe190380 0x0 0x20>; 978 }; 979 980 qos_usb3_1: qos@fe190400 { 981 compatible = "rockchip,rk3568-qos", "syscon"; 982 reg = <0x0 0xfe190400 0x0 0x20>; 983 }; 984 985 qos_rkvdec: qos@fe198000 { 986 compatible = "rockchip,rk3568-qos", "syscon"; 987 reg = <0x0 0xfe198000 0x0 0x20>; 988 }; 989 990 qos_hdcp: qos@fe1a8000 { 991 compatible = "rockchip,rk3568-qos", "syscon"; 992 reg = <0x0 0xfe1a8000 0x0 0x20>; 993 }; 994 995 qos_vop_m0: qos@fe1a8080 { 996 compatible = "rockchip,rk3568-qos", "syscon"; 997 reg = <0x0 0xfe1a8080 0x0 0x20>; 998 }; 999 1000 qos_vop_m1: qos@fe1a8100 { 1001 compatible = "rockchip,rk3568-qos", "syscon"; 1002 reg = <0x0 0xfe1a8100 0x0 0x20>; 1003 }; 1004 1005 dfi: dfi@fe230000 { 1006 compatible = "rockchip,rk3568-dfi"; 1007 reg = <0x00 0xfe230000 0x00 0x400>; 1008 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1009 rockchip,pmu = <&pmugrf>; 1010 }; 1011 1012 pcie2x1: pcie@fe260000 { 1013 compatible = "rockchip,rk3568-pcie"; 1014 reg = <0x3 0xc0000000 0x0 0x00400000>, 1015 <0x0 0xfe260000 0x0 0x00010000>, 1016 <0x0 0xf4000000 0x0 0x00100000>; 1017 reg-names = "dbi", "apb", "config"; 1018 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1023 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1024 bus-range = <0x0 0xf>; 1025 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 1026 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, 1027 <&cru CLK_PCIE20_AUX_NDFT>; 1028 clock-names = "aclk_mst", "aclk_slv", 1029 "aclk_dbi", "pclk", "aux"; 1030 device_type = "pci"; 1031 #interrupt-cells = <1>; 1032 interrupt-map-mask = <0 0 0 7>; 1033 interrupt-map = <0 0 0 1 &pcie_intc 0>, 1034 <0 0 0 2 &pcie_intc 1>, 1035 <0 0 0 3 &pcie_intc 2>, 1036 <0 0 0 4 &pcie_intc 3>; 1037 linux,pci-domain = <0>; 1038 num-ib-windows = <6>; 1039 num-ob-windows = <2>; 1040 max-link-speed = <2>; 1041 msi-map = <0x0 &gic 0x0 0x1000>; 1042 num-lanes = <1>; 1043 phys = <&combphy2 PHY_TYPE_PCIE>; 1044 phy-names = "pcie-phy"; 1045 power-domains = <&power RK3568_PD_PIPE>; 1046 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 1047 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, 1048 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; 1049 resets = <&cru SRST_PCIE20_POWERUP>; 1050 reset-names = "pipe"; 1051 #address-cells = <3>; 1052 #size-cells = <2>; 1053 status = "disabled"; 1054 1055 pcie_intc: legacy-interrupt-controller { 1056 #address-cells = <0>; 1057 #interrupt-cells = <1>; 1058 interrupt-controller; 1059 interrupt-parent = <&gic>; 1060 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 1061 }; 1062 }; 1063 1064 sdmmc0: mmc@fe2b0000 { 1065 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 1066 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1067 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 1069 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 1070 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1071 fifo-depth = <0x100>; 1072 max-frequency = <150000000>; 1073 resets = <&cru SRST_SDMMC0>; 1074 reset-names = "reset"; 1075 status = "disabled"; 1076 }; 1077 1078 sdmmc1: mmc@fe2c0000 { 1079 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 1080 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1081 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1082 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 1083 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 1084 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1085 fifo-depth = <0x100>; 1086 max-frequency = <150000000>; 1087 resets = <&cru SRST_SDMMC1>; 1088 reset-names = "reset"; 1089 status = "disabled"; 1090 }; 1091 1092 sfc: spi@fe300000 { 1093 compatible = "rockchip,sfc"; 1094 reg = <0x0 0xfe300000 0x0 0x4000>; 1095 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1097 clock-names = "clk_sfc", "hclk_sfc"; 1098 pinctrl-0 = <&fspi_pins>; 1099 pinctrl-names = "default"; 1100 status = "disabled"; 1101 }; 1102 1103 sdhci: mmc@fe310000 { 1104 compatible = "rockchip,rk3568-dwcmshc"; 1105 reg = <0x0 0xfe310000 0x0 0x10000>; 1106 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1107 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 1108 assigned-clock-rates = <200000000>, <24000000>; 1109 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1110 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1111 <&cru TCLK_EMMC>; 1112 clock-names = "core", "bus", "axi", "block", "timer"; 1113 status = "disabled"; 1114 }; 1115 1116 rng: rng@fe388000 { 1117 compatible = "rockchip,rk3568-rng"; 1118 reg = <0x0 0xfe388000 0x0 0x4000>; 1119 clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; 1120 clock-names = "core", "ahb"; 1121 resets = <&cru SRST_TRNG_NS>; 1122 status = "disabled"; 1123 }; 1124 1125 i2s0_8ch: i2s@fe400000 { 1126 compatible = "rockchip,rk3568-i2s-tdm"; 1127 reg = <0x0 0xfe400000 0x0 0x1000>; 1128 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1129 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1130 assigned-clock-rates = <1188000000>, <1188000000>; 1131 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1132 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1133 dmas = <&dmac1 0>; 1134 dma-names = "tx"; 1135 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1136 reset-names = "tx-m", "rx-m"; 1137 rockchip,grf = <&grf>; 1138 #sound-dai-cells = <0>; 1139 status = "disabled"; 1140 }; 1141 1142 i2s1_8ch: i2s@fe410000 { 1143 compatible = "rockchip,rk3568-i2s-tdm"; 1144 reg = <0x0 0xfe410000 0x0 0x1000>; 1145 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1146 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; 1147 assigned-clock-rates = <1188000000>, <1188000000>; 1148 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, 1149 <&cru HCLK_I2S1_8CH>; 1150 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1151 dmas = <&dmac1 3>, <&dmac1 2>; 1152 dma-names = "rx", "tx"; 1153 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1154 reset-names = "tx-m", "rx-m"; 1155 rockchip,grf = <&grf>; 1156 pinctrl-names = "default"; 1157 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx 1158 &i2s1m0_lrcktx &i2s1m0_lrckrx 1159 &i2s1m0_sdi0 &i2s1m0_sdi1 1160 &i2s1m0_sdi2 &i2s1m0_sdi3 1161 &i2s1m0_sdo0 &i2s1m0_sdo1 1162 &i2s1m0_sdo2 &i2s1m0_sdo3>; 1163 #sound-dai-cells = <0>; 1164 status = "disabled"; 1165 }; 1166 1167 i2s2_2ch: i2s@fe420000 { 1168 compatible = "rockchip,rk3568-i2s-tdm"; 1169 reg = <0x0 0xfe420000 0x0 0x1000>; 1170 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1171 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1172 assigned-clock-rates = <1188000000>; 1173 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1174 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1175 dmas = <&dmac1 4>, <&dmac1 5>; 1176 dma-names = "tx", "rx"; 1177 resets = <&cru SRST_M_I2S2_2CH>; 1178 reset-names = "tx-m"; 1179 rockchip,grf = <&grf>; 1180 pinctrl-names = "default"; 1181 pinctrl-0 = <&i2s2m0_sclktx 1182 &i2s2m0_lrcktx 1183 &i2s2m0_sdi 1184 &i2s2m0_sdo>; 1185 #sound-dai-cells = <0>; 1186 status = "disabled"; 1187 }; 1188 1189 i2s3_2ch: i2s@fe430000 { 1190 compatible = "rockchip,rk3568-i2s-tdm"; 1191 reg = <0x0 0xfe430000 0x0 0x1000>; 1192 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1193 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, 1194 <&cru HCLK_I2S3_2CH>; 1195 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1196 dmas = <&dmac1 6>, <&dmac1 7>; 1197 dma-names = "tx", "rx"; 1198 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; 1199 reset-names = "tx-m", "rx-m"; 1200 rockchip,grf = <&grf>; 1201 #sound-dai-cells = <0>; 1202 status = "disabled"; 1203 }; 1204 1205 pdm: pdm@fe440000 { 1206 compatible = "rockchip,rk3568-pdm"; 1207 reg = <0x0 0xfe440000 0x0 0x1000>; 1208 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1209 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1210 clock-names = "pdm_clk", "pdm_hclk"; 1211 dmas = <&dmac1 9>; 1212 dma-names = "rx"; 1213 pinctrl-0 = <&pdmm0_clk 1214 &pdmm0_clk1 1215 &pdmm0_sdi0 1216 &pdmm0_sdi1 1217 &pdmm0_sdi2 1218 &pdmm0_sdi3>; 1219 pinctrl-names = "default"; 1220 resets = <&cru SRST_M_PDM>; 1221 reset-names = "pdm-m"; 1222 #sound-dai-cells = <0>; 1223 status = "disabled"; 1224 }; 1225 1226 spdif: spdif@fe460000 { 1227 compatible = "rockchip,rk3568-spdif"; 1228 reg = <0x0 0xfe460000 0x0 0x1000>; 1229 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1230 clock-names = "mclk", "hclk"; 1231 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 1232 dmas = <&dmac1 1>; 1233 dma-names = "tx"; 1234 pinctrl-names = "default"; 1235 pinctrl-0 = <&spdifm0_tx>; 1236 #sound-dai-cells = <0>; 1237 status = "disabled"; 1238 }; 1239 1240 dmac0: dma-controller@fe530000 { 1241 compatible = "arm,pl330", "arm,primecell"; 1242 reg = <0x0 0xfe530000 0x0 0x4000>; 1243 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1245 arm,pl330-periph-burst; 1246 clocks = <&cru ACLK_BUS>; 1247 clock-names = "apb_pclk"; 1248 #dma-cells = <1>; 1249 }; 1250 1251 dmac1: dma-controller@fe550000 { 1252 compatible = "arm,pl330", "arm,primecell"; 1253 reg = <0x0 0xfe550000 0x0 0x4000>; 1254 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1256 arm,pl330-periph-burst; 1257 clocks = <&cru ACLK_BUS>; 1258 clock-names = "apb_pclk"; 1259 #dma-cells = <1>; 1260 }; 1261 1262 i2c1: i2c@fe5a0000 { 1263 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1264 reg = <0x0 0xfe5a0000 0x0 0x1000>; 1265 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1266 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1267 clock-names = "i2c", "pclk"; 1268 pinctrl-0 = <&i2c1_xfer>; 1269 pinctrl-names = "default"; 1270 #address-cells = <1>; 1271 #size-cells = <0>; 1272 status = "disabled"; 1273 }; 1274 1275 i2c2: i2c@fe5b0000 { 1276 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1277 reg = <0x0 0xfe5b0000 0x0 0x1000>; 1278 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1279 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1280 clock-names = "i2c", "pclk"; 1281 pinctrl-0 = <&i2c2m0_xfer>; 1282 pinctrl-names = "default"; 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 status = "disabled"; 1286 }; 1287 1288 i2c3: i2c@fe5c0000 { 1289 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1290 reg = <0x0 0xfe5c0000 0x0 0x1000>; 1291 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1292 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1293 clock-names = "i2c", "pclk"; 1294 pinctrl-0 = <&i2c3m0_xfer>; 1295 pinctrl-names = "default"; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 status = "disabled"; 1299 }; 1300 1301 i2c4: i2c@fe5d0000 { 1302 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1303 reg = <0x0 0xfe5d0000 0x0 0x1000>; 1304 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1305 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1306 clock-names = "i2c", "pclk"; 1307 pinctrl-0 = <&i2c4m0_xfer>; 1308 pinctrl-names = "default"; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 status = "disabled"; 1312 }; 1313 1314 i2c5: i2c@fe5e0000 { 1315 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1316 reg = <0x0 0xfe5e0000 0x0 0x1000>; 1317 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1318 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1319 clock-names = "i2c", "pclk"; 1320 pinctrl-0 = <&i2c5m0_xfer>; 1321 pinctrl-names = "default"; 1322 #address-cells = <1>; 1323 #size-cells = <0>; 1324 status = "disabled"; 1325 }; 1326 1327 wdt: watchdog@fe600000 { 1328 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; 1329 reg = <0x0 0xfe600000 0x0 0x100>; 1330 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 1331 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 1332 clock-names = "tclk", "pclk"; 1333 }; 1334 1335 spi0: spi@fe610000 { 1336 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1337 reg = <0x0 0xfe610000 0x0 0x1000>; 1338 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1339 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1340 clock-names = "spiclk", "apb_pclk"; 1341 dmas = <&dmac0 20>, <&dmac0 21>; 1342 dma-names = "tx", "rx"; 1343 pinctrl-names = "default"; 1344 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 status = "disabled"; 1348 }; 1349 1350 spi1: spi@fe620000 { 1351 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1352 reg = <0x0 0xfe620000 0x0 0x1000>; 1353 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1354 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1355 clock-names = "spiclk", "apb_pclk"; 1356 dmas = <&dmac0 22>, <&dmac0 23>; 1357 dma-names = "tx", "rx"; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 status = "disabled"; 1363 }; 1364 1365 spi2: spi@fe630000 { 1366 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1367 reg = <0x0 0xfe630000 0x0 0x1000>; 1368 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1369 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1370 clock-names = "spiclk", "apb_pclk"; 1371 dmas = <&dmac0 24>, <&dmac0 25>; 1372 dma-names = "tx", "rx"; 1373 pinctrl-names = "default"; 1374 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 1375 #address-cells = <1>; 1376 #size-cells = <0>; 1377 status = "disabled"; 1378 }; 1379 1380 spi3: spi@fe640000 { 1381 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1382 reg = <0x0 0xfe640000 0x0 0x1000>; 1383 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1384 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1385 clock-names = "spiclk", "apb_pclk"; 1386 dmas = <&dmac0 26>, <&dmac0 27>; 1387 dma-names = "tx", "rx"; 1388 pinctrl-names = "default"; 1389 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 status = "disabled"; 1393 }; 1394 1395 uart1: serial@fe650000 { 1396 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1397 reg = <0x0 0xfe650000 0x0 0x100>; 1398 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1399 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1400 clock-names = "baudclk", "apb_pclk"; 1401 dmas = <&dmac0 2>, <&dmac0 3>; 1402 pinctrl-0 = <&uart1m0_xfer>; 1403 pinctrl-names = "default"; 1404 reg-io-width = <4>; 1405 reg-shift = <2>; 1406 status = "disabled"; 1407 }; 1408 1409 uart2: serial@fe660000 { 1410 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1411 reg = <0x0 0xfe660000 0x0 0x100>; 1412 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1413 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1414 clock-names = "baudclk", "apb_pclk"; 1415 dmas = <&dmac0 4>, <&dmac0 5>; 1416 pinctrl-0 = <&uart2m0_xfer>; 1417 pinctrl-names = "default"; 1418 reg-io-width = <4>; 1419 reg-shift = <2>; 1420 status = "disabled"; 1421 }; 1422 1423 uart3: serial@fe670000 { 1424 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1425 reg = <0x0 0xfe670000 0x0 0x100>; 1426 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1427 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1428 clock-names = "baudclk", "apb_pclk"; 1429 dmas = <&dmac0 6>, <&dmac0 7>; 1430 pinctrl-0 = <&uart3m0_xfer>; 1431 pinctrl-names = "default"; 1432 reg-io-width = <4>; 1433 reg-shift = <2>; 1434 status = "disabled"; 1435 }; 1436 1437 uart4: serial@fe680000 { 1438 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1439 reg = <0x0 0xfe680000 0x0 0x100>; 1440 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1441 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1442 clock-names = "baudclk", "apb_pclk"; 1443 dmas = <&dmac0 8>, <&dmac0 9>; 1444 pinctrl-0 = <&uart4m0_xfer>; 1445 pinctrl-names = "default"; 1446 reg-io-width = <4>; 1447 reg-shift = <2>; 1448 status = "disabled"; 1449 }; 1450 1451 uart5: serial@fe690000 { 1452 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1453 reg = <0x0 0xfe690000 0x0 0x100>; 1454 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1455 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1456 clock-names = "baudclk", "apb_pclk"; 1457 dmas = <&dmac0 10>, <&dmac0 11>; 1458 pinctrl-0 = <&uart5m0_xfer>; 1459 pinctrl-names = "default"; 1460 reg-io-width = <4>; 1461 reg-shift = <2>; 1462 status = "disabled"; 1463 }; 1464 1465 uart6: serial@fe6a0000 { 1466 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1467 reg = <0x0 0xfe6a0000 0x0 0x100>; 1468 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1469 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1470 clock-names = "baudclk", "apb_pclk"; 1471 dmas = <&dmac0 12>, <&dmac0 13>; 1472 pinctrl-0 = <&uart6m0_xfer>; 1473 pinctrl-names = "default"; 1474 reg-io-width = <4>; 1475 reg-shift = <2>; 1476 status = "disabled"; 1477 }; 1478 1479 uart7: serial@fe6b0000 { 1480 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1481 reg = <0x0 0xfe6b0000 0x0 0x100>; 1482 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1483 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1484 clock-names = "baudclk", "apb_pclk"; 1485 dmas = <&dmac0 14>, <&dmac0 15>; 1486 pinctrl-0 = <&uart7m0_xfer>; 1487 pinctrl-names = "default"; 1488 reg-io-width = <4>; 1489 reg-shift = <2>; 1490 status = "disabled"; 1491 }; 1492 1493 uart8: serial@fe6c0000 { 1494 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1495 reg = <0x0 0xfe6c0000 0x0 0x100>; 1496 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1497 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1498 clock-names = "baudclk", "apb_pclk"; 1499 dmas = <&dmac0 16>, <&dmac0 17>; 1500 pinctrl-0 = <&uart8m0_xfer>; 1501 pinctrl-names = "default"; 1502 reg-io-width = <4>; 1503 reg-shift = <2>; 1504 status = "disabled"; 1505 }; 1506 1507 uart9: serial@fe6d0000 { 1508 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1509 reg = <0x0 0xfe6d0000 0x0 0x100>; 1510 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1511 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1512 clock-names = "baudclk", "apb_pclk"; 1513 dmas = <&dmac0 18>, <&dmac0 19>; 1514 pinctrl-0 = <&uart9m0_xfer>; 1515 pinctrl-names = "default"; 1516 reg-io-width = <4>; 1517 reg-shift = <2>; 1518 status = "disabled"; 1519 }; 1520 1521 thermal_zones: thermal-zones { 1522 cpu_thermal: cpu-thermal { 1523 polling-delay-passive = <100>; 1524 polling-delay = <1000>; 1525 1526 thermal-sensors = <&tsadc 0>; 1527 1528 trips { 1529 cpu_alert0: cpu_alert0 { 1530 temperature = <70000>; 1531 hysteresis = <2000>; 1532 type = "passive"; 1533 }; 1534 cpu_alert1: cpu_alert1 { 1535 temperature = <75000>; 1536 hysteresis = <2000>; 1537 type = "passive"; 1538 }; 1539 cpu_crit: cpu_crit { 1540 temperature = <95000>; 1541 hysteresis = <2000>; 1542 type = "critical"; 1543 }; 1544 }; 1545 1546 cooling-maps { 1547 map0 { 1548 trip = <&cpu_alert0>; 1549 cooling-device = 1550 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1551 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1552 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1553 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1554 }; 1555 }; 1556 }; 1557 1558 gpu_thermal: gpu-thermal { 1559 polling-delay-passive = <20>; /* milliseconds */ 1560 polling-delay = <1000>; /* milliseconds */ 1561 1562 thermal-sensors = <&tsadc 1>; 1563 1564 trips { 1565 gpu_threshold: gpu-threshold { 1566 temperature = <70000>; 1567 hysteresis = <2000>; 1568 type = "passive"; 1569 }; 1570 gpu_target: gpu-target { 1571 temperature = <75000>; 1572 hysteresis = <2000>; 1573 type = "passive"; 1574 }; 1575 gpu_crit: gpu-crit { 1576 temperature = <95000>; 1577 hysteresis = <2000>; 1578 type = "critical"; 1579 }; 1580 }; 1581 1582 cooling-maps { 1583 map0 { 1584 trip = <&gpu_target>; 1585 cooling-device = 1586 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1587 }; 1588 }; 1589 }; 1590 }; 1591 1592 tsadc: tsadc@fe710000 { 1593 compatible = "rockchip,rk3568-tsadc"; 1594 reg = <0x0 0xfe710000 0x0 0x100>; 1595 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1596 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 1597 assigned-clock-rates = <17000000>, <700000>; 1598 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 1599 clock-names = "tsadc", "apb_pclk"; 1600 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, 1601 <&cru SRST_TSADCPHY>; 1602 rockchip,grf = <&grf>; 1603 rockchip,hw-tshut-temp = <95000>; 1604 pinctrl-names = "init", "default", "sleep"; 1605 pinctrl-0 = <&tsadc_pin>; 1606 pinctrl-1 = <&tsadc_shutorg>; 1607 pinctrl-2 = <&tsadc_pin>; 1608 #thermal-sensor-cells = <1>; 1609 status = "disabled"; 1610 }; 1611 1612 saradc: saradc@fe720000 { 1613 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 1614 reg = <0x0 0xfe720000 0x0 0x100>; 1615 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1616 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1617 clock-names = "saradc", "apb_pclk"; 1618 resets = <&cru SRST_P_SARADC>; 1619 reset-names = "saradc-apb"; 1620 #io-channel-cells = <1>; 1621 status = "disabled"; 1622 }; 1623 1624 pwm4: pwm@fe6e0000 { 1625 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1626 reg = <0x0 0xfe6e0000 0x0 0x10>; 1627 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1628 clock-names = "pwm", "pclk"; 1629 pinctrl-0 = <&pwm4_pins>; 1630 pinctrl-names = "default"; 1631 #pwm-cells = <3>; 1632 status = "disabled"; 1633 }; 1634 1635 pwm5: pwm@fe6e0010 { 1636 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1637 reg = <0x0 0xfe6e0010 0x0 0x10>; 1638 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1639 clock-names = "pwm", "pclk"; 1640 pinctrl-0 = <&pwm5_pins>; 1641 pinctrl-names = "default"; 1642 #pwm-cells = <3>; 1643 status = "disabled"; 1644 }; 1645 1646 pwm6: pwm@fe6e0020 { 1647 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1648 reg = <0x0 0xfe6e0020 0x0 0x10>; 1649 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1650 clock-names = "pwm", "pclk"; 1651 pinctrl-0 = <&pwm6_pins>; 1652 pinctrl-names = "default"; 1653 #pwm-cells = <3>; 1654 status = "disabled"; 1655 }; 1656 1657 pwm7: pwm@fe6e0030 { 1658 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1659 reg = <0x0 0xfe6e0030 0x0 0x10>; 1660 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1661 clock-names = "pwm", "pclk"; 1662 pinctrl-0 = <&pwm7_pins>; 1663 pinctrl-names = "default"; 1664 #pwm-cells = <3>; 1665 status = "disabled"; 1666 }; 1667 1668 pwm8: pwm@fe6f0000 { 1669 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1670 reg = <0x0 0xfe6f0000 0x0 0x10>; 1671 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1672 clock-names = "pwm", "pclk"; 1673 pinctrl-0 = <&pwm8m0_pins>; 1674 pinctrl-names = "default"; 1675 #pwm-cells = <3>; 1676 status = "disabled"; 1677 }; 1678 1679 pwm9: pwm@fe6f0010 { 1680 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1681 reg = <0x0 0xfe6f0010 0x0 0x10>; 1682 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1683 clock-names = "pwm", "pclk"; 1684 pinctrl-0 = <&pwm9m0_pins>; 1685 pinctrl-names = "default"; 1686 #pwm-cells = <3>; 1687 status = "disabled"; 1688 }; 1689 1690 pwm10: pwm@fe6f0020 { 1691 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1692 reg = <0x0 0xfe6f0020 0x0 0x10>; 1693 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1694 clock-names = "pwm", "pclk"; 1695 pinctrl-0 = <&pwm10m0_pins>; 1696 pinctrl-names = "default"; 1697 #pwm-cells = <3>; 1698 status = "disabled"; 1699 }; 1700 1701 pwm11: pwm@fe6f0030 { 1702 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1703 reg = <0x0 0xfe6f0030 0x0 0x10>; 1704 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1705 clock-names = "pwm", "pclk"; 1706 pinctrl-0 = <&pwm11m0_pins>; 1707 pinctrl-names = "default"; 1708 #pwm-cells = <3>; 1709 status = "disabled"; 1710 }; 1711 1712 pwm12: pwm@fe700000 { 1713 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1714 reg = <0x0 0xfe700000 0x0 0x10>; 1715 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1716 clock-names = "pwm", "pclk"; 1717 pinctrl-0 = <&pwm12m0_pins>; 1718 pinctrl-names = "default"; 1719 #pwm-cells = <3>; 1720 status = "disabled"; 1721 }; 1722 1723 pwm13: pwm@fe700010 { 1724 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1725 reg = <0x0 0xfe700010 0x0 0x10>; 1726 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1727 clock-names = "pwm", "pclk"; 1728 pinctrl-0 = <&pwm13m0_pins>; 1729 pinctrl-names = "default"; 1730 #pwm-cells = <3>; 1731 status = "disabled"; 1732 }; 1733 1734 pwm14: pwm@fe700020 { 1735 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1736 reg = <0x0 0xfe700020 0x0 0x10>; 1737 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1738 clock-names = "pwm", "pclk"; 1739 pinctrl-0 = <&pwm14m0_pins>; 1740 pinctrl-names = "default"; 1741 #pwm-cells = <3>; 1742 status = "disabled"; 1743 }; 1744 1745 pwm15: pwm@fe700030 { 1746 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1747 reg = <0x0 0xfe700030 0x0 0x10>; 1748 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1749 clock-names = "pwm", "pclk"; 1750 pinctrl-0 = <&pwm15m0_pins>; 1751 pinctrl-names = "default"; 1752 #pwm-cells = <3>; 1753 status = "disabled"; 1754 }; 1755 1756 combphy1: phy@fe830000 { 1757 compatible = "rockchip,rk3568-naneng-combphy"; 1758 reg = <0x0 0xfe830000 0x0 0x100>; 1759 clocks = <&pmucru CLK_PCIEPHY1_REF>, 1760 <&cru PCLK_PIPEPHY1>, 1761 <&cru PCLK_PIPE>; 1762 clock-names = "ref", "apb", "pipe"; 1763 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; 1764 assigned-clock-rates = <100000000>; 1765 resets = <&cru SRST_PIPEPHY1>; 1766 rockchip,pipe-grf = <&pipegrf>; 1767 rockchip,pipe-phy-grf = <&pipe_phy_grf1>; 1768 #phy-cells = <1>; 1769 status = "disabled"; 1770 }; 1771 1772 combphy2: phy@fe840000 { 1773 compatible = "rockchip,rk3568-naneng-combphy"; 1774 reg = <0x0 0xfe840000 0x0 0x100>; 1775 clocks = <&pmucru CLK_PCIEPHY2_REF>, 1776 <&cru PCLK_PIPEPHY2>, 1777 <&cru PCLK_PIPE>; 1778 clock-names = "ref", "apb", "pipe"; 1779 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; 1780 assigned-clock-rates = <100000000>; 1781 resets = <&cru SRST_PIPEPHY2>; 1782 rockchip,pipe-grf = <&pipegrf>; 1783 rockchip,pipe-phy-grf = <&pipe_phy_grf2>; 1784 #phy-cells = <1>; 1785 status = "disabled"; 1786 }; 1787 1788 csi_dphy: phy@fe870000 { 1789 compatible = "rockchip,rk3568-csi-dphy"; 1790 reg = <0x0 0xfe870000 0x0 0x10000>; 1791 clocks = <&cru PCLK_MIPICSIPHY>; 1792 clock-names = "pclk"; 1793 #phy-cells = <0>; 1794 resets = <&cru SRST_P_MIPICSIPHY>; 1795 reset-names = "apb"; 1796 rockchip,grf = <&grf>; 1797 status = "disabled"; 1798 }; 1799 1800 dsi_dphy0: mipi-dphy@fe850000 { 1801 compatible = "rockchip,rk3568-dsi-dphy"; 1802 reg = <0x0 0xfe850000 0x0 0x10000>; 1803 clock-names = "ref", "pclk"; 1804 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; 1805 #phy-cells = <0>; 1806 power-domains = <&power RK3568_PD_VO>; 1807 reset-names = "apb"; 1808 resets = <&cru SRST_P_MIPIDSIPHY0>; 1809 status = "disabled"; 1810 }; 1811 1812 dsi_dphy1: mipi-dphy@fe860000 { 1813 compatible = "rockchip,rk3568-dsi-dphy"; 1814 reg = <0x0 0xfe860000 0x0 0x10000>; 1815 clock-names = "ref", "pclk"; 1816 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; 1817 #phy-cells = <0>; 1818 power-domains = <&power RK3568_PD_VO>; 1819 reset-names = "apb"; 1820 resets = <&cru SRST_P_MIPIDSIPHY1>; 1821 status = "disabled"; 1822 }; 1823 1824 usb2phy0: usb2phy@fe8a0000 { 1825 compatible = "rockchip,rk3568-usb2phy"; 1826 reg = <0x0 0xfe8a0000 0x0 0x10000>; 1827 clocks = <&pmucru CLK_USBPHY0_REF>; 1828 clock-names = "phyclk"; 1829 clock-output-names = "clk_usbphy0_480m"; 1830 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1831 rockchip,usbgrf = <&usb2phy0_grf>; 1832 #clock-cells = <0>; 1833 status = "disabled"; 1834 1835 usb2phy0_host: host-port { 1836 #phy-cells = <0>; 1837 status = "disabled"; 1838 }; 1839 1840 usb2phy0_otg: otg-port { 1841 #phy-cells = <0>; 1842 status = "disabled"; 1843 }; 1844 }; 1845 1846 usb2phy1: usb2phy@fe8b0000 { 1847 compatible = "rockchip,rk3568-usb2phy"; 1848 reg = <0x0 0xfe8b0000 0x0 0x10000>; 1849 clocks = <&pmucru CLK_USBPHY1_REF>; 1850 clock-names = "phyclk"; 1851 clock-output-names = "clk_usbphy1_480m"; 1852 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1853 rockchip,usbgrf = <&usb2phy1_grf>; 1854 #clock-cells = <0>; 1855 status = "disabled"; 1856 1857 usb2phy1_host: host-port { 1858 #phy-cells = <0>; 1859 status = "disabled"; 1860 }; 1861 1862 usb2phy1_otg: otg-port { 1863 #phy-cells = <0>; 1864 status = "disabled"; 1865 }; 1866 }; 1867 1868 pinctrl: pinctrl { 1869 compatible = "rockchip,rk3568-pinctrl"; 1870 rockchip,grf = <&grf>; 1871 rockchip,pmu = <&pmugrf>; 1872 #address-cells = <2>; 1873 #size-cells = <2>; 1874 ranges; 1875 1876 gpio0: gpio@fdd60000 { 1877 compatible = "rockchip,gpio-bank"; 1878 reg = <0x0 0xfdd60000 0x0 0x100>; 1879 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1880 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 1881 gpio-controller; 1882 gpio-ranges = <&pinctrl 0 0 32>; 1883 #gpio-cells = <2>; 1884 interrupt-controller; 1885 #interrupt-cells = <2>; 1886 }; 1887 1888 gpio1: gpio@fe740000 { 1889 compatible = "rockchip,gpio-bank"; 1890 reg = <0x0 0xfe740000 0x0 0x100>; 1891 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1892 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1893 gpio-controller; 1894 gpio-ranges = <&pinctrl 0 32 32>; 1895 #gpio-cells = <2>; 1896 interrupt-controller; 1897 #interrupt-cells = <2>; 1898 }; 1899 1900 gpio2: gpio@fe750000 { 1901 compatible = "rockchip,gpio-bank"; 1902 reg = <0x0 0xfe750000 0x0 0x100>; 1903 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1904 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1905 gpio-controller; 1906 gpio-ranges = <&pinctrl 0 64 32>; 1907 #gpio-cells = <2>; 1908 interrupt-controller; 1909 #interrupt-cells = <2>; 1910 }; 1911 1912 gpio3: gpio@fe760000 { 1913 compatible = "rockchip,gpio-bank"; 1914 reg = <0x0 0xfe760000 0x0 0x100>; 1915 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1916 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1917 gpio-controller; 1918 gpio-ranges = <&pinctrl 0 96 32>; 1919 #gpio-cells = <2>; 1920 interrupt-controller; 1921 #interrupt-cells = <2>; 1922 }; 1923 1924 gpio4: gpio@fe770000 { 1925 compatible = "rockchip,gpio-bank"; 1926 reg = <0x0 0xfe770000 0x0 0x100>; 1927 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1928 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1929 gpio-controller; 1930 gpio-ranges = <&pinctrl 0 128 32>; 1931 #gpio-cells = <2>; 1932 interrupt-controller; 1933 #interrupt-cells = <2>; 1934 }; 1935 }; 1936}; 1937 1938#include "rk3568-pinctrl.dtsi" 1939