1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3568-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 gpio0 = &gpio0; 22 gpio1 = &gpio1; 23 gpio2 = &gpio2; 24 gpio3 = &gpio3; 25 gpio4 = &gpio4; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 serial6 = &uart6; 39 serial7 = &uart7; 40 serial8 = &uart8; 41 serial9 = &uart9; 42 spi0 = &spi0; 43 spi1 = &spi1; 44 spi2 = &spi2; 45 spi3 = &spi3; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x0 0x0>; 56 clocks = <&scmi_clk 0>; 57 #cooling-cells = <2>; 58 enable-method = "psci"; 59 i-cache-size = <0x8000>; 60 i-cache-line-size = <64>; 61 i-cache-sets = <128>; 62 d-cache-size = <0x8000>; 63 d-cache-line-size = <64>; 64 d-cache-sets = <128>; 65 next-level-cache = <&l3_cache>; 66 }; 67 68 cpu1: cpu@100 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a55"; 71 reg = <0x0 0x100>; 72 #cooling-cells = <2>; 73 enable-method = "psci"; 74 i-cache-size = <0x8000>; 75 i-cache-line-size = <64>; 76 i-cache-sets = <128>; 77 d-cache-size = <0x8000>; 78 d-cache-line-size = <64>; 79 d-cache-sets = <128>; 80 next-level-cache = <&l3_cache>; 81 }; 82 83 cpu2: cpu@200 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a55"; 86 reg = <0x0 0x200>; 87 #cooling-cells = <2>; 88 enable-method = "psci"; 89 i-cache-size = <0x8000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <128>; 92 d-cache-size = <0x8000>; 93 d-cache-line-size = <64>; 94 d-cache-sets = <128>; 95 next-level-cache = <&l3_cache>; 96 }; 97 98 cpu3: cpu@300 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a55"; 101 reg = <0x0 0x300>; 102 #cooling-cells = <2>; 103 enable-method = "psci"; 104 i-cache-size = <0x8000>; 105 i-cache-line-size = <64>; 106 i-cache-sets = <128>; 107 d-cache-size = <0x8000>; 108 d-cache-line-size = <64>; 109 d-cache-sets = <128>; 110 next-level-cache = <&l3_cache>; 111 }; 112 }; 113 114 /* 115 * There are no private per-core L2 caches, but only the 116 * L3 cache that appears to the CPU cores as L2 caches 117 */ 118 l3_cache: l3-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 cache-unified; 122 cache-size = <0x80000>; 123 cache-line-size = <64>; 124 cache-sets = <512>; 125 }; 126 127 display_subsystem: display-subsystem { 128 compatible = "rockchip,display-subsystem"; 129 ports = <&vop_out>; 130 }; 131 132 firmware { 133 scmi: scmi { 134 compatible = "arm,scmi-smc"; 135 arm,smc-id = <0x82000010>; 136 shmem = <&scmi_shmem>; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 140 scmi_clk: protocol@14 { 141 reg = <0x14>; 142 #clock-cells = <1>; 143 }; 144 }; 145 }; 146 147 hdmi_sound: hdmi-sound { 148 compatible = "simple-audio-card"; 149 simple-audio-card,name = "HDMI"; 150 simple-audio-card,format = "i2s"; 151 simple-audio-card,mclk-fs = <256>; 152 status = "disabled"; 153 154 simple-audio-card,codec { 155 sound-dai = <&hdmi>; 156 }; 157 158 simple-audio-card,cpu { 159 sound-dai = <&i2s0_8ch>; 160 }; 161 }; 162 163 pmu { 164 compatible = "arm,cortex-a55-pmu"; 165 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 169 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 170 }; 171 172 psci { 173 compatible = "arm,psci-1.0"; 174 method = "smc"; 175 }; 176 177 timer { 178 compatible = "arm,armv8-timer"; 179 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 183 arm,no-tick-in-suspend; 184 }; 185 186 xin24m: xin24m { 187 compatible = "fixed-clock"; 188 clock-frequency = <24000000>; 189 clock-output-names = "xin24m"; 190 #clock-cells = <0>; 191 }; 192 193 xin32k: xin32k { 194 compatible = "fixed-clock"; 195 clock-frequency = <32768>; 196 clock-output-names = "xin32k"; 197 pinctrl-0 = <&clk32k_out0>; 198 pinctrl-names = "default"; 199 #clock-cells = <0>; 200 }; 201 202 sram@10f000 { 203 compatible = "mmio-sram"; 204 reg = <0x0 0x0010f000 0x0 0x100>; 205 #address-cells = <1>; 206 #size-cells = <1>; 207 ranges = <0 0x0 0x0010f000 0x100>; 208 209 scmi_shmem: sram@0 { 210 compatible = "arm,scmi-shmem"; 211 reg = <0x0 0x100>; 212 }; 213 }; 214 215 sata1: sata@fc400000 { 216 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 217 reg = <0 0xfc400000 0 0x1000>; 218 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, 219 <&cru CLK_SATA1_RXOOB>; 220 clock-names = "sata", "pmalive", "rxoob"; 221 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 222 phys = <&combphy1 PHY_TYPE_SATA>; 223 phy-names = "sata-phy"; 224 ports-implemented = <0x1>; 225 power-domains = <&power RK3568_PD_PIPE>; 226 status = "disabled"; 227 }; 228 229 sata2: sata@fc800000 { 230 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 231 reg = <0 0xfc800000 0 0x1000>; 232 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, 233 <&cru CLK_SATA2_RXOOB>; 234 clock-names = "sata", "pmalive", "rxoob"; 235 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 236 phys = <&combphy2 PHY_TYPE_SATA>; 237 phy-names = "sata-phy"; 238 ports-implemented = <0x1>; 239 power-domains = <&power RK3568_PD_PIPE>; 240 status = "disabled"; 241 }; 242 243 usb_host0_xhci: usb@fcc00000 { 244 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 245 reg = <0x0 0xfcc00000 0x0 0x400000>; 246 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 248 <&cru ACLK_USB3OTG0>; 249 clock-names = "ref_clk", "suspend_clk", 250 "bus_clk"; 251 dr_mode = "otg"; 252 phy_type = "utmi_wide"; 253 power-domains = <&power RK3568_PD_PIPE>; 254 resets = <&cru SRST_USB3OTG0>; 255 snps,dis_u2_susphy_quirk; 256 status = "disabled"; 257 }; 258 259 usb_host1_xhci: usb@fd000000 { 260 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 261 reg = <0x0 0xfd000000 0x0 0x400000>; 262 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 264 <&cru ACLK_USB3OTG1>; 265 clock-names = "ref_clk", "suspend_clk", 266 "bus_clk"; 267 dr_mode = "host"; 268 phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; 269 phy-names = "usb2-phy", "usb3-phy"; 270 phy_type = "utmi_wide"; 271 power-domains = <&power RK3568_PD_PIPE>; 272 resets = <&cru SRST_USB3OTG1>; 273 snps,dis_u2_susphy_quirk; 274 status = "disabled"; 275 }; 276 277 gic: interrupt-controller@fd400000 { 278 compatible = "arm,gic-v3"; 279 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 280 <0x0 0xfd460000 0 0x80000>; /* GICR */ 281 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 282 interrupt-controller; 283 #interrupt-cells = <3>; 284 mbi-alias = <0x0 0xfd410000>; 285 mbi-ranges = <296 24>; 286 msi-controller; 287 }; 288 289 usb_host0_ehci: usb@fd800000 { 290 compatible = "generic-ehci"; 291 reg = <0x0 0xfd800000 0x0 0x40000>; 292 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 294 <&cru PCLK_USB>; 295 phys = <&usb2phy1_otg>; 296 phy-names = "usb"; 297 status = "disabled"; 298 }; 299 300 usb_host0_ohci: usb@fd840000 { 301 compatible = "generic-ohci"; 302 reg = <0x0 0xfd840000 0x0 0x40000>; 303 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 305 <&cru PCLK_USB>; 306 phys = <&usb2phy1_otg>; 307 phy-names = "usb"; 308 status = "disabled"; 309 }; 310 311 usb_host1_ehci: usb@fd880000 { 312 compatible = "generic-ehci"; 313 reg = <0x0 0xfd880000 0x0 0x40000>; 314 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 316 <&cru PCLK_USB>; 317 phys = <&usb2phy1_host>; 318 phy-names = "usb"; 319 status = "disabled"; 320 }; 321 322 usb_host1_ohci: usb@fd8c0000 { 323 compatible = "generic-ohci"; 324 reg = <0x0 0xfd8c0000 0x0 0x40000>; 325 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 327 <&cru PCLK_USB>; 328 phys = <&usb2phy1_host>; 329 phy-names = "usb"; 330 status = "disabled"; 331 }; 332 333 pmugrf: syscon@fdc20000 { 334 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 335 reg = <0x0 0xfdc20000 0x0 0x10000>; 336 337 pmu_io_domains: io-domains { 338 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 339 status = "disabled"; 340 }; 341 }; 342 343 pipegrf: syscon@fdc50000 { 344 reg = <0x0 0xfdc50000 0x0 0x1000>; 345 }; 346 347 grf: syscon@fdc60000 { 348 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 349 reg = <0x0 0xfdc60000 0x0 0x10000>; 350 }; 351 352 pipe_phy_grf1: syscon@fdc80000 { 353 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 354 reg = <0x0 0xfdc80000 0x0 0x1000>; 355 }; 356 357 pipe_phy_grf2: syscon@fdc90000 { 358 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 359 reg = <0x0 0xfdc90000 0x0 0x1000>; 360 }; 361 362 usb2phy0_grf: syscon@fdca0000 { 363 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 364 reg = <0x0 0xfdca0000 0x0 0x8000>; 365 }; 366 367 usb2phy1_grf: syscon@fdca8000 { 368 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 369 reg = <0x0 0xfdca8000 0x0 0x8000>; 370 }; 371 372 pmucru: clock-controller@fdd00000 { 373 compatible = "rockchip,rk3568-pmucru"; 374 reg = <0x0 0xfdd00000 0x0 0x1000>; 375 #clock-cells = <1>; 376 #reset-cells = <1>; 377 }; 378 379 cru: clock-controller@fdd20000 { 380 compatible = "rockchip,rk3568-cru"; 381 reg = <0x0 0xfdd20000 0x0 0x1000>; 382 clocks = <&xin24m>; 383 clock-names = "xin24m"; 384 #clock-cells = <1>; 385 #reset-cells = <1>; 386 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; 387 assigned-clock-rates = <32768>, <1200000000>, <200000000>; 388 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; 389 rockchip,grf = <&grf>; 390 }; 391 392 i2c0: i2c@fdd40000 { 393 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 394 reg = <0x0 0xfdd40000 0x0 0x1000>; 395 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 397 clock-names = "i2c", "pclk"; 398 pinctrl-0 = <&i2c0_xfer>; 399 pinctrl-names = "default"; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 status = "disabled"; 403 }; 404 405 uart0: serial@fdd50000 { 406 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 407 reg = <0x0 0xfdd50000 0x0 0x100>; 408 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 410 clock-names = "baudclk", "apb_pclk"; 411 dmas = <&dmac0 0>, <&dmac0 1>; 412 pinctrl-0 = <&uart0_xfer>; 413 pinctrl-names = "default"; 414 reg-io-width = <4>; 415 reg-shift = <2>; 416 status = "disabled"; 417 }; 418 419 pwm0: pwm@fdd70000 { 420 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 421 reg = <0x0 0xfdd70000 0x0 0x10>; 422 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 423 clock-names = "pwm", "pclk"; 424 pinctrl-0 = <&pwm0m0_pins>; 425 pinctrl-names = "default"; 426 #pwm-cells = <3>; 427 status = "disabled"; 428 }; 429 430 pwm1: pwm@fdd70010 { 431 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 432 reg = <0x0 0xfdd70010 0x0 0x10>; 433 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 434 clock-names = "pwm", "pclk"; 435 pinctrl-0 = <&pwm1m0_pins>; 436 pinctrl-names = "default"; 437 #pwm-cells = <3>; 438 status = "disabled"; 439 }; 440 441 pwm2: pwm@fdd70020 { 442 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 443 reg = <0x0 0xfdd70020 0x0 0x10>; 444 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 445 clock-names = "pwm", "pclk"; 446 pinctrl-0 = <&pwm2m0_pins>; 447 pinctrl-names = "default"; 448 #pwm-cells = <3>; 449 status = "disabled"; 450 }; 451 452 pwm3: pwm@fdd70030 { 453 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 454 reg = <0x0 0xfdd70030 0x0 0x10>; 455 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 456 clock-names = "pwm", "pclk"; 457 pinctrl-0 = <&pwm3_pins>; 458 pinctrl-names = "default"; 459 #pwm-cells = <3>; 460 status = "disabled"; 461 }; 462 463 pmu: power-management@fdd90000 { 464 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 465 reg = <0x0 0xfdd90000 0x0 0x1000>; 466 467 power: power-controller { 468 compatible = "rockchip,rk3568-power-controller"; 469 #power-domain-cells = <1>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 473 /* These power domains are grouped by VD_GPU */ 474 power-domain@RK3568_PD_GPU { 475 reg = <RK3568_PD_GPU>; 476 clocks = <&cru ACLK_GPU_PRE>, 477 <&cru PCLK_GPU_PRE>; 478 pm_qos = <&qos_gpu>; 479 #power-domain-cells = <0>; 480 }; 481 482 /* These power domains are grouped by VD_LOGIC */ 483 power-domain@RK3568_PD_VI { 484 reg = <RK3568_PD_VI>; 485 clocks = <&cru HCLK_VI>, 486 <&cru PCLK_VI>; 487 pm_qos = <&qos_isp>, 488 <&qos_vicap0>, 489 <&qos_vicap1>; 490 #power-domain-cells = <0>; 491 }; 492 493 power-domain@RK3568_PD_VO { 494 reg = <RK3568_PD_VO>; 495 clocks = <&cru HCLK_VO>, 496 <&cru PCLK_VO>, 497 <&cru ACLK_VOP_PRE>; 498 pm_qos = <&qos_hdcp>, 499 <&qos_vop_m0>, 500 <&qos_vop_m1>; 501 #power-domain-cells = <0>; 502 }; 503 504 power-domain@RK3568_PD_RGA { 505 reg = <RK3568_PD_RGA>; 506 clocks = <&cru HCLK_RGA_PRE>, 507 <&cru PCLK_RGA_PRE>; 508 pm_qos = <&qos_ebc>, 509 <&qos_iep>, 510 <&qos_jpeg_dec>, 511 <&qos_jpeg_enc>, 512 <&qos_rga_rd>, 513 <&qos_rga_wr>; 514 #power-domain-cells = <0>; 515 }; 516 517 power-domain@RK3568_PD_VPU { 518 reg = <RK3568_PD_VPU>; 519 clocks = <&cru HCLK_VPU_PRE>; 520 pm_qos = <&qos_vpu>; 521 #power-domain-cells = <0>; 522 }; 523 524 power-domain@RK3568_PD_RKVDEC { 525 clocks = <&cru HCLK_RKVDEC_PRE>; 526 reg = <RK3568_PD_RKVDEC>; 527 pm_qos = <&qos_rkvdec>; 528 #power-domain-cells = <0>; 529 }; 530 531 power-domain@RK3568_PD_RKVENC { 532 reg = <RK3568_PD_RKVENC>; 533 clocks = <&cru HCLK_RKVENC_PRE>; 534 pm_qos = <&qos_rkvenc_rd_m0>, 535 <&qos_rkvenc_rd_m1>, 536 <&qos_rkvenc_wr_m0>; 537 #power-domain-cells = <0>; 538 }; 539 }; 540 }; 541 542 gpu: gpu@fde60000 { 543 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; 544 reg = <0x0 0xfde60000 0x0 0x4000>; 545 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 548 interrupt-names = "job", "mmu", "gpu"; 549 clocks = <&scmi_clk 1>, <&cru CLK_GPU>; 550 clock-names = "gpu", "bus"; 551 #cooling-cells = <2>; 552 power-domains = <&power RK3568_PD_GPU>; 553 status = "disabled"; 554 }; 555 556 vpu: video-codec@fdea0400 { 557 compatible = "rockchip,rk3568-vpu"; 558 reg = <0x0 0xfdea0000 0x0 0x800>; 559 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 560 interrupt-names = "vdpu"; 561 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 562 clock-names = "aclk", "hclk"; 563 iommus = <&vdpu_mmu>; 564 power-domains = <&power RK3568_PD_VPU>; 565 }; 566 567 vdpu_mmu: iommu@fdea0800 { 568 compatible = "rockchip,rk3568-iommu"; 569 reg = <0x0 0xfdea0800 0x0 0x40>; 570 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 571 clock-names = "aclk", "iface"; 572 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 573 power-domains = <&power RK3568_PD_VPU>; 574 #iommu-cells = <0>; 575 }; 576 577 rga: rga@fdeb0000 { 578 compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; 579 reg = <0x0 0xfdeb0000 0x0 0x180>; 580 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; 582 clock-names = "aclk", "hclk", "sclk"; 583 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 584 reset-names = "core", "axi", "ahb"; 585 power-domains = <&power RK3568_PD_RGA>; 586 }; 587 588 vepu: video-codec@fdee0000 { 589 compatible = "rockchip,rk3568-vepu"; 590 reg = <0x0 0xfdee0000 0x0 0x800>; 591 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 593 clock-names = "aclk", "hclk"; 594 iommus = <&vepu_mmu>; 595 power-domains = <&power RK3568_PD_RGA>; 596 }; 597 598 vepu_mmu: iommu@fdee0800 { 599 compatible = "rockchip,rk3568-iommu"; 600 reg = <0x0 0xfdee0800 0x0 0x40>; 601 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 603 clock-names = "aclk", "iface"; 604 power-domains = <&power RK3568_PD_RGA>; 605 #iommu-cells = <0>; 606 }; 607 608 sdmmc2: mmc@fe000000 { 609 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 610 reg = <0x0 0xfe000000 0x0 0x4000>; 611 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 613 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 614 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 615 fifo-depth = <0x100>; 616 max-frequency = <150000000>; 617 resets = <&cru SRST_SDMMC2>; 618 reset-names = "reset"; 619 status = "disabled"; 620 }; 621 622 gmac1: ethernet@fe010000 { 623 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 624 reg = <0x0 0xfe010000 0x0 0x10000>; 625 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 627 interrupt-names = "macirq", "eth_wake_irq"; 628 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 629 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 630 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 631 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 632 clock-names = "stmmaceth", "mac_clk_rx", 633 "mac_clk_tx", "clk_mac_refout", 634 "aclk_mac", "pclk_mac", 635 "clk_mac_speed", "ptp_ref"; 636 resets = <&cru SRST_A_GMAC1>; 637 reset-names = "stmmaceth"; 638 rockchip,grf = <&grf>; 639 snps,axi-config = <&gmac1_stmmac_axi_setup>; 640 snps,mixed-burst; 641 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 642 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 643 snps,tso; 644 status = "disabled"; 645 646 mdio1: mdio { 647 compatible = "snps,dwmac-mdio"; 648 #address-cells = <0x1>; 649 #size-cells = <0x0>; 650 }; 651 652 gmac1_stmmac_axi_setup: stmmac-axi-config { 653 snps,blen = <0 0 0 0 16 8 4>; 654 snps,rd_osr_lmt = <8>; 655 snps,wr_osr_lmt = <4>; 656 }; 657 658 gmac1_mtl_rx_setup: rx-queues-config { 659 snps,rx-queues-to-use = <1>; 660 queue0 {}; 661 }; 662 663 gmac1_mtl_tx_setup: tx-queues-config { 664 snps,tx-queues-to-use = <1>; 665 queue0 {}; 666 }; 667 }; 668 669 vop: vop@fe040000 { 670 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; 671 reg-names = "vop", "gamma-lut"; 672 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, 674 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; 675 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; 676 iommus = <&vop_mmu>; 677 power-domains = <&power RK3568_PD_VO>; 678 rockchip,grf = <&grf>; 679 status = "disabled"; 680 681 vop_out: ports { 682 #address-cells = <1>; 683 #size-cells = <0>; 684 685 vp0: port@0 { 686 reg = <0>; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 }; 690 691 vp1: port@1 { 692 reg = <1>; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 }; 696 697 vp2: port@2 { 698 reg = <2>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 }; 702 }; 703 }; 704 705 vop_mmu: iommu@fe043e00 { 706 compatible = "rockchip,rk3568-iommu"; 707 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; 708 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 710 clock-names = "aclk", "iface"; 711 #iommu-cells = <0>; 712 power-domains = <&power RK3568_PD_VO>; 713 status = "disabled"; 714 }; 715 716 dsi0: dsi@fe060000 { 717 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 718 reg = <0x00 0xfe060000 0x00 0x10000>; 719 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 720 clock-names = "pclk"; 721 clocks = <&cru PCLK_DSITX_0>; 722 phy-names = "dphy"; 723 phys = <&dsi_dphy0>; 724 power-domains = <&power RK3568_PD_VO>; 725 reset-names = "apb"; 726 resets = <&cru SRST_P_DSITX_0>; 727 rockchip,grf = <&grf>; 728 status = "disabled"; 729 730 ports { 731 #address-cells = <1>; 732 #size-cells = <0>; 733 734 dsi0_in: port@0 { 735 reg = <0>; 736 }; 737 738 dsi0_out: port@1 { 739 reg = <1>; 740 }; 741 }; 742 }; 743 744 dsi1: dsi@fe070000 { 745 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 746 reg = <0x0 0xfe070000 0x0 0x10000>; 747 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 748 clock-names = "pclk"; 749 clocks = <&cru PCLK_DSITX_1>; 750 phy-names = "dphy"; 751 phys = <&dsi_dphy1>; 752 power-domains = <&power RK3568_PD_VO>; 753 reset-names = "apb"; 754 resets = <&cru SRST_P_DSITX_1>; 755 rockchip,grf = <&grf>; 756 status = "disabled"; 757 758 ports { 759 #address-cells = <1>; 760 #size-cells = <0>; 761 762 dsi1_in: port@0 { 763 reg = <0>; 764 }; 765 766 dsi1_out: port@1 { 767 reg = <1>; 768 }; 769 }; 770 }; 771 772 hdmi: hdmi@fe0a0000 { 773 compatible = "rockchip,rk3568-dw-hdmi"; 774 reg = <0x0 0xfe0a0000 0x0 0x20000>; 775 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&cru PCLK_HDMI_HOST>, 777 <&cru CLK_HDMI_SFR>, 778 <&cru CLK_HDMI_CEC>, 779 <&pmucru CLK_HDMI_REF>, 780 <&cru HCLK_VO>; 781 clock-names = "iahb", "isfr", "cec", "ref"; 782 pinctrl-names = "default"; 783 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; 784 power-domains = <&power RK3568_PD_VO>; 785 reg-io-width = <4>; 786 rockchip,grf = <&grf>; 787 #sound-dai-cells = <0>; 788 status = "disabled"; 789 790 ports { 791 #address-cells = <1>; 792 #size-cells = <0>; 793 794 hdmi_in: port@0 { 795 reg = <0>; 796 }; 797 798 hdmi_out: port@1 { 799 reg = <1>; 800 }; 801 }; 802 }; 803 804 qos_gpu: qos@fe128000 { 805 compatible = "rockchip,rk3568-qos", "syscon"; 806 reg = <0x0 0xfe128000 0x0 0x20>; 807 }; 808 809 qos_rkvenc_rd_m0: qos@fe138080 { 810 compatible = "rockchip,rk3568-qos", "syscon"; 811 reg = <0x0 0xfe138080 0x0 0x20>; 812 }; 813 814 qos_rkvenc_rd_m1: qos@fe138100 { 815 compatible = "rockchip,rk3568-qos", "syscon"; 816 reg = <0x0 0xfe138100 0x0 0x20>; 817 }; 818 819 qos_rkvenc_wr_m0: qos@fe138180 { 820 compatible = "rockchip,rk3568-qos", "syscon"; 821 reg = <0x0 0xfe138180 0x0 0x20>; 822 }; 823 824 qos_isp: qos@fe148000 { 825 compatible = "rockchip,rk3568-qos", "syscon"; 826 reg = <0x0 0xfe148000 0x0 0x20>; 827 }; 828 829 qos_vicap0: qos@fe148080 { 830 compatible = "rockchip,rk3568-qos", "syscon"; 831 reg = <0x0 0xfe148080 0x0 0x20>; 832 }; 833 834 qos_vicap1: qos@fe148100 { 835 compatible = "rockchip,rk3568-qos", "syscon"; 836 reg = <0x0 0xfe148100 0x0 0x20>; 837 }; 838 839 qos_vpu: qos@fe150000 { 840 compatible = "rockchip,rk3568-qos", "syscon"; 841 reg = <0x0 0xfe150000 0x0 0x20>; 842 }; 843 844 qos_ebc: qos@fe158000 { 845 compatible = "rockchip,rk3568-qos", "syscon"; 846 reg = <0x0 0xfe158000 0x0 0x20>; 847 }; 848 849 qos_iep: qos@fe158100 { 850 compatible = "rockchip,rk3568-qos", "syscon"; 851 reg = <0x0 0xfe158100 0x0 0x20>; 852 }; 853 854 qos_jpeg_dec: qos@fe158180 { 855 compatible = "rockchip,rk3568-qos", "syscon"; 856 reg = <0x0 0xfe158180 0x0 0x20>; 857 }; 858 859 qos_jpeg_enc: qos@fe158200 { 860 compatible = "rockchip,rk3568-qos", "syscon"; 861 reg = <0x0 0xfe158200 0x0 0x20>; 862 }; 863 864 qos_rga_rd: qos@fe158280 { 865 compatible = "rockchip,rk3568-qos", "syscon"; 866 reg = <0x0 0xfe158280 0x0 0x20>; 867 }; 868 869 qos_rga_wr: qos@fe158300 { 870 compatible = "rockchip,rk3568-qos", "syscon"; 871 reg = <0x0 0xfe158300 0x0 0x20>; 872 }; 873 874 qos_npu: qos@fe180000 { 875 compatible = "rockchip,rk3568-qos", "syscon"; 876 reg = <0x0 0xfe180000 0x0 0x20>; 877 }; 878 879 qos_pcie2x1: qos@fe190000 { 880 compatible = "rockchip,rk3568-qos", "syscon"; 881 reg = <0x0 0xfe190000 0x0 0x20>; 882 }; 883 884 qos_sata1: qos@fe190280 { 885 compatible = "rockchip,rk3568-qos", "syscon"; 886 reg = <0x0 0xfe190280 0x0 0x20>; 887 }; 888 889 qos_sata2: qos@fe190300 { 890 compatible = "rockchip,rk3568-qos", "syscon"; 891 reg = <0x0 0xfe190300 0x0 0x20>; 892 }; 893 894 qos_usb3_0: qos@fe190380 { 895 compatible = "rockchip,rk3568-qos", "syscon"; 896 reg = <0x0 0xfe190380 0x0 0x20>; 897 }; 898 899 qos_usb3_1: qos@fe190400 { 900 compatible = "rockchip,rk3568-qos", "syscon"; 901 reg = <0x0 0xfe190400 0x0 0x20>; 902 }; 903 904 qos_rkvdec: qos@fe198000 { 905 compatible = "rockchip,rk3568-qos", "syscon"; 906 reg = <0x0 0xfe198000 0x0 0x20>; 907 }; 908 909 qos_hdcp: qos@fe1a8000 { 910 compatible = "rockchip,rk3568-qos", "syscon"; 911 reg = <0x0 0xfe1a8000 0x0 0x20>; 912 }; 913 914 qos_vop_m0: qos@fe1a8080 { 915 compatible = "rockchip,rk3568-qos", "syscon"; 916 reg = <0x0 0xfe1a8080 0x0 0x20>; 917 }; 918 919 qos_vop_m1: qos@fe1a8100 { 920 compatible = "rockchip,rk3568-qos", "syscon"; 921 reg = <0x0 0xfe1a8100 0x0 0x20>; 922 }; 923 924 dfi: dfi@fe230000 { 925 compatible = "rockchip,rk3568-dfi"; 926 reg = <0x00 0xfe230000 0x00 0x400>; 927 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 928 rockchip,pmu = <&pmugrf>; 929 }; 930 931 pcie2x1: pcie@fe260000 { 932 compatible = "rockchip,rk3568-pcie"; 933 reg = <0x3 0xc0000000 0x0 0x00400000>, 934 <0x0 0xfe260000 0x0 0x00010000>, 935 <0x0 0xf4000000 0x0 0x00100000>; 936 reg-names = "dbi", "apb", "config"; 937 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 942 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 943 bus-range = <0x0 0xf>; 944 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 945 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, 946 <&cru CLK_PCIE20_AUX_NDFT>; 947 clock-names = "aclk_mst", "aclk_slv", 948 "aclk_dbi", "pclk", "aux"; 949 device_type = "pci"; 950 #interrupt-cells = <1>; 951 interrupt-map-mask = <0 0 0 7>; 952 interrupt-map = <0 0 0 1 &pcie_intc 0>, 953 <0 0 0 2 &pcie_intc 1>, 954 <0 0 0 3 &pcie_intc 2>, 955 <0 0 0 4 &pcie_intc 3>; 956 linux,pci-domain = <0>; 957 num-ib-windows = <6>; 958 num-ob-windows = <2>; 959 max-link-speed = <2>; 960 msi-map = <0x0 &gic 0x0 0x1000>; 961 num-lanes = <1>; 962 phys = <&combphy2 PHY_TYPE_PCIE>; 963 phy-names = "pcie-phy"; 964 power-domains = <&power RK3568_PD_PIPE>; 965 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 966 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, 967 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; 968 resets = <&cru SRST_PCIE20_POWERUP>; 969 reset-names = "pipe"; 970 #address-cells = <3>; 971 #size-cells = <2>; 972 status = "disabled"; 973 974 pcie_intc: legacy-interrupt-controller { 975 #address-cells = <0>; 976 #interrupt-cells = <1>; 977 interrupt-controller; 978 interrupt-parent = <&gic>; 979 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 980 }; 981 }; 982 983 sdmmc0: mmc@fe2b0000 { 984 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 985 reg = <0x0 0xfe2b0000 0x0 0x4000>; 986 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 988 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 989 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 990 fifo-depth = <0x100>; 991 max-frequency = <150000000>; 992 resets = <&cru SRST_SDMMC0>; 993 reset-names = "reset"; 994 status = "disabled"; 995 }; 996 997 sdmmc1: mmc@fe2c0000 { 998 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 999 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1000 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 1002 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 1003 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1004 fifo-depth = <0x100>; 1005 max-frequency = <150000000>; 1006 resets = <&cru SRST_SDMMC1>; 1007 reset-names = "reset"; 1008 status = "disabled"; 1009 }; 1010 1011 sfc: spi@fe300000 { 1012 compatible = "rockchip,sfc"; 1013 reg = <0x0 0xfe300000 0x0 0x4000>; 1014 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1016 clock-names = "clk_sfc", "hclk_sfc"; 1017 pinctrl-0 = <&fspi_pins>; 1018 pinctrl-names = "default"; 1019 status = "disabled"; 1020 }; 1021 1022 sdhci: mmc@fe310000 { 1023 compatible = "rockchip,rk3568-dwcmshc"; 1024 reg = <0x0 0xfe310000 0x0 0x10000>; 1025 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1026 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 1027 assigned-clock-rates = <200000000>, <24000000>; 1028 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1029 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1030 <&cru TCLK_EMMC>; 1031 clock-names = "core", "bus", "axi", "block", "timer"; 1032 status = "disabled"; 1033 }; 1034 1035 rng: rng@fe388000 { 1036 compatible = "rockchip,rk3568-rng"; 1037 reg = <0x0 0xfe388000 0x0 0x4000>; 1038 clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; 1039 clock-names = "core", "ahb"; 1040 resets = <&cru SRST_TRNG_NS>; 1041 status = "disabled"; 1042 }; 1043 1044 i2s0_8ch: i2s@fe400000 { 1045 compatible = "rockchip,rk3568-i2s-tdm"; 1046 reg = <0x0 0xfe400000 0x0 0x1000>; 1047 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1048 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1049 assigned-clock-rates = <1188000000>, <1188000000>; 1050 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1051 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1052 dmas = <&dmac1 0>; 1053 dma-names = "tx"; 1054 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1055 reset-names = "tx-m", "rx-m"; 1056 rockchip,grf = <&grf>; 1057 #sound-dai-cells = <0>; 1058 status = "disabled"; 1059 }; 1060 1061 i2s1_8ch: i2s@fe410000 { 1062 compatible = "rockchip,rk3568-i2s-tdm"; 1063 reg = <0x0 0xfe410000 0x0 0x1000>; 1064 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1065 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; 1066 assigned-clock-rates = <1188000000>, <1188000000>; 1067 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, 1068 <&cru HCLK_I2S1_8CH>; 1069 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1070 dmas = <&dmac1 3>, <&dmac1 2>; 1071 dma-names = "rx", "tx"; 1072 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1073 reset-names = "tx-m", "rx-m"; 1074 rockchip,grf = <&grf>; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx 1077 &i2s1m0_lrcktx &i2s1m0_lrckrx 1078 &i2s1m0_sdi0 &i2s1m0_sdi1 1079 &i2s1m0_sdi2 &i2s1m0_sdi3 1080 &i2s1m0_sdo0 &i2s1m0_sdo1 1081 &i2s1m0_sdo2 &i2s1m0_sdo3>; 1082 #sound-dai-cells = <0>; 1083 status = "disabled"; 1084 }; 1085 1086 i2s2_2ch: i2s@fe420000 { 1087 compatible = "rockchip,rk3568-i2s-tdm"; 1088 reg = <0x0 0xfe420000 0x0 0x1000>; 1089 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1090 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1091 assigned-clock-rates = <1188000000>; 1092 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1093 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1094 dmas = <&dmac1 4>, <&dmac1 5>; 1095 dma-names = "tx", "rx"; 1096 resets = <&cru SRST_M_I2S2_2CH>; 1097 reset-names = "tx-m"; 1098 rockchip,grf = <&grf>; 1099 pinctrl-names = "default"; 1100 pinctrl-0 = <&i2s2m0_sclktx 1101 &i2s2m0_lrcktx 1102 &i2s2m0_sdi 1103 &i2s2m0_sdo>; 1104 #sound-dai-cells = <0>; 1105 status = "disabled"; 1106 }; 1107 1108 i2s3_2ch: i2s@fe430000 { 1109 compatible = "rockchip,rk3568-i2s-tdm"; 1110 reg = <0x0 0xfe430000 0x0 0x1000>; 1111 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1112 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, 1113 <&cru HCLK_I2S3_2CH>; 1114 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1115 dmas = <&dmac1 6>, <&dmac1 7>; 1116 dma-names = "tx", "rx"; 1117 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; 1118 reset-names = "tx-m", "rx-m"; 1119 rockchip,grf = <&grf>; 1120 #sound-dai-cells = <0>; 1121 status = "disabled"; 1122 }; 1123 1124 pdm: pdm@fe440000 { 1125 compatible = "rockchip,rk3568-pdm"; 1126 reg = <0x0 0xfe440000 0x0 0x1000>; 1127 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1128 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1129 clock-names = "pdm_clk", "pdm_hclk"; 1130 dmas = <&dmac1 9>; 1131 dma-names = "rx"; 1132 pinctrl-0 = <&pdmm0_clk 1133 &pdmm0_clk1 1134 &pdmm0_sdi0 1135 &pdmm0_sdi1 1136 &pdmm0_sdi2 1137 &pdmm0_sdi3>; 1138 pinctrl-names = "default"; 1139 resets = <&cru SRST_M_PDM>; 1140 reset-names = "pdm-m"; 1141 #sound-dai-cells = <0>; 1142 status = "disabled"; 1143 }; 1144 1145 spdif: spdif@fe460000 { 1146 compatible = "rockchip,rk3568-spdif"; 1147 reg = <0x0 0xfe460000 0x0 0x1000>; 1148 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1149 clock-names = "mclk", "hclk"; 1150 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 1151 dmas = <&dmac1 1>; 1152 dma-names = "tx"; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&spdifm0_tx>; 1155 #sound-dai-cells = <0>; 1156 status = "disabled"; 1157 }; 1158 1159 dmac0: dma-controller@fe530000 { 1160 compatible = "arm,pl330", "arm,primecell"; 1161 reg = <0x0 0xfe530000 0x0 0x4000>; 1162 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1164 arm,pl330-periph-burst; 1165 clocks = <&cru ACLK_BUS>; 1166 clock-names = "apb_pclk"; 1167 #dma-cells = <1>; 1168 }; 1169 1170 dmac1: dma-controller@fe550000 { 1171 compatible = "arm,pl330", "arm,primecell"; 1172 reg = <0x0 0xfe550000 0x0 0x4000>; 1173 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1175 arm,pl330-periph-burst; 1176 clocks = <&cru ACLK_BUS>; 1177 clock-names = "apb_pclk"; 1178 #dma-cells = <1>; 1179 }; 1180 1181 i2c1: i2c@fe5a0000 { 1182 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1183 reg = <0x0 0xfe5a0000 0x0 0x1000>; 1184 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1185 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1186 clock-names = "i2c", "pclk"; 1187 pinctrl-0 = <&i2c1_xfer>; 1188 pinctrl-names = "default"; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 status = "disabled"; 1192 }; 1193 1194 i2c2: i2c@fe5b0000 { 1195 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1196 reg = <0x0 0xfe5b0000 0x0 0x1000>; 1197 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1199 clock-names = "i2c", "pclk"; 1200 pinctrl-0 = <&i2c2m0_xfer>; 1201 pinctrl-names = "default"; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 status = "disabled"; 1205 }; 1206 1207 i2c3: i2c@fe5c0000 { 1208 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1209 reg = <0x0 0xfe5c0000 0x0 0x1000>; 1210 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1211 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1212 clock-names = "i2c", "pclk"; 1213 pinctrl-0 = <&i2c3m0_xfer>; 1214 pinctrl-names = "default"; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 status = "disabled"; 1218 }; 1219 1220 i2c4: i2c@fe5d0000 { 1221 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1222 reg = <0x0 0xfe5d0000 0x0 0x1000>; 1223 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1224 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1225 clock-names = "i2c", "pclk"; 1226 pinctrl-0 = <&i2c4m0_xfer>; 1227 pinctrl-names = "default"; 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 status = "disabled"; 1231 }; 1232 1233 i2c5: i2c@fe5e0000 { 1234 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1235 reg = <0x0 0xfe5e0000 0x0 0x1000>; 1236 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1237 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1238 clock-names = "i2c", "pclk"; 1239 pinctrl-0 = <&i2c5m0_xfer>; 1240 pinctrl-names = "default"; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 status = "disabled"; 1244 }; 1245 1246 wdt: watchdog@fe600000 { 1247 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; 1248 reg = <0x0 0xfe600000 0x0 0x100>; 1249 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 1250 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 1251 clock-names = "tclk", "pclk"; 1252 }; 1253 1254 spi0: spi@fe610000 { 1255 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1256 reg = <0x0 0xfe610000 0x0 0x1000>; 1257 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1258 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1259 clock-names = "spiclk", "apb_pclk"; 1260 dmas = <&dmac0 20>, <&dmac0 21>; 1261 dma-names = "tx", "rx"; 1262 pinctrl-names = "default"; 1263 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 status = "disabled"; 1267 }; 1268 1269 spi1: spi@fe620000 { 1270 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1271 reg = <0x0 0xfe620000 0x0 0x1000>; 1272 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1273 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1274 clock-names = "spiclk", "apb_pclk"; 1275 dmas = <&dmac0 22>, <&dmac0 23>; 1276 dma-names = "tx", "rx"; 1277 pinctrl-names = "default"; 1278 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 1279 #address-cells = <1>; 1280 #size-cells = <0>; 1281 status = "disabled"; 1282 }; 1283 1284 spi2: spi@fe630000 { 1285 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1286 reg = <0x0 0xfe630000 0x0 0x1000>; 1287 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1288 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1289 clock-names = "spiclk", "apb_pclk"; 1290 dmas = <&dmac0 24>, <&dmac0 25>; 1291 dma-names = "tx", "rx"; 1292 pinctrl-names = "default"; 1293 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 status = "disabled"; 1297 }; 1298 1299 spi3: spi@fe640000 { 1300 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1301 reg = <0x0 0xfe640000 0x0 0x1000>; 1302 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1303 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1304 clock-names = "spiclk", "apb_pclk"; 1305 dmas = <&dmac0 26>, <&dmac0 27>; 1306 dma-names = "tx", "rx"; 1307 pinctrl-names = "default"; 1308 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 status = "disabled"; 1312 }; 1313 1314 uart1: serial@fe650000 { 1315 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1316 reg = <0x0 0xfe650000 0x0 0x100>; 1317 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1318 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1319 clock-names = "baudclk", "apb_pclk"; 1320 dmas = <&dmac0 2>, <&dmac0 3>; 1321 pinctrl-0 = <&uart1m0_xfer>; 1322 pinctrl-names = "default"; 1323 reg-io-width = <4>; 1324 reg-shift = <2>; 1325 status = "disabled"; 1326 }; 1327 1328 uart2: serial@fe660000 { 1329 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1330 reg = <0x0 0xfe660000 0x0 0x100>; 1331 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1332 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1333 clock-names = "baudclk", "apb_pclk"; 1334 dmas = <&dmac0 4>, <&dmac0 5>; 1335 pinctrl-0 = <&uart2m0_xfer>; 1336 pinctrl-names = "default"; 1337 reg-io-width = <4>; 1338 reg-shift = <2>; 1339 status = "disabled"; 1340 }; 1341 1342 uart3: serial@fe670000 { 1343 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1344 reg = <0x0 0xfe670000 0x0 0x100>; 1345 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1346 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1347 clock-names = "baudclk", "apb_pclk"; 1348 dmas = <&dmac0 6>, <&dmac0 7>; 1349 pinctrl-0 = <&uart3m0_xfer>; 1350 pinctrl-names = "default"; 1351 reg-io-width = <4>; 1352 reg-shift = <2>; 1353 status = "disabled"; 1354 }; 1355 1356 uart4: serial@fe680000 { 1357 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1358 reg = <0x0 0xfe680000 0x0 0x100>; 1359 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1360 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1361 clock-names = "baudclk", "apb_pclk"; 1362 dmas = <&dmac0 8>, <&dmac0 9>; 1363 pinctrl-0 = <&uart4m0_xfer>; 1364 pinctrl-names = "default"; 1365 reg-io-width = <4>; 1366 reg-shift = <2>; 1367 status = "disabled"; 1368 }; 1369 1370 uart5: serial@fe690000 { 1371 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1372 reg = <0x0 0xfe690000 0x0 0x100>; 1373 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1374 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1375 clock-names = "baudclk", "apb_pclk"; 1376 dmas = <&dmac0 10>, <&dmac0 11>; 1377 pinctrl-0 = <&uart5m0_xfer>; 1378 pinctrl-names = "default"; 1379 reg-io-width = <4>; 1380 reg-shift = <2>; 1381 status = "disabled"; 1382 }; 1383 1384 uart6: serial@fe6a0000 { 1385 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1386 reg = <0x0 0xfe6a0000 0x0 0x100>; 1387 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1388 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1389 clock-names = "baudclk", "apb_pclk"; 1390 dmas = <&dmac0 12>, <&dmac0 13>; 1391 pinctrl-0 = <&uart6m0_xfer>; 1392 pinctrl-names = "default"; 1393 reg-io-width = <4>; 1394 reg-shift = <2>; 1395 status = "disabled"; 1396 }; 1397 1398 uart7: serial@fe6b0000 { 1399 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1400 reg = <0x0 0xfe6b0000 0x0 0x100>; 1401 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1402 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1403 clock-names = "baudclk", "apb_pclk"; 1404 dmas = <&dmac0 14>, <&dmac0 15>; 1405 pinctrl-0 = <&uart7m0_xfer>; 1406 pinctrl-names = "default"; 1407 reg-io-width = <4>; 1408 reg-shift = <2>; 1409 status = "disabled"; 1410 }; 1411 1412 uart8: serial@fe6c0000 { 1413 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1414 reg = <0x0 0xfe6c0000 0x0 0x100>; 1415 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1416 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1417 clock-names = "baudclk", "apb_pclk"; 1418 dmas = <&dmac0 16>, <&dmac0 17>; 1419 pinctrl-0 = <&uart8m0_xfer>; 1420 pinctrl-names = "default"; 1421 reg-io-width = <4>; 1422 reg-shift = <2>; 1423 status = "disabled"; 1424 }; 1425 1426 uart9: serial@fe6d0000 { 1427 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1428 reg = <0x0 0xfe6d0000 0x0 0x100>; 1429 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1430 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1431 clock-names = "baudclk", "apb_pclk"; 1432 dmas = <&dmac0 18>, <&dmac0 19>; 1433 pinctrl-0 = <&uart9m0_xfer>; 1434 pinctrl-names = "default"; 1435 reg-io-width = <4>; 1436 reg-shift = <2>; 1437 status = "disabled"; 1438 }; 1439 1440 thermal_zones: thermal-zones { 1441 cpu_thermal: cpu-thermal { 1442 polling-delay-passive = <100>; 1443 polling-delay = <1000>; 1444 1445 thermal-sensors = <&tsadc 0>; 1446 1447 trips { 1448 cpu_alert0: cpu_alert0 { 1449 temperature = <70000>; 1450 hysteresis = <2000>; 1451 type = "passive"; 1452 }; 1453 cpu_alert1: cpu_alert1 { 1454 temperature = <75000>; 1455 hysteresis = <2000>; 1456 type = "passive"; 1457 }; 1458 cpu_crit: cpu_crit { 1459 temperature = <95000>; 1460 hysteresis = <2000>; 1461 type = "critical"; 1462 }; 1463 }; 1464 1465 cooling-maps { 1466 map0 { 1467 trip = <&cpu_alert0>; 1468 cooling-device = 1469 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1470 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1471 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1472 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1473 }; 1474 }; 1475 }; 1476 1477 gpu_thermal: gpu-thermal { 1478 polling-delay-passive = <20>; /* milliseconds */ 1479 polling-delay = <1000>; /* milliseconds */ 1480 1481 thermal-sensors = <&tsadc 1>; 1482 1483 trips { 1484 gpu_threshold: gpu-threshold { 1485 temperature = <70000>; 1486 hysteresis = <2000>; 1487 type = "passive"; 1488 }; 1489 gpu_target: gpu-target { 1490 temperature = <75000>; 1491 hysteresis = <2000>; 1492 type = "passive"; 1493 }; 1494 gpu_crit: gpu-crit { 1495 temperature = <95000>; 1496 hysteresis = <2000>; 1497 type = "critical"; 1498 }; 1499 }; 1500 1501 cooling-maps { 1502 map0 { 1503 trip = <&gpu_target>; 1504 cooling-device = 1505 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1506 }; 1507 }; 1508 }; 1509 }; 1510 1511 tsadc: tsadc@fe710000 { 1512 compatible = "rockchip,rk3568-tsadc"; 1513 reg = <0x0 0xfe710000 0x0 0x100>; 1514 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1515 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 1516 assigned-clock-rates = <17000000>, <700000>; 1517 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 1518 clock-names = "tsadc", "apb_pclk"; 1519 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, 1520 <&cru SRST_TSADCPHY>; 1521 rockchip,grf = <&grf>; 1522 rockchip,hw-tshut-temp = <95000>; 1523 pinctrl-names = "default", "sleep"; 1524 pinctrl-0 = <&tsadc_shutorg>; 1525 pinctrl-1 = <&tsadc_pin>; 1526 #thermal-sensor-cells = <1>; 1527 status = "disabled"; 1528 }; 1529 1530 saradc: saradc@fe720000 { 1531 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 1532 reg = <0x0 0xfe720000 0x0 0x100>; 1533 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1534 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1535 clock-names = "saradc", "apb_pclk"; 1536 resets = <&cru SRST_P_SARADC>; 1537 reset-names = "saradc-apb"; 1538 #io-channel-cells = <1>; 1539 status = "disabled"; 1540 }; 1541 1542 pwm4: pwm@fe6e0000 { 1543 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1544 reg = <0x0 0xfe6e0000 0x0 0x10>; 1545 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1546 clock-names = "pwm", "pclk"; 1547 pinctrl-0 = <&pwm4_pins>; 1548 pinctrl-names = "default"; 1549 #pwm-cells = <3>; 1550 status = "disabled"; 1551 }; 1552 1553 pwm5: pwm@fe6e0010 { 1554 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1555 reg = <0x0 0xfe6e0010 0x0 0x10>; 1556 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1557 clock-names = "pwm", "pclk"; 1558 pinctrl-0 = <&pwm5_pins>; 1559 pinctrl-names = "default"; 1560 #pwm-cells = <3>; 1561 status = "disabled"; 1562 }; 1563 1564 pwm6: pwm@fe6e0020 { 1565 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1566 reg = <0x0 0xfe6e0020 0x0 0x10>; 1567 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1568 clock-names = "pwm", "pclk"; 1569 pinctrl-0 = <&pwm6_pins>; 1570 pinctrl-names = "default"; 1571 #pwm-cells = <3>; 1572 status = "disabled"; 1573 }; 1574 1575 pwm7: pwm@fe6e0030 { 1576 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1577 reg = <0x0 0xfe6e0030 0x0 0x10>; 1578 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1579 clock-names = "pwm", "pclk"; 1580 pinctrl-0 = <&pwm7_pins>; 1581 pinctrl-names = "default"; 1582 #pwm-cells = <3>; 1583 status = "disabled"; 1584 }; 1585 1586 pwm8: pwm@fe6f0000 { 1587 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1588 reg = <0x0 0xfe6f0000 0x0 0x10>; 1589 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1590 clock-names = "pwm", "pclk"; 1591 pinctrl-0 = <&pwm8m0_pins>; 1592 pinctrl-names = "default"; 1593 #pwm-cells = <3>; 1594 status = "disabled"; 1595 }; 1596 1597 pwm9: pwm@fe6f0010 { 1598 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1599 reg = <0x0 0xfe6f0010 0x0 0x10>; 1600 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1601 clock-names = "pwm", "pclk"; 1602 pinctrl-0 = <&pwm9m0_pins>; 1603 pinctrl-names = "default"; 1604 #pwm-cells = <3>; 1605 status = "disabled"; 1606 }; 1607 1608 pwm10: pwm@fe6f0020 { 1609 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1610 reg = <0x0 0xfe6f0020 0x0 0x10>; 1611 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1612 clock-names = "pwm", "pclk"; 1613 pinctrl-0 = <&pwm10m0_pins>; 1614 pinctrl-names = "default"; 1615 #pwm-cells = <3>; 1616 status = "disabled"; 1617 }; 1618 1619 pwm11: pwm@fe6f0030 { 1620 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1621 reg = <0x0 0xfe6f0030 0x0 0x10>; 1622 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1623 clock-names = "pwm", "pclk"; 1624 pinctrl-0 = <&pwm11m0_pins>; 1625 pinctrl-names = "default"; 1626 #pwm-cells = <3>; 1627 status = "disabled"; 1628 }; 1629 1630 pwm12: pwm@fe700000 { 1631 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1632 reg = <0x0 0xfe700000 0x0 0x10>; 1633 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1634 clock-names = "pwm", "pclk"; 1635 pinctrl-0 = <&pwm12m0_pins>; 1636 pinctrl-names = "default"; 1637 #pwm-cells = <3>; 1638 status = "disabled"; 1639 }; 1640 1641 pwm13: pwm@fe700010 { 1642 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1643 reg = <0x0 0xfe700010 0x0 0x10>; 1644 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1645 clock-names = "pwm", "pclk"; 1646 pinctrl-0 = <&pwm13m0_pins>; 1647 pinctrl-names = "default"; 1648 #pwm-cells = <3>; 1649 status = "disabled"; 1650 }; 1651 1652 pwm14: pwm@fe700020 { 1653 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1654 reg = <0x0 0xfe700020 0x0 0x10>; 1655 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1656 clock-names = "pwm", "pclk"; 1657 pinctrl-0 = <&pwm14m0_pins>; 1658 pinctrl-names = "default"; 1659 #pwm-cells = <3>; 1660 status = "disabled"; 1661 }; 1662 1663 pwm15: pwm@fe700030 { 1664 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1665 reg = <0x0 0xfe700030 0x0 0x10>; 1666 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1667 clock-names = "pwm", "pclk"; 1668 pinctrl-0 = <&pwm15m0_pins>; 1669 pinctrl-names = "default"; 1670 #pwm-cells = <3>; 1671 status = "disabled"; 1672 }; 1673 1674 combphy1: phy@fe830000 { 1675 compatible = "rockchip,rk3568-naneng-combphy"; 1676 reg = <0x0 0xfe830000 0x0 0x100>; 1677 clocks = <&pmucru CLK_PCIEPHY1_REF>, 1678 <&cru PCLK_PIPEPHY1>, 1679 <&cru PCLK_PIPE>; 1680 clock-names = "ref", "apb", "pipe"; 1681 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; 1682 assigned-clock-rates = <100000000>; 1683 resets = <&cru SRST_PIPEPHY1>; 1684 rockchip,pipe-grf = <&pipegrf>; 1685 rockchip,pipe-phy-grf = <&pipe_phy_grf1>; 1686 #phy-cells = <1>; 1687 status = "disabled"; 1688 }; 1689 1690 combphy2: phy@fe840000 { 1691 compatible = "rockchip,rk3568-naneng-combphy"; 1692 reg = <0x0 0xfe840000 0x0 0x100>; 1693 clocks = <&pmucru CLK_PCIEPHY2_REF>, 1694 <&cru PCLK_PIPEPHY2>, 1695 <&cru PCLK_PIPE>; 1696 clock-names = "ref", "apb", "pipe"; 1697 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; 1698 assigned-clock-rates = <100000000>; 1699 resets = <&cru SRST_PIPEPHY2>; 1700 rockchip,pipe-grf = <&pipegrf>; 1701 rockchip,pipe-phy-grf = <&pipe_phy_grf2>; 1702 #phy-cells = <1>; 1703 status = "disabled"; 1704 }; 1705 1706 csi_dphy: phy@fe870000 { 1707 compatible = "rockchip,rk3568-csi-dphy"; 1708 reg = <0x0 0xfe870000 0x0 0x10000>; 1709 clocks = <&cru PCLK_MIPICSIPHY>; 1710 clock-names = "pclk"; 1711 #phy-cells = <0>; 1712 resets = <&cru SRST_P_MIPICSIPHY>; 1713 reset-names = "apb"; 1714 rockchip,grf = <&grf>; 1715 status = "disabled"; 1716 }; 1717 1718 dsi_dphy0: mipi-dphy@fe850000 { 1719 compatible = "rockchip,rk3568-dsi-dphy"; 1720 reg = <0x0 0xfe850000 0x0 0x10000>; 1721 clock-names = "ref", "pclk"; 1722 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; 1723 #phy-cells = <0>; 1724 power-domains = <&power RK3568_PD_VO>; 1725 reset-names = "apb"; 1726 resets = <&cru SRST_P_MIPIDSIPHY0>; 1727 status = "disabled"; 1728 }; 1729 1730 dsi_dphy1: mipi-dphy@fe860000 { 1731 compatible = "rockchip,rk3568-dsi-dphy"; 1732 reg = <0x0 0xfe860000 0x0 0x10000>; 1733 clock-names = "ref", "pclk"; 1734 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; 1735 #phy-cells = <0>; 1736 power-domains = <&power RK3568_PD_VO>; 1737 reset-names = "apb"; 1738 resets = <&cru SRST_P_MIPIDSIPHY1>; 1739 status = "disabled"; 1740 }; 1741 1742 usb2phy0: usb2phy@fe8a0000 { 1743 compatible = "rockchip,rk3568-usb2phy"; 1744 reg = <0x0 0xfe8a0000 0x0 0x10000>; 1745 clocks = <&pmucru CLK_USBPHY0_REF>; 1746 clock-names = "phyclk"; 1747 clock-output-names = "clk_usbphy0_480m"; 1748 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1749 rockchip,usbgrf = <&usb2phy0_grf>; 1750 #clock-cells = <0>; 1751 status = "disabled"; 1752 1753 usb2phy0_host: host-port { 1754 #phy-cells = <0>; 1755 status = "disabled"; 1756 }; 1757 1758 usb2phy0_otg: otg-port { 1759 #phy-cells = <0>; 1760 status = "disabled"; 1761 }; 1762 }; 1763 1764 usb2phy1: usb2phy@fe8b0000 { 1765 compatible = "rockchip,rk3568-usb2phy"; 1766 reg = <0x0 0xfe8b0000 0x0 0x10000>; 1767 clocks = <&pmucru CLK_USBPHY1_REF>; 1768 clock-names = "phyclk"; 1769 clock-output-names = "clk_usbphy1_480m"; 1770 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1771 rockchip,usbgrf = <&usb2phy1_grf>; 1772 #clock-cells = <0>; 1773 status = "disabled"; 1774 1775 usb2phy1_host: host-port { 1776 #phy-cells = <0>; 1777 status = "disabled"; 1778 }; 1779 1780 usb2phy1_otg: otg-port { 1781 #phy-cells = <0>; 1782 status = "disabled"; 1783 }; 1784 }; 1785 1786 pinctrl: pinctrl { 1787 compatible = "rockchip,rk3568-pinctrl"; 1788 rockchip,grf = <&grf>; 1789 rockchip,pmu = <&pmugrf>; 1790 #address-cells = <2>; 1791 #size-cells = <2>; 1792 ranges; 1793 1794 gpio0: gpio@fdd60000 { 1795 compatible = "rockchip,gpio-bank"; 1796 reg = <0x0 0xfdd60000 0x0 0x100>; 1797 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1798 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 1799 gpio-controller; 1800 gpio-ranges = <&pinctrl 0 0 32>; 1801 #gpio-cells = <2>; 1802 interrupt-controller; 1803 #interrupt-cells = <2>; 1804 }; 1805 1806 gpio1: gpio@fe740000 { 1807 compatible = "rockchip,gpio-bank"; 1808 reg = <0x0 0xfe740000 0x0 0x100>; 1809 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1810 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1811 gpio-controller; 1812 gpio-ranges = <&pinctrl 0 32 32>; 1813 #gpio-cells = <2>; 1814 interrupt-controller; 1815 #interrupt-cells = <2>; 1816 }; 1817 1818 gpio2: gpio@fe750000 { 1819 compatible = "rockchip,gpio-bank"; 1820 reg = <0x0 0xfe750000 0x0 0x100>; 1821 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1822 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1823 gpio-controller; 1824 gpio-ranges = <&pinctrl 0 64 32>; 1825 #gpio-cells = <2>; 1826 interrupt-controller; 1827 #interrupt-cells = <2>; 1828 }; 1829 1830 gpio3: gpio@fe760000 { 1831 compatible = "rockchip,gpio-bank"; 1832 reg = <0x0 0xfe760000 0x0 0x100>; 1833 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1834 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1835 gpio-controller; 1836 gpio-ranges = <&pinctrl 0 96 32>; 1837 #gpio-cells = <2>; 1838 interrupt-controller; 1839 #interrupt-cells = <2>; 1840 }; 1841 1842 gpio4: gpio@fe770000 { 1843 compatible = "rockchip,gpio-bank"; 1844 reg = <0x0 0xfe770000 0x0 0x100>; 1845 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1846 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1847 gpio-controller; 1848 gpio-ranges = <&pinctrl 0 128 32>; 1849 #gpio-cells = <2>; 1850 interrupt-controller; 1851 #interrupt-cells = <2>; 1852 }; 1853 }; 1854}; 1855 1856#include "rk3568-pinctrl.dtsi" 1857