1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include "rk356x-base.dtsi" 7 8/ { 9 compatible = "rockchip,rk3568"; 10 11 cpu0_opp_table: opp-table-0 { 12 compatible = "operating-points-v2"; 13 opp-shared; 14 15 opp-408000000 { 16 opp-hz = /bits/ 64 <408000000>; 17 opp-microvolt = <850000 850000 1150000>; 18 clock-latency-ns = <40000>; 19 }; 20 21 opp-600000000 { 22 opp-hz = /bits/ 64 <600000000>; 23 opp-microvolt = <850000 850000 1150000>; 24 clock-latency-ns = <40000>; 25 }; 26 27 opp-816000000 { 28 opp-hz = /bits/ 64 <816000000>; 29 opp-microvolt = <850000 850000 1150000>; 30 clock-latency-ns = <40000>; 31 opp-suspend; 32 }; 33 34 opp-1104000000 { 35 opp-hz = /bits/ 64 <1104000000>; 36 opp-microvolt = <900000 900000 1150000>; 37 clock-latency-ns = <40000>; 38 }; 39 40 opp-1416000000 { 41 opp-hz = /bits/ 64 <1416000000>; 42 opp-microvolt = <1025000 1025000 1150000>; 43 clock-latency-ns = <40000>; 44 }; 45 46 opp-1608000000 { 47 opp-hz = /bits/ 64 <1608000000>; 48 opp-microvolt = <1100000 1100000 1150000>; 49 clock-latency-ns = <40000>; 50 }; 51 52 opp-1800000000 { 53 opp-hz = /bits/ 64 <1800000000>; 54 opp-microvolt = <1150000 1150000 1150000>; 55 clock-latency-ns = <40000>; 56 }; 57 58 opp-1992000000 { 59 opp-hz = /bits/ 64 <1992000000>; 60 opp-microvolt = <1150000 1150000 1150000>; 61 clock-latency-ns = <40000>; 62 }; 63 }; 64 65 gpu_opp_table: opp-table-1 { 66 compatible = "operating-points-v2"; 67 68 opp-200000000 { 69 opp-hz = /bits/ 64 <200000000>; 70 opp-microvolt = <850000 850000 1000000>; 71 }; 72 73 opp-300000000 { 74 opp-hz = /bits/ 64 <300000000>; 75 opp-microvolt = <850000 850000 1000000>; 76 }; 77 78 opp-400000000 { 79 opp-hz = /bits/ 64 <400000000>; 80 opp-microvolt = <850000 850000 1000000>; 81 }; 82 83 opp-600000000 { 84 opp-hz = /bits/ 64 <600000000>; 85 opp-microvolt = <900000 900000 1000000>; 86 }; 87 88 opp-700000000 { 89 opp-hz = /bits/ 64 <700000000>; 90 opp-microvolt = <950000 950000 1000000>; 91 }; 92 93 opp-800000000 { 94 opp-hz = /bits/ 64 <800000000>; 95 opp-microvolt = <1000000 1000000 1000000>; 96 }; 97 }; 98 99 sata0: sata@fc000000 { 100 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 101 reg = <0 0xfc000000 0 0x1000>; 102 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, 103 <&cru CLK_SATA0_RXOOB>; 104 clock-names = "sata", "pmalive", "rxoob"; 105 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 106 phys = <&combphy0 PHY_TYPE_SATA>; 107 phy-names = "sata-phy"; 108 ports-implemented = <0x1>; 109 power-domains = <&power RK3568_PD_PIPE>; 110 status = "disabled"; 111 }; 112 113 pipe_phy_grf0: syscon@fdc70000 { 114 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 115 reg = <0x0 0xfdc70000 0x0 0x1000>; 116 }; 117 118 qos_pcie3x1: qos@fe190080 { 119 compatible = "rockchip,rk3568-qos", "syscon"; 120 reg = <0x0 0xfe190080 0x0 0x20>; 121 }; 122 123 qos_pcie3x2: qos@fe190100 { 124 compatible = "rockchip,rk3568-qos", "syscon"; 125 reg = <0x0 0xfe190100 0x0 0x20>; 126 }; 127 128 qos_sata0: qos@fe190200 { 129 compatible = "rockchip,rk3568-qos", "syscon"; 130 reg = <0x0 0xfe190200 0x0 0x20>; 131 }; 132 133 pcie30_phy_grf: syscon@fdcb8000 { 134 compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; 135 reg = <0x0 0xfdcb8000 0x0 0x10000>; 136 }; 137 138 pcie30phy: phy@fe8c0000 { 139 compatible = "rockchip,rk3568-pcie3-phy"; 140 reg = <0x0 0xfe8c0000 0x0 0x20000>; 141 #phy-cells = <0>; 142 clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, 143 <&cru PCLK_PCIE30PHY>; 144 clock-names = "refclk_m", "refclk_n", "pclk"; 145 resets = <&cru SRST_PCIE30PHY>; 146 reset-names = "phy"; 147 rockchip,phy-grf = <&pcie30_phy_grf>; 148 status = "disabled"; 149 }; 150 151 pcie3x1: pcie@fe270000 { 152 compatible = "rockchip,rk3568-pcie"; 153 #address-cells = <3>; 154 #size-cells = <2>; 155 bus-range = <0x0 0xf>; 156 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, 157 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, 158 <&cru CLK_PCIE30X1_AUX_NDFT>; 159 clock-names = "aclk_mst", "aclk_slv", 160 "aclk_dbi", "pclk", "aux"; 161 device_type = "pci"; 162 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 167 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 168 #interrupt-cells = <1>; 169 interrupt-map-mask = <0 0 0 7>; 170 interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, 171 <0 0 0 2 &pcie3x1_intc 1>, 172 <0 0 0 3 &pcie3x1_intc 2>, 173 <0 0 0 4 &pcie3x1_intc 3>; 174 linux,pci-domain = <1>; 175 num-ib-windows = <6>; 176 num-ob-windows = <2>; 177 max-link-speed = <3>; 178 msi-map = <0x0 &gic 0x1000 0x1000>; 179 num-lanes = <1>; 180 phys = <&pcie30phy>; 181 phy-names = "pcie-phy"; 182 power-domains = <&power RK3568_PD_PIPE>; 183 reg = <0x3 0xc0400000 0x0 0x00400000>, 184 <0x0 0xfe270000 0x0 0x00010000>, 185 <0x0 0xf2000000 0x0 0x00100000>; 186 ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, 187 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>, 188 <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>; 189 reg-names = "dbi", "apb", "config"; 190 resets = <&cru SRST_PCIE30X1_POWERUP>; 191 reset-names = "pipe"; 192 /* bifurcation; lane1 when using 1+1 */ 193 status = "disabled"; 194 195 pcie3x1_intc: legacy-interrupt-controller { 196 interrupt-controller; 197 #address-cells = <0>; 198 #interrupt-cells = <1>; 199 interrupt-parent = <&gic>; 200 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 201 }; 202 }; 203 204 pcie3x2: pcie@fe280000 { 205 compatible = "rockchip,rk3568-pcie"; 206 #address-cells = <3>; 207 #size-cells = <2>; 208 bus-range = <0x0 0xf>; 209 clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, 210 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, 211 <&cru CLK_PCIE30X2_AUX_NDFT>; 212 clock-names = "aclk_mst", "aclk_slv", 213 "aclk_dbi", "pclk", "aux"; 214 device_type = "pci"; 215 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 220 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 221 #interrupt-cells = <1>; 222 interrupt-map-mask = <0 0 0 7>; 223 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, 224 <0 0 0 2 &pcie3x2_intc 1>, 225 <0 0 0 3 &pcie3x2_intc 2>, 226 <0 0 0 4 &pcie3x2_intc 3>; 227 linux,pci-domain = <2>; 228 num-ib-windows = <6>; 229 num-ob-windows = <2>; 230 max-link-speed = <3>; 231 msi-map = <0x0 &gic 0x2000 0x1000>; 232 num-lanes = <2>; 233 phys = <&pcie30phy>; 234 phy-names = "pcie-phy"; 235 power-domains = <&power RK3568_PD_PIPE>; 236 reg = <0x3 0xc0800000 0x0 0x00400000>, 237 <0x0 0xfe280000 0x0 0x00010000>, 238 <0x0 0xf0000000 0x0 0x00100000>; 239 ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, 240 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>, 241 <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>; 242 reg-names = "dbi", "apb", "config"; 243 resets = <&cru SRST_PCIE30X2_POWERUP>; 244 reset-names = "pipe"; 245 /* bifurcation; lane0 when using 1+1 */ 246 status = "disabled"; 247 248 pcie3x2_intc: legacy-interrupt-controller { 249 interrupt-controller; 250 #address-cells = <0>; 251 #interrupt-cells = <1>; 252 interrupt-parent = <&gic>; 253 interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>; 254 }; 255 }; 256 257 gmac0: ethernet@fe2a0000 { 258 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 259 reg = <0x0 0xfe2a0000 0x0 0x10000>; 260 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 262 interrupt-names = "macirq", "eth_wake_irq"; 263 clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, 264 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, 265 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, 266 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>; 267 clock-names = "stmmaceth", "mac_clk_rx", 268 "mac_clk_tx", "clk_mac_refout", 269 "aclk_mac", "pclk_mac", 270 "clk_mac_speed", "ptp_ref"; 271 resets = <&cru SRST_A_GMAC0>; 272 reset-names = "stmmaceth"; 273 rockchip,grf = <&grf>; 274 snps,axi-config = <&gmac0_stmmac_axi_setup>; 275 snps,mixed-burst; 276 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 277 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 278 snps,tso; 279 status = "disabled"; 280 281 mdio0: mdio { 282 compatible = "snps,dwmac-mdio"; 283 #address-cells = <0x1>; 284 #size-cells = <0x0>; 285 }; 286 287 gmac0_stmmac_axi_setup: stmmac-axi-config { 288 snps,blen = <0 0 0 0 16 8 4>; 289 snps,rd_osr_lmt = <8>; 290 snps,wr_osr_lmt = <4>; 291 }; 292 293 gmac0_mtl_rx_setup: rx-queues-config { 294 snps,rx-queues-to-use = <1>; 295 queue0 {}; 296 }; 297 298 gmac0_mtl_tx_setup: tx-queues-config { 299 snps,tx-queues-to-use = <1>; 300 queue0 {}; 301 }; 302 }; 303 304 can0: can@fe570000 { 305 compatible = "rockchip,rk3568v2-canfd"; 306 reg = <0x0 0xfe570000 0x0 0x1000>; 307 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; 309 clock-names = "baud", "pclk"; 310 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; 311 reset-names = "core", "apb"; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&can0m0_pins>; 314 status = "disabled"; 315 }; 316 317 can1: can@fe580000 { 318 compatible = "rockchip,rk3568v2-canfd"; 319 reg = <0x0 0xfe580000 0x0 0x1000>; 320 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; 322 clock-names = "baud", "pclk"; 323 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; 324 reset-names = "core", "apb"; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&can1m0_pins>; 327 status = "disabled"; 328 }; 329 330 can2: can@fe590000 { 331 compatible = "rockchip,rk3568v2-canfd"; 332 reg = <0x0 0xfe590000 0x0 0x1000>; 333 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; 335 clock-names = "baud", "pclk"; 336 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; 337 reset-names = "core", "apb"; 338 pinctrl-names = "default"; 339 pinctrl-0 = <&can2m0_pins>; 340 status = "disabled"; 341 }; 342 343 combphy0: phy@fe820000 { 344 compatible = "rockchip,rk3568-naneng-combphy"; 345 reg = <0x0 0xfe820000 0x0 0x100>; 346 clocks = <&pmucru CLK_PCIEPHY0_REF>, 347 <&cru PCLK_PIPEPHY0>, 348 <&cru PCLK_PIPE>; 349 clock-names = "ref", "apb", "pipe"; 350 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; 351 assigned-clock-rates = <100000000>; 352 resets = <&cru SRST_PIPEPHY0>; 353 rockchip,pipe-grf = <&pipegrf>; 354 rockchip,pipe-phy-grf = <&pipe_phy_grf0>; 355 #phy-cells = <1>; 356 status = "disabled"; 357 }; 358}; 359 360&cpu0 { 361 operating-points-v2 = <&cpu0_opp_table>; 362}; 363 364&cpu1 { 365 operating-points-v2 = <&cpu0_opp_table>; 366}; 367 368&cpu2 { 369 operating-points-v2 = <&cpu0_opp_table>; 370}; 371 372&cpu3 { 373 operating-points-v2 = <&cpu0_opp_table>; 374}; 375 376&gpu { 377 operating-points-v2 = <&gpu_opp_table>; 378}; 379 380&pipegrf { 381 compatible = "rockchip,rk3568-pipe-grf", "syscon"; 382}; 383 384&power { 385 power-domain@RK3568_PD_PIPE { 386 reg = <RK3568_PD_PIPE>; 387 clocks = <&cru PCLK_PIPE>; 388 pm_qos = <&qos_pcie2x1>, 389 <&qos_pcie3x1>, 390 <&qos_pcie3x2>, 391 <&qos_sata0>, 392 <&qos_sata1>, 393 <&qos_sata2>, 394 <&qos_usb3_0>, 395 <&qos_usb3_1>; 396 #power-domain-cells = <0>; 397 }; 398}; 399 400&rng { 401 status = "okay"; 402}; 403 404&usb_host0_xhci { 405 phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; 406 phy-names = "usb2-phy", "usb3-phy"; 407}; 408 409&vop { 410 compatible = "rockchip,rk3568-vop"; 411}; 412