1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Device tree for the WolfVision PF5 mainboard. 4 * 5 * Copyright (C) 2024 WolfVision GmbH. 6 */ 7 8/dts-v1/; 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/regulator/ti,tps62864.h> 12#include <dt-bindings/soc/rockchip,vop2.h> 13#include "rk3568.dtsi" 14 15/ { 16 model = "WolfVision PF5"; 17 compatible = "wolfvision,rk3568-pf5", "rockchip,rk3568"; 18 19 aliases { 20 ethernet0 = &gmac0; 21 mmc0 = &sdhci; 22 rtc0 = &pcf85623; 23 rtc1 = &rk809; 24 }; 25 26 chosen: chosen { 27 stdout-path = "serial2:115200n8"; 28 }; 29 30 hdmi_tx: hdmi-tx-connector { 31 compatible = "hdmi-connector"; 32 hdmi-pwr-supply = <&hdmi_tx_5v>; 33 type = "a"; 34 35 port { 36 hdmi_tx_in: endpoint { 37 remote-endpoint = <&hdmi_tx_out>; 38 }; 39 }; 40 }; 41 42 hdmi_tx_5v: hdmi-tx-5v-regulator { 43 compatible = "regulator-fixed"; 44 enable-active-high; 45 gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; 46 pinctrl-names = "default"; 47 pinctrl-0 = <&hdmi_tx_5v_en>; 48 regulator-name = "hdmi_tx_5v"; 49 regulator-min-microvolt = <5000000>; 50 regulator-max-microvolt = <5000000>; 51 vin-supply = <&vcc5v_in>; 52 }; 53 54 pdm_codec: pdm-codec { 55 compatible = "dmic-codec"; 56 num-channels = <1>; 57 #sound-dai-cells = <0>; 58 }; 59 60 pdm_sound: pdm-sound { 61 compatible = "simple-audio-card"; 62 simple-audio-card,name = "microphone"; 63 64 simple-audio-card,cpu { 65 sound-dai = <&pdm>; 66 }; 67 68 simple-audio-card,codec { 69 sound-dai = <&pdm_codec>; 70 }; 71 }; 72 73 vcc12v_cam: vcc12v-cam-regulator { 74 compatible = "regulator-fixed"; 75 enable-active-high; 76 gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>; 77 pinctrl-names = "default"; 78 pinctrl-0 = <&vcc12v_cam_en>; 79 regulator-name = "12v_cam"; 80 regulator-min-microvolt = <12000000>; 81 regulator-max-microvolt = <12000000>; 82 vin-supply = <&vcc12v_in>; 83 }; 84 85 vcc12v_in: vcc12v-in-regulator { 86 compatible = "regulator-fixed"; 87 regulator-name = "12v_in"; 88 regulator-always-on; 89 regulator-boot-on; 90 regulator-min-microvolt = <12000000>; 91 regulator-max-microvolt = <12000000>; 92 }; 93 94 vcc3v8_cam: vcc3v8-cam-regulator { 95 compatible = "regulator-fixed"; 96 enable-active-high; 97 gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; 98 pinctrl-names = "default"; 99 pinctrl-0 = <&vcc3v8_cam_en>; 100 regulator-name = "3v8_cam"; 101 regulator-min-microvolt = <3800000>; 102 regulator-max-microvolt = <3800000>; 103 vin-supply = <&vcc5v_in>; 104 }; 105 106 vcc3v3_sys: vcc3v3-sys-regulator { 107 compatible = "regulator-fixed"; 108 regulator-name = "3v3_sys"; 109 regulator-always-on; 110 regulator-boot-on; 111 regulator-min-microvolt = <3300000>; 112 regulator-max-microvolt = <3300000>; 113 vin-supply = <&vcc5v_in>; 114 }; 115 116 vcc5v_in: vcc5v-in-regulator { 117 compatible = "regulator-fixed"; 118 regulator-name = "5v_in"; 119 regulator-always-on; 120 regulator-boot-on; 121 regulator-min-microvolt = <5000000>; 122 regulator-max-microvolt = <5000000>; 123 vin-supply = <&vcc12v_in>; 124 }; 125}; 126 127&combphy0 { 128 status = "okay"; 129}; 130 131&cpu0 { 132 cpu-supply = <&vcc0v9_cpu>; 133}; 134 135&cpu1 { 136 cpu-supply = <&vcc0v9_cpu>; 137}; 138 139&cpu2 { 140 cpu-supply = <&vcc0v9_cpu>; 141}; 142 143&cpu3 { 144 cpu-supply = <&vcc0v9_cpu>; 145}; 146 147&gpu { 148 mali-supply = <&vcc0v9_gpu>; 149 status = "okay"; 150}; 151 152&hdmi { 153 avdd-0v9-supply = <&vcc0v9a_image>; 154 avdd-1v8-supply = <&vcc1v8a_image>; 155 status = "okay"; 156}; 157 158&hdmi_in { 159 hdmi_in_vp0: endpoint { 160 remote-endpoint = <&vp0_out_hdmi>; 161 }; 162}; 163 164&hdmi_out { 165 hdmi_tx_out: endpoint { 166 remote-endpoint = <&hdmi_tx_in>; 167 }; 168}; 169 170&i2c0 { 171 status = "okay"; 172 173 rk809: pmic@20 { 174 compatible = "rockchip,rk809"; 175 reg = <0x20>; 176 interrupt-parent = <&gpio0>; 177 interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; 178 #clock-cells = <0>; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pmic_int_l>; 181 rockchip,system-power-controller; 182 vcc1-supply = <&vcc5v_in>; 183 vcc2-supply = <&vcc5v_in>; 184 vcc3-supply = <&vcc5v_in>; 185 vcc4-supply = <&vcc5v_in>; 186 vcc5-supply = <&vcc3v3_sys>; 187 vcc6-supply = <&vcc5v_in>; 188 vcc7-supply = <&vcc3v3_sys>; 189 vcc8-supply = <&vcc3v3_sys>; 190 vcc9-supply = <&vcc3v3_sys>; 191 wakeup-source; 192 193 regulators { 194 vcc0v9_logic: DCDC_REG1 { 195 regulator-name = "0v9_logic"; 196 regulator-always-on; 197 regulator-boot-on; 198 regulator-initial-mode = <0x2>; 199 regulator-min-microvolt = <500000>; 200 regulator-max-microvolt = <1350000>; 201 regulator-ramp-delay = <6001>; 202 203 regulator-state-mem { 204 regulator-off-in-suspend; 205 }; 206 }; 207 208 vcc0v9_gpu: DCDC_REG2 { 209 regulator-name = "0v9_gpu"; 210 regulator-always-on; 211 regulator-initial-mode = <0x2>; 212 regulator-min-microvolt = <500000>; 213 regulator-max-microvolt = <1350000>; 214 regulator-ramp-delay = <6001>; 215 216 regulator-state-mem { 217 regulator-off-in-suspend; 218 }; 219 }; 220 221 vcc1v1_ddr4: DCDC_REG3 { 222 regulator-name = "1v1_ddr4"; 223 regulator-always-on; 224 regulator-boot-on; 225 regulator-initial-mode = <0x2>; 226 227 regulator-state-mem { 228 regulator-on-in-suspend; 229 }; 230 }; 231 232 vcc0v9_npu: DCDC_REG4 { 233 regulator-name = "0v9_npu"; 234 regulator-always-on; 235 regulator-initial-mode = <0x2>; 236 regulator-min-microvolt = <900000>; 237 regulator-max-microvolt = <1350000>; 238 regulator-ramp-delay = <6001>; 239 240 regulator-state-mem { 241 regulator-off-in-suspend; 242 }; 243 }; 244 245 vcc1v8: DCDC_REG5 { 246 regulator-name = "1v8"; 247 regulator-always-on; 248 regulator-boot-on; 249 regulator-min-microvolt = <1800000>; 250 regulator-max-microvolt = <1800000>; 251 252 regulator-state-mem { 253 regulator-off-in-suspend; 254 }; 255 }; 256 257 vcc0v9a_image: LDO_REG1 { 258 regulator-name = "0v9a_image"; 259 regulator-min-microvolt = <900000>; 260 regulator-max-microvolt = <900000>; 261 262 regulator-state-mem { 263 regulator-off-in-suspend; 264 }; 265 }; 266 267 vcc0v9a: LDO_REG2 { 268 regulator-name = "0v9a"; 269 regulator-always-on; 270 regulator-boot-on; 271 regulator-min-microvolt = <900000>; 272 regulator-max-microvolt = <900000>; 273 274 regulator-state-mem { 275 regulator-off-in-suspend; 276 }; 277 }; 278 279 vcc0v9a_pmu: LDO_REG3 { 280 regulator-name = "0v9a_pmu"; 281 regulator-always-on; 282 regulator-boot-on; 283 regulator-min-microvolt = <900000>; 284 regulator-max-microvolt = <900000>; 285 286 regulator-state-mem { 287 regulator-on-in-suspend; 288 regulator-suspend-microvolt = <900000>; 289 }; 290 }; 291 292 vcc3v3_acodec: LDO_REG4 { 293 regulator-name = "3v3_acodec"; 294 regulator-always-on; 295 regulator-min-microvolt = <3300000>; 296 regulator-max-microvolt = <3300000>; 297 298 regulator-state-mem { 299 regulator-off-in-suspend; 300 }; 301 }; 302 303 vcc3v3_sd: LDO_REG5 { 304 regulator-name = "3v3_sd"; 305 regulator-always-on; 306 regulator-boot-on; 307 regulator-min-microvolt = <3300000>; 308 regulator-max-microvolt = <3300000>; 309 310 regulator-state-mem { 311 regulator-off-in-suspend; 312 }; 313 }; 314 315 vcc3v3_pmu: LDO_REG6 { 316 regulator-name = "3v3_pmu"; 317 regulator-always-on; 318 regulator-boot-on; 319 regulator-min-microvolt = <3300000>; 320 regulator-max-microvolt = <3300000>; 321 322 regulator-state-mem { 323 regulator-on-in-suspend; 324 regulator-suspend-microvolt = <3300000>; 325 }; 326 }; 327 328 vcc1v8a: LDO_REG7 { 329 regulator-name = "1v8a"; 330 regulator-always-on; 331 regulator-boot-on; 332 regulator-min-microvolt = <1800000>; 333 regulator-max-microvolt = <1800000>; 334 335 regulator-state-mem { 336 regulator-off-in-suspend; 337 }; 338 }; 339 340 vcc1v8a_pmu: LDO_REG8 { 341 regulator-name = "1v8a_pmu"; 342 regulator-always-on; 343 regulator-boot-on; 344 regulator-min-microvolt = <1800000>; 345 regulator-max-microvolt = <1800000>; 346 347 regulator-state-mem { 348 regulator-on-in-suspend; 349 regulator-suspend-microvolt = <1800000>; 350 }; 351 }; 352 353 vcc1v8a_image: LDO_REG9 { 354 regulator-name = "1v8a_image"; 355 regulator-min-microvolt = <1800000>; 356 regulator-max-microvolt = <1800000>; 357 358 regulator-state-mem { 359 regulator-off-in-suspend; 360 }; 361 }; 362 363 vcc3v3_sw: SWITCH_REG1 { 364 regulator-name = "3v3_sw"; 365 regulator-always-on; 366 regulator-boot-on; 367 regulator-min-microvolt = <3300000>; 368 regulator-max-microvolt = <3300000>; 369 370 regulator-state-mem { 371 regulator-off-in-suspend; 372 }; 373 }; 374 }; 375 }; 376 377 regulator@42 { 378 compatible = "ti,tps62869"; 379 reg = <0x42>; 380 381 regulators { 382 vcc0v9_cpu: SW { 383 regulator-name = "0v9_cpu"; 384 regulator-always-on; 385 regulator-boot-on; 386 regulator-initial-mode = <TPS62864_MODE_FPWM>; 387 regulator-min-microvolt = <900000>; 388 regulator-max-microvolt = <1150000>; 389 vin-supply = <&vcc5v_in>; 390 391 regulator-state-mem { 392 regulator-off-in-suspend; 393 }; 394 }; 395 }; 396 }; 397 398 pcf85623: rtc@51 { 399 compatible = "nxp,pcf85263"; 400 reg = <0x51>; 401 pinctrl-names = "default"; 402 pinctrl-0 = <&clk32k_in>; 403 quartz-load-femtofarads = <12500>; 404 }; 405}; 406 407&i2c3 { 408 pinctrl-names = "default"; 409 pinctrl-0 = <&i2c3m0_xfer>; 410}; 411 412&i2c4 { 413 pinctrl-names = "default"; 414 pinctrl-0 = <&i2c4m1_xfer>; 415}; 416 417&pdm { 418 pinctrl-0 = <&pdmm0_clk 419 &pdmm0_sdi0>; 420 status = "okay"; 421}; 422 423&pinctrl { 424 cam { 425 vcc12v_cam_en: vcc12v-cam-en-pinctrl { 426 rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; 427 }; 428 429 vcc3v8_cam_en: vcc3v8-cam-en-pinctrl { 430 rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 431 }; 432 }; 433 434 hdmitx { 435 hdmi_tx_5v_en: hdmi-tx-5v-en-pinctrl { 436 rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 437 }; 438 }; 439 440 pmic { 441 pmic_int_l: pmic-int-l-pinctrl { 442 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 443 }; 444 }; 445}; 446 447&pmu_io_domains { 448 pmuio1-supply = <&vcc3v3_pmu>; 449 pmuio2-supply = <&vcc3v3_pmu>; 450 vccio1-supply = <&vcc3v3_acodec>; 451 vccio2-supply = <&vcc1v8>; 452 vccio3-supply = <&vcc3v3_sd>; 453 vccio4-supply = <&vcc1v8>; 454 vccio5-supply = <&vcc1v8>; 455 vccio6-supply = <&vcc3v3_sw>; 456 vccio7-supply = <&vcc3v3_sw>; 457 status = "okay"; 458}; 459 460&saradc { 461 vref-supply = <&vcc1v8a>; 462 status = "okay"; 463}; 464 465&sdhci { 466 bus-width = <8>; 467 max-frequency = <200000000>; 468 non-removable; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; 471 vmmc-supply = <&vcc3v3_sw>; 472 vqmmc-supply = <&vcc1v8>; 473 status = "okay"; 474}; 475 476&tsadc { 477 rockchip,hw-tshut-mode = <1>; 478 rockchip,hw-tshut-polarity = <0>; 479 status = "okay"; 480}; 481 482&uart2 { 483 status = "okay"; 484}; 485 486&usb_host0_xhci { 487 dr_mode = "peripheral"; 488 /* The following quirks are required since the bInterval is 1 and we 489 * handle steady ISOC streaming. See Usecase 3 in commit 729dcffd1ed3 490 * ("usb: dwc3: gadget: Add support for disabling U1 and U2 entries"). 491 */ 492 snps,dis-u1-entry-quirk; 493 snps,dis-u2-entry-quirk; 494 /* 495 * Without this quirk the available fifosize seems to be miscalculated 496 * in cases where many endpoints are used. In one particular situation 497 * 8 IN EPs and 3 OUT EPs where selected and lead to stalled transfers 498 * without the resize quirk. 499 */ 500 tx-fifo-resize; 501 502 status = "okay"; 503}; 504 505&usb2phy0 { 506 status = "okay"; 507}; 508 509&usb2phy0_otg { 510 status = "okay"; 511}; 512 513&vop { 514 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP2>; 515 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; 516 status = "okay"; 517}; 518 519&vop_mmu { 520 status = "okay"; 521}; 522 523&vp0 { 524 vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { 525 reg = <ROCKCHIP_VOP2_EP_HDMI0>; 526 remote-endpoint = <&hdmi_in_vp0>; 527 }; 528}; 529