1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3/dts-v1/; 4#include "rk3568-radxa-cm3i.dtsi" 5 6/ { 7 model = "Radxa E25 Carrier Board"; 8 compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568"; 9 10 aliases { 11 mmc1 = &sdmmc0; 12 }; 13 14 pwm-leds { 15 compatible = "pwm-leds-multicolor"; 16 17 multi-led { 18 color = <LED_COLOR_ID_RGB>; 19 function = LED_FUNCTION_STATUS; 20 max-brightness = <255>; 21 22 led-red { 23 color = <LED_COLOR_ID_RED>; 24 pwms = <&pwm1 0 1000000 0>; 25 }; 26 27 led-green { 28 color = <LED_COLOR_ID_GREEN>; 29 pwms = <&pwm2 0 1000000 0>; 30 }; 31 32 led-blue { 33 color = <LED_COLOR_ID_BLUE>; 34 pwms = <&pwm12 0 1000000 0>; 35 }; 36 }; 37 }; 38 39 vbus_typec: regulator-vbus-typec { 40 compatible = "regulator-fixed"; 41 enable-active-high; 42 gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&vbus_typec_en>; 45 regulator-name = "vbus_typec"; 46 regulator-min-microvolt = <5000000>; 47 regulator-max-microvolt = <5000000>; 48 vin-supply = <&vcc5v0_sys>; 49 }; 50 51 /* actually fed by vcc5v0_sys, dependent 52 * on pi6c clock generator 53 */ 54 vcc3v3_minipcie: regulator-vcc3v3-minipcie { 55 compatible = "regulator-fixed"; 56 enable-active-high; 57 gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&minipcie_enable_h>; 60 regulator-name = "vcc3v3_minipcie"; 61 regulator-min-microvolt = <3300000>; 62 regulator-max-microvolt = <3300000>; 63 vin-supply = <&vcc3v3_pi6c_05>; 64 }; 65 66 vcc3v3_ngff: regulator-vcc3v3-ngff { 67 compatible = "regulator-fixed"; 68 enable-active-high; 69 gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; 70 pinctrl-names = "default"; 71 pinctrl-0 = <&ngffpcie_enable_h>; 72 regulator-name = "vcc3v3_ngff"; 73 regulator-min-microvolt = <3300000>; 74 regulator-max-microvolt = <3300000>; 75 vin-supply = <&vcc5v0_sys>; 76 }; 77 78 vcc3v3_pcie30x1: regulator-vcc3v3-pcie30x1 { 79 compatible = "regulator-fixed"; 80 enable-active-high; 81 gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pcie30x1_enable_h>; 84 regulator-name = "vcc3v3_pcie30x1"; 85 regulator-min-microvolt = <3300000>; 86 regulator-max-microvolt = <3300000>; 87 vin-supply = <&vcc5v0_sys>; 88 }; 89 90 vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { 91 compatible = "regulator-fixed"; 92 enable-active-high; 93 gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; 94 pinctrl-names = "default"; 95 pinctrl-0 = <&pcie_enable_h>; 96 regulator-name = "vcc3v3_pcie"; 97 regulator-min-microvolt = <3300000>; 98 regulator-max-microvolt = <3300000>; 99 vin-supply = <&vcc5v0_sys>; 100 }; 101}; 102 103&combphy1 { 104 phy-supply = <&vcc3v3_pcie30x1>; 105}; 106 107&display_subsystem { 108 status = "disabled"; 109}; 110 111&pcie2x1 { 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pcie20_reset_h>; 114 reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 115 vpcie3v3-supply = <&vcc3v3_pi6c_05>; 116 status = "okay"; 117}; 118 119&pcie30phy { 120 data-lanes = <1 2>; 121 status = "okay"; 122}; 123 124&pcie3x1 { 125 num-lanes = <1>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pcie30x1_reset_h>; 128 reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; 129 vpcie3v3-supply = <&vcc3v3_minipcie>; 130 status = "okay"; 131}; 132 133&pcie3x2 { 134 num-lanes = <1>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pcie30x2_reset_h>; 137 reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; 138 vpcie3v3-supply = <&vcc3v3_pi6c_05>; 139 status = "okay"; 140}; 141 142&pinctrl { 143 pcie { 144 pcie20_reset_h: pcie20-reset-h { 145 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 146 }; 147 148 pcie30x1_enable_h: pcie30x1-enable-h { 149 rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 150 }; 151 152 pcie30x1_reset_h: pcie30x1-reset-h { 153 rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 154 }; 155 156 pcie30x2_reset_h: pcie30x2-reset-h { 157 rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; 158 }; 159 160 pcie_enable_h: pcie-enable-h { 161 rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; 162 }; 163 }; 164 165 usb { 166 minipcie_enable_h: minipcie-enable-h { 167 rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; 168 }; 169 170 ngffpcie_enable_h: ngffpcie-enable-h { 171 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; 172 }; 173 174 vbus_typec_en: vbus_typec_en { 175 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 176 }; 177 }; 178}; 179 180&pwm1 { 181 status = "okay"; 182}; 183 184&pwm2 { 185 status = "okay"; 186}; 187 188&pwm12 { 189 pinctrl-names = "default"; 190 pinctrl-0 = <&pwm12m1_pins>; 191 status = "okay"; 192}; 193 194&sata1 { 195 status = "okay"; 196}; 197 198&sdmmc0 { 199 bus-width = <4>; 200 cap-sd-highspeed; 201 cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 202 /* Also used in pcie30x1_clkreqnm0 */ 203 disable-wp; 204 pinctrl-names = "default"; 205 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; 206 sd-uhs-sdr104; 207 vmmc-supply = <&vcc3v3_sd>; 208 vqmmc-supply = <&vccio_sd>; 209 status = "okay"; 210}; 211 212&usb_host0_ehci { 213 status = "okay"; 214}; 215 216&usb_host0_ohci { 217 status = "okay"; 218}; 219 220&usb_host0_xhci { 221 status = "okay"; 222}; 223 224&usb_host1_ehci { 225 status = "okay"; 226}; 227 228&usb_host1_ohci { 229 status = "okay"; 230}; 231 232&usb2phy0_otg { 233 phy-supply = <&vbus_typec>; 234 status = "okay"; 235}; 236 237&usb2phy1_host { 238 phy-supply = <&vcc3v3_minipcie>; 239 status = "okay"; 240}; 241 242&usb2phy1_otg { 243 phy-supply = <&vcc3v3_ngff>; 244 status = "okay"; 245}; 246