1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 3#include "rk3568-fastrhino-r66s.dtsi" 4 5/ { 6 model = "Lunzn FastRhino R68S"; 7 compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568"; 8 9 aliases { 10 ethernet0 = &gmac0; 11 ethernet1 = &gmac1; 12 mmc0 = &sdhci; 13 }; 14 15 adc-keys { 16 compatible = "adc-keys"; 17 io-channels = <&saradc 0>; 18 io-channel-names = "buttons"; 19 keyup-threshold-microvolt = <1800000>; 20 21 button-recovery { 22 label = "Recovery"; 23 linux,code = <KEY_VENDOR>; 24 press-threshold-microvolt = <1750>; 25 }; 26 }; 27}; 28 29&gmac0 { 30 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 31 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 32 assigned-clock-rates = <0>, <125000000>; 33 clock_in_out = "output"; 34 phy-handle = <&rgmii_phy0>; 35 phy-mode = "rgmii-id"; 36 pinctrl-names = "default"; 37 pinctrl-0 = <&gmac0_miim 38 &gmac0_tx_bus2 39 &gmac0_rx_bus2 40 &gmac0_rgmii_clk 41 &gmac0_rgmii_bus>; 42 status = "okay"; 43}; 44 45&gmac1 { 46 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 47 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; 48 assigned-clock-rates = <0>, <125000000>; 49 clock_in_out = "output"; 50 phy-handle = <&rgmii_phy1>; 51 phy-mode = "rgmii-id"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&gmac1m1_miim 54 &gmac1m1_tx_bus2 55 &gmac1m1_rx_bus2 56 &gmac1m1_rgmii_clk 57 &gmac1m1_rgmii_bus>; 58 status = "okay"; 59}; 60 61&mdio0 { 62 rgmii_phy0: ethernet-phy@1 { 63 compatible = "ethernet-phy-ieee802.3-c22"; 64 reg = <0x1>; 65 pinctrl-0 = <ð_phy0_reset_pin>; 66 pinctrl-names = "default"; 67 reset-assert-us = <20000>; 68 reset-deassert-us = <100000>; 69 reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; 70 }; 71}; 72 73&mdio1 { 74 rgmii_phy1: ethernet-phy@1 { 75 compatible = "ethernet-phy-ieee802.3-c22"; 76 reg = <0x1>; 77 pinctrl-0 = <ð_phy1_reset_pin>; 78 pinctrl-names = "default"; 79 reset-assert-us = <20000>; 80 reset-deassert-us = <100000>; 81 reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; 82 }; 83}; 84 85&pinctrl { 86 gmac0 { 87 eth_phy0_reset_pin: eth-phy0-reset-pin { 88 rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 89 }; 90 }; 91 92 gmac1 { 93 eth_phy1_reset_pin: eth-phy1-reset-pin { 94 rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; 95 }; 96 }; 97}; 98 99&pmu_io_domains { 100 vccio3-supply = <&vcc_3v3>; 101}; 102 103&sdhci { 104 bus-width = <8>; 105 max-frequency = <200000000>; 106 non-removable; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; 109 status = "okay"; 110}; 111