1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rockchip,rk3528-cru.h> 12#include <dt-bindings/power/rockchip,rk3528-power.h> 13#include <dt-bindings/reset/rockchip,rk3528-cru.h> 14 15/ { 16 compatible = "rockchip,rk3528"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 gpio4 = &gpio4; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu-map { 35 cluster0 { 36 core0 { 37 cpu = <&cpu0>; 38 }; 39 core1 { 40 cpu = <&cpu1>; 41 }; 42 core2 { 43 cpu = <&cpu2>; 44 }; 45 core3 { 46 cpu = <&cpu3>; 47 }; 48 }; 49 }; 50 51 cpu0: cpu@0 { 52 compatible = "arm,cortex-a53"; 53 reg = <0x0>; 54 device_type = "cpu"; 55 enable-method = "psci"; 56 clocks = <&scmi_clk SCMI_CLK_CPU>; 57 operating-points-v2 = <&cpu_opp_table>; 58 }; 59 60 cpu1: cpu@1 { 61 compatible = "arm,cortex-a53"; 62 reg = <0x1>; 63 device_type = "cpu"; 64 enable-method = "psci"; 65 clocks = <&scmi_clk SCMI_CLK_CPU>; 66 operating-points-v2 = <&cpu_opp_table>; 67 }; 68 69 cpu2: cpu@2 { 70 compatible = "arm,cortex-a53"; 71 reg = <0x2>; 72 device_type = "cpu"; 73 enable-method = "psci"; 74 clocks = <&scmi_clk SCMI_CLK_CPU>; 75 operating-points-v2 = <&cpu_opp_table>; 76 }; 77 78 cpu3: cpu@3 { 79 compatible = "arm,cortex-a53"; 80 reg = <0x3>; 81 device_type = "cpu"; 82 enable-method = "psci"; 83 clocks = <&scmi_clk SCMI_CLK_CPU>; 84 operating-points-v2 = <&cpu_opp_table>; 85 }; 86 }; 87 88 firmware { 89 scmi: scmi { 90 compatible = "arm,scmi-smc"; 91 arm,smc-id = <0x82000010>; 92 shmem = <&scmi_shmem>; 93 #address-cells = <1>; 94 #size-cells = <0>; 95 96 scmi_clk: protocol@14 { 97 reg = <0x14>; 98 #clock-cells = <1>; 99 }; 100 }; 101 }; 102 103 cpu_opp_table: opp-table-cpu { 104 compatible = "operating-points-v2"; 105 opp-shared; 106 107 opp-1200000000 { 108 opp-hz = /bits/ 64 <1200000000>; 109 opp-microvolt = <875000 875000 1100000>; 110 clock-latency-ns = <40000>; 111 }; 112 113 opp-1416000000 { 114 opp-hz = /bits/ 64 <1416000000>; 115 opp-microvolt = <925000 925000 1100000>; 116 clock-latency-ns = <40000>; 117 }; 118 119 opp-1608000000 { 120 opp-hz = /bits/ 64 <1608000000>; 121 opp-microvolt = <975000 975000 1100000>; 122 clock-latency-ns = <40000>; 123 }; 124 125 opp-1800000000 { 126 opp-hz = /bits/ 64 <1800000000>; 127 opp-microvolt = <1037500 1037500 1100000>; 128 clock-latency-ns = <40000>; 129 }; 130 131 opp-2016000000 { 132 opp-hz = /bits/ 64 <2016000000>; 133 opp-microvolt = <1100000 1100000 1100000>; 134 clock-latency-ns = <40000>; 135 }; 136 }; 137 138 gpu_opp_table: opp-table-gpu { 139 compatible = "operating-points-v2"; 140 141 opp-300000000 { 142 opp-hz = /bits/ 64 <300000000>; 143 opp-microvolt = <875000 875000 1000000>; 144 opp-suspend; 145 }; 146 147 opp-500000000 { 148 opp-hz = /bits/ 64 <500000000>; 149 opp-microvolt = <875000 875000 1000000>; 150 }; 151 152 opp-600000000 { 153 opp-hz = /bits/ 64 <600000000>; 154 opp-microvolt = <875000 875000 1000000>; 155 }; 156 157 opp-700000000 { 158 opp-hz = /bits/ 64 <700000000>; 159 opp-microvolt = <900000 900000 1000000>; 160 }; 161 162 opp-800000000 { 163 opp-hz = /bits/ 64 <800000000>; 164 opp-microvolt = <950000 950000 1000000>; 165 }; 166 }; 167 168 pinctrl: pinctrl { 169 compatible = "rockchip,rk3528-pinctrl"; 170 rockchip,grf = <&ioc_grf>; 171 #address-cells = <2>; 172 #size-cells = <2>; 173 ranges; 174 175 gpio0: gpio@ff610000 { 176 compatible = "rockchip,gpio-bank"; 177 reg = <0x0 0xff610000 0x0 0x200>; 178 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 179 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 180 gpio-controller; 181 #gpio-cells = <2>; 182 gpio-ranges = <&pinctrl 0 0 32>; 183 interrupt-controller; 184 #interrupt-cells = <2>; 185 }; 186 187 gpio1: gpio@ffaf0000 { 188 compatible = "rockchip,gpio-bank"; 189 reg = <0x0 0xffaf0000 0x0 0x200>; 190 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 191 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 192 gpio-controller; 193 #gpio-cells = <2>; 194 gpio-ranges = <&pinctrl 0 32 32>; 195 interrupt-controller; 196 #interrupt-cells = <2>; 197 power-domains = <&power RK3528_PD_VPU>; 198 }; 199 200 gpio2: gpio@ffb00000 { 201 compatible = "rockchip,gpio-bank"; 202 reg = <0x0 0xffb00000 0x0 0x200>; 203 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 204 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 205 gpio-controller; 206 #gpio-cells = <2>; 207 gpio-ranges = <&pinctrl 0 64 32>; 208 interrupt-controller; 209 #interrupt-cells = <2>; 210 power-domains = <&power RK3528_PD_VO>; 211 }; 212 213 gpio3: gpio@ffb10000 { 214 compatible = "rockchip,gpio-bank"; 215 reg = <0x0 0xffb10000 0x0 0x200>; 216 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 217 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 218 gpio-controller; 219 #gpio-cells = <2>; 220 gpio-ranges = <&pinctrl 0 96 32>; 221 interrupt-controller; 222 #interrupt-cells = <2>; 223 power-domains = <&power RK3528_PD_VPU>; 224 }; 225 226 gpio4: gpio@ffb20000 { 227 compatible = "rockchip,gpio-bank"; 228 reg = <0x0 0xffb20000 0x0 0x200>; 229 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 230 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 231 gpio-controller; 232 #gpio-cells = <2>; 233 gpio-ranges = <&pinctrl 0 128 32>; 234 interrupt-controller; 235 #interrupt-cells = <2>; 236 power-domains = <&power RK3528_PD_RKVENC>; 237 }; 238 }; 239 240 psci { 241 compatible = "arm,psci-1.0", "arm,psci-0.2"; 242 method = "smc"; 243 }; 244 245 reserved-memory { 246 #address-cells = <2>; 247 #size-cells = <2>; 248 ranges; 249 250 scmi_shmem: shmem@10f000 { 251 compatible = "arm,scmi-shmem"; 252 reg = <0x0 0x0010f000 0x0 0x100>; 253 no-map; 254 }; 255 }; 256 257 timer { 258 compatible = "arm,armv8-timer"; 259 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 260 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 261 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 262 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 263 }; 264 265 xin24m: clock-xin24m { 266 compatible = "fixed-clock"; 267 clock-frequency = <24000000>; 268 clock-output-names = "xin24m"; 269 #clock-cells = <0>; 270 }; 271 272 gmac0_clk: clock-gmac50m { 273 compatible = "fixed-clock"; 274 clock-frequency = <50000000>; 275 clock-output-names = "gmac0"; 276 #clock-cells = <0>; 277 }; 278 279 soc { 280 compatible = "simple-bus"; 281 ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>; 282 #address-cells = <2>; 283 #size-cells = <2>; 284 285 gic: interrupt-controller@fed01000 { 286 compatible = "arm,gic-400"; 287 reg = <0x0 0xfed01000 0 0x1000>, 288 <0x0 0xfed02000 0 0x2000>, 289 <0x0 0xfed04000 0 0x2000>, 290 <0x0 0xfed06000 0 0x2000>; 291 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 292 IRQ_TYPE_LEVEL_LOW)>; 293 interrupt-controller; 294 #address-cells = <0>; 295 #interrupt-cells = <3>; 296 }; 297 298 qos_crypto_a: qos@ff200000 { 299 compatible = "rockchip,rk3528-qos", "syscon"; 300 reg = <0x0 0xff200000 0x0 0x20>; 301 }; 302 303 qos_crypto_p: qos@ff200080 { 304 compatible = "rockchip,rk3528-qos", "syscon"; 305 reg = <0x0 0xff200080 0x0 0x20>; 306 }; 307 308 qos_dcf: qos@ff200100 { 309 compatible = "rockchip,rk3528-qos", "syscon"; 310 reg = <0x0 0xff200100 0x0 0x20>; 311 }; 312 313 qos_dft2apb: qos@ff200200 { 314 compatible = "rockchip,rk3528-qos", "syscon"; 315 reg = <0x0 0xff200200 0x0 0x20>; 316 }; 317 318 qos_dma2ddr: qos@ff200280 { 319 compatible = "rockchip,rk3528-qos", "syscon"; 320 reg = <0x0 0xff200280 0x0 0x20>; 321 }; 322 323 qos_dmac: qos@ff200300 { 324 compatible = "rockchip,rk3528-qos", "syscon"; 325 reg = <0x0 0xff200300 0x0 0x20>; 326 }; 327 328 qos_keyreader: qos@ff200380 { 329 compatible = "rockchip,rk3528-qos", "syscon"; 330 reg = <0x0 0xff200380 0x0 0x20>; 331 }; 332 333 qos_cpu: qos@ff210000 { 334 compatible = "rockchip,rk3528-qos", "syscon"; 335 reg = <0x0 0xff210000 0x0 0x20>; 336 }; 337 338 qos_debug: qos@ff210080 { 339 compatible = "rockchip,rk3528-qos", "syscon"; 340 reg = <0x0 0xff210080 0x0 0x20>; 341 }; 342 343 qos_gpu_m0: qos@ff220000 { 344 compatible = "rockchip,rk3528-qos", "syscon"; 345 reg = <0x0 0xff220000 0x0 0x20>; 346 }; 347 348 qos_gpu_m1: qos@ff220080 { 349 compatible = "rockchip,rk3528-qos", "syscon"; 350 reg = <0x0 0xff220080 0x0 0x20>; 351 }; 352 353 qos_pmu_mcu: qos@ff240000 { 354 compatible = "rockchip,rk3528-qos", "syscon"; 355 reg = <0x0 0xff240000 0x0 0x20>; 356 }; 357 358 qos_rkvdec: qos@ff250000 { 359 compatible = "rockchip,rk3528-qos", "syscon"; 360 reg = <0x0 0xff250000 0x0 0x20>; 361 }; 362 363 qos_rkvenc: qos@ff260000 { 364 compatible = "rockchip,rk3528-qos", "syscon"; 365 reg = <0x0 0xff260000 0x0 0x20>; 366 }; 367 368 qos_gmac0: qos@ff270000 { 369 compatible = "rockchip,rk3528-qos", "syscon"; 370 reg = <0x0 0xff270000 0x0 0x20>; 371 }; 372 373 qos_hdcp: qos@ff270080 { 374 compatible = "rockchip,rk3528-qos", "syscon"; 375 reg = <0x0 0xff270080 0x0 0x20>; 376 }; 377 378 qos_jpegdec: qos@ff270100 { 379 compatible = "rockchip,rk3528-qos", "syscon"; 380 reg = <0x0 0xff270100 0x0 0x20>; 381 }; 382 383 qos_rga2_m0ro: qos@ff270200 { 384 compatible = "rockchip,rk3528-qos", "syscon"; 385 reg = <0x0 0xff270200 0x0 0x20>; 386 }; 387 388 qos_rga2_m0wo: qos@ff270280 { 389 compatible = "rockchip,rk3528-qos", "syscon"; 390 reg = <0x0 0xff270280 0x0 0x20>; 391 }; 392 393 qos_sdmmc0: qos@ff270300 { 394 compatible = "rockchip,rk3528-qos", "syscon"; 395 reg = <0x0 0xff270300 0x0 0x20>; 396 }; 397 398 qos_usb2host: qos@ff270380 { 399 compatible = "rockchip,rk3528-qos", "syscon"; 400 reg = <0x0 0xff270380 0x0 0x20>; 401 }; 402 403 qos_vdpp: qos@ff270480 { 404 compatible = "rockchip,rk3528-qos", "syscon"; 405 reg = <0x0 0xff270480 0x0 0x20>; 406 }; 407 408 qos_vop: qos@ff270500 { 409 compatible = "rockchip,rk3528-qos", "syscon"; 410 reg = <0x0 0xff270500 0x0 0x20>; 411 }; 412 413 qos_emmc: qos@ff280000 { 414 compatible = "rockchip,rk3528-qos", "syscon"; 415 reg = <0x0 0xff280000 0x0 0x20>; 416 }; 417 418 qos_fspi: qos@ff280080 { 419 compatible = "rockchip,rk3528-qos", "syscon"; 420 reg = <0x0 0xff280080 0x0 0x20>; 421 }; 422 423 qos_gmac1: qos@ff280100 { 424 compatible = "rockchip,rk3528-qos", "syscon"; 425 reg = <0x0 0xff280100 0x0 0x20>; 426 }; 427 428 qos_pcie: qos@ff280180 { 429 compatible = "rockchip,rk3528-qos", "syscon"; 430 reg = <0x0 0xff280180 0x0 0x20>; 431 }; 432 433 qos_sdio0: qos@ff280200 { 434 compatible = "rockchip,rk3528-qos", "syscon"; 435 reg = <0x0 0xff280200 0x0 0x20>; 436 }; 437 438 qos_sdio1: qos@ff280280 { 439 compatible = "rockchip,rk3528-qos", "syscon"; 440 reg = <0x0 0xff280280 0x0 0x20>; 441 }; 442 443 qos_tsp: qos@ff280300 { 444 compatible = "rockchip,rk3528-qos", "syscon"; 445 reg = <0x0 0xff280300 0x0 0x20>; 446 }; 447 448 qos_usb3otg: qos@ff280380 { 449 compatible = "rockchip,rk3528-qos", "syscon"; 450 reg = <0x0 0xff280380 0x0 0x20>; 451 }; 452 453 qos_vpu: qos@ff280400 { 454 compatible = "rockchip,rk3528-qos", "syscon"; 455 reg = <0x0 0xff280400 0x0 0x20>; 456 }; 457 458 vpu_grf: syscon@ff340000 { 459 compatible = "rockchip,rk3528-vpu-grf", "syscon"; 460 reg = <0x0 0xff340000 0x0 0x8000>; 461 }; 462 463 pipe_phy_grf: syscon@ff348000 { 464 compatible = "rockchip,rk3528-pipe-phy-grf", "syscon"; 465 reg = <0x0 0xff348000 0x0 0x8000>; 466 }; 467 468 vo_grf: syscon@ff360000 { 469 compatible = "rockchip,rk3528-vo-grf", "syscon"; 470 reg = <0x0 0xff360000 0x0 0x10000>; 471 }; 472 473 cru: clock-controller@ff4a0000 { 474 compatible = "rockchip,rk3528-cru"; 475 reg = <0x0 0xff4a0000 0x0 0x30000>; 476 assigned-clocks = 477 <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>, 478 <&cru PLL_PPLL>, <&cru PLL_CPLL>, 479 <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>, 480 <&cru CLK_MATRIX_500M_SRC>, 481 <&cru CLK_MATRIX_50M_SRC>, 482 <&cru CLK_MATRIX_100M_SRC>, 483 <&cru CLK_MATRIX_150M_SRC>, 484 <&cru CLK_MATRIX_200M_SRC>, 485 <&cru CLK_MATRIX_300M_SRC>, 486 <&cru CLK_MATRIX_339M_SRC>, 487 <&cru CLK_MATRIX_400M_SRC>, 488 <&cru CLK_MATRIX_600M_SRC>, 489 <&cru CLK_PPLL_50M_MATRIX>, 490 <&cru CLK_PPLL_100M_MATRIX>, 491 <&cru CLK_PPLL_125M_MATRIX>, 492 <&cru ACLK_BUS_VOPGL_ROOT>; 493 assigned-clock-rates = 494 <32768>, <1188000000>, 495 <1000000000>, <996000000>, 496 <408000000>, <250000000>, 497 <500000000>, 498 <50000000>, 499 <100000000>, 500 <150000000>, 501 <200000000>, 502 <300000000>, 503 <340000000>, 504 <400000000>, 505 <600000000>, 506 <50000000>, 507 <100000000>, 508 <125000000>, 509 <500000000>; 510 clocks = <&xin24m>, <&gmac0_clk>; 511 clock-names = "xin24m", "gmac0"; 512 #clock-cells = <1>; 513 #reset-cells = <1>; 514 }; 515 516 ioc_grf: syscon@ff540000 { 517 compatible = "rockchip,rk3528-ioc-grf", "syscon"; 518 reg = <0x0 0xff540000 0x0 0x40000>; 519 }; 520 521 pmu: power-management@ff600000 { 522 compatible = "rockchip,rk3528-pmu", "syscon", "simple-mfd"; 523 reg = <0x0 0xff600000 0x0 0x2000>; 524 525 power: power-controller { 526 compatible = "rockchip,rk3528-power-controller"; 527 #power-domain-cells = <1>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 531 /* These power domains are grouped by VD_GPU */ 532 power-domain@RK3528_PD_GPU { 533 reg = <RK3528_PD_GPU>; 534 clocks = <&cru ACLK_GPU_MALI>, 535 <&cru PCLK_GPU_ROOT>; 536 pm_qos = <&qos_gpu_m0>, 537 <&qos_gpu_m1>; 538 #power-domain-cells = <0>; 539 }; 540 541 /* These power domains are grouped by VD_LOGIC */ 542 power-domain@RK3528_PD_RKVDEC { 543 reg = <RK3528_PD_RKVDEC>; 544 pm_qos = <&qos_rkvdec>; 545 #power-domain-cells = <0>; 546 status = "disabled"; 547 }; 548 power-domain@RK3528_PD_RKVENC { 549 reg = <RK3528_PD_RKVENC>; 550 pm_qos = <&qos_rkvenc>; 551 #power-domain-cells = <0>; 552 }; 553 power-domain@RK3528_PD_VO { 554 reg = <RK3528_PD_VO>; 555 pm_qos = <&qos_gmac0>, 556 <&qos_hdcp>, 557 <&qos_jpegdec>, 558 <&qos_rga2_m0ro>, 559 <&qos_rga2_m0wo>, 560 <&qos_sdmmc0>, 561 <&qos_usb2host>, 562 <&qos_vdpp>, 563 <&qos_vop>; 564 #power-domain-cells = <0>; 565 }; 566 power-domain@RK3528_PD_VPU { 567 reg = <RK3528_PD_VPU>; 568 pm_qos = <&qos_emmc>, 569 <&qos_fspi>, 570 <&qos_gmac1>, 571 <&qos_pcie>, 572 <&qos_sdio0>, 573 <&qos_sdio1>, 574 <&qos_tsp>, 575 <&qos_usb3otg>, 576 <&qos_vpu>; 577 #power-domain-cells = <0>; 578 }; 579 }; 580 }; 581 582 gpu: gpu@ff700000 { 583 compatible = "rockchip,rk3528-mali", "arm,mali-450"; 584 reg = <0x0 0xff700000 0x0 0x40000>; 585 assigned-clocks = <&cru ACLK_GPU_MALI>, 586 <&scmi_clk SCMI_CLK_GPU>; 587 assigned-clock-rates = <297000000>, <300000000>; 588 clocks = <&cru ACLK_GPU_MALI>, <&scmi_clk SCMI_CLK_GPU>; 589 clock-names = "bus", "core"; 590 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 597 interrupt-names = "gp", 598 "gpmmu", 599 "pp", 600 "pp0", 601 "ppmmu0", 602 "pp1", 603 "ppmmu1"; 604 operating-points-v2 = <&gpu_opp_table>; 605 power-domains = <&power RK3528_PD_GPU>; 606 resets = <&cru SRST_A_GPU>; 607 status = "disabled"; 608 }; 609 610 spi0: spi@ff9c0000 { 611 compatible = "rockchip,rk3528-spi", 612 "rockchip,rk3066-spi"; 613 reg = <0x0 0xff9c0000 0x0 0x1000>; 614 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 615 clock-names = "spiclk", "apb_pclk"; 616 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 617 dmas = <&dmac 25>, <&dmac 24>; 618 dma-names = "tx", "rx"; 619 power-domains = <&power RK3528_PD_RKVENC>; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 status = "disabled"; 623 }; 624 625 spi1: spi@ff9d0000 { 626 compatible = "rockchip,rk3528-spi", 627 "rockchip,rk3066-spi"; 628 reg = <0x0 0xff9d0000 0x0 0x1000>; 629 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 630 clock-names = "spiclk", "apb_pclk"; 631 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 632 dmas = <&dmac 31>, <&dmac 30>; 633 dma-names = "tx", "rx"; 634 power-domains = <&power RK3528_PD_VPU>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 status = "disabled"; 638 }; 639 640 uart0: serial@ff9f0000 { 641 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 642 reg = <0x0 0xff9f0000 0x0 0x100>; 643 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 644 clock-names = "baudclk", "apb_pclk"; 645 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 646 dmas = <&dmac 9>, <&dmac 8>; 647 reg-io-width = <4>; 648 reg-shift = <2>; 649 status = "disabled"; 650 }; 651 652 uart1: serial@ff9f8000 { 653 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 654 reg = <0x0 0xff9f8000 0x0 0x100>; 655 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 656 clock-names = "baudclk", "apb_pclk"; 657 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 658 dmas = <&dmac 11>, <&dmac 10>; 659 power-domains = <&power RK3528_PD_RKVENC>; 660 reg-io-width = <4>; 661 reg-shift = <2>; 662 status = "disabled"; 663 }; 664 665 uart2: serial@ffa00000 { 666 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 667 reg = <0x0 0xffa00000 0x0 0x100>; 668 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 669 clock-names = "baudclk", "apb_pclk"; 670 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 671 dmas = <&dmac 13>, <&dmac 12>; 672 power-domains = <&power RK3528_PD_VPU>; 673 reg-io-width = <4>; 674 reg-shift = <2>; 675 status = "disabled"; 676 }; 677 678 uart3: serial@ffa08000 { 679 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 680 reg = <0x0 0xffa08000 0x0 0x100>; 681 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 682 clock-names = "baudclk", "apb_pclk"; 683 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 684 dmas = <&dmac 15>, <&dmac 14>; 685 power-domains = <&power RK3528_PD_RKVENC>; 686 reg-io-width = <4>; 687 reg-shift = <2>; 688 status = "disabled"; 689 }; 690 691 uart4: serial@ffa10000 { 692 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 693 reg = <0x0 0xffa10000 0x0 0x100>; 694 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 695 clock-names = "baudclk", "apb_pclk"; 696 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 697 dmas = <&dmac 17>, <&dmac 16>; 698 power-domains = <&power RK3528_PD_VO>; 699 reg-io-width = <4>; 700 reg-shift = <2>; 701 status = "disabled"; 702 }; 703 704 uart5: serial@ffa18000 { 705 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 706 reg = <0x0 0xffa18000 0x0 0x100>; 707 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 708 clock-names = "baudclk", "apb_pclk"; 709 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 710 dmas = <&dmac 19>, <&dmac 18>; 711 power-domains = <&power RK3528_PD_VPU>; 712 reg-io-width = <4>; 713 reg-shift = <2>; 714 status = "disabled"; 715 }; 716 717 uart6: serial@ffa20000 { 718 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 719 reg = <0x0 0xffa20000 0x0 0x100>; 720 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 721 clock-names = "baudclk", "apb_pclk"; 722 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 723 dmas = <&dmac 21>, <&dmac 20>; 724 power-domains = <&power RK3528_PD_VPU>; 725 reg-io-width = <4>; 726 reg-shift = <2>; 727 status = "disabled"; 728 }; 729 730 uart7: serial@ffa28000 { 731 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 732 reg = <0x0 0xffa28000 0x0 0x100>; 733 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 734 clock-names = "baudclk", "apb_pclk"; 735 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 736 dmas = <&dmac 23>, <&dmac 22>; 737 power-domains = <&power RK3528_PD_VPU>; 738 reg-io-width = <4>; 739 reg-shift = <2>; 740 status = "disabled"; 741 }; 742 743 i2c0: i2c@ffa50000 { 744 compatible = "rockchip,rk3528-i2c", 745 "rockchip,rk3399-i2c"; 746 reg = <0x0 0xffa50000 0x0 0x1000>; 747 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 748 clock-names = "i2c", "pclk"; 749 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 750 power-domains = <&power RK3528_PD_RKVENC>; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 status = "disabled"; 754 }; 755 756 i2c1: i2c@ffa58000 { 757 compatible = "rockchip,rk3528-i2c", 758 "rockchip,rk3399-i2c"; 759 reg = <0x0 0xffa58000 0x0 0x1000>; 760 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 761 clock-names = "i2c", "pclk"; 762 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 763 power-domains = <&power RK3528_PD_RKVENC>; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 status = "disabled"; 767 }; 768 769 i2c2: i2c@ffa60000 { 770 compatible = "rockchip,rk3528-i2c", 771 "rockchip,rk3399-i2c"; 772 reg = <0x0 0xffa60000 0x0 0x1000>; 773 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 774 clock-names = "i2c", "pclk"; 775 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 776 pinctrl-names = "default"; 777 pinctrl-0 = <&i2c2m1_xfer>; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 status = "disabled"; 781 }; 782 783 i2c3: i2c@ffa68000 { 784 compatible = "rockchip,rk3528-i2c", 785 "rockchip,rk3399-i2c"; 786 reg = <0x0 0xffa68000 0x0 0x1000>; 787 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 788 clock-names = "i2c", "pclk"; 789 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 790 power-domains = <&power RK3528_PD_VPU>; 791 #address-cells = <1>; 792 #size-cells = <0>; 793 status = "disabled"; 794 }; 795 796 i2c4: i2c@ffa70000 { 797 compatible = "rockchip,rk3528-i2c", 798 "rockchip,rk3399-i2c"; 799 reg = <0x0 0xffa70000 0x0 0x1000>; 800 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 801 clock-names = "i2c", "pclk"; 802 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&i2c4_xfer>; 805 power-domains = <&power RK3528_PD_VO>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 status = "disabled"; 809 }; 810 811 i2c5: i2c@ffa78000 { 812 compatible = "rockchip,rk3528-i2c", 813 "rockchip,rk3399-i2c"; 814 reg = <0x0 0xffa78000 0x0 0x1000>; 815 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 816 clock-names = "i2c", "pclk"; 817 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 818 power-domains = <&power RK3528_PD_VPU>; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 status = "disabled"; 822 }; 823 824 i2c6: i2c@ffa80000 { 825 compatible = "rockchip,rk3528-i2c", 826 "rockchip,rk3399-i2c"; 827 reg = <0x0 0xffa80000 0x0 0x1000>; 828 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 829 clock-names = "i2c", "pclk"; 830 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 831 power-domains = <&power RK3528_PD_VPU>; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 status = "disabled"; 835 }; 836 837 i2c7: i2c@ffa88000 { 838 compatible = "rockchip,rk3528-i2c", 839 "rockchip,rk3399-i2c"; 840 reg = <0x0 0xffa88000 0x0 0x1000>; 841 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 842 clock-names = "i2c", "pclk"; 843 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 844 pinctrl-names = "default"; 845 pinctrl-0 = <&i2c7_xfer>; 846 power-domains = <&power RK3528_PD_VO>; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 status = "disabled"; 850 }; 851 852 pwm0: pwm@ffa90000 { 853 compatible = "rockchip,rk3528-pwm", 854 "rockchip,rk3328-pwm"; 855 reg = <0x0 0xffa90000 0x0 0x10>; 856 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 857 clock-names = "pwm", "pclk"; 858 #pwm-cells = <3>; 859 status = "disabled"; 860 }; 861 862 pwm1: pwm@ffa90010 { 863 compatible = "rockchip,rk3528-pwm", 864 "rockchip,rk3328-pwm"; 865 reg = <0x0 0xffa90010 0x0 0x10>; 866 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 867 clock-names = "pwm", "pclk"; 868 #pwm-cells = <3>; 869 status = "disabled"; 870 }; 871 872 pwm2: pwm@ffa90020 { 873 compatible = "rockchip,rk3528-pwm", 874 "rockchip,rk3328-pwm"; 875 reg = <0x0 0xffa90020 0x0 0x10>; 876 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 877 clock-names = "pwm", "pclk"; 878 #pwm-cells = <3>; 879 status = "disabled"; 880 }; 881 882 pwm3: pwm@ffa90030 { 883 compatible = "rockchip,rk3528-pwm", 884 "rockchip,rk3328-pwm"; 885 reg = <0x0 0xffa90030 0x0 0x10>; 886 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 887 clock-names = "pwm", "pclk"; 888 #pwm-cells = <3>; 889 status = "disabled"; 890 }; 891 892 pwm4: pwm@ffa98000 { 893 compatible = "rockchip,rk3528-pwm", 894 "rockchip,rk3328-pwm"; 895 reg = <0x0 0xffa98000 0x0 0x10>; 896 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 897 clock-names = "pwm", "pclk"; 898 #pwm-cells = <3>; 899 status = "disabled"; 900 }; 901 902 pwm5: pwm@ffa98010 { 903 compatible = "rockchip,rk3528-pwm", 904 "rockchip,rk3328-pwm"; 905 reg = <0x0 0xffa98010 0x0 0x10>; 906 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 907 clock-names = "pwm", "pclk"; 908 #pwm-cells = <3>; 909 status = "disabled"; 910 }; 911 912 pwm6: pwm@ffa98020 { 913 compatible = "rockchip,rk3528-pwm", 914 "rockchip,rk3328-pwm"; 915 reg = <0x0 0xffa98020 0x0 0x10>; 916 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 917 clock-names = "pwm", "pclk"; 918 #pwm-cells = <3>; 919 status = "disabled"; 920 }; 921 922 pwm7: pwm@ffa98030 { 923 compatible = "rockchip,rk3528-pwm", 924 "rockchip,rk3328-pwm"; 925 reg = <0x0 0xffa98030 0x0 0x10>; 926 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 927 clock-names = "pwm", "pclk"; 928 #pwm-cells = <3>; 929 status = "disabled"; 930 }; 931 932 saradc: adc@ffae0000 { 933 compatible = "rockchip,rk3528-saradc"; 934 reg = <0x0 0xffae0000 0x0 0x10000>; 935 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 936 clock-names = "saradc", "apb_pclk"; 937 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 938 power-domains = <&power RK3528_PD_VPU>; 939 resets = <&cru SRST_P_SARADC>; 940 reset-names = "saradc-apb"; 941 #io-channel-cells = <1>; 942 status = "disabled"; 943 }; 944 945 gmac0: ethernet@ffbd0000 { 946 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; 947 reg = <0x0 0xffbd0000 0x0 0x10000>; 948 clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>, 949 <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>, 950 <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>; 951 clock-names = "stmmaceth", "clk_mac_ref", 952 "mac_clk_rx", "mac_clk_tx", 953 "pclk_mac", "aclk_mac"; 954 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 956 interrupt-names = "macirq", "eth_wake_irq"; 957 phy-handle = <&rmii0_phy>; 958 phy-mode = "rmii"; 959 power-domains = <&power RK3528_PD_VO>; 960 resets = <&cru SRST_A_MAC_VO>; 961 reset-names = "stmmaceth"; 962 rockchip,grf = <&vo_grf>; 963 snps,axi-config = <&gmac0_stmmac_axi_setup>; 964 snps,mixed-burst; 965 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 966 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 967 snps,tso; 968 status = "disabled"; 969 970 mdio0: mdio { 971 compatible = "snps,dwmac-mdio"; 972 #address-cells = <0x1>; 973 #size-cells = <0x0>; 974 975 rmii0_phy: ethernet-phy@2 { 976 compatible = "ethernet-phy-ieee802.3-c22"; 977 reg = <0x2>; 978 clocks = <&cru CLK_MACPHY>; 979 phy-is-integrated; 980 pinctrl-names = "default"; 981 pinctrl-0 = <&fephym0_led_link>, 982 <&fephym0_led_spd>; 983 resets = <&cru SRST_MACPHY>; 984 }; 985 }; 986 987 gmac0_stmmac_axi_setup: stmmac-axi-config { 988 snps,blen = <0 0 0 0 16 8 4>; 989 snps,rd_osr_lmt = <8>; 990 snps,wr_osr_lmt = <4>; 991 }; 992 993 gmac0_mtl_rx_setup: rx-queues-config { 994 snps,rx-queues-to-use = <1>; 995 queue0 {}; 996 }; 997 998 gmac0_mtl_tx_setup: tx-queues-config { 999 snps,tx-queues-to-use = <1>; 1000 queue0 {}; 1001 }; 1002 }; 1003 1004 gmac1: ethernet@ffbe0000 { 1005 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; 1006 reg = <0x0 0xffbe0000 0x0 0x10000>; 1007 clocks = <&cru CLK_GMAC1_SRC_VPU>, 1008 <&cru CLK_GMAC1_RMII_VPU>, 1009 <&cru PCLK_MAC_VPU>, 1010 <&cru ACLK_MAC_VPU>; 1011 clock-names = "stmmaceth", 1012 "clk_mac_ref", 1013 "pclk_mac", 1014 "aclk_mac"; 1015 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1017 interrupt-names = "macirq", "eth_wake_irq"; 1018 power-domains = <&power RK3528_PD_VPU>; 1019 resets = <&cru SRST_A_MAC>; 1020 reset-names = "stmmaceth"; 1021 rockchip,grf = <&vpu_grf>; 1022 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1023 snps,mixed-burst; 1024 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1025 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1026 snps,tso; 1027 status = "disabled"; 1028 1029 mdio1: mdio { 1030 compatible = "snps,dwmac-mdio"; 1031 #address-cells = <0x1>; 1032 #size-cells = <0x0>; 1033 }; 1034 1035 gmac1_stmmac_axi_setup: stmmac-axi-config { 1036 snps,blen = <0 0 0 0 16 8 4>; 1037 snps,rd_osr_lmt = <8>; 1038 snps,wr_osr_lmt = <4>; 1039 }; 1040 1041 gmac1_mtl_rx_setup: rx-queues-config { 1042 snps,rx-queues-to-use = <1>; 1043 queue0 {}; 1044 }; 1045 1046 gmac1_mtl_tx_setup: tx-queues-config { 1047 snps,tx-queues-to-use = <1>; 1048 queue0 {}; 1049 }; 1050 }; 1051 1052 sdhci: mmc@ffbf0000 { 1053 compatible = "rockchip,rk3528-dwcmshc", 1054 "rockchip,rk3588-dwcmshc"; 1055 reg = <0x0 0xffbf0000 0x0 0x10000>; 1056 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, 1057 <&cru CCLK_SRC_EMMC>; 1058 assigned-clock-rates = <200000000>, <24000000>, 1059 <200000000>; 1060 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 1061 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1062 <&cru TCLK_EMMC>; 1063 clock-names = "core", "bus", "axi", "block", "timer"; 1064 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1065 max-frequency = <200000000>; 1066 pinctrl-names = "default"; 1067 pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, 1068 <&emmc_strb>; 1069 power-domains = <&power RK3528_PD_VPU>; 1070 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1071 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1072 <&cru SRST_T_EMMC>; 1073 reset-names = "core", "bus", "axi", "block", "timer"; 1074 status = "disabled"; 1075 }; 1076 1077 sdio0: mmc@ffc10000 { 1078 compatible = "rockchip,rk3528-dw-mshc", 1079 "rockchip,rk3288-dw-mshc"; 1080 reg = <0x0 0xffc10000 0x0 0x4000>; 1081 clocks = <&cru HCLK_SDIO0>, 1082 <&cru CCLK_SRC_SDIO0>, 1083 <&cru SCLK_SDIO0_DRV>, 1084 <&cru SCLK_SDIO0_SAMPLE>; 1085 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1086 fifo-depth = <0x100>; 1087 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1088 max-frequency = <200000000>; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>; 1091 power-domains = <&power RK3528_PD_VPU>; 1092 resets = <&cru SRST_H_SDIO0>; 1093 reset-names = "reset"; 1094 status = "disabled"; 1095 }; 1096 1097 sdio1: mmc@ffc20000 { 1098 compatible = "rockchip,rk3528-dw-mshc", 1099 "rockchip,rk3288-dw-mshc"; 1100 reg = <0x0 0xffc20000 0x0 0x4000>; 1101 clocks = <&cru HCLK_SDIO1>, 1102 <&cru CCLK_SRC_SDIO1>, 1103 <&cru SCLK_SDIO1_DRV>, 1104 <&cru SCLK_SDIO1_SAMPLE>; 1105 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1106 fifo-depth = <0x100>; 1107 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1108 max-frequency = <200000000>; 1109 pinctrl-names = "default"; 1110 pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>; 1111 power-domains = <&power RK3528_PD_VPU>; 1112 resets = <&cru SRST_H_SDIO1>; 1113 reset-names = "reset"; 1114 status = "disabled"; 1115 }; 1116 1117 sdmmc: mmc@ffc30000 { 1118 compatible = "rockchip,rk3528-dw-mshc", 1119 "rockchip,rk3288-dw-mshc"; 1120 reg = <0x0 0xffc30000 0x0 0x4000>; 1121 clocks = <&cru HCLK_SDMMC0>, 1122 <&cru CCLK_SRC_SDMMC0>, 1123 <&cru SCLK_SDMMC_DRV>, 1124 <&cru SCLK_SDMMC_SAMPLE>; 1125 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1126 fifo-depth = <0x100>; 1127 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1128 max-frequency = <150000000>; 1129 pinctrl-names = "default"; 1130 pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, 1131 <&sdmmc_det>; 1132 power-domains = <&power RK3528_PD_VO>; 1133 resets = <&cru SRST_H_SDMMC0>; 1134 reset-names = "reset"; 1135 rockchip,default-sample-phase = <90>; 1136 status = "disabled"; 1137 }; 1138 1139 dmac: dma-controller@ffd60000 { 1140 compatible = "arm,pl330", "arm,primecell"; 1141 reg = <0x0 0xffd60000 0x0 0x4000>; 1142 clocks = <&cru ACLK_DMAC>; 1143 clock-names = "apb_pclk"; 1144 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1153 #dma-cells = <1>; 1154 arm,pl330-periph-burst; 1155 }; 1156 1157 combphy: phy@ffdc0000 { 1158 compatible = "rockchip,rk3528-naneng-combphy"; 1159 reg = <0x0 0xffdc0000 0x0 0x10000>; 1160 assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>; 1161 assigned-clock-rates = <100000000>; 1162 clocks = <&cru CLK_REF_PCIE_INNER_PHY>, 1163 <&cru PCLK_PCIE_PHY>, 1164 <&cru PCLK_PIPE_GRF>; 1165 clock-names = "ref", "apb", "pipe"; 1166 power-domains = <&power RK3528_PD_VPU>; 1167 resets = <&cru SRST_PCIE_PIPE_PHY>, 1168 <&cru SRST_P_PCIE_PHY>; 1169 reset-names = "phy", "apb"; 1170 #phy-cells = <1>; 1171 rockchip,pipe-grf = <&vpu_grf>; 1172 rockchip,pipe-phy-grf = <&pipe_phy_grf>; 1173 status = "disabled"; 1174 }; 1175 }; 1176}; 1177 1178#include "rk3528-pinctrl.dtsi" 1179