1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 compatible = "rockchip,rk3528"; 12 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 aliases { 18 serial0 = &uart0; 19 serial1 = &uart1; 20 serial2 = &uart2; 21 serial3 = &uart3; 22 serial4 = &uart4; 23 serial5 = &uart5; 24 serial6 = &uart6; 25 serial7 = &uart7; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu-map { 33 cluster0 { 34 core0 { 35 cpu = <&cpu0>; 36 }; 37 core1 { 38 cpu = <&cpu1>; 39 }; 40 core2 { 41 cpu = <&cpu2>; 42 }; 43 core3 { 44 cpu = <&cpu3>; 45 }; 46 }; 47 }; 48 49 cpu0: cpu@0 { 50 compatible = "arm,cortex-a53"; 51 reg = <0x0>; 52 device_type = "cpu"; 53 enable-method = "psci"; 54 }; 55 56 cpu1: cpu@1 { 57 compatible = "arm,cortex-a53"; 58 reg = <0x1>; 59 device_type = "cpu"; 60 enable-method = "psci"; 61 }; 62 63 cpu2: cpu@2 { 64 compatible = "arm,cortex-a53"; 65 reg = <0x2>; 66 device_type = "cpu"; 67 enable-method = "psci"; 68 }; 69 70 cpu3: cpu@3 { 71 compatible = "arm,cortex-a53"; 72 reg = <0x3>; 73 device_type = "cpu"; 74 enable-method = "psci"; 75 }; 76 }; 77 78 psci { 79 compatible = "arm,psci-1.0", "arm,psci-0.2"; 80 method = "smc"; 81 }; 82 83 timer { 84 compatible = "arm,armv8-timer"; 85 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 86 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 87 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 88 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 89 }; 90 91 xin24m: clock-xin24m { 92 compatible = "fixed-clock"; 93 clock-frequency = <24000000>; 94 clock-output-names = "xin24m"; 95 #clock-cells = <0>; 96 }; 97 98 soc { 99 compatible = "simple-bus"; 100 ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>; 101 #address-cells = <2>; 102 #size-cells = <2>; 103 104 gic: interrupt-controller@fed01000 { 105 compatible = "arm,gic-400"; 106 reg = <0x0 0xfed01000 0 0x1000>, 107 <0x0 0xfed02000 0 0x2000>, 108 <0x0 0xfed04000 0 0x2000>, 109 <0x0 0xfed06000 0 0x2000>; 110 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 111 IRQ_TYPE_LEVEL_LOW)>; 112 interrupt-controller; 113 #address-cells = <0>; 114 #interrupt-cells = <3>; 115 }; 116 117 uart0: serial@ff9f0000 { 118 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 119 reg = <0x0 0xff9f0000 0x0 0x100>; 120 clock-frequency = <24000000>; 121 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 122 reg-io-width = <4>; 123 reg-shift = <2>; 124 status = "disabled"; 125 }; 126 127 uart1: serial@ff9f8000 { 128 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 129 reg = <0x0 0xff9f8000 0x0 0x100>; 130 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 131 reg-io-width = <4>; 132 reg-shift = <2>; 133 status = "disabled"; 134 }; 135 136 uart2: serial@ffa00000 { 137 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 138 reg = <0x0 0xffa00000 0x0 0x100>; 139 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 140 reg-io-width = <4>; 141 reg-shift = <2>; 142 status = "disabled"; 143 }; 144 145 uart3: serial@ffa08000 { 146 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 147 reg = <0x0 0xffa08000 0x0 0x100>; 148 reg-io-width = <4>; 149 reg-shift = <2>; 150 status = "disabled"; 151 }; 152 153 uart4: serial@ffa10000 { 154 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 155 reg = <0x0 0xffa10000 0x0 0x100>; 156 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 157 reg-io-width = <4>; 158 reg-shift = <2>; 159 status = "disabled"; 160 }; 161 162 uart5: serial@ffa18000 { 163 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 164 reg = <0x0 0xffa18000 0x0 0x100>; 165 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 166 reg-io-width = <4>; 167 reg-shift = <2>; 168 status = "disabled"; 169 }; 170 171 uart6: serial@ffa20000 { 172 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 173 reg = <0x0 0xffa20000 0x0 0x100>; 174 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 175 reg-io-width = <4>; 176 reg-shift = <2>; 177 status = "disabled"; 178 }; 179 180 uart7: serial@ffa28000 { 181 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 182 reg = <0x0 0xffa28000 0x0 0x100>; 183 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 184 reg-io-width = <4>; 185 reg-shift = <2>; 186 status = "disabled"; 187 }; 188 }; 189}; 190