1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu-map { 44 cluster0 { 45 core0 { 46 cpu = <&cpu_l0>; 47 }; 48 core1 { 49 cpu = <&cpu_l1>; 50 }; 51 core2 { 52 cpu = <&cpu_l2>; 53 }; 54 core3 { 55 cpu = <&cpu_l3>; 56 }; 57 }; 58 59 cluster1 { 60 core0 { 61 cpu = <&cpu_b0>; 62 }; 63 core1 { 64 cpu = <&cpu_b1>; 65 }; 66 }; 67 }; 68 69 cpu_l0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 capacity-dmips-mhz = <485>; 75 clocks = <&cru ARMCLKL>; 76 #cooling-cells = <2>; /* min followed by max */ 77 dynamic-power-coefficient = <100>; 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 79 }; 80 81 cpu_l1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x1>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <485>; 87 clocks = <&cru ARMCLKL>; 88 #cooling-cells = <2>; /* min followed by max */ 89 dynamic-power-coefficient = <100>; 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 91 }; 92 93 cpu_l2: cpu@2 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x2>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <485>; 99 clocks = <&cru ARMCLKL>; 100 #cooling-cells = <2>; /* min followed by max */ 101 dynamic-power-coefficient = <100>; 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 103 }; 104 105 cpu_l3: cpu@3 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0 0x3>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <485>; 111 clocks = <&cru ARMCLKL>; 112 #cooling-cells = <2>; /* min followed by max */ 113 dynamic-power-coefficient = <100>; 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 115 }; 116 117 cpu_b0: cpu@100 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a72"; 120 reg = <0x0 0x100>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <1024>; 123 clocks = <&cru ARMCLKB>; 124 #cooling-cells = <2>; /* min followed by max */ 125 dynamic-power-coefficient = <436>; 126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 127 128 thermal-idle { 129 #cooling-cells = <2>; 130 duration-us = <10000>; 131 exit-latency-us = <500>; 132 }; 133 }; 134 135 cpu_b1: cpu@101 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a72"; 138 reg = <0x0 0x101>; 139 enable-method = "psci"; 140 capacity-dmips-mhz = <1024>; 141 clocks = <&cru ARMCLKB>; 142 #cooling-cells = <2>; /* min followed by max */ 143 dynamic-power-coefficient = <436>; 144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 145 146 thermal-idle { 147 #cooling-cells = <2>; 148 duration-us = <10000>; 149 exit-latency-us = <500>; 150 }; 151 }; 152 153 idle-states { 154 entry-method = "psci"; 155 156 CPU_SLEEP: cpu-sleep { 157 compatible = "arm,idle-state"; 158 local-timer-stop; 159 arm,psci-suspend-param = <0x0010000>; 160 entry-latency-us = <120>; 161 exit-latency-us = <250>; 162 min-residency-us = <900>; 163 }; 164 165 CLUSTER_SLEEP: cluster-sleep { 166 compatible = "arm,idle-state"; 167 local-timer-stop; 168 arm,psci-suspend-param = <0x1010000>; 169 entry-latency-us = <400>; 170 exit-latency-us = <500>; 171 min-residency-us = <2000>; 172 }; 173 }; 174 }; 175 176 display-subsystem { 177 compatible = "rockchip,display-subsystem"; 178 ports = <&vopl_out>, <&vopb_out>; 179 }; 180 181 pmu_a53 { 182 compatible = "arm,cortex-a53-pmu"; 183 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 184 }; 185 186 pmu_a72 { 187 compatible = "arm,cortex-a72-pmu"; 188 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 189 }; 190 191 psci { 192 compatible = "arm,psci-1.0"; 193 method = "smc"; 194 }; 195 196 timer { 197 compatible = "arm,armv8-timer"; 198 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 199 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 200 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 201 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 202 arm,no-tick-in-suspend; 203 }; 204 205 xin24m: xin24m { 206 compatible = "fixed-clock"; 207 clock-frequency = <24000000>; 208 clock-output-names = "xin24m"; 209 #clock-cells = <0>; 210 }; 211 212 pcie0: pcie@f8000000 { 213 compatible = "rockchip,rk3399-pcie"; 214 reg = <0x0 0xf8000000 0x0 0x2000000>, 215 <0x0 0xfd000000 0x0 0x1000000>; 216 reg-names = "axi-base", "apb-base"; 217 device_type = "pci"; 218 #address-cells = <3>; 219 #size-cells = <2>; 220 #interrupt-cells = <1>; 221 aspm-no-l0s; 222 bus-range = <0x0 0x1f>; 223 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 224 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 225 clock-names = "aclk", "aclk-perf", 226 "hclk", "pm"; 227 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 228 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 229 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 230 interrupt-names = "sys", "legacy", "client"; 231 interrupt-map-mask = <0 0 0 7>; 232 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 233 <0 0 0 2 &pcie0_intc 1>, 234 <0 0 0 3 &pcie0_intc 2>, 235 <0 0 0 4 &pcie0_intc 3>; 236 max-link-speed = <1>; 237 msi-map = <0x0 &its 0x0 0x1000>; 238 phys = <&pcie_phy 0>, <&pcie_phy 1>, 239 <&pcie_phy 2>, <&pcie_phy 3>; 240 phy-names = "pcie-phy-0", "pcie-phy-1", 241 "pcie-phy-2", "pcie-phy-3"; 242 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>, 243 <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 244 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 245 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 246 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 247 <&cru SRST_A_PCIE>; 248 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 249 "pm", "pclk", "aclk"; 250 status = "disabled"; 251 252 pcie0_intc: interrupt-controller { 253 interrupt-controller; 254 #address-cells = <0>; 255 #interrupt-cells = <1>; 256 }; 257 }; 258 259 gmac: ethernet@fe300000 { 260 compatible = "rockchip,rk3399-gmac"; 261 reg = <0x0 0xfe300000 0x0 0x10000>; 262 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 263 interrupt-names = "macirq"; 264 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 265 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 266 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 267 <&cru PCLK_GMAC>; 268 clock-names = "stmmaceth", "mac_clk_rx", 269 "mac_clk_tx", "clk_mac_ref", 270 "clk_mac_refout", "aclk_mac", 271 "pclk_mac"; 272 power-domains = <&power RK3399_PD_GMAC>; 273 resets = <&cru SRST_A_GMAC>; 274 reset-names = "stmmaceth"; 275 rockchip,grf = <&grf>; 276 snps,txpbl = <0x4>; 277 status = "disabled"; 278 }; 279 280 sdio0: mmc@fe310000 { 281 compatible = "rockchip,rk3399-dw-mshc", 282 "rockchip,rk3288-dw-mshc"; 283 reg = <0x0 0xfe310000 0x0 0x4000>; 284 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 285 max-frequency = <150000000>; 286 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 287 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 288 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 289 fifo-depth = <0x100>; 290 power-domains = <&power RK3399_PD_SDIOAUDIO>; 291 resets = <&cru SRST_SDIO0>; 292 reset-names = "reset"; 293 status = "disabled"; 294 }; 295 296 sdmmc: mmc@fe320000 { 297 compatible = "rockchip,rk3399-dw-mshc", 298 "rockchip,rk3288-dw-mshc"; 299 reg = <0x0 0xfe320000 0x0 0x4000>; 300 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 301 max-frequency = <150000000>; 302 assigned-clocks = <&cru HCLK_SD>; 303 assigned-clock-rates = <200000000>; 304 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 305 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 306 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 307 fifo-depth = <0x100>; 308 power-domains = <&power RK3399_PD_SD>; 309 resets = <&cru SRST_SDMMC>; 310 reset-names = "reset"; 311 status = "disabled"; 312 }; 313 314 sdhci: mmc@fe330000 { 315 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 316 reg = <0x0 0xfe330000 0x0 0x10000>; 317 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 318 arasan,soc-ctl-syscon = <&grf>; 319 assigned-clocks = <&cru SCLK_EMMC>; 320 assigned-clock-rates = <200000000>; 321 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 322 clock-names = "clk_xin", "clk_ahb"; 323 clock-output-names = "emmc_cardclock"; 324 #clock-cells = <0>; 325 phys = <&emmc_phy>; 326 phy-names = "phy_arasan"; 327 power-domains = <&power RK3399_PD_EMMC>; 328 disable-cqe-dcmd; 329 status = "disabled"; 330 }; 331 332 usb_host0_ehci: usb@fe380000 { 333 compatible = "generic-ehci"; 334 reg = <0x0 0xfe380000 0x0 0x20000>; 335 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 336 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 337 <&u2phy0>; 338 phys = <&u2phy0_host>; 339 phy-names = "usb"; 340 status = "disabled"; 341 }; 342 343 usb_host0_ohci: usb@fe3a0000 { 344 compatible = "generic-ohci"; 345 reg = <0x0 0xfe3a0000 0x0 0x20000>; 346 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 347 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 348 <&u2phy0>; 349 phys = <&u2phy0_host>; 350 phy-names = "usb"; 351 status = "disabled"; 352 }; 353 354 usb_host1_ehci: usb@fe3c0000 { 355 compatible = "generic-ehci"; 356 reg = <0x0 0xfe3c0000 0x0 0x20000>; 357 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 358 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 359 <&u2phy1>; 360 phys = <&u2phy1_host>; 361 phy-names = "usb"; 362 status = "disabled"; 363 }; 364 365 usb_host1_ohci: usb@fe3e0000 { 366 compatible = "generic-ohci"; 367 reg = <0x0 0xfe3e0000 0x0 0x20000>; 368 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 369 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 370 <&u2phy1>; 371 phys = <&u2phy1_host>; 372 phy-names = "usb"; 373 status = "disabled"; 374 }; 375 376 debug@fe430000 { 377 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 378 reg = <0 0xfe430000 0 0x1000>; 379 clocks = <&cru PCLK_COREDBG_L>; 380 clock-names = "apb_pclk"; 381 cpu = <&cpu_l0>; 382 }; 383 384 debug@fe432000 { 385 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 386 reg = <0 0xfe432000 0 0x1000>; 387 clocks = <&cru PCLK_COREDBG_L>; 388 clock-names = "apb_pclk"; 389 cpu = <&cpu_l1>; 390 }; 391 392 debug@fe434000 { 393 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 394 reg = <0 0xfe434000 0 0x1000>; 395 clocks = <&cru PCLK_COREDBG_L>; 396 clock-names = "apb_pclk"; 397 cpu = <&cpu_l2>; 398 }; 399 400 debug@fe436000 { 401 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 402 reg = <0 0xfe436000 0 0x1000>; 403 clocks = <&cru PCLK_COREDBG_L>; 404 clock-names = "apb_pclk"; 405 cpu = <&cpu_l3>; 406 }; 407 408 debug@fe610000 { 409 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 410 reg = <0 0xfe610000 0 0x1000>; 411 clocks = <&cru PCLK_COREDBG_B>; 412 clock-names = "apb_pclk"; 413 cpu = <&cpu_b0>; 414 }; 415 416 debug@fe710000 { 417 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 418 reg = <0 0xfe710000 0 0x1000>; 419 clocks = <&cru PCLK_COREDBG_B>; 420 clock-names = "apb_pclk"; 421 cpu = <&cpu_b1>; 422 }; 423 424 usbdrd3_0: usb@fe800000 { 425 compatible = "rockchip,rk3399-dwc3"; 426 #address-cells = <2>; 427 #size-cells = <2>; 428 ranges; 429 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 430 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 431 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 432 clock-names = "ref_clk", "suspend_clk", 433 "bus_clk", "aclk_usb3_rksoc_axi_perf", 434 "aclk_usb3", "grf_clk"; 435 resets = <&cru SRST_A_USB3_OTG0>; 436 reset-names = "usb3-otg"; 437 status = "disabled"; 438 439 usbdrd_dwc3_0: usb@fe800000 { 440 compatible = "snps,dwc3"; 441 reg = <0x0 0xfe800000 0x0 0x100000>; 442 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 443 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 444 <&cru SCLK_USB3OTG0_SUSPEND>; 445 clock-names = "ref", "bus_early", "suspend"; 446 dr_mode = "otg"; 447 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 448 phy-names = "usb2-phy", "usb3-phy"; 449 phy_type = "utmi_wide"; 450 snps,dis_enblslpm_quirk; 451 snps,dis-u2-freeclk-exists-quirk; 452 snps,dis_u2_susphy_quirk; 453 snps,dis-del-phy-power-chg-quirk; 454 snps,dis-tx-ipgap-linecheck-quirk; 455 power-domains = <&power RK3399_PD_USB3>; 456 status = "disabled"; 457 }; 458 }; 459 460 usbdrd3_1: usb@fe900000 { 461 compatible = "rockchip,rk3399-dwc3"; 462 #address-cells = <2>; 463 #size-cells = <2>; 464 ranges; 465 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 466 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 467 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 468 clock-names = "ref_clk", "suspend_clk", 469 "bus_clk", "aclk_usb3_rksoc_axi_perf", 470 "aclk_usb3", "grf_clk"; 471 resets = <&cru SRST_A_USB3_OTG1>; 472 reset-names = "usb3-otg"; 473 status = "disabled"; 474 475 usbdrd_dwc3_1: usb@fe900000 { 476 compatible = "snps,dwc3"; 477 reg = <0x0 0xfe900000 0x0 0x100000>; 478 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 479 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, 480 <&cru SCLK_USB3OTG1_SUSPEND>; 481 clock-names = "ref", "bus_early", "suspend"; 482 dr_mode = "otg"; 483 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 484 phy-names = "usb2-phy", "usb3-phy"; 485 phy_type = "utmi_wide"; 486 snps,dis_enblslpm_quirk; 487 snps,dis-u2-freeclk-exists-quirk; 488 snps,dis_u2_susphy_quirk; 489 snps,dis-del-phy-power-chg-quirk; 490 snps,dis-tx-ipgap-linecheck-quirk; 491 power-domains = <&power RK3399_PD_USB3>; 492 status = "disabled"; 493 }; 494 }; 495 496 cdn_dp: dp@fec00000 { 497 compatible = "rockchip,rk3399-cdn-dp"; 498 reg = <0x0 0xfec00000 0x0 0x100000>; 499 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 500 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 501 assigned-clock-rates = <100000000>, <200000000>; 502 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 503 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 504 clock-names = "core-clk", "pclk", "spdif", "grf"; 505 phys = <&tcphy0_dp>, <&tcphy1_dp>; 506 power-domains = <&power RK3399_PD_HDCP>; 507 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 508 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 509 reset-names = "spdif", "dptx", "apb", "core"; 510 rockchip,grf = <&grf>; 511 #sound-dai-cells = <1>; 512 status = "disabled"; 513 514 ports { 515 dp_in: port { 516 #address-cells = <1>; 517 #size-cells = <0>; 518 519 dp_in_vopb: endpoint@0 { 520 reg = <0>; 521 remote-endpoint = <&vopb_out_dp>; 522 }; 523 524 dp_in_vopl: endpoint@1 { 525 reg = <1>; 526 remote-endpoint = <&vopl_out_dp>; 527 }; 528 }; 529 }; 530 }; 531 532 gic: interrupt-controller@fee00000 { 533 compatible = "arm,gic-v3"; 534 #interrupt-cells = <4>; 535 #address-cells = <2>; 536 #size-cells = <2>; 537 ranges; 538 interrupt-controller; 539 540 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 541 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 542 <0x0 0xfff00000 0 0x10000>, /* GICC */ 543 <0x0 0xfff10000 0 0x10000>, /* GICH */ 544 <0x0 0xfff20000 0 0x10000>; /* GICV */ 545 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 546 its: interrupt-controller@fee20000 { 547 compatible = "arm,gic-v3-its"; 548 msi-controller; 549 #msi-cells = <1>; 550 reg = <0x0 0xfee20000 0x0 0x20000>; 551 }; 552 553 ppi-partitions { 554 ppi_cluster0: interrupt-partition-0 { 555 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 556 }; 557 558 ppi_cluster1: interrupt-partition-1 { 559 affinity = <&cpu_b0 &cpu_b1>; 560 }; 561 }; 562 }; 563 564 saradc: saradc@ff100000 { 565 compatible = "rockchip,rk3399-saradc"; 566 reg = <0x0 0xff100000 0x0 0x100>; 567 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 568 #io-channel-cells = <1>; 569 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 570 clock-names = "saradc", "apb_pclk"; 571 resets = <&cru SRST_P_SARADC>; 572 reset-names = "saradc-apb"; 573 status = "disabled"; 574 }; 575 576 i2c1: i2c@ff110000 { 577 compatible = "rockchip,rk3399-i2c"; 578 reg = <0x0 0xff110000 0x0 0x1000>; 579 assigned-clocks = <&cru SCLK_I2C1>; 580 assigned-clock-rates = <200000000>; 581 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 582 clock-names = "i2c", "pclk"; 583 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&i2c1_xfer>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 status = "disabled"; 589 }; 590 591 i2c2: i2c@ff120000 { 592 compatible = "rockchip,rk3399-i2c"; 593 reg = <0x0 0xff120000 0x0 0x1000>; 594 assigned-clocks = <&cru SCLK_I2C2>; 595 assigned-clock-rates = <200000000>; 596 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 597 clock-names = "i2c", "pclk"; 598 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 599 pinctrl-names = "default"; 600 pinctrl-0 = <&i2c2_xfer>; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 status = "disabled"; 604 }; 605 606 i2c3: i2c@ff130000 { 607 compatible = "rockchip,rk3399-i2c"; 608 reg = <0x0 0xff130000 0x0 0x1000>; 609 assigned-clocks = <&cru SCLK_I2C3>; 610 assigned-clock-rates = <200000000>; 611 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 612 clock-names = "i2c", "pclk"; 613 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 614 pinctrl-names = "default"; 615 pinctrl-0 = <&i2c3_xfer>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 status = "disabled"; 619 }; 620 621 i2c5: i2c@ff140000 { 622 compatible = "rockchip,rk3399-i2c"; 623 reg = <0x0 0xff140000 0x0 0x1000>; 624 assigned-clocks = <&cru SCLK_I2C5>; 625 assigned-clock-rates = <200000000>; 626 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 627 clock-names = "i2c", "pclk"; 628 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 629 pinctrl-names = "default"; 630 pinctrl-0 = <&i2c5_xfer>; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 status = "disabled"; 634 }; 635 636 i2c6: i2c@ff150000 { 637 compatible = "rockchip,rk3399-i2c"; 638 reg = <0x0 0xff150000 0x0 0x1000>; 639 assigned-clocks = <&cru SCLK_I2C6>; 640 assigned-clock-rates = <200000000>; 641 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 642 clock-names = "i2c", "pclk"; 643 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&i2c6_xfer>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 status = "disabled"; 649 }; 650 651 i2c7: i2c@ff160000 { 652 compatible = "rockchip,rk3399-i2c"; 653 reg = <0x0 0xff160000 0x0 0x1000>; 654 assigned-clocks = <&cru SCLK_I2C7>; 655 assigned-clock-rates = <200000000>; 656 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 657 clock-names = "i2c", "pclk"; 658 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&i2c7_xfer>; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 status = "disabled"; 664 }; 665 666 uart0: serial@ff180000 { 667 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 668 reg = <0x0 0xff180000 0x0 0x100>; 669 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 670 clock-names = "baudclk", "apb_pclk"; 671 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 672 reg-shift = <2>; 673 reg-io-width = <4>; 674 pinctrl-names = "default"; 675 pinctrl-0 = <&uart0_xfer>; 676 status = "disabled"; 677 }; 678 679 uart1: serial@ff190000 { 680 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 681 reg = <0x0 0xff190000 0x0 0x100>; 682 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 683 clock-names = "baudclk", "apb_pclk"; 684 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 685 reg-shift = <2>; 686 reg-io-width = <4>; 687 pinctrl-names = "default"; 688 pinctrl-0 = <&uart1_xfer>; 689 status = "disabled"; 690 }; 691 692 uart2: serial@ff1a0000 { 693 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 694 reg = <0x0 0xff1a0000 0x0 0x100>; 695 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 696 clock-names = "baudclk", "apb_pclk"; 697 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 698 reg-shift = <2>; 699 reg-io-width = <4>; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&uart2c_xfer>; 702 status = "disabled"; 703 }; 704 705 uart3: serial@ff1b0000 { 706 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 707 reg = <0x0 0xff1b0000 0x0 0x100>; 708 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 709 clock-names = "baudclk", "apb_pclk"; 710 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 711 reg-shift = <2>; 712 reg-io-width = <4>; 713 pinctrl-names = "default"; 714 pinctrl-0 = <&uart3_xfer>; 715 status = "disabled"; 716 }; 717 718 spi0: spi@ff1c0000 { 719 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 720 reg = <0x0 0xff1c0000 0x0 0x1000>; 721 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 722 clock-names = "spiclk", "apb_pclk"; 723 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 724 dmas = <&dmac_peri 10>, <&dmac_peri 11>; 725 dma-names = "tx", "rx"; 726 pinctrl-names = "default"; 727 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 728 #address-cells = <1>; 729 #size-cells = <0>; 730 status = "disabled"; 731 }; 732 733 spi1: spi@ff1d0000 { 734 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 735 reg = <0x0 0xff1d0000 0x0 0x1000>; 736 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 737 clock-names = "spiclk", "apb_pclk"; 738 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 739 dmas = <&dmac_peri 12>, <&dmac_peri 13>; 740 dma-names = "tx", "rx"; 741 pinctrl-names = "default"; 742 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 status = "disabled"; 746 }; 747 748 spi2: spi@ff1e0000 { 749 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 750 reg = <0x0 0xff1e0000 0x0 0x1000>; 751 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 752 clock-names = "spiclk", "apb_pclk"; 753 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 754 dmas = <&dmac_peri 14>, <&dmac_peri 15>; 755 dma-names = "tx", "rx"; 756 pinctrl-names = "default"; 757 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 status = "disabled"; 761 }; 762 763 spi4: spi@ff1f0000 { 764 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 765 reg = <0x0 0xff1f0000 0x0 0x1000>; 766 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 767 clock-names = "spiclk", "apb_pclk"; 768 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 769 dmas = <&dmac_peri 18>, <&dmac_peri 19>; 770 dma-names = "tx", "rx"; 771 pinctrl-names = "default"; 772 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 status = "disabled"; 776 }; 777 778 spi5: spi@ff200000 { 779 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 780 reg = <0x0 0xff200000 0x0 0x1000>; 781 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 782 clock-names = "spiclk", "apb_pclk"; 783 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 784 dmas = <&dmac_bus 8>, <&dmac_bus 9>; 785 dma-names = "tx", "rx"; 786 pinctrl-names = "default"; 787 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 788 power-domains = <&power RK3399_PD_SDIOAUDIO>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 status = "disabled"; 792 }; 793 794 thermal_zones: thermal-zones { 795 cpu_thermal: cpu-thermal { 796 polling-delay-passive = <100>; 797 polling-delay = <1000>; 798 799 thermal-sensors = <&tsadc 0>; 800 801 trips { 802 cpu_alert0: cpu_alert0 { 803 temperature = <70000>; 804 hysteresis = <2000>; 805 type = "passive"; 806 }; 807 cpu_alert1: cpu_alert1 { 808 temperature = <75000>; 809 hysteresis = <2000>; 810 type = "passive"; 811 }; 812 cpu_crit: cpu_crit { 813 temperature = <95000>; 814 hysteresis = <2000>; 815 type = "critical"; 816 }; 817 }; 818 819 cooling-maps { 820 map0 { 821 trip = <&cpu_alert0>; 822 cooling-device = 823 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 824 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 825 }; 826 map1 { 827 trip = <&cpu_alert1>; 828 cooling-device = 829 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 830 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 831 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 832 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 833 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 834 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 835 }; 836 }; 837 }; 838 839 gpu_thermal: gpu-thermal { 840 polling-delay-passive = <100>; 841 polling-delay = <1000>; 842 843 thermal-sensors = <&tsadc 1>; 844 845 trips { 846 gpu_alert0: gpu_alert0 { 847 temperature = <75000>; 848 hysteresis = <2000>; 849 type = "passive"; 850 }; 851 gpu_crit: gpu_crit { 852 temperature = <95000>; 853 hysteresis = <2000>; 854 type = "critical"; 855 }; 856 }; 857 858 cooling-maps { 859 map0 { 860 trip = <&gpu_alert0>; 861 cooling-device = 862 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 863 }; 864 }; 865 }; 866 }; 867 868 tsadc: tsadc@ff260000 { 869 compatible = "rockchip,rk3399-tsadc"; 870 reg = <0x0 0xff260000 0x0 0x100>; 871 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 872 assigned-clocks = <&cru SCLK_TSADC>; 873 assigned-clock-rates = <750000>; 874 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 875 clock-names = "tsadc", "apb_pclk"; 876 resets = <&cru SRST_TSADC>; 877 reset-names = "tsadc-apb"; 878 rockchip,grf = <&grf>; 879 rockchip,hw-tshut-temp = <95000>; 880 pinctrl-names = "init", "default", "sleep"; 881 pinctrl-0 = <&otp_pin>; 882 pinctrl-1 = <&otp_out>; 883 pinctrl-2 = <&otp_pin>; 884 #thermal-sensor-cells = <1>; 885 status = "disabled"; 886 }; 887 888 qos_emmc: qos@ffa58000 { 889 compatible = "rockchip,rk3399-qos", "syscon"; 890 reg = <0x0 0xffa58000 0x0 0x20>; 891 }; 892 893 qos_gmac: qos@ffa5c000 { 894 compatible = "rockchip,rk3399-qos", "syscon"; 895 reg = <0x0 0xffa5c000 0x0 0x20>; 896 }; 897 898 qos_pcie: qos@ffa60080 { 899 compatible = "rockchip,rk3399-qos", "syscon"; 900 reg = <0x0 0xffa60080 0x0 0x20>; 901 }; 902 903 qos_usb_host0: qos@ffa60100 { 904 compatible = "rockchip,rk3399-qos", "syscon"; 905 reg = <0x0 0xffa60100 0x0 0x20>; 906 }; 907 908 qos_usb_host1: qos@ffa60180 { 909 compatible = "rockchip,rk3399-qos", "syscon"; 910 reg = <0x0 0xffa60180 0x0 0x20>; 911 }; 912 913 qos_usb_otg0: qos@ffa70000 { 914 compatible = "rockchip,rk3399-qos", "syscon"; 915 reg = <0x0 0xffa70000 0x0 0x20>; 916 }; 917 918 qos_usb_otg1: qos@ffa70080 { 919 compatible = "rockchip,rk3399-qos", "syscon"; 920 reg = <0x0 0xffa70080 0x0 0x20>; 921 }; 922 923 qos_sd: qos@ffa74000 { 924 compatible = "rockchip,rk3399-qos", "syscon"; 925 reg = <0x0 0xffa74000 0x0 0x20>; 926 }; 927 928 qos_sdioaudio: qos@ffa76000 { 929 compatible = "rockchip,rk3399-qos", "syscon"; 930 reg = <0x0 0xffa76000 0x0 0x20>; 931 }; 932 933 qos_hdcp: qos@ffa90000 { 934 compatible = "rockchip,rk3399-qos", "syscon"; 935 reg = <0x0 0xffa90000 0x0 0x20>; 936 }; 937 938 qos_iep: qos@ffa98000 { 939 compatible = "rockchip,rk3399-qos", "syscon"; 940 reg = <0x0 0xffa98000 0x0 0x20>; 941 }; 942 943 qos_isp0_m0: qos@ffaa0000 { 944 compatible = "rockchip,rk3399-qos", "syscon"; 945 reg = <0x0 0xffaa0000 0x0 0x20>; 946 }; 947 948 qos_isp0_m1: qos@ffaa0080 { 949 compatible = "rockchip,rk3399-qos", "syscon"; 950 reg = <0x0 0xffaa0080 0x0 0x20>; 951 }; 952 953 qos_isp1_m0: qos@ffaa8000 { 954 compatible = "rockchip,rk3399-qos", "syscon"; 955 reg = <0x0 0xffaa8000 0x0 0x20>; 956 }; 957 958 qos_isp1_m1: qos@ffaa8080 { 959 compatible = "rockchip,rk3399-qos", "syscon"; 960 reg = <0x0 0xffaa8080 0x0 0x20>; 961 }; 962 963 qos_rga_r: qos@ffab0000 { 964 compatible = "rockchip,rk3399-qos", "syscon"; 965 reg = <0x0 0xffab0000 0x0 0x20>; 966 }; 967 968 qos_rga_w: qos@ffab0080 { 969 compatible = "rockchip,rk3399-qos", "syscon"; 970 reg = <0x0 0xffab0080 0x0 0x20>; 971 }; 972 973 qos_video_m0: qos@ffab8000 { 974 compatible = "rockchip,rk3399-qos", "syscon"; 975 reg = <0x0 0xffab8000 0x0 0x20>; 976 }; 977 978 qos_video_m1_r: qos@ffac0000 { 979 compatible = "rockchip,rk3399-qos", "syscon"; 980 reg = <0x0 0xffac0000 0x0 0x20>; 981 }; 982 983 qos_video_m1_w: qos@ffac0080 { 984 compatible = "rockchip,rk3399-qos", "syscon"; 985 reg = <0x0 0xffac0080 0x0 0x20>; 986 }; 987 988 qos_vop_big_r: qos@ffac8000 { 989 compatible = "rockchip,rk3399-qos", "syscon"; 990 reg = <0x0 0xffac8000 0x0 0x20>; 991 }; 992 993 qos_vop_big_w: qos@ffac8080 { 994 compatible = "rockchip,rk3399-qos", "syscon"; 995 reg = <0x0 0xffac8080 0x0 0x20>; 996 }; 997 998 qos_vop_little: qos@ffad0000 { 999 compatible = "rockchip,rk3399-qos", "syscon"; 1000 reg = <0x0 0xffad0000 0x0 0x20>; 1001 }; 1002 1003 qos_perihp: qos@ffad8080 { 1004 compatible = "rockchip,rk3399-qos", "syscon"; 1005 reg = <0x0 0xffad8080 0x0 0x20>; 1006 }; 1007 1008 qos_gpu: qos@ffae0000 { 1009 compatible = "rockchip,rk3399-qos", "syscon"; 1010 reg = <0x0 0xffae0000 0x0 0x20>; 1011 }; 1012 1013 pmu: power-management@ff310000 { 1014 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 1015 reg = <0x0 0xff310000 0x0 0x1000>; 1016 1017 /* 1018 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 1019 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 1020 * Some of the power domains are grouped together for every 1021 * voltage domain. 1022 * The detail contents as below. 1023 */ 1024 power: power-controller { 1025 compatible = "rockchip,rk3399-power-controller"; 1026 #power-domain-cells = <1>; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 1030 /* These power domains are grouped by VD_CENTER */ 1031 power-domain@RK3399_PD_IEP { 1032 reg = <RK3399_PD_IEP>; 1033 clocks = <&cru ACLK_IEP>, 1034 <&cru HCLK_IEP>; 1035 pm_qos = <&qos_iep>; 1036 #power-domain-cells = <0>; 1037 }; 1038 power-domain@RK3399_PD_RGA { 1039 reg = <RK3399_PD_RGA>; 1040 clocks = <&cru ACLK_RGA>, 1041 <&cru HCLK_RGA>; 1042 pm_qos = <&qos_rga_r>, 1043 <&qos_rga_w>; 1044 #power-domain-cells = <0>; 1045 }; 1046 power-domain@RK3399_PD_VCODEC { 1047 reg = <RK3399_PD_VCODEC>; 1048 clocks = <&cru ACLK_VCODEC>, 1049 <&cru HCLK_VCODEC>; 1050 pm_qos = <&qos_video_m0>; 1051 #power-domain-cells = <0>; 1052 }; 1053 power-domain@RK3399_PD_VDU { 1054 reg = <RK3399_PD_VDU>; 1055 clocks = <&cru ACLK_VDU>, 1056 <&cru HCLK_VDU>; 1057 pm_qos = <&qos_video_m1_r>, 1058 <&qos_video_m1_w>; 1059 #power-domain-cells = <0>; 1060 }; 1061 1062 /* These power domains are grouped by VD_GPU */ 1063 power-domain@RK3399_PD_GPU { 1064 reg = <RK3399_PD_GPU>; 1065 clocks = <&cru ACLK_GPU>; 1066 pm_qos = <&qos_gpu>; 1067 #power-domain-cells = <0>; 1068 }; 1069 1070 /* These power domains are grouped by VD_LOGIC */ 1071 power-domain@RK3399_PD_EDP { 1072 reg = <RK3399_PD_EDP>; 1073 clocks = <&cru PCLK_EDP_CTRL>; 1074 #power-domain-cells = <0>; 1075 }; 1076 power-domain@RK3399_PD_EMMC { 1077 reg = <RK3399_PD_EMMC>; 1078 clocks = <&cru ACLK_EMMC>; 1079 pm_qos = <&qos_emmc>; 1080 #power-domain-cells = <0>; 1081 }; 1082 power-domain@RK3399_PD_GMAC { 1083 reg = <RK3399_PD_GMAC>; 1084 clocks = <&cru ACLK_GMAC>, 1085 <&cru PCLK_GMAC>; 1086 pm_qos = <&qos_gmac>; 1087 #power-domain-cells = <0>; 1088 }; 1089 power-domain@RK3399_PD_SD { 1090 reg = <RK3399_PD_SD>; 1091 clocks = <&cru HCLK_SDMMC>, 1092 <&cru SCLK_SDMMC>; 1093 pm_qos = <&qos_sd>; 1094 #power-domain-cells = <0>; 1095 }; 1096 power-domain@RK3399_PD_SDIOAUDIO { 1097 reg = <RK3399_PD_SDIOAUDIO>; 1098 clocks = <&cru HCLK_SDIO>; 1099 pm_qos = <&qos_sdioaudio>; 1100 #power-domain-cells = <0>; 1101 }; 1102 power-domain@RK3399_PD_TCPD0 { 1103 reg = <RK3399_PD_TCPD0>; 1104 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1105 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1106 #power-domain-cells = <0>; 1107 }; 1108 power-domain@RK3399_PD_TCPD1 { 1109 reg = <RK3399_PD_TCPD1>; 1110 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1111 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1112 #power-domain-cells = <0>; 1113 }; 1114 power-domain@RK3399_PD_USB3 { 1115 reg = <RK3399_PD_USB3>; 1116 clocks = <&cru ACLK_USB3>; 1117 pm_qos = <&qos_usb_otg0>, 1118 <&qos_usb_otg1>; 1119 #power-domain-cells = <0>; 1120 }; 1121 power-domain@RK3399_PD_VIO { 1122 reg = <RK3399_PD_VIO>; 1123 #power-domain-cells = <1>; 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 1127 power-domain@RK3399_PD_HDCP { 1128 reg = <RK3399_PD_HDCP>; 1129 clocks = <&cru ACLK_HDCP>, 1130 <&cru HCLK_HDCP>, 1131 <&cru PCLK_HDCP>; 1132 pm_qos = <&qos_hdcp>; 1133 #power-domain-cells = <0>; 1134 }; 1135 power-domain@RK3399_PD_ISP0 { 1136 reg = <RK3399_PD_ISP0>; 1137 clocks = <&cru ACLK_ISP0>, 1138 <&cru HCLK_ISP0>; 1139 pm_qos = <&qos_isp0_m0>, 1140 <&qos_isp0_m1>; 1141 #power-domain-cells = <0>; 1142 }; 1143 power-domain@RK3399_PD_ISP1 { 1144 reg = <RK3399_PD_ISP1>; 1145 clocks = <&cru ACLK_ISP1>, 1146 <&cru HCLK_ISP1>; 1147 pm_qos = <&qos_isp1_m0>, 1148 <&qos_isp1_m1>; 1149 #power-domain-cells = <0>; 1150 }; 1151 power-domain@RK3399_PD_VO { 1152 reg = <RK3399_PD_VO>; 1153 #power-domain-cells = <1>; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 1157 power-domain@RK3399_PD_VOPB { 1158 reg = <RK3399_PD_VOPB>; 1159 clocks = <&cru ACLK_VOP0>, 1160 <&cru HCLK_VOP0>; 1161 pm_qos = <&qos_vop_big_r>, 1162 <&qos_vop_big_w>; 1163 #power-domain-cells = <0>; 1164 }; 1165 power-domain@RK3399_PD_VOPL { 1166 reg = <RK3399_PD_VOPL>; 1167 clocks = <&cru ACLK_VOP1>, 1168 <&cru HCLK_VOP1>; 1169 pm_qos = <&qos_vop_little>; 1170 #power-domain-cells = <0>; 1171 }; 1172 }; 1173 }; 1174 }; 1175 }; 1176 1177 pmugrf: syscon@ff320000 { 1178 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1179 reg = <0x0 0xff320000 0x0 0x1000>; 1180 1181 pmu_io_domains: io-domains { 1182 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1183 status = "disabled"; 1184 }; 1185 }; 1186 1187 spi3: spi@ff350000 { 1188 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1189 reg = <0x0 0xff350000 0x0 0x1000>; 1190 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1191 clock-names = "spiclk", "apb_pclk"; 1192 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 status = "disabled"; 1198 }; 1199 1200 uart4: serial@ff370000 { 1201 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1202 reg = <0x0 0xff370000 0x0 0x100>; 1203 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1204 clock-names = "baudclk", "apb_pclk"; 1205 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1206 reg-shift = <2>; 1207 reg-io-width = <4>; 1208 pinctrl-names = "default"; 1209 pinctrl-0 = <&uart4_xfer>; 1210 status = "disabled"; 1211 }; 1212 1213 i2c0: i2c@ff3c0000 { 1214 compatible = "rockchip,rk3399-i2c"; 1215 reg = <0x0 0xff3c0000 0x0 0x1000>; 1216 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1217 assigned-clock-rates = <200000000>; 1218 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1219 clock-names = "i2c", "pclk"; 1220 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1221 pinctrl-names = "default"; 1222 pinctrl-0 = <&i2c0_xfer>; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 status = "disabled"; 1226 }; 1227 1228 i2c4: i2c@ff3d0000 { 1229 compatible = "rockchip,rk3399-i2c"; 1230 reg = <0x0 0xff3d0000 0x0 0x1000>; 1231 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1232 assigned-clock-rates = <200000000>; 1233 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1234 clock-names = "i2c", "pclk"; 1235 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1236 pinctrl-names = "default"; 1237 pinctrl-0 = <&i2c4_xfer>; 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 status = "disabled"; 1241 }; 1242 1243 i2c8: i2c@ff3e0000 { 1244 compatible = "rockchip,rk3399-i2c"; 1245 reg = <0x0 0xff3e0000 0x0 0x1000>; 1246 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1247 assigned-clock-rates = <200000000>; 1248 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1249 clock-names = "i2c", "pclk"; 1250 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&i2c8_xfer>; 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 status = "disabled"; 1256 }; 1257 1258 pwm0: pwm@ff420000 { 1259 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1260 reg = <0x0 0xff420000 0x0 0x10>; 1261 #pwm-cells = <3>; 1262 pinctrl-names = "default"; 1263 pinctrl-0 = <&pwm0_pin>; 1264 clocks = <&pmucru PCLK_RKPWM_PMU>; 1265 status = "disabled"; 1266 }; 1267 1268 pwm1: pwm@ff420010 { 1269 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1270 reg = <0x0 0xff420010 0x0 0x10>; 1271 #pwm-cells = <3>; 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&pwm1_pin>; 1274 clocks = <&pmucru PCLK_RKPWM_PMU>; 1275 status = "disabled"; 1276 }; 1277 1278 pwm2: pwm@ff420020 { 1279 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1280 reg = <0x0 0xff420020 0x0 0x10>; 1281 #pwm-cells = <3>; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&pwm2_pin>; 1284 clocks = <&pmucru PCLK_RKPWM_PMU>; 1285 status = "disabled"; 1286 }; 1287 1288 pwm3: pwm@ff420030 { 1289 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1290 reg = <0x0 0xff420030 0x0 0x10>; 1291 #pwm-cells = <3>; 1292 pinctrl-names = "default"; 1293 pinctrl-0 = <&pwm3a_pin>; 1294 clocks = <&pmucru PCLK_RKPWM_PMU>; 1295 status = "disabled"; 1296 }; 1297 1298 vpu: video-codec@ff650000 { 1299 compatible = "rockchip,rk3399-vpu"; 1300 reg = <0x0 0xff650000 0x0 0x800>; 1301 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1302 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1303 interrupt-names = "vepu", "vdpu"; 1304 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1305 clock-names = "aclk", "hclk"; 1306 iommus = <&vpu_mmu>; 1307 power-domains = <&power RK3399_PD_VCODEC>; 1308 }; 1309 1310 vpu_mmu: iommu@ff650800 { 1311 compatible = "rockchip,iommu"; 1312 reg = <0x0 0xff650800 0x0 0x40>; 1313 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1314 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1315 clock-names = "aclk", "iface"; 1316 #iommu-cells = <0>; 1317 power-domains = <&power RK3399_PD_VCODEC>; 1318 }; 1319 1320 vdec: video-codec@ff660000 { 1321 compatible = "rockchip,rk3399-vdec"; 1322 reg = <0x0 0xff660000 0x0 0x400>; 1323 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1324 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, 1325 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; 1326 clock-names = "axi", "ahb", "cabac", "core"; 1327 iommus = <&vdec_mmu>; 1328 power-domains = <&power RK3399_PD_VDU>; 1329 }; 1330 1331 vdec_mmu: iommu@ff660480 { 1332 compatible = "rockchip,iommu"; 1333 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1334 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1335 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1336 clock-names = "aclk", "iface"; 1337 power-domains = <&power RK3399_PD_VDU>; 1338 #iommu-cells = <0>; 1339 }; 1340 1341 iep_mmu: iommu@ff670800 { 1342 compatible = "rockchip,iommu"; 1343 reg = <0x0 0xff670800 0x0 0x40>; 1344 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1345 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1346 clock-names = "aclk", "iface"; 1347 #iommu-cells = <0>; 1348 status = "disabled"; 1349 }; 1350 1351 rga: rga@ff680000 { 1352 compatible = "rockchip,rk3399-rga"; 1353 reg = <0x0 0xff680000 0x0 0x10000>; 1354 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1355 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1356 clock-names = "aclk", "hclk", "sclk"; 1357 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1358 reset-names = "core", "axi", "ahb"; 1359 power-domains = <&power RK3399_PD_RGA>; 1360 }; 1361 1362 efuse0: efuse@ff690000 { 1363 compatible = "rockchip,rk3399-efuse"; 1364 reg = <0x0 0xff690000 0x0 0x80>; 1365 #address-cells = <1>; 1366 #size-cells = <1>; 1367 clocks = <&cru PCLK_EFUSE1024NS>; 1368 clock-names = "pclk_efuse"; 1369 1370 /* Data cells */ 1371 cpu_id: cpu-id@7 { 1372 reg = <0x07 0x10>; 1373 }; 1374 cpub_leakage: cpu-leakage@17 { 1375 reg = <0x17 0x1>; 1376 }; 1377 gpu_leakage: gpu-leakage@18 { 1378 reg = <0x18 0x1>; 1379 }; 1380 center_leakage: center-leakage@19 { 1381 reg = <0x19 0x1>; 1382 }; 1383 cpul_leakage: cpu-leakage@1a { 1384 reg = <0x1a 0x1>; 1385 }; 1386 logic_leakage: logic-leakage@1b { 1387 reg = <0x1b 0x1>; 1388 }; 1389 wafer_info: wafer-info@1c { 1390 reg = <0x1c 0x1>; 1391 }; 1392 }; 1393 1394 dmac_bus: dma-controller@ff6d0000 { 1395 compatible = "arm,pl330", "arm,primecell"; 1396 reg = <0x0 0xff6d0000 0x0 0x4000>; 1397 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 1398 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 1399 #dma-cells = <1>; 1400 arm,pl330-periph-burst; 1401 clocks = <&cru ACLK_DMAC0_PERILP>; 1402 clock-names = "apb_pclk"; 1403 }; 1404 1405 dmac_peri: dma-controller@ff6e0000 { 1406 compatible = "arm,pl330", "arm,primecell"; 1407 reg = <0x0 0xff6e0000 0x0 0x4000>; 1408 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 1409 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 1410 #dma-cells = <1>; 1411 arm,pl330-periph-burst; 1412 clocks = <&cru ACLK_DMAC1_PERILP>; 1413 clock-names = "apb_pclk"; 1414 }; 1415 1416 pmucru: pmu-clock-controller@ff750000 { 1417 compatible = "rockchip,rk3399-pmucru"; 1418 reg = <0x0 0xff750000 0x0 0x1000>; 1419 rockchip,grf = <&pmugrf>; 1420 #clock-cells = <1>; 1421 #reset-cells = <1>; 1422 assigned-clocks = <&pmucru PLL_PPLL>; 1423 assigned-clock-rates = <676000000>; 1424 }; 1425 1426 cru: clock-controller@ff760000 { 1427 compatible = "rockchip,rk3399-cru"; 1428 reg = <0x0 0xff760000 0x0 0x1000>; 1429 rockchip,grf = <&grf>; 1430 #clock-cells = <1>; 1431 #reset-cells = <1>; 1432 assigned-clocks = 1433 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1434 <&cru PLL_NPLL>, 1435 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1436 <&cru PCLK_PERIHP>, 1437 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1438 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1439 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1440 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1441 <&cru ACLK_GIC_PRE>, 1442 <&cru PCLK_DDR>; 1443 assigned-clock-rates = 1444 <594000000>, <800000000>, 1445 <1000000000>, 1446 <150000000>, <75000000>, 1447 <37500000>, 1448 <100000000>, <100000000>, 1449 <50000000>, <600000000>, 1450 <100000000>, <50000000>, 1451 <400000000>, <400000000>, 1452 <200000000>, 1453 <200000000>; 1454 }; 1455 1456 grf: syscon@ff770000 { 1457 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1458 reg = <0x0 0xff770000 0x0 0x10000>; 1459 #address-cells = <1>; 1460 #size-cells = <1>; 1461 1462 io_domains: io-domains { 1463 compatible = "rockchip,rk3399-io-voltage-domain"; 1464 status = "disabled"; 1465 }; 1466 1467 mipi_dphy_rx0: mipi-dphy-rx0 { 1468 compatible = "rockchip,rk3399-mipi-dphy-rx0"; 1469 clocks = <&cru SCLK_MIPIDPHY_REF>, 1470 <&cru SCLK_DPHY_RX0_CFG>, 1471 <&cru PCLK_VIO_GRF>; 1472 clock-names = "dphy-ref", "dphy-cfg", "grf"; 1473 power-domains = <&power RK3399_PD_VIO>; 1474 #phy-cells = <0>; 1475 status = "disabled"; 1476 }; 1477 1478 u2phy0: usb2phy@e450 { 1479 compatible = "rockchip,rk3399-usb2phy"; 1480 reg = <0xe450 0x10>; 1481 clocks = <&cru SCLK_USB2PHY0_REF>; 1482 clock-names = "phyclk"; 1483 #clock-cells = <0>; 1484 clock-output-names = "clk_usbphy0_480m"; 1485 status = "disabled"; 1486 1487 u2phy0_host: host-port { 1488 #phy-cells = <0>; 1489 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1490 interrupt-names = "linestate"; 1491 status = "disabled"; 1492 }; 1493 1494 u2phy0_otg: otg-port { 1495 #phy-cells = <0>; 1496 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1497 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1498 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1499 interrupt-names = "otg-bvalid", "otg-id", 1500 "linestate"; 1501 status = "disabled"; 1502 }; 1503 }; 1504 1505 u2phy1: usb2phy@e460 { 1506 compatible = "rockchip,rk3399-usb2phy"; 1507 reg = <0xe460 0x10>; 1508 clocks = <&cru SCLK_USB2PHY1_REF>; 1509 clock-names = "phyclk"; 1510 #clock-cells = <0>; 1511 clock-output-names = "clk_usbphy1_480m"; 1512 status = "disabled"; 1513 1514 u2phy1_host: host-port { 1515 #phy-cells = <0>; 1516 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1517 interrupt-names = "linestate"; 1518 status = "disabled"; 1519 }; 1520 1521 u2phy1_otg: otg-port { 1522 #phy-cells = <0>; 1523 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1524 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1525 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1526 interrupt-names = "otg-bvalid", "otg-id", 1527 "linestate"; 1528 status = "disabled"; 1529 }; 1530 }; 1531 1532 emmc_phy: phy@f780 { 1533 compatible = "rockchip,rk3399-emmc-phy"; 1534 reg = <0xf780 0x24>; 1535 clocks = <&sdhci>; 1536 clock-names = "emmcclk"; 1537 #phy-cells = <0>; 1538 status = "disabled"; 1539 }; 1540 1541 pcie_phy: pcie-phy { 1542 compatible = "rockchip,rk3399-pcie-phy"; 1543 clocks = <&cru SCLK_PCIEPHY_REF>; 1544 clock-names = "refclk"; 1545 #phy-cells = <1>; 1546 resets = <&cru SRST_PCIEPHY>; 1547 drive-impedance-ohm = <50>; 1548 reset-names = "phy"; 1549 status = "disabled"; 1550 }; 1551 }; 1552 1553 tcphy0: phy@ff7c0000 { 1554 compatible = "rockchip,rk3399-typec-phy"; 1555 reg = <0x0 0xff7c0000 0x0 0x40000>; 1556 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1557 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1558 clock-names = "tcpdcore", "tcpdphy-ref"; 1559 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1560 assigned-clock-rates = <50000000>; 1561 power-domains = <&power RK3399_PD_TCPD0>; 1562 resets = <&cru SRST_UPHY0>, 1563 <&cru SRST_UPHY0_PIPE_L00>, 1564 <&cru SRST_P_UPHY0_TCPHY>; 1565 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1566 rockchip,grf = <&grf>; 1567 status = "disabled"; 1568 1569 tcphy0_dp: dp-port { 1570 #phy-cells = <0>; 1571 }; 1572 1573 tcphy0_usb3: usb3-port { 1574 #phy-cells = <0>; 1575 }; 1576 }; 1577 1578 tcphy1: phy@ff800000 { 1579 compatible = "rockchip,rk3399-typec-phy"; 1580 reg = <0x0 0xff800000 0x0 0x40000>; 1581 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1582 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1583 clock-names = "tcpdcore", "tcpdphy-ref"; 1584 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1585 assigned-clock-rates = <50000000>; 1586 power-domains = <&power RK3399_PD_TCPD1>; 1587 resets = <&cru SRST_UPHY1>, 1588 <&cru SRST_UPHY1_PIPE_L00>, 1589 <&cru SRST_P_UPHY1_TCPHY>; 1590 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1591 rockchip,grf = <&grf>; 1592 status = "disabled"; 1593 1594 tcphy1_dp: dp-port { 1595 #phy-cells = <0>; 1596 }; 1597 1598 tcphy1_usb3: usb3-port { 1599 #phy-cells = <0>; 1600 }; 1601 }; 1602 1603 watchdog@ff848000 { 1604 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt"; 1605 reg = <0x0 0xff848000 0x0 0x100>; 1606 clocks = <&cru PCLK_WDT>; 1607 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1608 }; 1609 1610 rktimer: rktimer@ff850000 { 1611 compatible = "rockchip,rk3399-timer"; 1612 reg = <0x0 0xff850000 0x0 0x1000>; 1613 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1614 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1615 clock-names = "pclk", "timer"; 1616 }; 1617 1618 spdif: spdif@ff870000 { 1619 compatible = "rockchip,rk3399-spdif"; 1620 reg = <0x0 0xff870000 0x0 0x1000>; 1621 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1622 dmas = <&dmac_bus 7>; 1623 dma-names = "tx"; 1624 clock-names = "mclk", "hclk"; 1625 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1626 pinctrl-names = "default"; 1627 pinctrl-0 = <&spdif_bus>; 1628 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1629 #sound-dai-cells = <0>; 1630 status = "disabled"; 1631 }; 1632 1633 i2s0: i2s@ff880000 { 1634 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1635 reg = <0x0 0xff880000 0x0 0x1000>; 1636 rockchip,grf = <&grf>; 1637 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1638 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1639 dma-names = "tx", "rx"; 1640 clock-names = "i2s_clk", "i2s_hclk"; 1641 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1642 pinctrl-names = "default"; 1643 pinctrl-0 = <&i2s0_8ch_bus>; 1644 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1645 #sound-dai-cells = <0>; 1646 status = "disabled"; 1647 }; 1648 1649 i2s1: i2s@ff890000 { 1650 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1651 reg = <0x0 0xff890000 0x0 0x1000>; 1652 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1653 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1654 dma-names = "tx", "rx"; 1655 clock-names = "i2s_clk", "i2s_hclk"; 1656 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1657 pinctrl-names = "default"; 1658 pinctrl-0 = <&i2s1_2ch_bus>; 1659 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1660 #sound-dai-cells = <0>; 1661 status = "disabled"; 1662 }; 1663 1664 i2s2: i2s@ff8a0000 { 1665 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1666 reg = <0x0 0xff8a0000 0x0 0x1000>; 1667 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1668 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1669 dma-names = "tx", "rx"; 1670 clock-names = "i2s_clk", "i2s_hclk"; 1671 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1672 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1673 #sound-dai-cells = <0>; 1674 status = "disabled"; 1675 }; 1676 1677 vopl: vop@ff8f0000 { 1678 compatible = "rockchip,rk3399-vop-lit"; 1679 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1680 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1681 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1682 assigned-clock-rates = <400000000>, <100000000>; 1683 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1684 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1685 iommus = <&vopl_mmu>; 1686 power-domains = <&power RK3399_PD_VOPL>; 1687 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1688 reset-names = "axi", "ahb", "dclk"; 1689 status = "disabled"; 1690 1691 vopl_out: port { 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 1695 vopl_out_mipi: endpoint@0 { 1696 reg = <0>; 1697 remote-endpoint = <&mipi_in_vopl>; 1698 }; 1699 1700 vopl_out_edp: endpoint@1 { 1701 reg = <1>; 1702 remote-endpoint = <&edp_in_vopl>; 1703 }; 1704 1705 vopl_out_hdmi: endpoint@2 { 1706 reg = <2>; 1707 remote-endpoint = <&hdmi_in_vopl>; 1708 }; 1709 1710 vopl_out_mipi1: endpoint@3 { 1711 reg = <3>; 1712 remote-endpoint = <&mipi1_in_vopl>; 1713 }; 1714 1715 vopl_out_dp: endpoint@4 { 1716 reg = <4>; 1717 remote-endpoint = <&dp_in_vopl>; 1718 }; 1719 }; 1720 }; 1721 1722 vopl_mmu: iommu@ff8f3f00 { 1723 compatible = "rockchip,iommu"; 1724 reg = <0x0 0xff8f3f00 0x0 0x100>; 1725 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1726 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1727 clock-names = "aclk", "iface"; 1728 power-domains = <&power RK3399_PD_VOPL>; 1729 #iommu-cells = <0>; 1730 status = "disabled"; 1731 }; 1732 1733 vopb: vop@ff900000 { 1734 compatible = "rockchip,rk3399-vop-big"; 1735 reg = <0x0 0xff900000 0x0 0x3efc>; 1736 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1737 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1738 assigned-clock-rates = <400000000>, <100000000>; 1739 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1740 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1741 iommus = <&vopb_mmu>; 1742 power-domains = <&power RK3399_PD_VOPB>; 1743 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1744 reset-names = "axi", "ahb", "dclk"; 1745 status = "disabled"; 1746 1747 vopb_out: port { 1748 #address-cells = <1>; 1749 #size-cells = <0>; 1750 1751 vopb_out_edp: endpoint@0 { 1752 reg = <0>; 1753 remote-endpoint = <&edp_in_vopb>; 1754 }; 1755 1756 vopb_out_mipi: endpoint@1 { 1757 reg = <1>; 1758 remote-endpoint = <&mipi_in_vopb>; 1759 }; 1760 1761 vopb_out_hdmi: endpoint@2 { 1762 reg = <2>; 1763 remote-endpoint = <&hdmi_in_vopb>; 1764 }; 1765 1766 vopb_out_mipi1: endpoint@3 { 1767 reg = <3>; 1768 remote-endpoint = <&mipi1_in_vopb>; 1769 }; 1770 1771 vopb_out_dp: endpoint@4 { 1772 reg = <4>; 1773 remote-endpoint = <&dp_in_vopb>; 1774 }; 1775 }; 1776 }; 1777 1778 vopb_mmu: iommu@ff903f00 { 1779 compatible = "rockchip,iommu"; 1780 reg = <0x0 0xff903f00 0x0 0x100>; 1781 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1782 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1783 clock-names = "aclk", "iface"; 1784 power-domains = <&power RK3399_PD_VOPB>; 1785 #iommu-cells = <0>; 1786 status = "disabled"; 1787 }; 1788 1789 isp0: isp0@ff910000 { 1790 compatible = "rockchip,rk3399-cif-isp"; 1791 reg = <0x0 0xff910000 0x0 0x4000>; 1792 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1793 clocks = <&cru SCLK_ISP0>, 1794 <&cru ACLK_ISP0_WRAPPER>, 1795 <&cru HCLK_ISP0_WRAPPER>; 1796 clock-names = "isp", "aclk", "hclk"; 1797 iommus = <&isp0_mmu>; 1798 phys = <&mipi_dphy_rx0>; 1799 phy-names = "dphy"; 1800 power-domains = <&power RK3399_PD_ISP0>; 1801 status = "disabled"; 1802 1803 ports { 1804 #address-cells = <1>; 1805 #size-cells = <0>; 1806 1807 port@0 { 1808 reg = <0>; 1809 #address-cells = <1>; 1810 #size-cells = <0>; 1811 }; 1812 }; 1813 }; 1814 1815 isp0_mmu: iommu@ff914000 { 1816 compatible = "rockchip,iommu"; 1817 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1818 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1819 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1820 clock-names = "aclk", "iface"; 1821 #iommu-cells = <0>; 1822 power-domains = <&power RK3399_PD_ISP0>; 1823 rockchip,disable-mmu-reset; 1824 }; 1825 1826 isp1: isp1@ff920000 { 1827 compatible = "rockchip,rk3399-cif-isp"; 1828 reg = <0x0 0xff920000 0x0 0x4000>; 1829 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1830 clocks = <&cru SCLK_ISP1>, 1831 <&cru ACLK_ISP1_WRAPPER>, 1832 <&cru HCLK_ISP1_WRAPPER>; 1833 clock-names = "isp", "aclk", "hclk"; 1834 iommus = <&isp1_mmu>; 1835 phys = <&mipi_dsi1>; 1836 phy-names = "dphy"; 1837 power-domains = <&power RK3399_PD_ISP1>; 1838 status = "disabled"; 1839 1840 ports { 1841 #address-cells = <1>; 1842 #size-cells = <0>; 1843 1844 port@0 { 1845 reg = <0>; 1846 #address-cells = <1>; 1847 #size-cells = <0>; 1848 }; 1849 }; 1850 }; 1851 1852 isp1_mmu: iommu@ff924000 { 1853 compatible = "rockchip,iommu"; 1854 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1855 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1856 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; 1857 clock-names = "aclk", "iface"; 1858 #iommu-cells = <0>; 1859 power-domains = <&power RK3399_PD_ISP1>; 1860 rockchip,disable-mmu-reset; 1861 }; 1862 1863 hdmi_sound: hdmi-sound { 1864 compatible = "simple-audio-card"; 1865 simple-audio-card,format = "i2s"; 1866 simple-audio-card,mclk-fs = <256>; 1867 simple-audio-card,name = "hdmi-sound"; 1868 status = "disabled"; 1869 1870 simple-audio-card,cpu { 1871 sound-dai = <&i2s2>; 1872 }; 1873 simple-audio-card,codec { 1874 sound-dai = <&hdmi>; 1875 }; 1876 }; 1877 1878 hdmi: hdmi@ff940000 { 1879 compatible = "rockchip,rk3399-dw-hdmi"; 1880 reg = <0x0 0xff940000 0x0 0x20000>; 1881 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1882 clocks = <&cru PCLK_HDMI_CTRL>, 1883 <&cru SCLK_HDMI_SFR>, 1884 <&cru SCLK_HDMI_CEC>, 1885 <&cru PCLK_VIO_GRF>, 1886 <&cru PLL_VPLL>; 1887 clock-names = "iahb", "isfr", "cec", "grf", "vpll"; 1888 power-domains = <&power RK3399_PD_HDCP>; 1889 reg-io-width = <4>; 1890 rockchip,grf = <&grf>; 1891 #sound-dai-cells = <0>; 1892 status = "disabled"; 1893 1894 ports { 1895 hdmi_in: port { 1896 #address-cells = <1>; 1897 #size-cells = <0>; 1898 1899 hdmi_in_vopb: endpoint@0 { 1900 reg = <0>; 1901 remote-endpoint = <&vopb_out_hdmi>; 1902 }; 1903 hdmi_in_vopl: endpoint@1 { 1904 reg = <1>; 1905 remote-endpoint = <&vopl_out_hdmi>; 1906 }; 1907 }; 1908 }; 1909 }; 1910 1911 mipi_dsi: mipi@ff960000 { 1912 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1913 reg = <0x0 0xff960000 0x0 0x8000>; 1914 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1915 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1916 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1917 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1918 power-domains = <&power RK3399_PD_VIO>; 1919 resets = <&cru SRST_P_MIPI_DSI0>; 1920 reset-names = "apb"; 1921 rockchip,grf = <&grf>; 1922 #address-cells = <1>; 1923 #size-cells = <0>; 1924 status = "disabled"; 1925 1926 ports { 1927 #address-cells = <1>; 1928 #size-cells = <0>; 1929 1930 mipi_in: port@0 { 1931 reg = <0>; 1932 #address-cells = <1>; 1933 #size-cells = <0>; 1934 1935 mipi_in_vopb: endpoint@0 { 1936 reg = <0>; 1937 remote-endpoint = <&vopb_out_mipi>; 1938 }; 1939 mipi_in_vopl: endpoint@1 { 1940 reg = <1>; 1941 remote-endpoint = <&vopl_out_mipi>; 1942 }; 1943 }; 1944 }; 1945 }; 1946 1947 mipi_dsi1: mipi@ff968000 { 1948 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1949 reg = <0x0 0xff968000 0x0 0x8000>; 1950 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 1951 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 1952 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 1953 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1954 power-domains = <&power RK3399_PD_VIO>; 1955 resets = <&cru SRST_P_MIPI_DSI1>; 1956 reset-names = "apb"; 1957 rockchip,grf = <&grf>; 1958 #address-cells = <1>; 1959 #size-cells = <0>; 1960 #phy-cells = <0>; 1961 status = "disabled"; 1962 1963 ports { 1964 #address-cells = <1>; 1965 #size-cells = <0>; 1966 1967 mipi1_in: port@0 { 1968 reg = <0>; 1969 #address-cells = <1>; 1970 #size-cells = <0>; 1971 1972 mipi1_in_vopb: endpoint@0 { 1973 reg = <0>; 1974 remote-endpoint = <&vopb_out_mipi1>; 1975 }; 1976 1977 mipi1_in_vopl: endpoint@1 { 1978 reg = <1>; 1979 remote-endpoint = <&vopl_out_mipi1>; 1980 }; 1981 }; 1982 }; 1983 }; 1984 1985 edp: edp@ff970000 { 1986 compatible = "rockchip,rk3399-edp"; 1987 reg = <0x0 0xff970000 0x0 0x8000>; 1988 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1989 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 1990 clock-names = "dp", "pclk", "grf"; 1991 pinctrl-names = "default"; 1992 pinctrl-0 = <&edp_hpd>; 1993 power-domains = <&power RK3399_PD_EDP>; 1994 resets = <&cru SRST_P_EDP_CTRL>; 1995 reset-names = "dp"; 1996 rockchip,grf = <&grf>; 1997 status = "disabled"; 1998 1999 ports { 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 edp_in: port@0 { 2003 reg = <0>; 2004 #address-cells = <1>; 2005 #size-cells = <0>; 2006 2007 edp_in_vopb: endpoint@0 { 2008 reg = <0>; 2009 remote-endpoint = <&vopb_out_edp>; 2010 }; 2011 2012 edp_in_vopl: endpoint@1 { 2013 reg = <1>; 2014 remote-endpoint = <&vopl_out_edp>; 2015 }; 2016 }; 2017 }; 2018 }; 2019 2020 gpu: gpu@ff9a0000 { 2021 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 2022 reg = <0x0 0xff9a0000 0x0 0x10000>; 2023 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 2024 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, 2025 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 2026 interrupt-names = "job", "mmu", "gpu"; 2027 clocks = <&cru ACLK_GPU>; 2028 #cooling-cells = <2>; 2029 power-domains = <&power RK3399_PD_GPU>; 2030 status = "disabled"; 2031 }; 2032 2033 pinctrl: pinctrl { 2034 compatible = "rockchip,rk3399-pinctrl"; 2035 rockchip,grf = <&grf>; 2036 rockchip,pmu = <&pmugrf>; 2037 #address-cells = <2>; 2038 #size-cells = <2>; 2039 ranges; 2040 2041 gpio0: gpio@ff720000 { 2042 compatible = "rockchip,gpio-bank"; 2043 reg = <0x0 0xff720000 0x0 0x100>; 2044 clocks = <&pmucru PCLK_GPIO0_PMU>; 2045 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 2046 2047 gpio-controller; 2048 #gpio-cells = <0x2>; 2049 2050 interrupt-controller; 2051 #interrupt-cells = <0x2>; 2052 }; 2053 2054 gpio1: gpio@ff730000 { 2055 compatible = "rockchip,gpio-bank"; 2056 reg = <0x0 0xff730000 0x0 0x100>; 2057 clocks = <&pmucru PCLK_GPIO1_PMU>; 2058 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 2059 2060 gpio-controller; 2061 #gpio-cells = <0x2>; 2062 2063 interrupt-controller; 2064 #interrupt-cells = <0x2>; 2065 }; 2066 2067 gpio2: gpio@ff780000 { 2068 compatible = "rockchip,gpio-bank"; 2069 reg = <0x0 0xff780000 0x0 0x100>; 2070 clocks = <&cru PCLK_GPIO2>; 2071 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 2072 2073 gpio-controller; 2074 #gpio-cells = <0x2>; 2075 2076 interrupt-controller; 2077 #interrupt-cells = <0x2>; 2078 }; 2079 2080 gpio3: gpio@ff788000 { 2081 compatible = "rockchip,gpio-bank"; 2082 reg = <0x0 0xff788000 0x0 0x100>; 2083 clocks = <&cru PCLK_GPIO3>; 2084 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 2085 2086 gpio-controller; 2087 #gpio-cells = <0x2>; 2088 2089 interrupt-controller; 2090 #interrupt-cells = <0x2>; 2091 }; 2092 2093 gpio4: gpio@ff790000 { 2094 compatible = "rockchip,gpio-bank"; 2095 reg = <0x0 0xff790000 0x0 0x100>; 2096 clocks = <&cru PCLK_GPIO4>; 2097 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 2098 2099 gpio-controller; 2100 #gpio-cells = <0x2>; 2101 2102 interrupt-controller; 2103 #interrupt-cells = <0x2>; 2104 }; 2105 2106 pcfg_pull_up: pcfg-pull-up { 2107 bias-pull-up; 2108 }; 2109 2110 pcfg_pull_down: pcfg-pull-down { 2111 bias-pull-down; 2112 }; 2113 2114 pcfg_pull_none: pcfg-pull-none { 2115 bias-disable; 2116 }; 2117 2118 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 2119 bias-disable; 2120 drive-strength = <12>; 2121 }; 2122 2123 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 2124 bias-disable; 2125 drive-strength = <13>; 2126 }; 2127 2128 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 2129 bias-disable; 2130 drive-strength = <18>; 2131 }; 2132 2133 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 2134 bias-disable; 2135 drive-strength = <20>; 2136 }; 2137 2138 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2139 bias-pull-up; 2140 drive-strength = <2>; 2141 }; 2142 2143 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2144 bias-pull-up; 2145 drive-strength = <8>; 2146 }; 2147 2148 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 2149 bias-pull-up; 2150 drive-strength = <18>; 2151 }; 2152 2153 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 2154 bias-pull-up; 2155 drive-strength = <20>; 2156 }; 2157 2158 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2159 bias-pull-down; 2160 drive-strength = <4>; 2161 }; 2162 2163 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 2164 bias-pull-down; 2165 drive-strength = <8>; 2166 }; 2167 2168 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 2169 bias-pull-down; 2170 drive-strength = <12>; 2171 }; 2172 2173 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2174 bias-pull-down; 2175 drive-strength = <18>; 2176 }; 2177 2178 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2179 bias-pull-down; 2180 drive-strength = <20>; 2181 }; 2182 2183 pcfg_output_high: pcfg-output-high { 2184 output-high; 2185 }; 2186 2187 pcfg_output_low: pcfg-output-low { 2188 output-low; 2189 }; 2190 2191 clock { 2192 clk_32k: clk-32k { 2193 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 2194 }; 2195 }; 2196 2197 cif { 2198 cif_clkin: cif-clkin { 2199 rockchip,pins = 2200 <2 RK_PB2 3 &pcfg_pull_none>; 2201 }; 2202 2203 cif_clkouta: cif-clkouta { 2204 rockchip,pins = 2205 <2 RK_PB3 3 &pcfg_pull_none>; 2206 }; 2207 }; 2208 2209 edp { 2210 edp_hpd: edp-hpd { 2211 rockchip,pins = 2212 <4 RK_PC7 2 &pcfg_pull_none>; 2213 }; 2214 }; 2215 2216 gmac { 2217 rgmii_pins: rgmii-pins { 2218 rockchip,pins = 2219 /* mac_txclk */ 2220 <3 RK_PC1 1 &pcfg_pull_none_13ma>, 2221 /* mac_rxclk */ 2222 <3 RK_PB6 1 &pcfg_pull_none>, 2223 /* mac_mdio */ 2224 <3 RK_PB5 1 &pcfg_pull_none>, 2225 /* mac_txen */ 2226 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2227 /* mac_clk */ 2228 <3 RK_PB3 1 &pcfg_pull_none>, 2229 /* mac_rxdv */ 2230 <3 RK_PB1 1 &pcfg_pull_none>, 2231 /* mac_mdc */ 2232 <3 RK_PB0 1 &pcfg_pull_none>, 2233 /* mac_rxd1 */ 2234 <3 RK_PA7 1 &pcfg_pull_none>, 2235 /* mac_rxd0 */ 2236 <3 RK_PA6 1 &pcfg_pull_none>, 2237 /* mac_txd1 */ 2238 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2239 /* mac_txd0 */ 2240 <3 RK_PA4 1 &pcfg_pull_none_13ma>, 2241 /* mac_rxd3 */ 2242 <3 RK_PA3 1 &pcfg_pull_none>, 2243 /* mac_rxd2 */ 2244 <3 RK_PA2 1 &pcfg_pull_none>, 2245 /* mac_txd3 */ 2246 <3 RK_PA1 1 &pcfg_pull_none_13ma>, 2247 /* mac_txd2 */ 2248 <3 RK_PA0 1 &pcfg_pull_none_13ma>; 2249 }; 2250 2251 rmii_pins: rmii-pins { 2252 rockchip,pins = 2253 /* mac_mdio */ 2254 <3 RK_PB5 1 &pcfg_pull_none>, 2255 /* mac_txen */ 2256 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2257 /* mac_clk */ 2258 <3 RK_PB3 1 &pcfg_pull_none>, 2259 /* mac_rxer */ 2260 <3 RK_PB2 1 &pcfg_pull_none>, 2261 /* mac_rxdv */ 2262 <3 RK_PB1 1 &pcfg_pull_none>, 2263 /* mac_mdc */ 2264 <3 RK_PB0 1 &pcfg_pull_none>, 2265 /* mac_rxd1 */ 2266 <3 RK_PA7 1 &pcfg_pull_none>, 2267 /* mac_rxd0 */ 2268 <3 RK_PA6 1 &pcfg_pull_none>, 2269 /* mac_txd1 */ 2270 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2271 /* mac_txd0 */ 2272 <3 RK_PA4 1 &pcfg_pull_none_13ma>; 2273 }; 2274 }; 2275 2276 i2c0 { 2277 i2c0_xfer: i2c0-xfer { 2278 rockchip,pins = 2279 <1 RK_PB7 2 &pcfg_pull_none>, 2280 <1 RK_PC0 2 &pcfg_pull_none>; 2281 }; 2282 }; 2283 2284 i2c1 { 2285 i2c1_xfer: i2c1-xfer { 2286 rockchip,pins = 2287 <4 RK_PA2 1 &pcfg_pull_none>, 2288 <4 RK_PA1 1 &pcfg_pull_none>; 2289 }; 2290 }; 2291 2292 i2c2 { 2293 i2c2_xfer: i2c2-xfer { 2294 rockchip,pins = 2295 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 2296 <2 RK_PA0 2 &pcfg_pull_none_12ma>; 2297 }; 2298 }; 2299 2300 i2c3 { 2301 i2c3_xfer: i2c3-xfer { 2302 rockchip,pins = 2303 <4 RK_PC1 1 &pcfg_pull_none>, 2304 <4 RK_PC0 1 &pcfg_pull_none>; 2305 }; 2306 }; 2307 2308 i2c4 { 2309 i2c4_xfer: i2c4-xfer { 2310 rockchip,pins = 2311 <1 RK_PB4 1 &pcfg_pull_none>, 2312 <1 RK_PB3 1 &pcfg_pull_none>; 2313 }; 2314 }; 2315 2316 i2c5 { 2317 i2c5_xfer: i2c5-xfer { 2318 rockchip,pins = 2319 <3 RK_PB3 2 &pcfg_pull_none>, 2320 <3 RK_PB2 2 &pcfg_pull_none>; 2321 }; 2322 }; 2323 2324 i2c6 { 2325 i2c6_xfer: i2c6-xfer { 2326 rockchip,pins = 2327 <2 RK_PB2 2 &pcfg_pull_none>, 2328 <2 RK_PB1 2 &pcfg_pull_none>; 2329 }; 2330 }; 2331 2332 i2c7 { 2333 i2c7_xfer: i2c7-xfer { 2334 rockchip,pins = 2335 <2 RK_PB0 2 &pcfg_pull_none>, 2336 <2 RK_PA7 2 &pcfg_pull_none>; 2337 }; 2338 }; 2339 2340 i2c8 { 2341 i2c8_xfer: i2c8-xfer { 2342 rockchip,pins = 2343 <1 RK_PC5 1 &pcfg_pull_none>, 2344 <1 RK_PC4 1 &pcfg_pull_none>; 2345 }; 2346 }; 2347 2348 i2s0 { 2349 i2s0_2ch_bus: i2s0-2ch-bus { 2350 rockchip,pins = 2351 <3 RK_PD0 1 &pcfg_pull_none>, 2352 <3 RK_PD1 1 &pcfg_pull_none>, 2353 <3 RK_PD2 1 &pcfg_pull_none>, 2354 <3 RK_PD3 1 &pcfg_pull_none>, 2355 <3 RK_PD7 1 &pcfg_pull_none>, 2356 <4 RK_PA0 1 &pcfg_pull_none>; 2357 }; 2358 2359 i2s0_8ch_bus: i2s0-8ch-bus { 2360 rockchip,pins = 2361 <3 RK_PD0 1 &pcfg_pull_none>, 2362 <3 RK_PD1 1 &pcfg_pull_none>, 2363 <3 RK_PD2 1 &pcfg_pull_none>, 2364 <3 RK_PD3 1 &pcfg_pull_none>, 2365 <3 RK_PD4 1 &pcfg_pull_none>, 2366 <3 RK_PD5 1 &pcfg_pull_none>, 2367 <3 RK_PD6 1 &pcfg_pull_none>, 2368 <3 RK_PD7 1 &pcfg_pull_none>, 2369 <4 RK_PA0 1 &pcfg_pull_none>; 2370 }; 2371 }; 2372 2373 i2s1 { 2374 i2s1_2ch_bus: i2s1-2ch-bus { 2375 rockchip,pins = 2376 <4 RK_PA3 1 &pcfg_pull_none>, 2377 <4 RK_PA4 1 &pcfg_pull_none>, 2378 <4 RK_PA5 1 &pcfg_pull_none>, 2379 <4 RK_PA6 1 &pcfg_pull_none>, 2380 <4 RK_PA7 1 &pcfg_pull_none>; 2381 }; 2382 }; 2383 2384 sdio0 { 2385 sdio0_bus1: sdio0-bus1 { 2386 rockchip,pins = 2387 <2 RK_PC4 1 &pcfg_pull_up>; 2388 }; 2389 2390 sdio0_bus4: sdio0-bus4 { 2391 rockchip,pins = 2392 <2 RK_PC4 1 &pcfg_pull_up>, 2393 <2 RK_PC5 1 &pcfg_pull_up>, 2394 <2 RK_PC6 1 &pcfg_pull_up>, 2395 <2 RK_PC7 1 &pcfg_pull_up>; 2396 }; 2397 2398 sdio0_cmd: sdio0-cmd { 2399 rockchip,pins = 2400 <2 RK_PD0 1 &pcfg_pull_up>; 2401 }; 2402 2403 sdio0_clk: sdio0-clk { 2404 rockchip,pins = 2405 <2 RK_PD1 1 &pcfg_pull_none>; 2406 }; 2407 2408 sdio0_cd: sdio0-cd { 2409 rockchip,pins = 2410 <2 RK_PD2 1 &pcfg_pull_up>; 2411 }; 2412 2413 sdio0_pwr: sdio0-pwr { 2414 rockchip,pins = 2415 <2 RK_PD3 1 &pcfg_pull_up>; 2416 }; 2417 2418 sdio0_bkpwr: sdio0-bkpwr { 2419 rockchip,pins = 2420 <2 RK_PD4 1 &pcfg_pull_up>; 2421 }; 2422 2423 sdio0_wp: sdio0-wp { 2424 rockchip,pins = 2425 <0 RK_PA3 1 &pcfg_pull_up>; 2426 }; 2427 2428 sdio0_int: sdio0-int { 2429 rockchip,pins = 2430 <0 RK_PA4 1 &pcfg_pull_up>; 2431 }; 2432 }; 2433 2434 sdmmc { 2435 sdmmc_bus1: sdmmc-bus1 { 2436 rockchip,pins = 2437 <4 RK_PB0 1 &pcfg_pull_up>; 2438 }; 2439 2440 sdmmc_bus4: sdmmc-bus4 { 2441 rockchip,pins = 2442 <4 RK_PB0 1 &pcfg_pull_up>, 2443 <4 RK_PB1 1 &pcfg_pull_up>, 2444 <4 RK_PB2 1 &pcfg_pull_up>, 2445 <4 RK_PB3 1 &pcfg_pull_up>; 2446 }; 2447 2448 sdmmc_clk: sdmmc-clk { 2449 rockchip,pins = 2450 <4 RK_PB4 1 &pcfg_pull_none>; 2451 }; 2452 2453 sdmmc_cmd: sdmmc-cmd { 2454 rockchip,pins = 2455 <4 RK_PB5 1 &pcfg_pull_up>; 2456 }; 2457 2458 sdmmc_cd: sdmmc-cd { 2459 rockchip,pins = 2460 <0 RK_PA7 1 &pcfg_pull_up>; 2461 }; 2462 2463 sdmmc_wp: sdmmc-wp { 2464 rockchip,pins = 2465 <0 RK_PB0 1 &pcfg_pull_up>; 2466 }; 2467 }; 2468 2469 suspend { 2470 ap_pwroff: ap-pwroff { 2471 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; 2472 }; 2473 2474 ddrio_pwroff: ddrio-pwroff { 2475 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 2476 }; 2477 }; 2478 2479 spdif { 2480 spdif_bus: spdif-bus { 2481 rockchip,pins = 2482 <4 RK_PC5 1 &pcfg_pull_none>; 2483 }; 2484 2485 spdif_bus_1: spdif-bus-1 { 2486 rockchip,pins = 2487 <3 RK_PC0 3 &pcfg_pull_none>; 2488 }; 2489 }; 2490 2491 spi0 { 2492 spi0_clk: spi0-clk { 2493 rockchip,pins = 2494 <3 RK_PA6 2 &pcfg_pull_up>; 2495 }; 2496 spi0_cs0: spi0-cs0 { 2497 rockchip,pins = 2498 <3 RK_PA7 2 &pcfg_pull_up>; 2499 }; 2500 spi0_cs1: spi0-cs1 { 2501 rockchip,pins = 2502 <3 RK_PB0 2 &pcfg_pull_up>; 2503 }; 2504 spi0_tx: spi0-tx { 2505 rockchip,pins = 2506 <3 RK_PA5 2 &pcfg_pull_up>; 2507 }; 2508 spi0_rx: spi0-rx { 2509 rockchip,pins = 2510 <3 RK_PA4 2 &pcfg_pull_up>; 2511 }; 2512 }; 2513 2514 spi1 { 2515 spi1_clk: spi1-clk { 2516 rockchip,pins = 2517 <1 RK_PB1 2 &pcfg_pull_up>; 2518 }; 2519 spi1_cs0: spi1-cs0 { 2520 rockchip,pins = 2521 <1 RK_PB2 2 &pcfg_pull_up>; 2522 }; 2523 spi1_rx: spi1-rx { 2524 rockchip,pins = 2525 <1 RK_PA7 2 &pcfg_pull_up>; 2526 }; 2527 spi1_tx: spi1-tx { 2528 rockchip,pins = 2529 <1 RK_PB0 2 &pcfg_pull_up>; 2530 }; 2531 }; 2532 2533 spi2 { 2534 spi2_clk: spi2-clk { 2535 rockchip,pins = 2536 <2 RK_PB3 1 &pcfg_pull_up>; 2537 }; 2538 spi2_cs0: spi2-cs0 { 2539 rockchip,pins = 2540 <2 RK_PB4 1 &pcfg_pull_up>; 2541 }; 2542 spi2_rx: spi2-rx { 2543 rockchip,pins = 2544 <2 RK_PB1 1 &pcfg_pull_up>; 2545 }; 2546 spi2_tx: spi2-tx { 2547 rockchip,pins = 2548 <2 RK_PB2 1 &pcfg_pull_up>; 2549 }; 2550 }; 2551 2552 spi3 { 2553 spi3_clk: spi3-clk { 2554 rockchip,pins = 2555 <1 RK_PC1 1 &pcfg_pull_up>; 2556 }; 2557 spi3_cs0: spi3-cs0 { 2558 rockchip,pins = 2559 <1 RK_PC2 1 &pcfg_pull_up>; 2560 }; 2561 spi3_rx: spi3-rx { 2562 rockchip,pins = 2563 <1 RK_PB7 1 &pcfg_pull_up>; 2564 }; 2565 spi3_tx: spi3-tx { 2566 rockchip,pins = 2567 <1 RK_PC0 1 &pcfg_pull_up>; 2568 }; 2569 }; 2570 2571 spi4 { 2572 spi4_clk: spi4-clk { 2573 rockchip,pins = 2574 <3 RK_PA2 2 &pcfg_pull_up>; 2575 }; 2576 spi4_cs0: spi4-cs0 { 2577 rockchip,pins = 2578 <3 RK_PA3 2 &pcfg_pull_up>; 2579 }; 2580 spi4_rx: spi4-rx { 2581 rockchip,pins = 2582 <3 RK_PA0 2 &pcfg_pull_up>; 2583 }; 2584 spi4_tx: spi4-tx { 2585 rockchip,pins = 2586 <3 RK_PA1 2 &pcfg_pull_up>; 2587 }; 2588 }; 2589 2590 spi5 { 2591 spi5_clk: spi5-clk { 2592 rockchip,pins = 2593 <2 RK_PC6 2 &pcfg_pull_up>; 2594 }; 2595 spi5_cs0: spi5-cs0 { 2596 rockchip,pins = 2597 <2 RK_PC7 2 &pcfg_pull_up>; 2598 }; 2599 spi5_rx: spi5-rx { 2600 rockchip,pins = 2601 <2 RK_PC4 2 &pcfg_pull_up>; 2602 }; 2603 spi5_tx: spi5-tx { 2604 rockchip,pins = 2605 <2 RK_PC5 2 &pcfg_pull_up>; 2606 }; 2607 }; 2608 2609 testclk { 2610 test_clkout0: test-clkout0 { 2611 rockchip,pins = 2612 <0 RK_PA0 1 &pcfg_pull_none>; 2613 }; 2614 2615 test_clkout1: test-clkout1 { 2616 rockchip,pins = 2617 <2 RK_PD1 2 &pcfg_pull_none>; 2618 }; 2619 2620 test_clkout2: test-clkout2 { 2621 rockchip,pins = 2622 <0 RK_PB0 3 &pcfg_pull_none>; 2623 }; 2624 }; 2625 2626 tsadc { 2627 otp_pin: otp-pin { 2628 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2629 }; 2630 2631 otp_out: otp-out { 2632 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 2633 }; 2634 }; 2635 2636 uart0 { 2637 uart0_xfer: uart0-xfer { 2638 rockchip,pins = 2639 <2 RK_PC0 1 &pcfg_pull_up>, 2640 <2 RK_PC1 1 &pcfg_pull_none>; 2641 }; 2642 2643 uart0_cts: uart0-cts { 2644 rockchip,pins = 2645 <2 RK_PC2 1 &pcfg_pull_none>; 2646 }; 2647 2648 uart0_rts: uart0-rts { 2649 rockchip,pins = 2650 <2 RK_PC3 1 &pcfg_pull_none>; 2651 }; 2652 }; 2653 2654 uart1 { 2655 uart1_xfer: uart1-xfer { 2656 rockchip,pins = 2657 <3 RK_PB4 2 &pcfg_pull_up>, 2658 <3 RK_PB5 2 &pcfg_pull_none>; 2659 }; 2660 }; 2661 2662 uart2a { 2663 uart2a_xfer: uart2a-xfer { 2664 rockchip,pins = 2665 <4 RK_PB0 2 &pcfg_pull_up>, 2666 <4 RK_PB1 2 &pcfg_pull_none>; 2667 }; 2668 }; 2669 2670 uart2b { 2671 uart2b_xfer: uart2b-xfer { 2672 rockchip,pins = 2673 <4 RK_PC0 2 &pcfg_pull_up>, 2674 <4 RK_PC1 2 &pcfg_pull_none>; 2675 }; 2676 }; 2677 2678 uart2c { 2679 uart2c_xfer: uart2c-xfer { 2680 rockchip,pins = 2681 <4 RK_PC3 1 &pcfg_pull_up>, 2682 <4 RK_PC4 1 &pcfg_pull_none>; 2683 }; 2684 }; 2685 2686 uart3 { 2687 uart3_xfer: uart3-xfer { 2688 rockchip,pins = 2689 <3 RK_PB6 2 &pcfg_pull_up>, 2690 <3 RK_PB7 2 &pcfg_pull_none>; 2691 }; 2692 2693 uart3_cts: uart3-cts { 2694 rockchip,pins = 2695 <3 RK_PC0 2 &pcfg_pull_none>; 2696 }; 2697 2698 uart3_rts: uart3-rts { 2699 rockchip,pins = 2700 <3 RK_PC1 2 &pcfg_pull_none>; 2701 }; 2702 }; 2703 2704 uart4 { 2705 uart4_xfer: uart4-xfer { 2706 rockchip,pins = 2707 <1 RK_PA7 1 &pcfg_pull_up>, 2708 <1 RK_PB0 1 &pcfg_pull_none>; 2709 }; 2710 }; 2711 2712 uarthdcp { 2713 uarthdcp_xfer: uarthdcp-xfer { 2714 rockchip,pins = 2715 <4 RK_PC5 2 &pcfg_pull_up>, 2716 <4 RK_PC6 2 &pcfg_pull_none>; 2717 }; 2718 }; 2719 2720 pwm0 { 2721 pwm0_pin: pwm0-pin { 2722 rockchip,pins = 2723 <4 RK_PC2 1 &pcfg_pull_none>; 2724 }; 2725 2726 pwm0_pin_pull_down: pwm0-pin-pull-down { 2727 rockchip,pins = 2728 <4 RK_PC2 1 &pcfg_pull_down>; 2729 }; 2730 2731 vop0_pwm_pin: vop0-pwm-pin { 2732 rockchip,pins = 2733 <4 RK_PC2 2 &pcfg_pull_none>; 2734 }; 2735 2736 vop1_pwm_pin: vop1-pwm-pin { 2737 rockchip,pins = 2738 <4 RK_PC2 3 &pcfg_pull_none>; 2739 }; 2740 }; 2741 2742 pwm1 { 2743 pwm1_pin: pwm1-pin { 2744 rockchip,pins = 2745 <4 RK_PC6 1 &pcfg_pull_none>; 2746 }; 2747 2748 pwm1_pin_pull_down: pwm1-pin-pull-down { 2749 rockchip,pins = 2750 <4 RK_PC6 1 &pcfg_pull_down>; 2751 }; 2752 }; 2753 2754 pwm2 { 2755 pwm2_pin: pwm2-pin { 2756 rockchip,pins = 2757 <1 RK_PC3 1 &pcfg_pull_none>; 2758 }; 2759 2760 pwm2_pin_pull_down: pwm2-pin-pull-down { 2761 rockchip,pins = 2762 <1 RK_PC3 1 &pcfg_pull_down>; 2763 }; 2764 }; 2765 2766 pwm3a { 2767 pwm3a_pin: pwm3a-pin { 2768 rockchip,pins = 2769 <0 RK_PA6 1 &pcfg_pull_none>; 2770 }; 2771 }; 2772 2773 pwm3b { 2774 pwm3b_pin: pwm3b-pin { 2775 rockchip,pins = 2776 <1 RK_PB6 1 &pcfg_pull_none>; 2777 }; 2778 }; 2779 2780 hdmi { 2781 hdmi_i2c_xfer: hdmi-i2c-xfer { 2782 rockchip,pins = 2783 <4 RK_PC1 3 &pcfg_pull_none>, 2784 <4 RK_PC0 3 &pcfg_pull_none>; 2785 }; 2786 2787 hdmi_cec: hdmi-cec { 2788 rockchip,pins = 2789 <4 RK_PC7 1 &pcfg_pull_none>; 2790 }; 2791 }; 2792 2793 pcie { 2794 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2795 rockchip,pins = 2796 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2797 }; 2798 2799 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2800 rockchip,pins = 2801 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2802 }; 2803 }; 2804 2805 }; 2806}; 2807