1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include "rk3399-base.dtsi" 7 8/ { 9 cluster0_opp: opp-table-0 { 10 compatible = "operating-points-v2"; 11 opp-shared; 12 13 opp00 { 14 opp-hz = /bits/ 64 <408000000>; 15 opp-microvolt = <825000 825000 1250000>; 16 clock-latency-ns = <40000>; 17 }; 18 opp01 { 19 opp-hz = /bits/ 64 <600000000>; 20 opp-microvolt = <825000 825000 1250000>; 21 }; 22 opp02 { 23 opp-hz = /bits/ 64 <816000000>; 24 opp-microvolt = <850000 850000 1250000>; 25 }; 26 opp03 { 27 opp-hz = /bits/ 64 <1008000000>; 28 opp-microvolt = <925000 925000 1250000>; 29 }; 30 opp04 { 31 opp-hz = /bits/ 64 <1200000000>; 32 opp-microvolt = <1000000 1000000 1250000>; 33 }; 34 opp05 { 35 opp-hz = /bits/ 64 <1416000000>; 36 opp-microvolt = <1125000 1125000 1250000>; 37 }; 38 }; 39 40 cluster1_opp: opp-table-1 { 41 compatible = "operating-points-v2"; 42 opp-shared; 43 44 opp00 { 45 opp-hz = /bits/ 64 <408000000>; 46 opp-microvolt = <825000 825000 1250000>; 47 clock-latency-ns = <40000>; 48 }; 49 opp01 { 50 opp-hz = /bits/ 64 <600000000>; 51 opp-microvolt = <825000 825000 1250000>; 52 }; 53 opp02 { 54 opp-hz = /bits/ 64 <816000000>; 55 opp-microvolt = <825000 825000 1250000>; 56 }; 57 opp03 { 58 opp-hz = /bits/ 64 <1008000000>; 59 opp-microvolt = <875000 875000 1250000>; 60 }; 61 opp04 { 62 opp-hz = /bits/ 64 <1200000000>; 63 opp-microvolt = <950000 950000 1250000>; 64 }; 65 opp05 { 66 opp-hz = /bits/ 64 <1416000000>; 67 opp-microvolt = <1025000 1025000 1250000>; 68 }; 69 opp06 { 70 opp-hz = /bits/ 64 <1608000000>; 71 opp-microvolt = <1100000 1100000 1250000>; 72 }; 73 opp07 { 74 opp-hz = /bits/ 64 <1800000000>; 75 opp-microvolt = <1200000 1200000 1250000>; 76 }; 77 }; 78 79 gpu_opp_table: opp-table-2 { 80 compatible = "operating-points-v2"; 81 82 opp00 { 83 opp-hz = /bits/ 64 <200000000>; 84 opp-microvolt = <825000 825000 1150000>; 85 }; 86 opp01 { 87 opp-hz = /bits/ 64 <297000000>; 88 opp-microvolt = <825000 825000 1150000>; 89 }; 90 opp02 { 91 opp-hz = /bits/ 64 <400000000>; 92 opp-microvolt = <825000 825000 1150000>; 93 }; 94 opp03 { 95 opp-hz = /bits/ 64 <500000000>; 96 opp-microvolt = <875000 875000 1150000>; 97 }; 98 opp04 { 99 opp-hz = /bits/ 64 <600000000>; 100 opp-microvolt = <925000 925000 1150000>; 101 }; 102 opp05 { 103 opp-hz = /bits/ 64 <800000000>; 104 opp-microvolt = <1100000 1100000 1150000>; 105 }; 106 }; 107}; 108 109&cpu_l0 { 110 operating-points-v2 = <&cluster0_opp>; 111}; 112 113&cpu_l1 { 114 operating-points-v2 = <&cluster0_opp>; 115}; 116 117&cpu_l2 { 118 operating-points-v2 = <&cluster0_opp>; 119}; 120 121&cpu_l3 { 122 operating-points-v2 = <&cluster0_opp>; 123}; 124 125&cpu_b0 { 126 operating-points-v2 = <&cluster1_opp>; 127}; 128 129&cpu_b1 { 130 operating-points-v2 = <&cluster1_opp>; 131}; 132 133&gpu { 134 operating-points-v2 = <&gpu_opp_table>; 135}; 136