1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu-map { 44 cluster0 { 45 core0 { 46 cpu = <&cpu_l0>; 47 }; 48 core1 { 49 cpu = <&cpu_l1>; 50 }; 51 core2 { 52 cpu = <&cpu_l2>; 53 }; 54 core3 { 55 cpu = <&cpu_l3>; 56 }; 57 }; 58 59 cluster1 { 60 core0 { 61 cpu = <&cpu_b0>; 62 }; 63 core1 { 64 cpu = <&cpu_b1>; 65 }; 66 }; 67 }; 68 69 cpu_l0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 clocks = <&cru ARMCLKL>; 75 #cooling-cells = <2>; /* min followed by max */ 76 dynamic-power-coefficient = <100>; 77 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 78 }; 79 80 cpu_l1: cpu@1 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53", "arm,armv8"; 83 reg = <0x0 0x1>; 84 enable-method = "psci"; 85 clocks = <&cru ARMCLKL>; 86 #cooling-cells = <2>; /* min followed by max */ 87 dynamic-power-coefficient = <100>; 88 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 89 }; 90 91 cpu_l2: cpu@2 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a53", "arm,armv8"; 94 reg = <0x0 0x2>; 95 enable-method = "psci"; 96 clocks = <&cru ARMCLKL>; 97 #cooling-cells = <2>; /* min followed by max */ 98 dynamic-power-coefficient = <100>; 99 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 100 }; 101 102 cpu_l3: cpu@3 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a53", "arm,armv8"; 105 reg = <0x0 0x3>; 106 enable-method = "psci"; 107 clocks = <&cru ARMCLKL>; 108 #cooling-cells = <2>; /* min followed by max */ 109 dynamic-power-coefficient = <100>; 110 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 111 }; 112 113 cpu_b0: cpu@100 { 114 device_type = "cpu"; 115 compatible = "arm,cortex-a72", "arm,armv8"; 116 reg = <0x0 0x100>; 117 enable-method = "psci"; 118 clocks = <&cru ARMCLKB>; 119 #cooling-cells = <2>; /* min followed by max */ 120 dynamic-power-coefficient = <436>; 121 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 122 }; 123 124 cpu_b1: cpu@101 { 125 device_type = "cpu"; 126 compatible = "arm,cortex-a72", "arm,armv8"; 127 reg = <0x0 0x101>; 128 enable-method = "psci"; 129 clocks = <&cru ARMCLKB>; 130 #cooling-cells = <2>; /* min followed by max */ 131 dynamic-power-coefficient = <436>; 132 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 133 }; 134 135 idle-states { 136 entry-method = "psci"; 137 138 CPU_SLEEP: cpu-sleep { 139 compatible = "arm,idle-state"; 140 local-timer-stop; 141 arm,psci-suspend-param = <0x0010000>; 142 entry-latency-us = <120>; 143 exit-latency-us = <250>; 144 min-residency-us = <900>; 145 }; 146 147 CLUSTER_SLEEP: cluster-sleep { 148 compatible = "arm,idle-state"; 149 local-timer-stop; 150 arm,psci-suspend-param = <0x1010000>; 151 entry-latency-us = <400>; 152 exit-latency-us = <500>; 153 min-residency-us = <2000>; 154 }; 155 }; 156 }; 157 158 display-subsystem { 159 compatible = "rockchip,display-subsystem"; 160 ports = <&vopl_out>, <&vopb_out>; 161 }; 162 163 pmu_a53 { 164 compatible = "arm,cortex-a53-pmu"; 165 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 166 }; 167 168 pmu_a72 { 169 compatible = "arm,cortex-a72-pmu"; 170 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 171 }; 172 173 psci { 174 compatible = "arm,psci-1.0"; 175 method = "smc"; 176 }; 177 178 timer { 179 compatible = "arm,armv8-timer"; 180 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 181 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 182 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 183 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 184 arm,no-tick-in-suspend; 185 }; 186 187 xin24m: xin24m { 188 compatible = "fixed-clock"; 189 clock-frequency = <24000000>; 190 clock-output-names = "xin24m"; 191 #clock-cells = <0>; 192 }; 193 194 amba { 195 compatible = "simple-bus"; 196 #address-cells = <2>; 197 #size-cells = <2>; 198 ranges; 199 200 dmac_bus: dma-controller@ff6d0000 { 201 compatible = "arm,pl330", "arm,primecell"; 202 reg = <0x0 0xff6d0000 0x0 0x4000>; 203 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 204 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 205 #dma-cells = <1>; 206 clocks = <&cru ACLK_DMAC0_PERILP>; 207 clock-names = "apb_pclk"; 208 }; 209 210 dmac_peri: dma-controller@ff6e0000 { 211 compatible = "arm,pl330", "arm,primecell"; 212 reg = <0x0 0xff6e0000 0x0 0x4000>; 213 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 214 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 215 #dma-cells = <1>; 216 clocks = <&cru ACLK_DMAC1_PERILP>; 217 clock-names = "apb_pclk"; 218 }; 219 }; 220 221 pcie0: pcie@f8000000 { 222 compatible = "rockchip,rk3399-pcie"; 223 reg = <0x0 0xf8000000 0x0 0x2000000>, 224 <0x0 0xfd000000 0x0 0x1000000>; 225 reg-names = "axi-base", "apb-base"; 226 #address-cells = <3>; 227 #size-cells = <2>; 228 #interrupt-cells = <1>; 229 aspm-no-l0s; 230 bus-range = <0x0 0x1f>; 231 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 232 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 233 clock-names = "aclk", "aclk-perf", 234 "hclk", "pm"; 235 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 236 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 237 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 238 interrupt-names = "sys", "legacy", "client"; 239 interrupt-map-mask = <0 0 0 7>; 240 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 241 <0 0 0 2 &pcie0_intc 1>, 242 <0 0 0 3 &pcie0_intc 2>, 243 <0 0 0 4 &pcie0_intc 3>; 244 linux,pci-domain = <0>; 245 max-link-speed = <1>; 246 msi-map = <0x0 &its 0x0 0x1000>; 247 phys = <&pcie_phy 0>, <&pcie_phy 1>, 248 <&pcie_phy 2>, <&pcie_phy 3>; 249 phy-names = "pcie-phy-0", "pcie-phy-1", 250 "pcie-phy-2", "pcie-phy-3"; 251 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 252 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 253 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 254 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 255 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 256 <&cru SRST_A_PCIE>; 257 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 258 "pm", "pclk", "aclk"; 259 status = "disabled"; 260 261 pcie0_intc: interrupt-controller { 262 interrupt-controller; 263 #address-cells = <0>; 264 #interrupt-cells = <1>; 265 }; 266 }; 267 268 gmac: ethernet@fe300000 { 269 compatible = "rockchip,rk3399-gmac"; 270 reg = <0x0 0xfe300000 0x0 0x10000>; 271 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 272 interrupt-names = "macirq"; 273 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 274 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 275 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 276 <&cru PCLK_GMAC>; 277 clock-names = "stmmaceth", "mac_clk_rx", 278 "mac_clk_tx", "clk_mac_ref", 279 "clk_mac_refout", "aclk_mac", 280 "pclk_mac"; 281 power-domains = <&power RK3399_PD_GMAC>; 282 resets = <&cru SRST_A_GMAC>; 283 reset-names = "stmmaceth"; 284 rockchip,grf = <&grf>; 285 status = "disabled"; 286 }; 287 288 sdio0: dwmmc@fe310000 { 289 compatible = "rockchip,rk3399-dw-mshc", 290 "rockchip,rk3288-dw-mshc"; 291 reg = <0x0 0xfe310000 0x0 0x4000>; 292 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 293 max-frequency = <150000000>; 294 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 295 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 296 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 297 fifo-depth = <0x100>; 298 power-domains = <&power RK3399_PD_SDIOAUDIO>; 299 resets = <&cru SRST_SDIO0>; 300 reset-names = "reset"; 301 status = "disabled"; 302 }; 303 304 sdmmc: dwmmc@fe320000 { 305 compatible = "rockchip,rk3399-dw-mshc", 306 "rockchip,rk3288-dw-mshc"; 307 reg = <0x0 0xfe320000 0x0 0x4000>; 308 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 309 max-frequency = <150000000>; 310 assigned-clocks = <&cru HCLK_SD>; 311 assigned-clock-rates = <200000000>; 312 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 313 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 314 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 315 fifo-depth = <0x100>; 316 power-domains = <&power RK3399_PD_SD>; 317 resets = <&cru SRST_SDMMC>; 318 reset-names = "reset"; 319 status = "disabled"; 320 }; 321 322 sdhci: sdhci@fe330000 { 323 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 324 reg = <0x0 0xfe330000 0x0 0x10000>; 325 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 326 arasan,soc-ctl-syscon = <&grf>; 327 assigned-clocks = <&cru SCLK_EMMC>; 328 assigned-clock-rates = <200000000>; 329 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 330 clock-names = "clk_xin", "clk_ahb"; 331 clock-output-names = "emmc_cardclock"; 332 #clock-cells = <0>; 333 phys = <&emmc_phy>; 334 phy-names = "phy_arasan"; 335 power-domains = <&power RK3399_PD_EMMC>; 336 status = "disabled"; 337 }; 338 339 usb_host0_ehci: usb@fe380000 { 340 compatible = "generic-ehci"; 341 reg = <0x0 0xfe380000 0x0 0x20000>; 342 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 343 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 344 <&u2phy0>; 345 clock-names = "usbhost", "arbiter", 346 "utmi"; 347 phys = <&u2phy0_host>; 348 phy-names = "usb"; 349 status = "disabled"; 350 }; 351 352 usb_host0_ohci: usb@fe3a0000 { 353 compatible = "generic-ohci"; 354 reg = <0x0 0xfe3a0000 0x0 0x20000>; 355 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 356 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 357 <&u2phy0>; 358 clock-names = "usbhost", "arbiter", 359 "utmi"; 360 phys = <&u2phy0_host>; 361 phy-names = "usb"; 362 status = "disabled"; 363 }; 364 365 usb_host1_ehci: usb@fe3c0000 { 366 compatible = "generic-ehci"; 367 reg = <0x0 0xfe3c0000 0x0 0x20000>; 368 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 369 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 370 <&u2phy1>; 371 clock-names = "usbhost", "arbiter", 372 "utmi"; 373 phys = <&u2phy1_host>; 374 phy-names = "usb"; 375 status = "disabled"; 376 }; 377 378 usb_host1_ohci: usb@fe3e0000 { 379 compatible = "generic-ohci"; 380 reg = <0x0 0xfe3e0000 0x0 0x20000>; 381 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 382 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 383 <&u2phy1>; 384 clock-names = "usbhost", "arbiter", 385 "utmi"; 386 phys = <&u2phy1_host>; 387 phy-names = "usb"; 388 status = "disabled"; 389 }; 390 391 usbdrd3_0: usb@fe800000 { 392 compatible = "rockchip,rk3399-dwc3"; 393 #address-cells = <2>; 394 #size-cells = <2>; 395 ranges; 396 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 397 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 398 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 399 clock-names = "ref_clk", "suspend_clk", 400 "bus_clk", "aclk_usb3_rksoc_axi_perf", 401 "aclk_usb3", "grf_clk"; 402 resets = <&cru SRST_A_USB3_OTG0>; 403 reset-names = "usb3-otg"; 404 status = "disabled"; 405 406 usbdrd_dwc3_0: dwc3 { 407 compatible = "snps,dwc3"; 408 reg = <0x0 0xfe800000 0x0 0x100000>; 409 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 410 dr_mode = "otg"; 411 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 412 phy-names = "usb2-phy", "usb3-phy"; 413 phy_type = "utmi_wide"; 414 snps,dis_enblslpm_quirk; 415 snps,dis-u2-freeclk-exists-quirk; 416 snps,dis_u2_susphy_quirk; 417 snps,dis-del-phy-power-chg-quirk; 418 snps,dis-tx-ipgap-linecheck-quirk; 419 power-domains = <&power RK3399_PD_USB3>; 420 status = "disabled"; 421 }; 422 }; 423 424 usbdrd3_1: usb@fe900000 { 425 compatible = "rockchip,rk3399-dwc3"; 426 #address-cells = <2>; 427 #size-cells = <2>; 428 ranges; 429 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 430 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 431 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 432 clock-names = "ref_clk", "suspend_clk", 433 "bus_clk", "aclk_usb3_rksoc_axi_perf", 434 "aclk_usb3", "grf_clk"; 435 resets = <&cru SRST_A_USB3_OTG1>; 436 reset-names = "usb3-otg"; 437 status = "disabled"; 438 439 usbdrd_dwc3_1: dwc3 { 440 compatible = "snps,dwc3"; 441 reg = <0x0 0xfe900000 0x0 0x100000>; 442 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 443 dr_mode = "otg"; 444 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 445 phy-names = "usb2-phy", "usb3-phy"; 446 phy_type = "utmi_wide"; 447 snps,dis_enblslpm_quirk; 448 snps,dis-u2-freeclk-exists-quirk; 449 snps,dis_u2_susphy_quirk; 450 snps,dis-del-phy-power-chg-quirk; 451 snps,dis-tx-ipgap-linecheck-quirk; 452 power-domains = <&power RK3399_PD_USB3>; 453 status = "disabled"; 454 }; 455 }; 456 457 cdn_dp: dp@fec00000 { 458 compatible = "rockchip,rk3399-cdn-dp"; 459 reg = <0x0 0xfec00000 0x0 0x100000>; 460 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 461 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 462 assigned-clock-rates = <100000000>, <200000000>; 463 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 464 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 465 clock-names = "core-clk", "pclk", "spdif", "grf"; 466 phys = <&tcphy0_dp>, <&tcphy1_dp>; 467 power-domains = <&power RK3399_PD_HDCP>; 468 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 469 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 470 reset-names = "spdif", "dptx", "apb", "core"; 471 rockchip,grf = <&grf>; 472 #sound-dai-cells = <1>; 473 status = "disabled"; 474 475 ports { 476 dp_in: port { 477 #address-cells = <1>; 478 #size-cells = <0>; 479 480 dp_in_vopb: endpoint@0 { 481 reg = <0>; 482 remote-endpoint = <&vopb_out_dp>; 483 }; 484 485 dp_in_vopl: endpoint@1 { 486 reg = <1>; 487 remote-endpoint = <&vopl_out_dp>; 488 }; 489 }; 490 }; 491 }; 492 493 gic: interrupt-controller@fee00000 { 494 compatible = "arm,gic-v3"; 495 #interrupt-cells = <4>; 496 #address-cells = <2>; 497 #size-cells = <2>; 498 ranges; 499 interrupt-controller; 500 501 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 502 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 503 <0x0 0xfff00000 0 0x10000>, /* GICC */ 504 <0x0 0xfff10000 0 0x10000>, /* GICH */ 505 <0x0 0xfff20000 0 0x10000>; /* GICV */ 506 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 507 its: interrupt-controller@fee20000 { 508 compatible = "arm,gic-v3-its"; 509 msi-controller; 510 reg = <0x0 0xfee20000 0x0 0x20000>; 511 }; 512 513 ppi-partitions { 514 ppi_cluster0: interrupt-partition-0 { 515 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 516 }; 517 518 ppi_cluster1: interrupt-partition-1 { 519 affinity = <&cpu_b0 &cpu_b1>; 520 }; 521 }; 522 }; 523 524 saradc: saradc@ff100000 { 525 compatible = "rockchip,rk3399-saradc"; 526 reg = <0x0 0xff100000 0x0 0x100>; 527 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 528 #io-channel-cells = <1>; 529 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 530 clock-names = "saradc", "apb_pclk"; 531 resets = <&cru SRST_P_SARADC>; 532 reset-names = "saradc-apb"; 533 status = "disabled"; 534 }; 535 536 i2c1: i2c@ff110000 { 537 compatible = "rockchip,rk3399-i2c"; 538 reg = <0x0 0xff110000 0x0 0x1000>; 539 assigned-clocks = <&cru SCLK_I2C1>; 540 assigned-clock-rates = <200000000>; 541 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 542 clock-names = "i2c", "pclk"; 543 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 544 pinctrl-names = "default"; 545 pinctrl-0 = <&i2c1_xfer>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 status = "disabled"; 549 }; 550 551 i2c2: i2c@ff120000 { 552 compatible = "rockchip,rk3399-i2c"; 553 reg = <0x0 0xff120000 0x0 0x1000>; 554 assigned-clocks = <&cru SCLK_I2C2>; 555 assigned-clock-rates = <200000000>; 556 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 557 clock-names = "i2c", "pclk"; 558 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 559 pinctrl-names = "default"; 560 pinctrl-0 = <&i2c2_xfer>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 status = "disabled"; 564 }; 565 566 i2c3: i2c@ff130000 { 567 compatible = "rockchip,rk3399-i2c"; 568 reg = <0x0 0xff130000 0x0 0x1000>; 569 assigned-clocks = <&cru SCLK_I2C3>; 570 assigned-clock-rates = <200000000>; 571 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 572 clock-names = "i2c", "pclk"; 573 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 574 pinctrl-names = "default"; 575 pinctrl-0 = <&i2c3_xfer>; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 status = "disabled"; 579 }; 580 581 i2c5: i2c@ff140000 { 582 compatible = "rockchip,rk3399-i2c"; 583 reg = <0x0 0xff140000 0x0 0x1000>; 584 assigned-clocks = <&cru SCLK_I2C5>; 585 assigned-clock-rates = <200000000>; 586 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 587 clock-names = "i2c", "pclk"; 588 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 589 pinctrl-names = "default"; 590 pinctrl-0 = <&i2c5_xfer>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 status = "disabled"; 594 }; 595 596 i2c6: i2c@ff150000 { 597 compatible = "rockchip,rk3399-i2c"; 598 reg = <0x0 0xff150000 0x0 0x1000>; 599 assigned-clocks = <&cru SCLK_I2C6>; 600 assigned-clock-rates = <200000000>; 601 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 602 clock-names = "i2c", "pclk"; 603 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&i2c6_xfer>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 status = "disabled"; 609 }; 610 611 i2c7: i2c@ff160000 { 612 compatible = "rockchip,rk3399-i2c"; 613 reg = <0x0 0xff160000 0x0 0x1000>; 614 assigned-clocks = <&cru SCLK_I2C7>; 615 assigned-clock-rates = <200000000>; 616 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 617 clock-names = "i2c", "pclk"; 618 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&i2c7_xfer>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 status = "disabled"; 624 }; 625 626 uart0: serial@ff180000 { 627 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 628 reg = <0x0 0xff180000 0x0 0x100>; 629 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 630 clock-names = "baudclk", "apb_pclk"; 631 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 632 reg-shift = <2>; 633 reg-io-width = <4>; 634 pinctrl-names = "default"; 635 pinctrl-0 = <&uart0_xfer>; 636 status = "disabled"; 637 }; 638 639 uart1: serial@ff190000 { 640 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 641 reg = <0x0 0xff190000 0x0 0x100>; 642 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 643 clock-names = "baudclk", "apb_pclk"; 644 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 645 reg-shift = <2>; 646 reg-io-width = <4>; 647 pinctrl-names = "default"; 648 pinctrl-0 = <&uart1_xfer>; 649 status = "disabled"; 650 }; 651 652 uart2: serial@ff1a0000 { 653 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 654 reg = <0x0 0xff1a0000 0x0 0x100>; 655 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 656 clock-names = "baudclk", "apb_pclk"; 657 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 658 reg-shift = <2>; 659 reg-io-width = <4>; 660 pinctrl-names = "default"; 661 pinctrl-0 = <&uart2c_xfer>; 662 status = "disabled"; 663 }; 664 665 uart3: serial@ff1b0000 { 666 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 667 reg = <0x0 0xff1b0000 0x0 0x100>; 668 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 669 clock-names = "baudclk", "apb_pclk"; 670 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 671 reg-shift = <2>; 672 reg-io-width = <4>; 673 pinctrl-names = "default"; 674 pinctrl-0 = <&uart3_xfer>; 675 status = "disabled"; 676 }; 677 678 spi0: spi@ff1c0000 { 679 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 680 reg = <0x0 0xff1c0000 0x0 0x1000>; 681 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 682 clock-names = "spiclk", "apb_pclk"; 683 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 684 pinctrl-names = "default"; 685 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 686 #address-cells = <1>; 687 #size-cells = <0>; 688 status = "disabled"; 689 }; 690 691 spi1: spi@ff1d0000 { 692 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 693 reg = <0x0 0xff1d0000 0x0 0x1000>; 694 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 695 clock-names = "spiclk", "apb_pclk"; 696 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 697 pinctrl-names = "default"; 698 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 status = "disabled"; 702 }; 703 704 spi2: spi@ff1e0000 { 705 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 706 reg = <0x0 0xff1e0000 0x0 0x1000>; 707 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 708 clock-names = "spiclk", "apb_pclk"; 709 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 710 pinctrl-names = "default"; 711 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 status = "disabled"; 715 }; 716 717 spi4: spi@ff1f0000 { 718 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 719 reg = <0x0 0xff1f0000 0x0 0x1000>; 720 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 721 clock-names = "spiclk", "apb_pclk"; 722 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 723 pinctrl-names = "default"; 724 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 725 #address-cells = <1>; 726 #size-cells = <0>; 727 status = "disabled"; 728 }; 729 730 spi5: spi@ff200000 { 731 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 732 reg = <0x0 0xff200000 0x0 0x1000>; 733 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 734 clock-names = "spiclk", "apb_pclk"; 735 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 736 pinctrl-names = "default"; 737 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 738 power-domains = <&power RK3399_PD_SDIOAUDIO>; 739 #address-cells = <1>; 740 #size-cells = <0>; 741 status = "disabled"; 742 }; 743 744 thermal_zones: thermal-zones { 745 cpu_thermal: cpu { 746 polling-delay-passive = <100>; 747 polling-delay = <1000>; 748 749 thermal-sensors = <&tsadc 0>; 750 751 trips { 752 cpu_alert0: cpu_alert0 { 753 temperature = <70000>; 754 hysteresis = <2000>; 755 type = "passive"; 756 }; 757 cpu_alert1: cpu_alert1 { 758 temperature = <75000>; 759 hysteresis = <2000>; 760 type = "passive"; 761 }; 762 cpu_crit: cpu_crit { 763 temperature = <95000>; 764 hysteresis = <2000>; 765 type = "critical"; 766 }; 767 }; 768 769 cooling-maps { 770 map0 { 771 trip = <&cpu_alert0>; 772 cooling-device = 773 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 774 }; 775 map1 { 776 trip = <&cpu_alert1>; 777 cooling-device = 778 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 779 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 780 }; 781 }; 782 }; 783 784 gpu_thermal: gpu { 785 polling-delay-passive = <100>; 786 polling-delay = <1000>; 787 788 thermal-sensors = <&tsadc 1>; 789 790 trips { 791 gpu_alert0: gpu_alert0 { 792 temperature = <75000>; 793 hysteresis = <2000>; 794 type = "passive"; 795 }; 796 gpu_crit: gpu_crit { 797 temperature = <95000>; 798 hysteresis = <2000>; 799 type = "critical"; 800 }; 801 }; 802 803 cooling-maps { 804 map0 { 805 trip = <&gpu_alert0>; 806 cooling-device = 807 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 808 }; 809 }; 810 }; 811 }; 812 813 tsadc: tsadc@ff260000 { 814 compatible = "rockchip,rk3399-tsadc"; 815 reg = <0x0 0xff260000 0x0 0x100>; 816 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 817 assigned-clocks = <&cru SCLK_TSADC>; 818 assigned-clock-rates = <750000>; 819 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 820 clock-names = "tsadc", "apb_pclk"; 821 resets = <&cru SRST_TSADC>; 822 reset-names = "tsadc-apb"; 823 rockchip,grf = <&grf>; 824 rockchip,hw-tshut-temp = <95000>; 825 pinctrl-names = "init", "default", "sleep"; 826 pinctrl-0 = <&otp_gpio>; 827 pinctrl-1 = <&otp_out>; 828 pinctrl-2 = <&otp_gpio>; 829 #thermal-sensor-cells = <1>; 830 status = "disabled"; 831 }; 832 833 qos_emmc: qos@ffa58000 { 834 compatible = "syscon"; 835 reg = <0x0 0xffa58000 0x0 0x20>; 836 }; 837 838 qos_gmac: qos@ffa5c000 { 839 compatible = "syscon"; 840 reg = <0x0 0xffa5c000 0x0 0x20>; 841 }; 842 843 qos_pcie: qos@ffa60080 { 844 compatible = "syscon"; 845 reg = <0x0 0xffa60080 0x0 0x20>; 846 }; 847 848 qos_usb_host0: qos@ffa60100 { 849 compatible = "syscon"; 850 reg = <0x0 0xffa60100 0x0 0x20>; 851 }; 852 853 qos_usb_host1: qos@ffa60180 { 854 compatible = "syscon"; 855 reg = <0x0 0xffa60180 0x0 0x20>; 856 }; 857 858 qos_usb_otg0: qos@ffa70000 { 859 compatible = "syscon"; 860 reg = <0x0 0xffa70000 0x0 0x20>; 861 }; 862 863 qos_usb_otg1: qos@ffa70080 { 864 compatible = "syscon"; 865 reg = <0x0 0xffa70080 0x0 0x20>; 866 }; 867 868 qos_sd: qos@ffa74000 { 869 compatible = "syscon"; 870 reg = <0x0 0xffa74000 0x0 0x20>; 871 }; 872 873 qos_sdioaudio: qos@ffa76000 { 874 compatible = "syscon"; 875 reg = <0x0 0xffa76000 0x0 0x20>; 876 }; 877 878 qos_hdcp: qos@ffa90000 { 879 compatible = "syscon"; 880 reg = <0x0 0xffa90000 0x0 0x20>; 881 }; 882 883 qos_iep: qos@ffa98000 { 884 compatible = "syscon"; 885 reg = <0x0 0xffa98000 0x0 0x20>; 886 }; 887 888 qos_isp0_m0: qos@ffaa0000 { 889 compatible = "syscon"; 890 reg = <0x0 0xffaa0000 0x0 0x20>; 891 }; 892 893 qos_isp0_m1: qos@ffaa0080 { 894 compatible = "syscon"; 895 reg = <0x0 0xffaa0080 0x0 0x20>; 896 }; 897 898 qos_isp1_m0: qos@ffaa8000 { 899 compatible = "syscon"; 900 reg = <0x0 0xffaa8000 0x0 0x20>; 901 }; 902 903 qos_isp1_m1: qos@ffaa8080 { 904 compatible = "syscon"; 905 reg = <0x0 0xffaa8080 0x0 0x20>; 906 }; 907 908 qos_rga_r: qos@ffab0000 { 909 compatible = "syscon"; 910 reg = <0x0 0xffab0000 0x0 0x20>; 911 }; 912 913 qos_rga_w: qos@ffab0080 { 914 compatible = "syscon"; 915 reg = <0x0 0xffab0080 0x0 0x20>; 916 }; 917 918 qos_video_m0: qos@ffab8000 { 919 compatible = "syscon"; 920 reg = <0x0 0xffab8000 0x0 0x20>; 921 }; 922 923 qos_video_m1_r: qos@ffac0000 { 924 compatible = "syscon"; 925 reg = <0x0 0xffac0000 0x0 0x20>; 926 }; 927 928 qos_video_m1_w: qos@ffac0080 { 929 compatible = "syscon"; 930 reg = <0x0 0xffac0080 0x0 0x20>; 931 }; 932 933 qos_vop_big_r: qos@ffac8000 { 934 compatible = "syscon"; 935 reg = <0x0 0xffac8000 0x0 0x20>; 936 }; 937 938 qos_vop_big_w: qos@ffac8080 { 939 compatible = "syscon"; 940 reg = <0x0 0xffac8080 0x0 0x20>; 941 }; 942 943 qos_vop_little: qos@ffad0000 { 944 compatible = "syscon"; 945 reg = <0x0 0xffad0000 0x0 0x20>; 946 }; 947 948 qos_perihp: qos@ffad8080 { 949 compatible = "syscon"; 950 reg = <0x0 0xffad8080 0x0 0x20>; 951 }; 952 953 qos_gpu: qos@ffae0000 { 954 compatible = "syscon"; 955 reg = <0x0 0xffae0000 0x0 0x20>; 956 }; 957 958 pmu: power-management@ff310000 { 959 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 960 reg = <0x0 0xff310000 0x0 0x1000>; 961 962 /* 963 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 964 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 965 * Some of the power domains are grouped together for every 966 * voltage domain. 967 * The detail contents as below. 968 */ 969 power: power-controller { 970 compatible = "rockchip,rk3399-power-controller"; 971 #power-domain-cells = <1>; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 975 /* These power domains are grouped by VD_CENTER */ 976 pd_iep@RK3399_PD_IEP { 977 reg = <RK3399_PD_IEP>; 978 clocks = <&cru ACLK_IEP>, 979 <&cru HCLK_IEP>; 980 pm_qos = <&qos_iep>; 981 }; 982 pd_rga@RK3399_PD_RGA { 983 reg = <RK3399_PD_RGA>; 984 clocks = <&cru ACLK_RGA>, 985 <&cru HCLK_RGA>; 986 pm_qos = <&qos_rga_r>, 987 <&qos_rga_w>; 988 }; 989 pd_vcodec@RK3399_PD_VCODEC { 990 reg = <RK3399_PD_VCODEC>; 991 clocks = <&cru ACLK_VCODEC>, 992 <&cru HCLK_VCODEC>; 993 pm_qos = <&qos_video_m0>; 994 }; 995 pd_vdu@RK3399_PD_VDU { 996 reg = <RK3399_PD_VDU>; 997 clocks = <&cru ACLK_VDU>, 998 <&cru HCLK_VDU>; 999 pm_qos = <&qos_video_m1_r>, 1000 <&qos_video_m1_w>; 1001 }; 1002 1003 /* These power domains are grouped by VD_GPU */ 1004 pd_gpu@RK3399_PD_GPU { 1005 reg = <RK3399_PD_GPU>; 1006 clocks = <&cru ACLK_GPU>; 1007 pm_qos = <&qos_gpu>; 1008 }; 1009 1010 /* These power domains are grouped by VD_LOGIC */ 1011 pd_edp@RK3399_PD_EDP { 1012 reg = <RK3399_PD_EDP>; 1013 clocks = <&cru PCLK_EDP_CTRL>; 1014 }; 1015 pd_emmc@RK3399_PD_EMMC { 1016 reg = <RK3399_PD_EMMC>; 1017 clocks = <&cru ACLK_EMMC>; 1018 pm_qos = <&qos_emmc>; 1019 }; 1020 pd_gmac@RK3399_PD_GMAC { 1021 reg = <RK3399_PD_GMAC>; 1022 clocks = <&cru ACLK_GMAC>, 1023 <&cru PCLK_GMAC>; 1024 pm_qos = <&qos_gmac>; 1025 }; 1026 pd_sd@RK3399_PD_SD { 1027 reg = <RK3399_PD_SD>; 1028 clocks = <&cru HCLK_SDMMC>, 1029 <&cru SCLK_SDMMC>; 1030 pm_qos = <&qos_sd>; 1031 }; 1032 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 1033 reg = <RK3399_PD_SDIOAUDIO>; 1034 clocks = <&cru HCLK_SDIO>; 1035 pm_qos = <&qos_sdioaudio>; 1036 }; 1037 pd_usb3@RK3399_PD_USB3 { 1038 reg = <RK3399_PD_USB3>; 1039 clocks = <&cru ACLK_USB3>; 1040 pm_qos = <&qos_usb_otg0>, 1041 <&qos_usb_otg1>; 1042 }; 1043 pd_vio@RK3399_PD_VIO { 1044 reg = <RK3399_PD_VIO>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 1048 pd_hdcp@RK3399_PD_HDCP { 1049 reg = <RK3399_PD_HDCP>; 1050 clocks = <&cru ACLK_HDCP>, 1051 <&cru HCLK_HDCP>, 1052 <&cru PCLK_HDCP>; 1053 pm_qos = <&qos_hdcp>; 1054 }; 1055 pd_isp0@RK3399_PD_ISP0 { 1056 reg = <RK3399_PD_ISP0>; 1057 clocks = <&cru ACLK_ISP0>, 1058 <&cru HCLK_ISP0>; 1059 pm_qos = <&qos_isp0_m0>, 1060 <&qos_isp0_m1>; 1061 }; 1062 pd_isp1@RK3399_PD_ISP1 { 1063 reg = <RK3399_PD_ISP1>; 1064 clocks = <&cru ACLK_ISP1>, 1065 <&cru HCLK_ISP1>; 1066 pm_qos = <&qos_isp1_m0>, 1067 <&qos_isp1_m1>; 1068 }; 1069 pd_tcpc0@RK3399_PD_TCPC0 { 1070 reg = <RK3399_PD_TCPD0>; 1071 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1072 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1073 }; 1074 pd_tcpc1@RK3399_PD_TCPC1 { 1075 reg = <RK3399_PD_TCPD1>; 1076 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1077 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1078 }; 1079 pd_vo@RK3399_PD_VO { 1080 reg = <RK3399_PD_VO>; 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 1084 pd_vopb@RK3399_PD_VOPB { 1085 reg = <RK3399_PD_VOPB>; 1086 clocks = <&cru ACLK_VOP0>, 1087 <&cru HCLK_VOP0>; 1088 pm_qos = <&qos_vop_big_r>, 1089 <&qos_vop_big_w>; 1090 }; 1091 pd_vopl@RK3399_PD_VOPL { 1092 reg = <RK3399_PD_VOPL>; 1093 clocks = <&cru ACLK_VOP1>, 1094 <&cru HCLK_VOP1>; 1095 pm_qos = <&qos_vop_little>; 1096 }; 1097 }; 1098 }; 1099 }; 1100 }; 1101 1102 pmugrf: syscon@ff320000 { 1103 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1104 reg = <0x0 0xff320000 0x0 0x1000>; 1105 #address-cells = <1>; 1106 #size-cells = <1>; 1107 1108 pmu_io_domains: io-domains { 1109 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1110 status = "disabled"; 1111 }; 1112 }; 1113 1114 spi3: spi@ff350000 { 1115 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1116 reg = <0x0 0xff350000 0x0 0x1000>; 1117 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1118 clock-names = "spiclk", "apb_pclk"; 1119 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1120 pinctrl-names = "default"; 1121 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 status = "disabled"; 1125 }; 1126 1127 uart4: serial@ff370000 { 1128 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1129 reg = <0x0 0xff370000 0x0 0x100>; 1130 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1131 clock-names = "baudclk", "apb_pclk"; 1132 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1133 reg-shift = <2>; 1134 reg-io-width = <4>; 1135 pinctrl-names = "default"; 1136 pinctrl-0 = <&uart4_xfer>; 1137 status = "disabled"; 1138 }; 1139 1140 i2c0: i2c@ff3c0000 { 1141 compatible = "rockchip,rk3399-i2c"; 1142 reg = <0x0 0xff3c0000 0x0 0x1000>; 1143 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1144 assigned-clock-rates = <200000000>; 1145 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1146 clock-names = "i2c", "pclk"; 1147 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1148 pinctrl-names = "default"; 1149 pinctrl-0 = <&i2c0_xfer>; 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 status = "disabled"; 1153 }; 1154 1155 i2c4: i2c@ff3d0000 { 1156 compatible = "rockchip,rk3399-i2c"; 1157 reg = <0x0 0xff3d0000 0x0 0x1000>; 1158 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1159 assigned-clock-rates = <200000000>; 1160 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1161 clock-names = "i2c", "pclk"; 1162 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&i2c4_xfer>; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 status = "disabled"; 1168 }; 1169 1170 i2c8: i2c@ff3e0000 { 1171 compatible = "rockchip,rk3399-i2c"; 1172 reg = <0x0 0xff3e0000 0x0 0x1000>; 1173 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1174 assigned-clock-rates = <200000000>; 1175 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1176 clock-names = "i2c", "pclk"; 1177 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1178 pinctrl-names = "default"; 1179 pinctrl-0 = <&i2c8_xfer>; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 status = "disabled"; 1183 }; 1184 1185 pwm0: pwm@ff420000 { 1186 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1187 reg = <0x0 0xff420000 0x0 0x10>; 1188 #pwm-cells = <3>; 1189 pinctrl-names = "default"; 1190 pinctrl-0 = <&pwm0_pin>; 1191 clocks = <&pmucru PCLK_RKPWM_PMU>; 1192 clock-names = "pwm"; 1193 status = "disabled"; 1194 }; 1195 1196 pwm1: pwm@ff420010 { 1197 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1198 reg = <0x0 0xff420010 0x0 0x10>; 1199 #pwm-cells = <3>; 1200 pinctrl-names = "default"; 1201 pinctrl-0 = <&pwm1_pin>; 1202 clocks = <&pmucru PCLK_RKPWM_PMU>; 1203 clock-names = "pwm"; 1204 status = "disabled"; 1205 }; 1206 1207 pwm2: pwm@ff420020 { 1208 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1209 reg = <0x0 0xff420020 0x0 0x10>; 1210 #pwm-cells = <3>; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&pwm2_pin>; 1213 clocks = <&pmucru PCLK_RKPWM_PMU>; 1214 clock-names = "pwm"; 1215 status = "disabled"; 1216 }; 1217 1218 pwm3: pwm@ff420030 { 1219 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1220 reg = <0x0 0xff420030 0x0 0x10>; 1221 #pwm-cells = <3>; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&pwm3a_pin>; 1224 clocks = <&pmucru PCLK_RKPWM_PMU>; 1225 clock-names = "pwm"; 1226 status = "disabled"; 1227 }; 1228 1229 vpu_mmu: iommu@ff650800 { 1230 compatible = "rockchip,iommu"; 1231 reg = <0x0 0xff650800 0x0 0x40>; 1232 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1233 interrupt-names = "vpu_mmu"; 1234 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1235 clock-names = "aclk", "iface"; 1236 #iommu-cells = <0>; 1237 status = "disabled"; 1238 }; 1239 1240 vdec_mmu: iommu@ff660480 { 1241 compatible = "rockchip,iommu"; 1242 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1243 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1244 interrupt-names = "vdec_mmu"; 1245 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1246 clock-names = "aclk", "iface"; 1247 #iommu-cells = <0>; 1248 status = "disabled"; 1249 }; 1250 1251 iep_mmu: iommu@ff670800 { 1252 compatible = "rockchip,iommu"; 1253 reg = <0x0 0xff670800 0x0 0x40>; 1254 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1255 interrupt-names = "iep_mmu"; 1256 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1257 clock-names = "aclk", "iface"; 1258 #iommu-cells = <0>; 1259 status = "disabled"; 1260 }; 1261 1262 rga: rga@ff680000 { 1263 compatible = "rockchip,rk3399-rga"; 1264 reg = <0x0 0xff680000 0x0 0x10000>; 1265 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1266 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1267 clock-names = "aclk", "hclk", "sclk"; 1268 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1269 reset-names = "core", "axi", "ahb"; 1270 power-domains = <&power RK3399_PD_RGA>; 1271 }; 1272 1273 efuse0: efuse@ff690000 { 1274 compatible = "rockchip,rk3399-efuse"; 1275 reg = <0x0 0xff690000 0x0 0x80>; 1276 #address-cells = <1>; 1277 #size-cells = <1>; 1278 clocks = <&cru PCLK_EFUSE1024NS>; 1279 clock-names = "pclk_efuse"; 1280 1281 /* Data cells */ 1282 cpu_id: cpu-id@7 { 1283 reg = <0x07 0x10>; 1284 }; 1285 cpub_leakage: cpu-leakage@17 { 1286 reg = <0x17 0x1>; 1287 }; 1288 gpu_leakage: gpu-leakage@18 { 1289 reg = <0x18 0x1>; 1290 }; 1291 center_leakage: center-leakage@19 { 1292 reg = <0x19 0x1>; 1293 }; 1294 cpul_leakage: cpu-leakage@1a { 1295 reg = <0x1a 0x1>; 1296 }; 1297 logic_leakage: logic-leakage@1b { 1298 reg = <0x1b 0x1>; 1299 }; 1300 wafer_info: wafer-info@1c { 1301 reg = <0x1c 0x1>; 1302 }; 1303 }; 1304 1305 pmucru: pmu-clock-controller@ff750000 { 1306 compatible = "rockchip,rk3399-pmucru"; 1307 reg = <0x0 0xff750000 0x0 0x1000>; 1308 rockchip,grf = <&pmugrf>; 1309 #clock-cells = <1>; 1310 #reset-cells = <1>; 1311 assigned-clocks = <&pmucru PLL_PPLL>; 1312 assigned-clock-rates = <676000000>; 1313 }; 1314 1315 cru: clock-controller@ff760000 { 1316 compatible = "rockchip,rk3399-cru"; 1317 reg = <0x0 0xff760000 0x0 0x1000>; 1318 rockchip,grf = <&grf>; 1319 #clock-cells = <1>; 1320 #reset-cells = <1>; 1321 assigned-clocks = 1322 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1323 <&cru PLL_NPLL>, 1324 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1325 <&cru PCLK_PERIHP>, 1326 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1327 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1328 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1329 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1330 <&cru ACLK_GIC_PRE>, 1331 <&cru PCLK_DDR>; 1332 assigned-clock-rates = 1333 <594000000>, <800000000>, 1334 <1000000000>, 1335 <150000000>, <75000000>, 1336 <37500000>, 1337 <100000000>, <100000000>, 1338 <50000000>, <600000000>, 1339 <100000000>, <50000000>, 1340 <400000000>, <400000000>, 1341 <200000000>, 1342 <200000000>; 1343 }; 1344 1345 grf: syscon@ff770000 { 1346 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1347 reg = <0x0 0xff770000 0x0 0x10000>; 1348 #address-cells = <1>; 1349 #size-cells = <1>; 1350 1351 io_domains: io-domains { 1352 compatible = "rockchip,rk3399-io-voltage-domain"; 1353 status = "disabled"; 1354 }; 1355 1356 u2phy0: usb2-phy@e450 { 1357 compatible = "rockchip,rk3399-usb2phy"; 1358 reg = <0xe450 0x10>; 1359 clocks = <&cru SCLK_USB2PHY0_REF>; 1360 clock-names = "phyclk"; 1361 #clock-cells = <0>; 1362 clock-output-names = "clk_usbphy0_480m"; 1363 status = "disabled"; 1364 1365 u2phy0_host: host-port { 1366 #phy-cells = <0>; 1367 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1368 interrupt-names = "linestate"; 1369 status = "disabled"; 1370 }; 1371 1372 u2phy0_otg: otg-port { 1373 #phy-cells = <0>; 1374 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1375 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1376 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1377 interrupt-names = "otg-bvalid", "otg-id", 1378 "linestate"; 1379 status = "disabled"; 1380 }; 1381 }; 1382 1383 u2phy1: usb2-phy@e460 { 1384 compatible = "rockchip,rk3399-usb2phy"; 1385 reg = <0xe460 0x10>; 1386 clocks = <&cru SCLK_USB2PHY1_REF>; 1387 clock-names = "phyclk"; 1388 #clock-cells = <0>; 1389 clock-output-names = "clk_usbphy1_480m"; 1390 status = "disabled"; 1391 1392 u2phy1_host: host-port { 1393 #phy-cells = <0>; 1394 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1395 interrupt-names = "linestate"; 1396 status = "disabled"; 1397 }; 1398 1399 u2phy1_otg: otg-port { 1400 #phy-cells = <0>; 1401 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1402 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1403 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1404 interrupt-names = "otg-bvalid", "otg-id", 1405 "linestate"; 1406 status = "disabled"; 1407 }; 1408 }; 1409 1410 emmc_phy: phy@f780 { 1411 compatible = "rockchip,rk3399-emmc-phy"; 1412 reg = <0xf780 0x24>; 1413 clocks = <&sdhci>; 1414 clock-names = "emmcclk"; 1415 #phy-cells = <0>; 1416 status = "disabled"; 1417 }; 1418 1419 pcie_phy: pcie-phy { 1420 compatible = "rockchip,rk3399-pcie-phy"; 1421 clocks = <&cru SCLK_PCIEPHY_REF>; 1422 clock-names = "refclk"; 1423 #phy-cells = <1>; 1424 resets = <&cru SRST_PCIEPHY>; 1425 reset-names = "phy"; 1426 status = "disabled"; 1427 }; 1428 }; 1429 1430 tcphy0: phy@ff7c0000 { 1431 compatible = "rockchip,rk3399-typec-phy"; 1432 reg = <0x0 0xff7c0000 0x0 0x40000>; 1433 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1434 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1435 clock-names = "tcpdcore", "tcpdphy-ref"; 1436 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1437 assigned-clock-rates = <50000000>; 1438 power-domains = <&power RK3399_PD_TCPD0>; 1439 resets = <&cru SRST_UPHY0>, 1440 <&cru SRST_UPHY0_PIPE_L00>, 1441 <&cru SRST_P_UPHY0_TCPHY>; 1442 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1443 rockchip,grf = <&grf>; 1444 status = "disabled"; 1445 1446 tcphy0_dp: dp-port { 1447 #phy-cells = <0>; 1448 }; 1449 1450 tcphy0_usb3: usb3-port { 1451 #phy-cells = <0>; 1452 }; 1453 }; 1454 1455 tcphy1: phy@ff800000 { 1456 compatible = "rockchip,rk3399-typec-phy"; 1457 reg = <0x0 0xff800000 0x0 0x40000>; 1458 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1459 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1460 clock-names = "tcpdcore", "tcpdphy-ref"; 1461 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1462 assigned-clock-rates = <50000000>; 1463 power-domains = <&power RK3399_PD_TCPD1>; 1464 resets = <&cru SRST_UPHY1>, 1465 <&cru SRST_UPHY1_PIPE_L00>, 1466 <&cru SRST_P_UPHY1_TCPHY>; 1467 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1468 rockchip,grf = <&grf>; 1469 status = "disabled"; 1470 1471 tcphy1_dp: dp-port { 1472 #phy-cells = <0>; 1473 }; 1474 1475 tcphy1_usb3: usb3-port { 1476 #phy-cells = <0>; 1477 }; 1478 }; 1479 1480 watchdog@ff848000 { 1481 compatible = "snps,dw-wdt"; 1482 reg = <0x0 0xff848000 0x0 0x100>; 1483 clocks = <&cru PCLK_WDT>; 1484 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1485 }; 1486 1487 rktimer: rktimer@ff850000 { 1488 compatible = "rockchip,rk3399-timer"; 1489 reg = <0x0 0xff850000 0x0 0x1000>; 1490 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1491 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1492 clock-names = "pclk", "timer"; 1493 }; 1494 1495 spdif: spdif@ff870000 { 1496 compatible = "rockchip,rk3399-spdif"; 1497 reg = <0x0 0xff870000 0x0 0x1000>; 1498 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1499 dmas = <&dmac_bus 7>; 1500 dma-names = "tx"; 1501 clock-names = "mclk", "hclk"; 1502 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1503 pinctrl-names = "default"; 1504 pinctrl-0 = <&spdif_bus>; 1505 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1506 #sound-dai-cells = <0>; 1507 status = "disabled"; 1508 }; 1509 1510 i2s0: i2s@ff880000 { 1511 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1512 reg = <0x0 0xff880000 0x0 0x1000>; 1513 rockchip,grf = <&grf>; 1514 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1515 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1516 dma-names = "tx", "rx"; 1517 clock-names = "i2s_clk", "i2s_hclk"; 1518 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1519 pinctrl-names = "default"; 1520 pinctrl-0 = <&i2s0_8ch_bus>; 1521 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1522 #sound-dai-cells = <0>; 1523 status = "disabled"; 1524 }; 1525 1526 i2s1: i2s@ff890000 { 1527 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1528 reg = <0x0 0xff890000 0x0 0x1000>; 1529 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1530 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1531 dma-names = "tx", "rx"; 1532 clock-names = "i2s_clk", "i2s_hclk"; 1533 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1534 pinctrl-names = "default"; 1535 pinctrl-0 = <&i2s1_2ch_bus>; 1536 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1537 #sound-dai-cells = <0>; 1538 status = "disabled"; 1539 }; 1540 1541 i2s2: i2s@ff8a0000 { 1542 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1543 reg = <0x0 0xff8a0000 0x0 0x1000>; 1544 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1545 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1546 dma-names = "tx", "rx"; 1547 clock-names = "i2s_clk", "i2s_hclk"; 1548 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1549 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1550 #sound-dai-cells = <0>; 1551 status = "disabled"; 1552 }; 1553 1554 vopl: vop@ff8f0000 { 1555 compatible = "rockchip,rk3399-vop-lit"; 1556 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1557 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1558 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1559 assigned-clock-rates = <400000000>, <100000000>; 1560 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1561 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1562 iommus = <&vopl_mmu>; 1563 power-domains = <&power RK3399_PD_VOPL>; 1564 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1565 reset-names = "axi", "ahb", "dclk"; 1566 status = "disabled"; 1567 1568 vopl_out: port { 1569 #address-cells = <1>; 1570 #size-cells = <0>; 1571 1572 vopl_out_mipi: endpoint@0 { 1573 reg = <0>; 1574 remote-endpoint = <&mipi_in_vopl>; 1575 }; 1576 1577 vopl_out_edp: endpoint@1 { 1578 reg = <1>; 1579 remote-endpoint = <&edp_in_vopl>; 1580 }; 1581 1582 vopl_out_hdmi: endpoint@2 { 1583 reg = <2>; 1584 remote-endpoint = <&hdmi_in_vopl>; 1585 }; 1586 1587 vopl_out_mipi1: endpoint@3 { 1588 reg = <3>; 1589 remote-endpoint = <&mipi1_in_vopl>; 1590 }; 1591 1592 vopl_out_dp: endpoint@4 { 1593 reg = <4>; 1594 remote-endpoint = <&dp_in_vopl>; 1595 }; 1596 }; 1597 }; 1598 1599 vopl_mmu: iommu@ff8f3f00 { 1600 compatible = "rockchip,iommu"; 1601 reg = <0x0 0xff8f3f00 0x0 0x100>; 1602 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1603 interrupt-names = "vopl_mmu"; 1604 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1605 clock-names = "aclk", "iface"; 1606 power-domains = <&power RK3399_PD_VOPL>; 1607 #iommu-cells = <0>; 1608 status = "disabled"; 1609 }; 1610 1611 vopb: vop@ff900000 { 1612 compatible = "rockchip,rk3399-vop-big"; 1613 reg = <0x0 0xff900000 0x0 0x3efc>; 1614 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1615 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1616 assigned-clock-rates = <400000000>, <100000000>; 1617 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1618 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1619 iommus = <&vopb_mmu>; 1620 power-domains = <&power RK3399_PD_VOPB>; 1621 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1622 reset-names = "axi", "ahb", "dclk"; 1623 status = "disabled"; 1624 1625 vopb_out: port { 1626 #address-cells = <1>; 1627 #size-cells = <0>; 1628 1629 vopb_out_edp: endpoint@0 { 1630 reg = <0>; 1631 remote-endpoint = <&edp_in_vopb>; 1632 }; 1633 1634 vopb_out_mipi: endpoint@1 { 1635 reg = <1>; 1636 remote-endpoint = <&mipi_in_vopb>; 1637 }; 1638 1639 vopb_out_hdmi: endpoint@2 { 1640 reg = <2>; 1641 remote-endpoint = <&hdmi_in_vopb>; 1642 }; 1643 1644 vopb_out_mipi1: endpoint@3 { 1645 reg = <3>; 1646 remote-endpoint = <&mipi1_in_vopb>; 1647 }; 1648 1649 vopb_out_dp: endpoint@4 { 1650 reg = <4>; 1651 remote-endpoint = <&dp_in_vopb>; 1652 }; 1653 }; 1654 }; 1655 1656 vopb_mmu: iommu@ff903f00 { 1657 compatible = "rockchip,iommu"; 1658 reg = <0x0 0xff903f00 0x0 0x100>; 1659 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1660 interrupt-names = "vopb_mmu"; 1661 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1662 clock-names = "aclk", "iface"; 1663 power-domains = <&power RK3399_PD_VOPB>; 1664 #iommu-cells = <0>; 1665 status = "disabled"; 1666 }; 1667 1668 isp0_mmu: iommu@ff914000 { 1669 compatible = "rockchip,iommu"; 1670 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1671 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1672 interrupt-names = "isp0_mmu"; 1673 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>; 1674 clock-names = "aclk", "iface"; 1675 #iommu-cells = <0>; 1676 rockchip,disable-mmu-reset; 1677 status = "disabled"; 1678 }; 1679 1680 isp1_mmu: iommu@ff924000 { 1681 compatible = "rockchip,iommu"; 1682 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1683 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1684 interrupt-names = "isp1_mmu"; 1685 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>; 1686 clock-names = "aclk", "iface"; 1687 #iommu-cells = <0>; 1688 rockchip,disable-mmu-reset; 1689 status = "disabled"; 1690 }; 1691 1692 hdmi_sound: hdmi-sound { 1693 compatible = "simple-audio-card"; 1694 simple-audio-card,format = "i2s"; 1695 simple-audio-card,mclk-fs = <256>; 1696 simple-audio-card,name = "hdmi-sound"; 1697 status = "disabled"; 1698 1699 simple-audio-card,cpu { 1700 sound-dai = <&i2s2>; 1701 }; 1702 simple-audio-card,codec { 1703 sound-dai = <&hdmi>; 1704 }; 1705 }; 1706 1707 hdmi: hdmi@ff940000 { 1708 compatible = "rockchip,rk3399-dw-hdmi"; 1709 reg = <0x0 0xff940000 0x0 0x20000>; 1710 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1711 clocks = <&cru PCLK_HDMI_CTRL>, 1712 <&cru SCLK_HDMI_SFR>, 1713 <&cru PLL_VPLL>, 1714 <&cru PCLK_VIO_GRF>, 1715 <&cru SCLK_HDMI_CEC>; 1716 clock-names = "iahb", "isfr", "vpll", "grf", "cec"; 1717 power-domains = <&power RK3399_PD_HDCP>; 1718 reg-io-width = <4>; 1719 rockchip,grf = <&grf>; 1720 #sound-dai-cells = <0>; 1721 status = "disabled"; 1722 1723 ports { 1724 hdmi_in: port { 1725 #address-cells = <1>; 1726 #size-cells = <0>; 1727 1728 hdmi_in_vopb: endpoint@0 { 1729 reg = <0>; 1730 remote-endpoint = <&vopb_out_hdmi>; 1731 }; 1732 hdmi_in_vopl: endpoint@1 { 1733 reg = <1>; 1734 remote-endpoint = <&vopl_out_hdmi>; 1735 }; 1736 }; 1737 }; 1738 }; 1739 1740 mipi_dsi: mipi@ff960000 { 1741 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1742 reg = <0x0 0xff960000 0x0 0x8000>; 1743 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1744 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1745 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1746 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1747 power-domains = <&power RK3399_PD_VIO>; 1748 resets = <&cru SRST_P_MIPI_DSI0>; 1749 reset-names = "apb"; 1750 rockchip,grf = <&grf>; 1751 #address-cells = <1>; 1752 #size-cells = <0>; 1753 status = "disabled"; 1754 1755 ports { 1756 #address-cells = <1>; 1757 #size-cells = <0>; 1758 1759 mipi_in: port@0 { 1760 reg = <0>; 1761 #address-cells = <1>; 1762 #size-cells = <0>; 1763 1764 mipi_in_vopb: endpoint@0 { 1765 reg = <0>; 1766 remote-endpoint = <&vopb_out_mipi>; 1767 }; 1768 mipi_in_vopl: endpoint@1 { 1769 reg = <1>; 1770 remote-endpoint = <&vopl_out_mipi>; 1771 }; 1772 }; 1773 }; 1774 }; 1775 1776 mipi_dsi1: mipi@ff968000 { 1777 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1778 reg = <0x0 0xff968000 0x0 0x8000>; 1779 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 1780 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 1781 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 1782 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1783 power-domains = <&power RK3399_PD_VIO>; 1784 resets = <&cru SRST_P_MIPI_DSI1>; 1785 reset-names = "apb"; 1786 rockchip,grf = <&grf>; 1787 #address-cells = <1>; 1788 #size-cells = <0>; 1789 status = "disabled"; 1790 1791 ports { 1792 #address-cells = <1>; 1793 #size-cells = <0>; 1794 1795 mipi1_in: port@0 { 1796 reg = <0>; 1797 #address-cells = <1>; 1798 #size-cells = <0>; 1799 1800 mipi1_in_vopb: endpoint@0 { 1801 reg = <0>; 1802 remote-endpoint = <&vopb_out_mipi1>; 1803 }; 1804 1805 mipi1_in_vopl: endpoint@1 { 1806 reg = <1>; 1807 remote-endpoint = <&vopl_out_mipi1>; 1808 }; 1809 }; 1810 }; 1811 }; 1812 1813 edp: edp@ff970000 { 1814 compatible = "rockchip,rk3399-edp"; 1815 reg = <0x0 0xff970000 0x0 0x8000>; 1816 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1817 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 1818 clock-names = "dp", "pclk", "grf"; 1819 pinctrl-names = "default"; 1820 pinctrl-0 = <&edp_hpd>; 1821 power-domains = <&power RK3399_PD_EDP>; 1822 resets = <&cru SRST_P_EDP_CTRL>; 1823 reset-names = "dp"; 1824 rockchip,grf = <&grf>; 1825 status = "disabled"; 1826 1827 ports { 1828 #address-cells = <1>; 1829 #size-cells = <0>; 1830 edp_in: port@0 { 1831 reg = <0>; 1832 #address-cells = <1>; 1833 #size-cells = <0>; 1834 1835 edp_in_vopb: endpoint@0 { 1836 reg = <0>; 1837 remote-endpoint = <&vopb_out_edp>; 1838 }; 1839 1840 edp_in_vopl: endpoint@1 { 1841 reg = <1>; 1842 remote-endpoint = <&vopl_out_edp>; 1843 }; 1844 }; 1845 }; 1846 }; 1847 1848 gpu: gpu@ff9a0000 { 1849 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1850 reg = <0x0 0xff9a0000 0x0 0x10000>; 1851 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>, 1852 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1853 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>; 1854 interrupt-names = "gpu", "job", "mmu"; 1855 clocks = <&cru ACLK_GPU>; 1856 power-domains = <&power RK3399_PD_GPU>; 1857 status = "disabled"; 1858 }; 1859 1860 pinctrl: pinctrl { 1861 compatible = "rockchip,rk3399-pinctrl"; 1862 rockchip,grf = <&grf>; 1863 rockchip,pmu = <&pmugrf>; 1864 #address-cells = <2>; 1865 #size-cells = <2>; 1866 ranges; 1867 1868 gpio0: gpio0@ff720000 { 1869 compatible = "rockchip,gpio-bank"; 1870 reg = <0x0 0xff720000 0x0 0x100>; 1871 clocks = <&pmucru PCLK_GPIO0_PMU>; 1872 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1873 1874 gpio-controller; 1875 #gpio-cells = <0x2>; 1876 1877 interrupt-controller; 1878 #interrupt-cells = <0x2>; 1879 }; 1880 1881 gpio1: gpio1@ff730000 { 1882 compatible = "rockchip,gpio-bank"; 1883 reg = <0x0 0xff730000 0x0 0x100>; 1884 clocks = <&pmucru PCLK_GPIO1_PMU>; 1885 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1886 1887 gpio-controller; 1888 #gpio-cells = <0x2>; 1889 1890 interrupt-controller; 1891 #interrupt-cells = <0x2>; 1892 }; 1893 1894 gpio2: gpio2@ff780000 { 1895 compatible = "rockchip,gpio-bank"; 1896 reg = <0x0 0xff780000 0x0 0x100>; 1897 clocks = <&cru PCLK_GPIO2>; 1898 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1899 1900 gpio-controller; 1901 #gpio-cells = <0x2>; 1902 1903 interrupt-controller; 1904 #interrupt-cells = <0x2>; 1905 }; 1906 1907 gpio3: gpio3@ff788000 { 1908 compatible = "rockchip,gpio-bank"; 1909 reg = <0x0 0xff788000 0x0 0x100>; 1910 clocks = <&cru PCLK_GPIO3>; 1911 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1912 1913 gpio-controller; 1914 #gpio-cells = <0x2>; 1915 1916 interrupt-controller; 1917 #interrupt-cells = <0x2>; 1918 }; 1919 1920 gpio4: gpio4@ff790000 { 1921 compatible = "rockchip,gpio-bank"; 1922 reg = <0x0 0xff790000 0x0 0x100>; 1923 clocks = <&cru PCLK_GPIO4>; 1924 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1925 1926 gpio-controller; 1927 #gpio-cells = <0x2>; 1928 1929 interrupt-controller; 1930 #interrupt-cells = <0x2>; 1931 }; 1932 1933 pcfg_pull_up: pcfg-pull-up { 1934 bias-pull-up; 1935 }; 1936 1937 pcfg_pull_down: pcfg-pull-down { 1938 bias-pull-down; 1939 }; 1940 1941 pcfg_pull_none: pcfg-pull-none { 1942 bias-disable; 1943 }; 1944 1945 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1946 bias-disable; 1947 drive-strength = <12>; 1948 }; 1949 1950 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1951 bias-disable; 1952 drive-strength = <13>; 1953 }; 1954 1955 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 1956 bias-disable; 1957 drive-strength = <18>; 1958 }; 1959 1960 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 1961 bias-disable; 1962 drive-strength = <20>; 1963 }; 1964 1965 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1966 bias-pull-up; 1967 drive-strength = <2>; 1968 }; 1969 1970 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1971 bias-pull-up; 1972 drive-strength = <8>; 1973 }; 1974 1975 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 1976 bias-pull-up; 1977 drive-strength = <18>; 1978 }; 1979 1980 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 1981 bias-pull-up; 1982 drive-strength = <20>; 1983 }; 1984 1985 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1986 bias-pull-down; 1987 drive-strength = <4>; 1988 }; 1989 1990 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 1991 bias-pull-down; 1992 drive-strength = <8>; 1993 }; 1994 1995 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 1996 bias-pull-down; 1997 drive-strength = <12>; 1998 }; 1999 2000 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2001 bias-pull-down; 2002 drive-strength = <18>; 2003 }; 2004 2005 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2006 bias-pull-down; 2007 drive-strength = <20>; 2008 }; 2009 2010 pcfg_output_high: pcfg-output-high { 2011 output-high; 2012 }; 2013 2014 pcfg_output_low: pcfg-output-low { 2015 output-low; 2016 }; 2017 2018 clock { 2019 clk_32k: clk-32k { 2020 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 2021 }; 2022 }; 2023 2024 edp { 2025 edp_hpd: edp-hpd { 2026 rockchip,pins = 2027 <4 23 RK_FUNC_2 &pcfg_pull_none>; 2028 }; 2029 }; 2030 2031 gmac { 2032 rgmii_pins: rgmii-pins { 2033 rockchip,pins = 2034 /* mac_txclk */ 2035 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>, 2036 /* mac_rxclk */ 2037 <3 14 RK_FUNC_1 &pcfg_pull_none>, 2038 /* mac_mdio */ 2039 <3 13 RK_FUNC_1 &pcfg_pull_none>, 2040 /* mac_txen */ 2041 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 2042 /* mac_clk */ 2043 <3 11 RK_FUNC_1 &pcfg_pull_none>, 2044 /* mac_rxdv */ 2045 <3 9 RK_FUNC_1 &pcfg_pull_none>, 2046 /* mac_mdc */ 2047 <3 8 RK_FUNC_1 &pcfg_pull_none>, 2048 /* mac_rxd1 */ 2049 <3 7 RK_FUNC_1 &pcfg_pull_none>, 2050 /* mac_rxd0 */ 2051 <3 6 RK_FUNC_1 &pcfg_pull_none>, 2052 /* mac_txd1 */ 2053 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 2054 /* mac_txd0 */ 2055 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>, 2056 /* mac_rxd3 */ 2057 <3 3 RK_FUNC_1 &pcfg_pull_none>, 2058 /* mac_rxd2 */ 2059 <3 2 RK_FUNC_1 &pcfg_pull_none>, 2060 /* mac_txd3 */ 2061 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>, 2062 /* mac_txd2 */ 2063 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>; 2064 }; 2065 2066 rmii_pins: rmii-pins { 2067 rockchip,pins = 2068 /* mac_mdio */ 2069 <3 13 RK_FUNC_1 &pcfg_pull_none>, 2070 /* mac_txen */ 2071 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 2072 /* mac_clk */ 2073 <3 11 RK_FUNC_1 &pcfg_pull_none>, 2074 /* mac_rxer */ 2075 <3 10 RK_FUNC_1 &pcfg_pull_none>, 2076 /* mac_rxdv */ 2077 <3 9 RK_FUNC_1 &pcfg_pull_none>, 2078 /* mac_mdc */ 2079 <3 8 RK_FUNC_1 &pcfg_pull_none>, 2080 /* mac_rxd1 */ 2081 <3 7 RK_FUNC_1 &pcfg_pull_none>, 2082 /* mac_rxd0 */ 2083 <3 6 RK_FUNC_1 &pcfg_pull_none>, 2084 /* mac_txd1 */ 2085 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 2086 /* mac_txd0 */ 2087 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>; 2088 }; 2089 }; 2090 2091 i2c0 { 2092 i2c0_xfer: i2c0-xfer { 2093 rockchip,pins = 2094 <1 15 RK_FUNC_2 &pcfg_pull_none>, 2095 <1 16 RK_FUNC_2 &pcfg_pull_none>; 2096 }; 2097 }; 2098 2099 i2c1 { 2100 i2c1_xfer: i2c1-xfer { 2101 rockchip,pins = 2102 <4 2 RK_FUNC_1 &pcfg_pull_none>, 2103 <4 1 RK_FUNC_1 &pcfg_pull_none>; 2104 }; 2105 }; 2106 2107 i2c2 { 2108 i2c2_xfer: i2c2-xfer { 2109 rockchip,pins = 2110 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 2111 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; 2112 }; 2113 }; 2114 2115 i2c3 { 2116 i2c3_xfer: i2c3-xfer { 2117 rockchip,pins = 2118 <4 17 RK_FUNC_1 &pcfg_pull_none>, 2119 <4 16 RK_FUNC_1 &pcfg_pull_none>; 2120 }; 2121 }; 2122 2123 i2c4 { 2124 i2c4_xfer: i2c4-xfer { 2125 rockchip,pins = 2126 <1 12 RK_FUNC_1 &pcfg_pull_none>, 2127 <1 11 RK_FUNC_1 &pcfg_pull_none>; 2128 }; 2129 }; 2130 2131 i2c5 { 2132 i2c5_xfer: i2c5-xfer { 2133 rockchip,pins = 2134 <3 11 RK_FUNC_2 &pcfg_pull_none>, 2135 <3 10 RK_FUNC_2 &pcfg_pull_none>; 2136 }; 2137 }; 2138 2139 i2c6 { 2140 i2c6_xfer: i2c6-xfer { 2141 rockchip,pins = 2142 <2 10 RK_FUNC_2 &pcfg_pull_none>, 2143 <2 9 RK_FUNC_2 &pcfg_pull_none>; 2144 }; 2145 }; 2146 2147 i2c7 { 2148 i2c7_xfer: i2c7-xfer { 2149 rockchip,pins = 2150 <2 8 RK_FUNC_2 &pcfg_pull_none>, 2151 <2 7 RK_FUNC_2 &pcfg_pull_none>; 2152 }; 2153 }; 2154 2155 i2c8 { 2156 i2c8_xfer: i2c8-xfer { 2157 rockchip,pins = 2158 <1 21 RK_FUNC_1 &pcfg_pull_none>, 2159 <1 20 RK_FUNC_1 &pcfg_pull_none>; 2160 }; 2161 }; 2162 2163 i2s0 { 2164 i2s0_2ch_bus: i2s0-2ch-bus { 2165 rockchip,pins = 2166 <3 24 RK_FUNC_1 &pcfg_pull_none>, 2167 <3 25 RK_FUNC_1 &pcfg_pull_none>, 2168 <3 26 RK_FUNC_1 &pcfg_pull_none>, 2169 <3 27 RK_FUNC_1 &pcfg_pull_none>, 2170 <3 31 RK_FUNC_1 &pcfg_pull_none>, 2171 <4 0 RK_FUNC_1 &pcfg_pull_none>; 2172 }; 2173 2174 i2s0_8ch_bus: i2s0-8ch-bus { 2175 rockchip,pins = 2176 <3 24 RK_FUNC_1 &pcfg_pull_none>, 2177 <3 25 RK_FUNC_1 &pcfg_pull_none>, 2178 <3 26 RK_FUNC_1 &pcfg_pull_none>, 2179 <3 27 RK_FUNC_1 &pcfg_pull_none>, 2180 <3 28 RK_FUNC_1 &pcfg_pull_none>, 2181 <3 29 RK_FUNC_1 &pcfg_pull_none>, 2182 <3 30 RK_FUNC_1 &pcfg_pull_none>, 2183 <3 31 RK_FUNC_1 &pcfg_pull_none>, 2184 <4 0 RK_FUNC_1 &pcfg_pull_none>; 2185 }; 2186 }; 2187 2188 i2s1 { 2189 i2s1_2ch_bus: i2s1-2ch-bus { 2190 rockchip,pins = 2191 <4 3 RK_FUNC_1 &pcfg_pull_none>, 2192 <4 4 RK_FUNC_1 &pcfg_pull_none>, 2193 <4 5 RK_FUNC_1 &pcfg_pull_none>, 2194 <4 6 RK_FUNC_1 &pcfg_pull_none>, 2195 <4 7 RK_FUNC_1 &pcfg_pull_none>; 2196 }; 2197 }; 2198 2199 sdio0 { 2200 sdio0_bus1: sdio0-bus1 { 2201 rockchip,pins = 2202 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 2203 }; 2204 2205 sdio0_bus4: sdio0-bus4 { 2206 rockchip,pins = 2207 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>, 2208 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>, 2209 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 2210 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>; 2211 }; 2212 2213 sdio0_cmd: sdio0-cmd { 2214 rockchip,pins = 2215 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>; 2216 }; 2217 2218 sdio0_clk: sdio0-clk { 2219 rockchip,pins = 2220 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 2221 }; 2222 2223 sdio0_cd: sdio0-cd { 2224 rockchip,pins = 2225 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>; 2226 }; 2227 2228 sdio0_pwr: sdio0-pwr { 2229 rockchip,pins = 2230 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>; 2231 }; 2232 2233 sdio0_bkpwr: sdio0-bkpwr { 2234 rockchip,pins = 2235 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 2236 }; 2237 2238 sdio0_wp: sdio0-wp { 2239 rockchip,pins = 2240 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; 2241 }; 2242 2243 sdio0_int: sdio0-int { 2244 rockchip,pins = 2245 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; 2246 }; 2247 }; 2248 2249 sdmmc { 2250 sdmmc_bus1: sdmmc-bus1 { 2251 rockchip,pins = 2252 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 2253 }; 2254 2255 sdmmc_bus4: sdmmc-bus4 { 2256 rockchip,pins = 2257 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>, 2258 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>, 2259 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 2260 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 2261 }; 2262 2263 sdmmc_clk: sdmmc-clk { 2264 rockchip,pins = 2265 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 2266 }; 2267 2268 sdmmc_cmd: sdmmc-cmd { 2269 rockchip,pins = 2270 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; 2271 }; 2272 2273 sdmmc_cd: sdmmc-cd { 2274 rockchip,pins = 2275 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; 2276 }; 2277 2278 sdmmc_wp: sdmmc-wp { 2279 rockchip,pins = 2280 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 2281 }; 2282 }; 2283 2284 sleep { 2285 ap_pwroff: ap-pwroff { 2286 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>; 2287 }; 2288 2289 ddrio_pwroff: ddrio-pwroff { 2290 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 2291 }; 2292 }; 2293 2294 spdif { 2295 spdif_bus: spdif-bus { 2296 rockchip,pins = 2297 <4 21 RK_FUNC_1 &pcfg_pull_none>; 2298 }; 2299 2300 spdif_bus_1: spdif-bus-1 { 2301 rockchip,pins = 2302 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2303 }; 2304 }; 2305 2306 spi0 { 2307 spi0_clk: spi0-clk { 2308 rockchip,pins = 2309 <3 6 RK_FUNC_2 &pcfg_pull_up>; 2310 }; 2311 spi0_cs0: spi0-cs0 { 2312 rockchip,pins = 2313 <3 7 RK_FUNC_2 &pcfg_pull_up>; 2314 }; 2315 spi0_cs1: spi0-cs1 { 2316 rockchip,pins = 2317 <3 8 RK_FUNC_2 &pcfg_pull_up>; 2318 }; 2319 spi0_tx: spi0-tx { 2320 rockchip,pins = 2321 <3 5 RK_FUNC_2 &pcfg_pull_up>; 2322 }; 2323 spi0_rx: spi0-rx { 2324 rockchip,pins = 2325 <3 4 RK_FUNC_2 &pcfg_pull_up>; 2326 }; 2327 }; 2328 2329 spi1 { 2330 spi1_clk: spi1-clk { 2331 rockchip,pins = 2332 <1 9 RK_FUNC_2 &pcfg_pull_up>; 2333 }; 2334 spi1_cs0: spi1-cs0 { 2335 rockchip,pins = 2336 <1 10 RK_FUNC_2 &pcfg_pull_up>; 2337 }; 2338 spi1_rx: spi1-rx { 2339 rockchip,pins = 2340 <1 7 RK_FUNC_2 &pcfg_pull_up>; 2341 }; 2342 spi1_tx: spi1-tx { 2343 rockchip,pins = 2344 <1 8 RK_FUNC_2 &pcfg_pull_up>; 2345 }; 2346 }; 2347 2348 spi2 { 2349 spi2_clk: spi2-clk { 2350 rockchip,pins = 2351 <2 11 RK_FUNC_1 &pcfg_pull_up>; 2352 }; 2353 spi2_cs0: spi2-cs0 { 2354 rockchip,pins = 2355 <2 12 RK_FUNC_1 &pcfg_pull_up>; 2356 }; 2357 spi2_rx: spi2-rx { 2358 rockchip,pins = 2359 <2 9 RK_FUNC_1 &pcfg_pull_up>; 2360 }; 2361 spi2_tx: spi2-tx { 2362 rockchip,pins = 2363 <2 10 RK_FUNC_1 &pcfg_pull_up>; 2364 }; 2365 }; 2366 2367 spi3 { 2368 spi3_clk: spi3-clk { 2369 rockchip,pins = 2370 <1 17 RK_FUNC_1 &pcfg_pull_up>; 2371 }; 2372 spi3_cs0: spi3-cs0 { 2373 rockchip,pins = 2374 <1 18 RK_FUNC_1 &pcfg_pull_up>; 2375 }; 2376 spi3_rx: spi3-rx { 2377 rockchip,pins = 2378 <1 15 RK_FUNC_1 &pcfg_pull_up>; 2379 }; 2380 spi3_tx: spi3-tx { 2381 rockchip,pins = 2382 <1 16 RK_FUNC_1 &pcfg_pull_up>; 2383 }; 2384 }; 2385 2386 spi4 { 2387 spi4_clk: spi4-clk { 2388 rockchip,pins = 2389 <3 2 RK_FUNC_2 &pcfg_pull_up>; 2390 }; 2391 spi4_cs0: spi4-cs0 { 2392 rockchip,pins = 2393 <3 3 RK_FUNC_2 &pcfg_pull_up>; 2394 }; 2395 spi4_rx: spi4-rx { 2396 rockchip,pins = 2397 <3 0 RK_FUNC_2 &pcfg_pull_up>; 2398 }; 2399 spi4_tx: spi4-tx { 2400 rockchip,pins = 2401 <3 1 RK_FUNC_2 &pcfg_pull_up>; 2402 }; 2403 }; 2404 2405 spi5 { 2406 spi5_clk: spi5-clk { 2407 rockchip,pins = 2408 <2 22 RK_FUNC_2 &pcfg_pull_up>; 2409 }; 2410 spi5_cs0: spi5-cs0 { 2411 rockchip,pins = 2412 <2 23 RK_FUNC_2 &pcfg_pull_up>; 2413 }; 2414 spi5_rx: spi5-rx { 2415 rockchip,pins = 2416 <2 20 RK_FUNC_2 &pcfg_pull_up>; 2417 }; 2418 spi5_tx: spi5-tx { 2419 rockchip,pins = 2420 <2 21 RK_FUNC_2 &pcfg_pull_up>; 2421 }; 2422 }; 2423 2424 testclk { 2425 test_clkout0: test-clkout0 { 2426 rockchip,pins = 2427 <0 0 RK_FUNC_1 &pcfg_pull_none>; 2428 }; 2429 2430 test_clkout1: test-clkout1 { 2431 rockchip,pins = 2432 <2 25 RK_FUNC_2 &pcfg_pull_none>; 2433 }; 2434 2435 test_clkout2: test-clkout2 { 2436 rockchip,pins = 2437 <0 8 RK_FUNC_3 &pcfg_pull_none>; 2438 }; 2439 }; 2440 2441 tsadc { 2442 otp_gpio: otp-gpio { 2443 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>; 2444 }; 2445 2446 otp_out: otp-out { 2447 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>; 2448 }; 2449 }; 2450 2451 uart0 { 2452 uart0_xfer: uart0-xfer { 2453 rockchip,pins = 2454 <2 16 RK_FUNC_1 &pcfg_pull_up>, 2455 <2 17 RK_FUNC_1 &pcfg_pull_none>; 2456 }; 2457 2458 uart0_cts: uart0-cts { 2459 rockchip,pins = 2460 <2 18 RK_FUNC_1 &pcfg_pull_none>; 2461 }; 2462 2463 uart0_rts: uart0-rts { 2464 rockchip,pins = 2465 <2 19 RK_FUNC_1 &pcfg_pull_none>; 2466 }; 2467 }; 2468 2469 uart1 { 2470 uart1_xfer: uart1-xfer { 2471 rockchip,pins = 2472 <3 12 RK_FUNC_2 &pcfg_pull_up>, 2473 <3 13 RK_FUNC_2 &pcfg_pull_none>; 2474 }; 2475 }; 2476 2477 uart2a { 2478 uart2a_xfer: uart2a-xfer { 2479 rockchip,pins = 2480 <4 8 RK_FUNC_2 &pcfg_pull_up>, 2481 <4 9 RK_FUNC_2 &pcfg_pull_none>; 2482 }; 2483 }; 2484 2485 uart2b { 2486 uart2b_xfer: uart2b-xfer { 2487 rockchip,pins = 2488 <4 16 RK_FUNC_2 &pcfg_pull_up>, 2489 <4 17 RK_FUNC_2 &pcfg_pull_none>; 2490 }; 2491 }; 2492 2493 uart2c { 2494 uart2c_xfer: uart2c-xfer { 2495 rockchip,pins = 2496 <4 19 RK_FUNC_1 &pcfg_pull_up>, 2497 <4 20 RK_FUNC_1 &pcfg_pull_none>; 2498 }; 2499 }; 2500 2501 uart3 { 2502 uart3_xfer: uart3-xfer { 2503 rockchip,pins = 2504 <3 14 RK_FUNC_2 &pcfg_pull_up>, 2505 <3 15 RK_FUNC_2 &pcfg_pull_none>; 2506 }; 2507 2508 uart3_cts: uart3-cts { 2509 rockchip,pins = 2510 <3 18 RK_FUNC_2 &pcfg_pull_none>; 2511 }; 2512 2513 uart3_rts: uart3-rts { 2514 rockchip,pins = 2515 <3 19 RK_FUNC_2 &pcfg_pull_none>; 2516 }; 2517 }; 2518 2519 uart4 { 2520 uart4_xfer: uart4-xfer { 2521 rockchip,pins = 2522 <1 7 RK_FUNC_1 &pcfg_pull_up>, 2523 <1 8 RK_FUNC_1 &pcfg_pull_none>; 2524 }; 2525 }; 2526 2527 uarthdcp { 2528 uarthdcp_xfer: uarthdcp-xfer { 2529 rockchip,pins = 2530 <4 21 RK_FUNC_2 &pcfg_pull_up>, 2531 <4 22 RK_FUNC_2 &pcfg_pull_none>; 2532 }; 2533 }; 2534 2535 pwm0 { 2536 pwm0_pin: pwm0-pin { 2537 rockchip,pins = 2538 <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 2539 }; 2540 2541 pwm0_pin_pull_down: pwm0-pin-pull-down { 2542 rockchip,pins = 2543 <4 RK_PC2 RK_FUNC_1 &pcfg_pull_down>; 2544 }; 2545 2546 vop0_pwm_pin: vop0-pwm-pin { 2547 rockchip,pins = 2548 <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 2549 }; 2550 2551 vop1_pwm_pin: vop1-pwm-pin { 2552 rockchip,pins = 2553 <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2554 }; 2555 }; 2556 2557 pwm1 { 2558 pwm1_pin: pwm1-pin { 2559 rockchip,pins = 2560 <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 2561 }; 2562 2563 pwm1_pin_pull_down: pwm1-pin-pull-down { 2564 rockchip,pins = 2565 <4 RK_PC6 RK_FUNC_1 &pcfg_pull_down>; 2566 }; 2567 }; 2568 2569 pwm2 { 2570 pwm2_pin: pwm2-pin { 2571 rockchip,pins = 2572 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 2573 }; 2574 2575 pwm2_pin_pull_down: pwm2-pin-pull-down { 2576 rockchip,pins = 2577 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>; 2578 }; 2579 }; 2580 2581 pwm3a { 2582 pwm3a_pin: pwm3a-pin { 2583 rockchip,pins = 2584 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 2585 }; 2586 }; 2587 2588 pwm3b { 2589 pwm3b_pin: pwm3b-pin { 2590 rockchip,pins = 2591 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 2592 }; 2593 }; 2594 2595 hdmi { 2596 hdmi_i2c_xfer: hdmi-i2c-xfer { 2597 rockchip,pins = 2598 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>, 2599 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2600 }; 2601 2602 hdmi_cec: hdmi-cec { 2603 rockchip,pins = 2604 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; 2605 }; 2606 }; 2607 2608 pcie { 2609 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2610 rockchip,pins = 2611 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2612 }; 2613 2614 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2615 rockchip,pins = 2616 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2617 }; 2618 }; 2619 2620 }; 2621}; 2622