1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu-map { 44 cluster0 { 45 core0 { 46 cpu = <&cpu_l0>; 47 }; 48 core1 { 49 cpu = <&cpu_l1>; 50 }; 51 core2 { 52 cpu = <&cpu_l2>; 53 }; 54 core3 { 55 cpu = <&cpu_l3>; 56 }; 57 }; 58 59 cluster1 { 60 core0 { 61 cpu = <&cpu_b0>; 62 }; 63 core1 { 64 cpu = <&cpu_b1>; 65 }; 66 }; 67 }; 68 69 cpu_l0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 capacity-dmips-mhz = <485>; 75 clocks = <&cru ARMCLKL>; 76 #cooling-cells = <2>; /* min followed by max */ 77 dynamic-power-coefficient = <100>; 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 79 }; 80 81 cpu_l1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x1>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <485>; 87 clocks = <&cru ARMCLKL>; 88 #cooling-cells = <2>; /* min followed by max */ 89 dynamic-power-coefficient = <100>; 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 91 }; 92 93 cpu_l2: cpu@2 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x2>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <485>; 99 clocks = <&cru ARMCLKL>; 100 #cooling-cells = <2>; /* min followed by max */ 101 dynamic-power-coefficient = <100>; 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 103 }; 104 105 cpu_l3: cpu@3 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0 0x3>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <485>; 111 clocks = <&cru ARMCLKL>; 112 #cooling-cells = <2>; /* min followed by max */ 113 dynamic-power-coefficient = <100>; 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 115 }; 116 117 cpu_b0: cpu@100 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a72"; 120 reg = <0x0 0x100>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <1024>; 123 clocks = <&cru ARMCLKB>; 124 #cooling-cells = <2>; /* min followed by max */ 125 dynamic-power-coefficient = <436>; 126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 127 }; 128 129 cpu_b1: cpu@101 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a72"; 132 reg = <0x0 0x101>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <1024>; 135 clocks = <&cru ARMCLKB>; 136 #cooling-cells = <2>; /* min followed by max */ 137 dynamic-power-coefficient = <436>; 138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 139 }; 140 141 idle-states { 142 entry-method = "psci"; 143 144 CPU_SLEEP: cpu-sleep { 145 compatible = "arm,idle-state"; 146 local-timer-stop; 147 arm,psci-suspend-param = <0x0010000>; 148 entry-latency-us = <120>; 149 exit-latency-us = <250>; 150 min-residency-us = <900>; 151 }; 152 153 CLUSTER_SLEEP: cluster-sleep { 154 compatible = "arm,idle-state"; 155 local-timer-stop; 156 arm,psci-suspend-param = <0x1010000>; 157 entry-latency-us = <400>; 158 exit-latency-us = <500>; 159 min-residency-us = <2000>; 160 }; 161 }; 162 }; 163 164 display-subsystem { 165 compatible = "rockchip,display-subsystem"; 166 ports = <&vopl_out>, <&vopb_out>; 167 }; 168 169 pmu_a53 { 170 compatible = "arm,cortex-a53-pmu"; 171 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 172 }; 173 174 pmu_a72 { 175 compatible = "arm,cortex-a72-pmu"; 176 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 177 }; 178 179 psci { 180 compatible = "arm,psci-1.0"; 181 method = "smc"; 182 }; 183 184 timer { 185 compatible = "arm,armv8-timer"; 186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 190 arm,no-tick-in-suspend; 191 }; 192 193 xin24m: xin24m { 194 compatible = "fixed-clock"; 195 clock-frequency = <24000000>; 196 clock-output-names = "xin24m"; 197 #clock-cells = <0>; 198 }; 199 200 pcie0: pcie@f8000000 { 201 compatible = "rockchip,rk3399-pcie"; 202 reg = <0x0 0xf8000000 0x0 0x2000000>, 203 <0x0 0xfd000000 0x0 0x1000000>; 204 reg-names = "axi-base", "apb-base"; 205 device_type = "pci"; 206 #address-cells = <3>; 207 #size-cells = <2>; 208 #interrupt-cells = <1>; 209 aspm-no-l0s; 210 bus-range = <0x0 0x1f>; 211 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 212 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 213 clock-names = "aclk", "aclk-perf", 214 "hclk", "pm"; 215 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 216 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 217 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 218 interrupt-names = "sys", "legacy", "client"; 219 interrupt-map-mask = <0 0 0 7>; 220 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 221 <0 0 0 2 &pcie0_intc 1>, 222 <0 0 0 3 &pcie0_intc 2>, 223 <0 0 0 4 &pcie0_intc 3>; 224 max-link-speed = <1>; 225 msi-map = <0x0 &its 0x0 0x1000>; 226 phys = <&pcie_phy 0>, <&pcie_phy 1>, 227 <&pcie_phy 2>, <&pcie_phy 3>; 228 phy-names = "pcie-phy-0", "pcie-phy-1", 229 "pcie-phy-2", "pcie-phy-3"; 230 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>, 231 <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 232 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 233 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 234 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 235 <&cru SRST_A_PCIE>; 236 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 237 "pm", "pclk", "aclk"; 238 status = "disabled"; 239 240 pcie0_intc: interrupt-controller { 241 interrupt-controller; 242 #address-cells = <0>; 243 #interrupt-cells = <1>; 244 }; 245 }; 246 247 gmac: ethernet@fe300000 { 248 compatible = "rockchip,rk3399-gmac"; 249 reg = <0x0 0xfe300000 0x0 0x10000>; 250 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 251 interrupt-names = "macirq"; 252 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 253 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 254 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 255 <&cru PCLK_GMAC>; 256 clock-names = "stmmaceth", "mac_clk_rx", 257 "mac_clk_tx", "clk_mac_ref", 258 "clk_mac_refout", "aclk_mac", 259 "pclk_mac"; 260 power-domains = <&power RK3399_PD_GMAC>; 261 resets = <&cru SRST_A_GMAC>; 262 reset-names = "stmmaceth"; 263 rockchip,grf = <&grf>; 264 snps,txpbl = <0x4>; 265 status = "disabled"; 266 }; 267 268 sdio0: mmc@fe310000 { 269 compatible = "rockchip,rk3399-dw-mshc", 270 "rockchip,rk3288-dw-mshc"; 271 reg = <0x0 0xfe310000 0x0 0x4000>; 272 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 273 max-frequency = <150000000>; 274 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 275 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 276 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 277 fifo-depth = <0x100>; 278 power-domains = <&power RK3399_PD_SDIOAUDIO>; 279 resets = <&cru SRST_SDIO0>; 280 reset-names = "reset"; 281 status = "disabled"; 282 }; 283 284 sdmmc: mmc@fe320000 { 285 compatible = "rockchip,rk3399-dw-mshc", 286 "rockchip,rk3288-dw-mshc"; 287 reg = <0x0 0xfe320000 0x0 0x4000>; 288 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 289 max-frequency = <150000000>; 290 assigned-clocks = <&cru HCLK_SD>; 291 assigned-clock-rates = <200000000>; 292 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 293 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 294 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 295 fifo-depth = <0x100>; 296 power-domains = <&power RK3399_PD_SD>; 297 resets = <&cru SRST_SDMMC>; 298 reset-names = "reset"; 299 status = "disabled"; 300 }; 301 302 sdhci: mmc@fe330000 { 303 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 304 reg = <0x0 0xfe330000 0x0 0x10000>; 305 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 306 arasan,soc-ctl-syscon = <&grf>; 307 assigned-clocks = <&cru SCLK_EMMC>; 308 assigned-clock-rates = <200000000>; 309 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 310 clock-names = "clk_xin", "clk_ahb"; 311 clock-output-names = "emmc_cardclock"; 312 #clock-cells = <0>; 313 phys = <&emmc_phy>; 314 phy-names = "phy_arasan"; 315 power-domains = <&power RK3399_PD_EMMC>; 316 disable-cqe-dcmd; 317 status = "disabled"; 318 }; 319 320 usb_host0_ehci: usb@fe380000 { 321 compatible = "generic-ehci"; 322 reg = <0x0 0xfe380000 0x0 0x20000>; 323 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 324 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 325 <&u2phy0>; 326 phys = <&u2phy0_host>; 327 phy-names = "usb"; 328 status = "disabled"; 329 }; 330 331 usb_host0_ohci: usb@fe3a0000 { 332 compatible = "generic-ohci"; 333 reg = <0x0 0xfe3a0000 0x0 0x20000>; 334 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 335 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 336 <&u2phy0>; 337 phys = <&u2phy0_host>; 338 phy-names = "usb"; 339 status = "disabled"; 340 }; 341 342 usb_host1_ehci: usb@fe3c0000 { 343 compatible = "generic-ehci"; 344 reg = <0x0 0xfe3c0000 0x0 0x20000>; 345 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 346 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 347 <&u2phy1>; 348 phys = <&u2phy1_host>; 349 phy-names = "usb"; 350 status = "disabled"; 351 }; 352 353 usb_host1_ohci: usb@fe3e0000 { 354 compatible = "generic-ohci"; 355 reg = <0x0 0xfe3e0000 0x0 0x20000>; 356 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 357 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 358 <&u2phy1>; 359 phys = <&u2phy1_host>; 360 phy-names = "usb"; 361 status = "disabled"; 362 }; 363 364 usbdrd3_0: usb@fe800000 { 365 compatible = "rockchip,rk3399-dwc3"; 366 #address-cells = <2>; 367 #size-cells = <2>; 368 ranges; 369 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 370 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 371 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 372 clock-names = "ref_clk", "suspend_clk", 373 "bus_clk", "aclk_usb3_rksoc_axi_perf", 374 "aclk_usb3", "grf_clk"; 375 resets = <&cru SRST_A_USB3_OTG0>; 376 reset-names = "usb3-otg"; 377 status = "disabled"; 378 379 usbdrd_dwc3_0: usb@fe800000 { 380 compatible = "snps,dwc3"; 381 reg = <0x0 0xfe800000 0x0 0x100000>; 382 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 383 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 384 <&cru SCLK_USB3OTG0_SUSPEND>; 385 clock-names = "ref", "bus_early", "suspend"; 386 dr_mode = "otg"; 387 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 388 phy-names = "usb2-phy", "usb3-phy"; 389 phy_type = "utmi_wide"; 390 snps,dis_enblslpm_quirk; 391 snps,dis-u2-freeclk-exists-quirk; 392 snps,dis_u2_susphy_quirk; 393 snps,dis-del-phy-power-chg-quirk; 394 snps,dis-tx-ipgap-linecheck-quirk; 395 power-domains = <&power RK3399_PD_USB3>; 396 status = "disabled"; 397 }; 398 }; 399 400 usbdrd3_1: usb@fe900000 { 401 compatible = "rockchip,rk3399-dwc3"; 402 #address-cells = <2>; 403 #size-cells = <2>; 404 ranges; 405 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 406 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 407 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 408 clock-names = "ref_clk", "suspend_clk", 409 "bus_clk", "aclk_usb3_rksoc_axi_perf", 410 "aclk_usb3", "grf_clk"; 411 resets = <&cru SRST_A_USB3_OTG1>; 412 reset-names = "usb3-otg"; 413 status = "disabled"; 414 415 usbdrd_dwc3_1: usb@fe900000 { 416 compatible = "snps,dwc3"; 417 reg = <0x0 0xfe900000 0x0 0x100000>; 418 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 419 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, 420 <&cru SCLK_USB3OTG1_SUSPEND>; 421 clock-names = "ref", "bus_early", "suspend"; 422 dr_mode = "otg"; 423 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 424 phy-names = "usb2-phy", "usb3-phy"; 425 phy_type = "utmi_wide"; 426 snps,dis_enblslpm_quirk; 427 snps,dis-u2-freeclk-exists-quirk; 428 snps,dis_u2_susphy_quirk; 429 snps,dis-del-phy-power-chg-quirk; 430 snps,dis-tx-ipgap-linecheck-quirk; 431 power-domains = <&power RK3399_PD_USB3>; 432 status = "disabled"; 433 }; 434 }; 435 436 cdn_dp: dp@fec00000 { 437 compatible = "rockchip,rk3399-cdn-dp"; 438 reg = <0x0 0xfec00000 0x0 0x100000>; 439 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 440 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 441 assigned-clock-rates = <100000000>, <200000000>; 442 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 443 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 444 clock-names = "core-clk", "pclk", "spdif", "grf"; 445 phys = <&tcphy0_dp>, <&tcphy1_dp>; 446 power-domains = <&power RK3399_PD_HDCP>; 447 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 448 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 449 reset-names = "spdif", "dptx", "apb", "core"; 450 rockchip,grf = <&grf>; 451 #sound-dai-cells = <1>; 452 status = "disabled"; 453 454 ports { 455 dp_in: port { 456 #address-cells = <1>; 457 #size-cells = <0>; 458 459 dp_in_vopb: endpoint@0 { 460 reg = <0>; 461 remote-endpoint = <&vopb_out_dp>; 462 }; 463 464 dp_in_vopl: endpoint@1 { 465 reg = <1>; 466 remote-endpoint = <&vopl_out_dp>; 467 }; 468 }; 469 }; 470 }; 471 472 gic: interrupt-controller@fee00000 { 473 compatible = "arm,gic-v3"; 474 #interrupt-cells = <4>; 475 #address-cells = <2>; 476 #size-cells = <2>; 477 ranges; 478 interrupt-controller; 479 480 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 481 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 482 <0x0 0xfff00000 0 0x10000>, /* GICC */ 483 <0x0 0xfff10000 0 0x10000>, /* GICH */ 484 <0x0 0xfff20000 0 0x10000>; /* GICV */ 485 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 486 its: interrupt-controller@fee20000 { 487 compatible = "arm,gic-v3-its"; 488 msi-controller; 489 #msi-cells = <1>; 490 reg = <0x0 0xfee20000 0x0 0x20000>; 491 }; 492 493 ppi-partitions { 494 ppi_cluster0: interrupt-partition-0 { 495 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 496 }; 497 498 ppi_cluster1: interrupt-partition-1 { 499 affinity = <&cpu_b0 &cpu_b1>; 500 }; 501 }; 502 }; 503 504 saradc: saradc@ff100000 { 505 compatible = "rockchip,rk3399-saradc"; 506 reg = <0x0 0xff100000 0x0 0x100>; 507 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 508 #io-channel-cells = <1>; 509 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 510 clock-names = "saradc", "apb_pclk"; 511 resets = <&cru SRST_P_SARADC>; 512 reset-names = "saradc-apb"; 513 status = "disabled"; 514 }; 515 516 i2c1: i2c@ff110000 { 517 compatible = "rockchip,rk3399-i2c"; 518 reg = <0x0 0xff110000 0x0 0x1000>; 519 assigned-clocks = <&cru SCLK_I2C1>; 520 assigned-clock-rates = <200000000>; 521 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 522 clock-names = "i2c", "pclk"; 523 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 524 pinctrl-names = "default"; 525 pinctrl-0 = <&i2c1_xfer>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 status = "disabled"; 529 }; 530 531 i2c2: i2c@ff120000 { 532 compatible = "rockchip,rk3399-i2c"; 533 reg = <0x0 0xff120000 0x0 0x1000>; 534 assigned-clocks = <&cru SCLK_I2C2>; 535 assigned-clock-rates = <200000000>; 536 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 537 clock-names = "i2c", "pclk"; 538 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 539 pinctrl-names = "default"; 540 pinctrl-0 = <&i2c2_xfer>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 status = "disabled"; 544 }; 545 546 i2c3: i2c@ff130000 { 547 compatible = "rockchip,rk3399-i2c"; 548 reg = <0x0 0xff130000 0x0 0x1000>; 549 assigned-clocks = <&cru SCLK_I2C3>; 550 assigned-clock-rates = <200000000>; 551 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 552 clock-names = "i2c", "pclk"; 553 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&i2c3_xfer>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 status = "disabled"; 559 }; 560 561 i2c5: i2c@ff140000 { 562 compatible = "rockchip,rk3399-i2c"; 563 reg = <0x0 0xff140000 0x0 0x1000>; 564 assigned-clocks = <&cru SCLK_I2C5>; 565 assigned-clock-rates = <200000000>; 566 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 567 clock-names = "i2c", "pclk"; 568 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&i2c5_xfer>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 status = "disabled"; 574 }; 575 576 i2c6: i2c@ff150000 { 577 compatible = "rockchip,rk3399-i2c"; 578 reg = <0x0 0xff150000 0x0 0x1000>; 579 assigned-clocks = <&cru SCLK_I2C6>; 580 assigned-clock-rates = <200000000>; 581 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 582 clock-names = "i2c", "pclk"; 583 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&i2c6_xfer>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 status = "disabled"; 589 }; 590 591 i2c7: i2c@ff160000 { 592 compatible = "rockchip,rk3399-i2c"; 593 reg = <0x0 0xff160000 0x0 0x1000>; 594 assigned-clocks = <&cru SCLK_I2C7>; 595 assigned-clock-rates = <200000000>; 596 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 597 clock-names = "i2c", "pclk"; 598 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 599 pinctrl-names = "default"; 600 pinctrl-0 = <&i2c7_xfer>; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 status = "disabled"; 604 }; 605 606 uart0: serial@ff180000 { 607 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 608 reg = <0x0 0xff180000 0x0 0x100>; 609 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 610 clock-names = "baudclk", "apb_pclk"; 611 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 612 reg-shift = <2>; 613 reg-io-width = <4>; 614 pinctrl-names = "default"; 615 pinctrl-0 = <&uart0_xfer>; 616 status = "disabled"; 617 }; 618 619 uart1: serial@ff190000 { 620 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 621 reg = <0x0 0xff190000 0x0 0x100>; 622 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 623 clock-names = "baudclk", "apb_pclk"; 624 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 625 reg-shift = <2>; 626 reg-io-width = <4>; 627 pinctrl-names = "default"; 628 pinctrl-0 = <&uart1_xfer>; 629 status = "disabled"; 630 }; 631 632 uart2: serial@ff1a0000 { 633 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 634 reg = <0x0 0xff1a0000 0x0 0x100>; 635 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 636 clock-names = "baudclk", "apb_pclk"; 637 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 638 reg-shift = <2>; 639 reg-io-width = <4>; 640 pinctrl-names = "default"; 641 pinctrl-0 = <&uart2c_xfer>; 642 status = "disabled"; 643 }; 644 645 uart3: serial@ff1b0000 { 646 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 647 reg = <0x0 0xff1b0000 0x0 0x100>; 648 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 649 clock-names = "baudclk", "apb_pclk"; 650 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 651 reg-shift = <2>; 652 reg-io-width = <4>; 653 pinctrl-names = "default"; 654 pinctrl-0 = <&uart3_xfer>; 655 status = "disabled"; 656 }; 657 658 spi0: spi@ff1c0000 { 659 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 660 reg = <0x0 0xff1c0000 0x0 0x1000>; 661 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 662 clock-names = "spiclk", "apb_pclk"; 663 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 664 dmas = <&dmac_peri 10>, <&dmac_peri 11>; 665 dma-names = "tx", "rx"; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 status = "disabled"; 671 }; 672 673 spi1: spi@ff1d0000 { 674 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 675 reg = <0x0 0xff1d0000 0x0 0x1000>; 676 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 677 clock-names = "spiclk", "apb_pclk"; 678 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 679 dmas = <&dmac_peri 12>, <&dmac_peri 13>; 680 dma-names = "tx", "rx"; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 683 #address-cells = <1>; 684 #size-cells = <0>; 685 status = "disabled"; 686 }; 687 688 spi2: spi@ff1e0000 { 689 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 690 reg = <0x0 0xff1e0000 0x0 0x1000>; 691 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 692 clock-names = "spiclk", "apb_pclk"; 693 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 694 dmas = <&dmac_peri 14>, <&dmac_peri 15>; 695 dma-names = "tx", "rx"; 696 pinctrl-names = "default"; 697 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 status = "disabled"; 701 }; 702 703 spi4: spi@ff1f0000 { 704 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 705 reg = <0x0 0xff1f0000 0x0 0x1000>; 706 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 707 clock-names = "spiclk", "apb_pclk"; 708 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 709 dmas = <&dmac_peri 18>, <&dmac_peri 19>; 710 dma-names = "tx", "rx"; 711 pinctrl-names = "default"; 712 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 status = "disabled"; 716 }; 717 718 spi5: spi@ff200000 { 719 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 720 reg = <0x0 0xff200000 0x0 0x1000>; 721 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 722 clock-names = "spiclk", "apb_pclk"; 723 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 724 dmas = <&dmac_bus 8>, <&dmac_bus 9>; 725 dma-names = "tx", "rx"; 726 pinctrl-names = "default"; 727 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 728 power-domains = <&power RK3399_PD_SDIOAUDIO>; 729 #address-cells = <1>; 730 #size-cells = <0>; 731 status = "disabled"; 732 }; 733 734 thermal_zones: thermal-zones { 735 cpu_thermal: cpu-thermal { 736 polling-delay-passive = <100>; 737 polling-delay = <1000>; 738 739 thermal-sensors = <&tsadc 0>; 740 741 trips { 742 cpu_alert0: cpu_alert0 { 743 temperature = <70000>; 744 hysteresis = <2000>; 745 type = "passive"; 746 }; 747 cpu_alert1: cpu_alert1 { 748 temperature = <75000>; 749 hysteresis = <2000>; 750 type = "passive"; 751 }; 752 cpu_crit: cpu_crit { 753 temperature = <95000>; 754 hysteresis = <2000>; 755 type = "critical"; 756 }; 757 }; 758 759 cooling-maps { 760 map0 { 761 trip = <&cpu_alert0>; 762 cooling-device = 763 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 764 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 765 }; 766 map1 { 767 trip = <&cpu_alert1>; 768 cooling-device = 769 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 770 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 771 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 772 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 773 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 774 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 775 }; 776 }; 777 }; 778 779 gpu_thermal: gpu-thermal { 780 polling-delay-passive = <100>; 781 polling-delay = <1000>; 782 783 thermal-sensors = <&tsadc 1>; 784 785 trips { 786 gpu_alert0: gpu_alert0 { 787 temperature = <75000>; 788 hysteresis = <2000>; 789 type = "passive"; 790 }; 791 gpu_crit: gpu_crit { 792 temperature = <95000>; 793 hysteresis = <2000>; 794 type = "critical"; 795 }; 796 }; 797 798 cooling-maps { 799 map0 { 800 trip = <&gpu_alert0>; 801 cooling-device = 802 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 803 }; 804 }; 805 }; 806 }; 807 808 tsadc: tsadc@ff260000 { 809 compatible = "rockchip,rk3399-tsadc"; 810 reg = <0x0 0xff260000 0x0 0x100>; 811 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 812 assigned-clocks = <&cru SCLK_TSADC>; 813 assigned-clock-rates = <750000>; 814 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 815 clock-names = "tsadc", "apb_pclk"; 816 resets = <&cru SRST_TSADC>; 817 reset-names = "tsadc-apb"; 818 rockchip,grf = <&grf>; 819 rockchip,hw-tshut-temp = <95000>; 820 pinctrl-names = "init", "default", "sleep"; 821 pinctrl-0 = <&otp_pin>; 822 pinctrl-1 = <&otp_out>; 823 pinctrl-2 = <&otp_pin>; 824 #thermal-sensor-cells = <1>; 825 status = "disabled"; 826 }; 827 828 qos_emmc: qos@ffa58000 { 829 compatible = "rockchip,rk3399-qos", "syscon"; 830 reg = <0x0 0xffa58000 0x0 0x20>; 831 }; 832 833 qos_gmac: qos@ffa5c000 { 834 compatible = "rockchip,rk3399-qos", "syscon"; 835 reg = <0x0 0xffa5c000 0x0 0x20>; 836 }; 837 838 qos_pcie: qos@ffa60080 { 839 compatible = "rockchip,rk3399-qos", "syscon"; 840 reg = <0x0 0xffa60080 0x0 0x20>; 841 }; 842 843 qos_usb_host0: qos@ffa60100 { 844 compatible = "rockchip,rk3399-qos", "syscon"; 845 reg = <0x0 0xffa60100 0x0 0x20>; 846 }; 847 848 qos_usb_host1: qos@ffa60180 { 849 compatible = "rockchip,rk3399-qos", "syscon"; 850 reg = <0x0 0xffa60180 0x0 0x20>; 851 }; 852 853 qos_usb_otg0: qos@ffa70000 { 854 compatible = "rockchip,rk3399-qos", "syscon"; 855 reg = <0x0 0xffa70000 0x0 0x20>; 856 }; 857 858 qos_usb_otg1: qos@ffa70080 { 859 compatible = "rockchip,rk3399-qos", "syscon"; 860 reg = <0x0 0xffa70080 0x0 0x20>; 861 }; 862 863 qos_sd: qos@ffa74000 { 864 compatible = "rockchip,rk3399-qos", "syscon"; 865 reg = <0x0 0xffa74000 0x0 0x20>; 866 }; 867 868 qos_sdioaudio: qos@ffa76000 { 869 compatible = "rockchip,rk3399-qos", "syscon"; 870 reg = <0x0 0xffa76000 0x0 0x20>; 871 }; 872 873 qos_hdcp: qos@ffa90000 { 874 compatible = "rockchip,rk3399-qos", "syscon"; 875 reg = <0x0 0xffa90000 0x0 0x20>; 876 }; 877 878 qos_iep: qos@ffa98000 { 879 compatible = "rockchip,rk3399-qos", "syscon"; 880 reg = <0x0 0xffa98000 0x0 0x20>; 881 }; 882 883 qos_isp0_m0: qos@ffaa0000 { 884 compatible = "rockchip,rk3399-qos", "syscon"; 885 reg = <0x0 0xffaa0000 0x0 0x20>; 886 }; 887 888 qos_isp0_m1: qos@ffaa0080 { 889 compatible = "rockchip,rk3399-qos", "syscon"; 890 reg = <0x0 0xffaa0080 0x0 0x20>; 891 }; 892 893 qos_isp1_m0: qos@ffaa8000 { 894 compatible = "rockchip,rk3399-qos", "syscon"; 895 reg = <0x0 0xffaa8000 0x0 0x20>; 896 }; 897 898 qos_isp1_m1: qos@ffaa8080 { 899 compatible = "rockchip,rk3399-qos", "syscon"; 900 reg = <0x0 0xffaa8080 0x0 0x20>; 901 }; 902 903 qos_rga_r: qos@ffab0000 { 904 compatible = "rockchip,rk3399-qos", "syscon"; 905 reg = <0x0 0xffab0000 0x0 0x20>; 906 }; 907 908 qos_rga_w: qos@ffab0080 { 909 compatible = "rockchip,rk3399-qos", "syscon"; 910 reg = <0x0 0xffab0080 0x0 0x20>; 911 }; 912 913 qos_video_m0: qos@ffab8000 { 914 compatible = "rockchip,rk3399-qos", "syscon"; 915 reg = <0x0 0xffab8000 0x0 0x20>; 916 }; 917 918 qos_video_m1_r: qos@ffac0000 { 919 compatible = "rockchip,rk3399-qos", "syscon"; 920 reg = <0x0 0xffac0000 0x0 0x20>; 921 }; 922 923 qos_video_m1_w: qos@ffac0080 { 924 compatible = "rockchip,rk3399-qos", "syscon"; 925 reg = <0x0 0xffac0080 0x0 0x20>; 926 }; 927 928 qos_vop_big_r: qos@ffac8000 { 929 compatible = "rockchip,rk3399-qos", "syscon"; 930 reg = <0x0 0xffac8000 0x0 0x20>; 931 }; 932 933 qos_vop_big_w: qos@ffac8080 { 934 compatible = "rockchip,rk3399-qos", "syscon"; 935 reg = <0x0 0xffac8080 0x0 0x20>; 936 }; 937 938 qos_vop_little: qos@ffad0000 { 939 compatible = "rockchip,rk3399-qos", "syscon"; 940 reg = <0x0 0xffad0000 0x0 0x20>; 941 }; 942 943 qos_perihp: qos@ffad8080 { 944 compatible = "rockchip,rk3399-qos", "syscon"; 945 reg = <0x0 0xffad8080 0x0 0x20>; 946 }; 947 948 qos_gpu: qos@ffae0000 { 949 compatible = "rockchip,rk3399-qos", "syscon"; 950 reg = <0x0 0xffae0000 0x0 0x20>; 951 }; 952 953 pmu: power-management@ff310000 { 954 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 955 reg = <0x0 0xff310000 0x0 0x1000>; 956 957 /* 958 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 959 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 960 * Some of the power domains are grouped together for every 961 * voltage domain. 962 * The detail contents as below. 963 */ 964 power: power-controller { 965 compatible = "rockchip,rk3399-power-controller"; 966 #power-domain-cells = <1>; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 970 /* These power domains are grouped by VD_CENTER */ 971 pd_iep@RK3399_PD_IEP { 972 reg = <RK3399_PD_IEP>; 973 clocks = <&cru ACLK_IEP>, 974 <&cru HCLK_IEP>; 975 pm_qos = <&qos_iep>; 976 }; 977 pd_rga@RK3399_PD_RGA { 978 reg = <RK3399_PD_RGA>; 979 clocks = <&cru ACLK_RGA>, 980 <&cru HCLK_RGA>; 981 pm_qos = <&qos_rga_r>, 982 <&qos_rga_w>; 983 }; 984 pd_vcodec@RK3399_PD_VCODEC { 985 reg = <RK3399_PD_VCODEC>; 986 clocks = <&cru ACLK_VCODEC>, 987 <&cru HCLK_VCODEC>; 988 pm_qos = <&qos_video_m0>; 989 }; 990 pd_vdu@RK3399_PD_VDU { 991 reg = <RK3399_PD_VDU>; 992 clocks = <&cru ACLK_VDU>, 993 <&cru HCLK_VDU>; 994 pm_qos = <&qos_video_m1_r>, 995 <&qos_video_m1_w>; 996 }; 997 998 /* These power domains are grouped by VD_GPU */ 999 pd_gpu@RK3399_PD_GPU { 1000 reg = <RK3399_PD_GPU>; 1001 clocks = <&cru ACLK_GPU>; 1002 pm_qos = <&qos_gpu>; 1003 }; 1004 1005 /* These power domains are grouped by VD_LOGIC */ 1006 pd_edp@RK3399_PD_EDP { 1007 reg = <RK3399_PD_EDP>; 1008 clocks = <&cru PCLK_EDP_CTRL>; 1009 }; 1010 pd_emmc@RK3399_PD_EMMC { 1011 reg = <RK3399_PD_EMMC>; 1012 clocks = <&cru ACLK_EMMC>; 1013 pm_qos = <&qos_emmc>; 1014 }; 1015 pd_gmac@RK3399_PD_GMAC { 1016 reg = <RK3399_PD_GMAC>; 1017 clocks = <&cru ACLK_GMAC>, 1018 <&cru PCLK_GMAC>; 1019 pm_qos = <&qos_gmac>; 1020 }; 1021 pd_sd@RK3399_PD_SD { 1022 reg = <RK3399_PD_SD>; 1023 clocks = <&cru HCLK_SDMMC>, 1024 <&cru SCLK_SDMMC>; 1025 pm_qos = <&qos_sd>; 1026 }; 1027 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 1028 reg = <RK3399_PD_SDIOAUDIO>; 1029 clocks = <&cru HCLK_SDIO>; 1030 pm_qos = <&qos_sdioaudio>; 1031 }; 1032 pd_tcpc0@RK3399_PD_TCPD0 { 1033 reg = <RK3399_PD_TCPD0>; 1034 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1035 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1036 }; 1037 pd_tcpc1@RK3399_PD_TCPD1 { 1038 reg = <RK3399_PD_TCPD1>; 1039 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1040 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1041 }; 1042 pd_usb3@RK3399_PD_USB3 { 1043 reg = <RK3399_PD_USB3>; 1044 clocks = <&cru ACLK_USB3>; 1045 pm_qos = <&qos_usb_otg0>, 1046 <&qos_usb_otg1>; 1047 }; 1048 pd_vio@RK3399_PD_VIO { 1049 reg = <RK3399_PD_VIO>; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 1053 pd_hdcp@RK3399_PD_HDCP { 1054 reg = <RK3399_PD_HDCP>; 1055 clocks = <&cru ACLK_HDCP>, 1056 <&cru HCLK_HDCP>, 1057 <&cru PCLK_HDCP>; 1058 pm_qos = <&qos_hdcp>; 1059 }; 1060 pd_isp0@RK3399_PD_ISP0 { 1061 reg = <RK3399_PD_ISP0>; 1062 clocks = <&cru ACLK_ISP0>, 1063 <&cru HCLK_ISP0>; 1064 pm_qos = <&qos_isp0_m0>, 1065 <&qos_isp0_m1>; 1066 }; 1067 pd_isp1@RK3399_PD_ISP1 { 1068 reg = <RK3399_PD_ISP1>; 1069 clocks = <&cru ACLK_ISP1>, 1070 <&cru HCLK_ISP1>; 1071 pm_qos = <&qos_isp1_m0>, 1072 <&qos_isp1_m1>; 1073 }; 1074 pd_vo@RK3399_PD_VO { 1075 reg = <RK3399_PD_VO>; 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 1079 pd_vopb@RK3399_PD_VOPB { 1080 reg = <RK3399_PD_VOPB>; 1081 clocks = <&cru ACLK_VOP0>, 1082 <&cru HCLK_VOP0>; 1083 pm_qos = <&qos_vop_big_r>, 1084 <&qos_vop_big_w>; 1085 }; 1086 pd_vopl@RK3399_PD_VOPL { 1087 reg = <RK3399_PD_VOPL>; 1088 clocks = <&cru ACLK_VOP1>, 1089 <&cru HCLK_VOP1>; 1090 pm_qos = <&qos_vop_little>; 1091 }; 1092 }; 1093 }; 1094 }; 1095 }; 1096 1097 pmugrf: syscon@ff320000 { 1098 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1099 reg = <0x0 0xff320000 0x0 0x1000>; 1100 1101 pmu_io_domains: io-domains { 1102 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1103 status = "disabled"; 1104 }; 1105 }; 1106 1107 spi3: spi@ff350000 { 1108 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1109 reg = <0x0 0xff350000 0x0 0x1000>; 1110 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1111 clock-names = "spiclk", "apb_pclk"; 1112 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1113 pinctrl-names = "default"; 1114 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 status = "disabled"; 1118 }; 1119 1120 uart4: serial@ff370000 { 1121 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1122 reg = <0x0 0xff370000 0x0 0x100>; 1123 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1124 clock-names = "baudclk", "apb_pclk"; 1125 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1126 reg-shift = <2>; 1127 reg-io-width = <4>; 1128 pinctrl-names = "default"; 1129 pinctrl-0 = <&uart4_xfer>; 1130 status = "disabled"; 1131 }; 1132 1133 i2c0: i2c@ff3c0000 { 1134 compatible = "rockchip,rk3399-i2c"; 1135 reg = <0x0 0xff3c0000 0x0 0x1000>; 1136 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1137 assigned-clock-rates = <200000000>; 1138 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1139 clock-names = "i2c", "pclk"; 1140 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&i2c0_xfer>; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 status = "disabled"; 1146 }; 1147 1148 i2c4: i2c@ff3d0000 { 1149 compatible = "rockchip,rk3399-i2c"; 1150 reg = <0x0 0xff3d0000 0x0 0x1000>; 1151 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1152 assigned-clock-rates = <200000000>; 1153 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1154 clock-names = "i2c", "pclk"; 1155 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1156 pinctrl-names = "default"; 1157 pinctrl-0 = <&i2c4_xfer>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 status = "disabled"; 1161 }; 1162 1163 i2c8: i2c@ff3e0000 { 1164 compatible = "rockchip,rk3399-i2c"; 1165 reg = <0x0 0xff3e0000 0x0 0x1000>; 1166 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1167 assigned-clock-rates = <200000000>; 1168 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1169 clock-names = "i2c", "pclk"; 1170 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1171 pinctrl-names = "default"; 1172 pinctrl-0 = <&i2c8_xfer>; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 status = "disabled"; 1176 }; 1177 1178 pwm0: pwm@ff420000 { 1179 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1180 reg = <0x0 0xff420000 0x0 0x10>; 1181 #pwm-cells = <3>; 1182 pinctrl-names = "default"; 1183 pinctrl-0 = <&pwm0_pin>; 1184 clocks = <&pmucru PCLK_RKPWM_PMU>; 1185 clock-names = "pwm"; 1186 status = "disabled"; 1187 }; 1188 1189 pwm1: pwm@ff420010 { 1190 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1191 reg = <0x0 0xff420010 0x0 0x10>; 1192 #pwm-cells = <3>; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&pwm1_pin>; 1195 clocks = <&pmucru PCLK_RKPWM_PMU>; 1196 clock-names = "pwm"; 1197 status = "disabled"; 1198 }; 1199 1200 pwm2: pwm@ff420020 { 1201 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1202 reg = <0x0 0xff420020 0x0 0x10>; 1203 #pwm-cells = <3>; 1204 pinctrl-names = "default"; 1205 pinctrl-0 = <&pwm2_pin>; 1206 clocks = <&pmucru PCLK_RKPWM_PMU>; 1207 clock-names = "pwm"; 1208 status = "disabled"; 1209 }; 1210 1211 pwm3: pwm@ff420030 { 1212 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1213 reg = <0x0 0xff420030 0x0 0x10>; 1214 #pwm-cells = <3>; 1215 pinctrl-names = "default"; 1216 pinctrl-0 = <&pwm3a_pin>; 1217 clocks = <&pmucru PCLK_RKPWM_PMU>; 1218 clock-names = "pwm"; 1219 status = "disabled"; 1220 }; 1221 1222 vpu: video-codec@ff650000 { 1223 compatible = "rockchip,rk3399-vpu"; 1224 reg = <0x0 0xff650000 0x0 0x800>; 1225 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1226 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1227 interrupt-names = "vepu", "vdpu"; 1228 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1229 clock-names = "aclk", "hclk"; 1230 iommus = <&vpu_mmu>; 1231 power-domains = <&power RK3399_PD_VCODEC>; 1232 }; 1233 1234 vpu_mmu: iommu@ff650800 { 1235 compatible = "rockchip,iommu"; 1236 reg = <0x0 0xff650800 0x0 0x40>; 1237 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1238 interrupt-names = "vpu_mmu"; 1239 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1240 clock-names = "aclk", "iface"; 1241 #iommu-cells = <0>; 1242 power-domains = <&power RK3399_PD_VCODEC>; 1243 }; 1244 1245 vdec: video-codec@ff660000 { 1246 compatible = "rockchip,rk3399-vdec"; 1247 reg = <0x0 0xff660000 0x0 0x400>; 1248 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1249 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, 1250 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; 1251 clock-names = "axi", "ahb", "cabac", "core"; 1252 iommus = <&vdec_mmu>; 1253 power-domains = <&power RK3399_PD_VDU>; 1254 }; 1255 1256 vdec_mmu: iommu@ff660480 { 1257 compatible = "rockchip,iommu"; 1258 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1259 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1260 interrupt-names = "vdec_mmu"; 1261 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1262 clock-names = "aclk", "iface"; 1263 power-domains = <&power RK3399_PD_VDU>; 1264 #iommu-cells = <0>; 1265 }; 1266 1267 iep_mmu: iommu@ff670800 { 1268 compatible = "rockchip,iommu"; 1269 reg = <0x0 0xff670800 0x0 0x40>; 1270 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1271 interrupt-names = "iep_mmu"; 1272 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1273 clock-names = "aclk", "iface"; 1274 #iommu-cells = <0>; 1275 status = "disabled"; 1276 }; 1277 1278 rga: rga@ff680000 { 1279 compatible = "rockchip,rk3399-rga"; 1280 reg = <0x0 0xff680000 0x0 0x10000>; 1281 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1282 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1283 clock-names = "aclk", "hclk", "sclk"; 1284 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1285 reset-names = "core", "axi", "ahb"; 1286 power-domains = <&power RK3399_PD_RGA>; 1287 }; 1288 1289 efuse0: efuse@ff690000 { 1290 compatible = "rockchip,rk3399-efuse"; 1291 reg = <0x0 0xff690000 0x0 0x80>; 1292 #address-cells = <1>; 1293 #size-cells = <1>; 1294 clocks = <&cru PCLK_EFUSE1024NS>; 1295 clock-names = "pclk_efuse"; 1296 1297 /* Data cells */ 1298 cpu_id: cpu-id@7 { 1299 reg = <0x07 0x10>; 1300 }; 1301 cpub_leakage: cpu-leakage@17 { 1302 reg = <0x17 0x1>; 1303 }; 1304 gpu_leakage: gpu-leakage@18 { 1305 reg = <0x18 0x1>; 1306 }; 1307 center_leakage: center-leakage@19 { 1308 reg = <0x19 0x1>; 1309 }; 1310 cpul_leakage: cpu-leakage@1a { 1311 reg = <0x1a 0x1>; 1312 }; 1313 logic_leakage: logic-leakage@1b { 1314 reg = <0x1b 0x1>; 1315 }; 1316 wafer_info: wafer-info@1c { 1317 reg = <0x1c 0x1>; 1318 }; 1319 }; 1320 1321 dmac_bus: dma-controller@ff6d0000 { 1322 compatible = "arm,pl330", "arm,primecell"; 1323 reg = <0x0 0xff6d0000 0x0 0x4000>; 1324 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 1325 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 1326 #dma-cells = <1>; 1327 arm,pl330-periph-burst; 1328 clocks = <&cru ACLK_DMAC0_PERILP>; 1329 clock-names = "apb_pclk"; 1330 }; 1331 1332 dmac_peri: dma-controller@ff6e0000 { 1333 compatible = "arm,pl330", "arm,primecell"; 1334 reg = <0x0 0xff6e0000 0x0 0x4000>; 1335 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 1336 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 1337 #dma-cells = <1>; 1338 arm,pl330-periph-burst; 1339 clocks = <&cru ACLK_DMAC1_PERILP>; 1340 clock-names = "apb_pclk"; 1341 }; 1342 1343 pmucru: pmu-clock-controller@ff750000 { 1344 compatible = "rockchip,rk3399-pmucru"; 1345 reg = <0x0 0xff750000 0x0 0x1000>; 1346 rockchip,grf = <&pmugrf>; 1347 #clock-cells = <1>; 1348 #reset-cells = <1>; 1349 assigned-clocks = <&pmucru PLL_PPLL>; 1350 assigned-clock-rates = <676000000>; 1351 }; 1352 1353 cru: clock-controller@ff760000 { 1354 compatible = "rockchip,rk3399-cru"; 1355 reg = <0x0 0xff760000 0x0 0x1000>; 1356 rockchip,grf = <&grf>; 1357 #clock-cells = <1>; 1358 #reset-cells = <1>; 1359 assigned-clocks = 1360 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1361 <&cru PLL_NPLL>, 1362 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1363 <&cru PCLK_PERIHP>, 1364 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1365 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1366 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1367 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1368 <&cru ACLK_GIC_PRE>, 1369 <&cru PCLK_DDR>; 1370 assigned-clock-rates = 1371 <594000000>, <800000000>, 1372 <1000000000>, 1373 <150000000>, <75000000>, 1374 <37500000>, 1375 <100000000>, <100000000>, 1376 <50000000>, <600000000>, 1377 <100000000>, <50000000>, 1378 <400000000>, <400000000>, 1379 <200000000>, 1380 <200000000>; 1381 }; 1382 1383 grf: syscon@ff770000 { 1384 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1385 reg = <0x0 0xff770000 0x0 0x10000>; 1386 #address-cells = <1>; 1387 #size-cells = <1>; 1388 1389 io_domains: io-domains { 1390 compatible = "rockchip,rk3399-io-voltage-domain"; 1391 status = "disabled"; 1392 }; 1393 1394 mipi_dphy_rx0: mipi-dphy-rx0 { 1395 compatible = "rockchip,rk3399-mipi-dphy-rx0"; 1396 clocks = <&cru SCLK_MIPIDPHY_REF>, 1397 <&cru SCLK_DPHY_RX0_CFG>, 1398 <&cru PCLK_VIO_GRF>; 1399 clock-names = "dphy-ref", "dphy-cfg", "grf"; 1400 power-domains = <&power RK3399_PD_VIO>; 1401 #phy-cells = <0>; 1402 status = "disabled"; 1403 }; 1404 1405 u2phy0: usb2-phy@e450 { 1406 compatible = "rockchip,rk3399-usb2phy"; 1407 reg = <0xe450 0x10>; 1408 clocks = <&cru SCLK_USB2PHY0_REF>; 1409 clock-names = "phyclk"; 1410 #clock-cells = <0>; 1411 clock-output-names = "clk_usbphy0_480m"; 1412 status = "disabled"; 1413 1414 u2phy0_host: host-port { 1415 #phy-cells = <0>; 1416 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1417 interrupt-names = "linestate"; 1418 status = "disabled"; 1419 }; 1420 1421 u2phy0_otg: otg-port { 1422 #phy-cells = <0>; 1423 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1424 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1425 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1426 interrupt-names = "otg-bvalid", "otg-id", 1427 "linestate"; 1428 status = "disabled"; 1429 }; 1430 }; 1431 1432 u2phy1: usb2-phy@e460 { 1433 compatible = "rockchip,rk3399-usb2phy"; 1434 reg = <0xe460 0x10>; 1435 clocks = <&cru SCLK_USB2PHY1_REF>; 1436 clock-names = "phyclk"; 1437 #clock-cells = <0>; 1438 clock-output-names = "clk_usbphy1_480m"; 1439 status = "disabled"; 1440 1441 u2phy1_host: host-port { 1442 #phy-cells = <0>; 1443 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1444 interrupt-names = "linestate"; 1445 status = "disabled"; 1446 }; 1447 1448 u2phy1_otg: otg-port { 1449 #phy-cells = <0>; 1450 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1451 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1452 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1453 interrupt-names = "otg-bvalid", "otg-id", 1454 "linestate"; 1455 status = "disabled"; 1456 }; 1457 }; 1458 1459 emmc_phy: phy@f780 { 1460 compatible = "rockchip,rk3399-emmc-phy"; 1461 reg = <0xf780 0x24>; 1462 clocks = <&sdhci>; 1463 clock-names = "emmcclk"; 1464 #phy-cells = <0>; 1465 status = "disabled"; 1466 }; 1467 1468 pcie_phy: pcie-phy { 1469 compatible = "rockchip,rk3399-pcie-phy"; 1470 clocks = <&cru SCLK_PCIEPHY_REF>; 1471 clock-names = "refclk"; 1472 #phy-cells = <1>; 1473 resets = <&cru SRST_PCIEPHY>; 1474 drive-impedance-ohm = <50>; 1475 reset-names = "phy"; 1476 status = "disabled"; 1477 }; 1478 }; 1479 1480 tcphy0: phy@ff7c0000 { 1481 compatible = "rockchip,rk3399-typec-phy"; 1482 reg = <0x0 0xff7c0000 0x0 0x40000>; 1483 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1484 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1485 clock-names = "tcpdcore", "tcpdphy-ref"; 1486 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1487 assigned-clock-rates = <50000000>; 1488 power-domains = <&power RK3399_PD_TCPD0>; 1489 resets = <&cru SRST_UPHY0>, 1490 <&cru SRST_UPHY0_PIPE_L00>, 1491 <&cru SRST_P_UPHY0_TCPHY>; 1492 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1493 rockchip,grf = <&grf>; 1494 status = "disabled"; 1495 1496 tcphy0_dp: dp-port { 1497 #phy-cells = <0>; 1498 }; 1499 1500 tcphy0_usb3: usb3-port { 1501 #phy-cells = <0>; 1502 }; 1503 }; 1504 1505 tcphy1: phy@ff800000 { 1506 compatible = "rockchip,rk3399-typec-phy"; 1507 reg = <0x0 0xff800000 0x0 0x40000>; 1508 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1509 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1510 clock-names = "tcpdcore", "tcpdphy-ref"; 1511 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1512 assigned-clock-rates = <50000000>; 1513 power-domains = <&power RK3399_PD_TCPD1>; 1514 resets = <&cru SRST_UPHY1>, 1515 <&cru SRST_UPHY1_PIPE_L00>, 1516 <&cru SRST_P_UPHY1_TCPHY>; 1517 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1518 rockchip,grf = <&grf>; 1519 status = "disabled"; 1520 1521 tcphy1_dp: dp-port { 1522 #phy-cells = <0>; 1523 }; 1524 1525 tcphy1_usb3: usb3-port { 1526 #phy-cells = <0>; 1527 }; 1528 }; 1529 1530 watchdog@ff848000 { 1531 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt"; 1532 reg = <0x0 0xff848000 0x0 0x100>; 1533 clocks = <&cru PCLK_WDT>; 1534 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1535 }; 1536 1537 rktimer: rktimer@ff850000 { 1538 compatible = "rockchip,rk3399-timer"; 1539 reg = <0x0 0xff850000 0x0 0x1000>; 1540 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1541 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1542 clock-names = "pclk", "timer"; 1543 }; 1544 1545 spdif: spdif@ff870000 { 1546 compatible = "rockchip,rk3399-spdif"; 1547 reg = <0x0 0xff870000 0x0 0x1000>; 1548 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1549 dmas = <&dmac_bus 7>; 1550 dma-names = "tx"; 1551 clock-names = "mclk", "hclk"; 1552 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1553 pinctrl-names = "default"; 1554 pinctrl-0 = <&spdif_bus>; 1555 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1556 #sound-dai-cells = <0>; 1557 status = "disabled"; 1558 }; 1559 1560 i2s0: i2s@ff880000 { 1561 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1562 reg = <0x0 0xff880000 0x0 0x1000>; 1563 rockchip,grf = <&grf>; 1564 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1565 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1566 dma-names = "tx", "rx"; 1567 clock-names = "i2s_clk", "i2s_hclk"; 1568 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1569 pinctrl-names = "default"; 1570 pinctrl-0 = <&i2s0_8ch_bus>; 1571 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1572 #sound-dai-cells = <0>; 1573 status = "disabled"; 1574 }; 1575 1576 i2s1: i2s@ff890000 { 1577 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1578 reg = <0x0 0xff890000 0x0 0x1000>; 1579 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1580 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1581 dma-names = "tx", "rx"; 1582 clock-names = "i2s_clk", "i2s_hclk"; 1583 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1584 pinctrl-names = "default"; 1585 pinctrl-0 = <&i2s1_2ch_bus>; 1586 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1587 #sound-dai-cells = <0>; 1588 status = "disabled"; 1589 }; 1590 1591 i2s2: i2s@ff8a0000 { 1592 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1593 reg = <0x0 0xff8a0000 0x0 0x1000>; 1594 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1595 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1596 dma-names = "tx", "rx"; 1597 clock-names = "i2s_clk", "i2s_hclk"; 1598 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1599 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1600 #sound-dai-cells = <0>; 1601 status = "disabled"; 1602 }; 1603 1604 vopl: vop@ff8f0000 { 1605 compatible = "rockchip,rk3399-vop-lit"; 1606 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1607 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1608 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1609 assigned-clock-rates = <400000000>, <100000000>; 1610 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1611 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1612 iommus = <&vopl_mmu>; 1613 power-domains = <&power RK3399_PD_VOPL>; 1614 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1615 reset-names = "axi", "ahb", "dclk"; 1616 status = "disabled"; 1617 1618 vopl_out: port { 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 1622 vopl_out_mipi: endpoint@0 { 1623 reg = <0>; 1624 remote-endpoint = <&mipi_in_vopl>; 1625 }; 1626 1627 vopl_out_edp: endpoint@1 { 1628 reg = <1>; 1629 remote-endpoint = <&edp_in_vopl>; 1630 }; 1631 1632 vopl_out_hdmi: endpoint@2 { 1633 reg = <2>; 1634 remote-endpoint = <&hdmi_in_vopl>; 1635 }; 1636 1637 vopl_out_mipi1: endpoint@3 { 1638 reg = <3>; 1639 remote-endpoint = <&mipi1_in_vopl>; 1640 }; 1641 1642 vopl_out_dp: endpoint@4 { 1643 reg = <4>; 1644 remote-endpoint = <&dp_in_vopl>; 1645 }; 1646 }; 1647 }; 1648 1649 vopl_mmu: iommu@ff8f3f00 { 1650 compatible = "rockchip,iommu"; 1651 reg = <0x0 0xff8f3f00 0x0 0x100>; 1652 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1653 interrupt-names = "vopl_mmu"; 1654 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1655 clock-names = "aclk", "iface"; 1656 power-domains = <&power RK3399_PD_VOPL>; 1657 #iommu-cells = <0>; 1658 status = "disabled"; 1659 }; 1660 1661 vopb: vop@ff900000 { 1662 compatible = "rockchip,rk3399-vop-big"; 1663 reg = <0x0 0xff900000 0x0 0x3efc>; 1664 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1665 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1666 assigned-clock-rates = <400000000>, <100000000>; 1667 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1668 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1669 iommus = <&vopb_mmu>; 1670 power-domains = <&power RK3399_PD_VOPB>; 1671 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1672 reset-names = "axi", "ahb", "dclk"; 1673 status = "disabled"; 1674 1675 vopb_out: port { 1676 #address-cells = <1>; 1677 #size-cells = <0>; 1678 1679 vopb_out_edp: endpoint@0 { 1680 reg = <0>; 1681 remote-endpoint = <&edp_in_vopb>; 1682 }; 1683 1684 vopb_out_mipi: endpoint@1 { 1685 reg = <1>; 1686 remote-endpoint = <&mipi_in_vopb>; 1687 }; 1688 1689 vopb_out_hdmi: endpoint@2 { 1690 reg = <2>; 1691 remote-endpoint = <&hdmi_in_vopb>; 1692 }; 1693 1694 vopb_out_mipi1: endpoint@3 { 1695 reg = <3>; 1696 remote-endpoint = <&mipi1_in_vopb>; 1697 }; 1698 1699 vopb_out_dp: endpoint@4 { 1700 reg = <4>; 1701 remote-endpoint = <&dp_in_vopb>; 1702 }; 1703 }; 1704 }; 1705 1706 vopb_mmu: iommu@ff903f00 { 1707 compatible = "rockchip,iommu"; 1708 reg = <0x0 0xff903f00 0x0 0x100>; 1709 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1710 interrupt-names = "vopb_mmu"; 1711 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1712 clock-names = "aclk", "iface"; 1713 power-domains = <&power RK3399_PD_VOPB>; 1714 #iommu-cells = <0>; 1715 status = "disabled"; 1716 }; 1717 1718 isp0: isp0@ff910000 { 1719 compatible = "rockchip,rk3399-cif-isp"; 1720 reg = <0x0 0xff910000 0x0 0x4000>; 1721 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1722 clocks = <&cru SCLK_ISP0>, 1723 <&cru ACLK_ISP0_WRAPPER>, 1724 <&cru HCLK_ISP0_WRAPPER>; 1725 clock-names = "isp", "aclk", "hclk"; 1726 iommus = <&isp0_mmu>; 1727 phys = <&mipi_dphy_rx0>; 1728 phy-names = "dphy"; 1729 power-domains = <&power RK3399_PD_ISP0>; 1730 status = "disabled"; 1731 1732 ports { 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 1736 port@0 { 1737 reg = <0>; 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 }; 1741 }; 1742 }; 1743 1744 isp0_mmu: iommu@ff914000 { 1745 compatible = "rockchip,iommu"; 1746 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1747 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1748 interrupt-names = "isp0_mmu"; 1749 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1750 clock-names = "aclk", "iface"; 1751 #iommu-cells = <0>; 1752 power-domains = <&power RK3399_PD_ISP0>; 1753 rockchip,disable-mmu-reset; 1754 }; 1755 1756 isp1_mmu: iommu@ff924000 { 1757 compatible = "rockchip,iommu"; 1758 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1759 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1760 interrupt-names = "isp1_mmu"; 1761 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; 1762 clock-names = "aclk", "iface"; 1763 #iommu-cells = <0>; 1764 power-domains = <&power RK3399_PD_ISP1>; 1765 rockchip,disable-mmu-reset; 1766 }; 1767 1768 hdmi_sound: hdmi-sound { 1769 compatible = "simple-audio-card"; 1770 simple-audio-card,format = "i2s"; 1771 simple-audio-card,mclk-fs = <256>; 1772 simple-audio-card,name = "hdmi-sound"; 1773 status = "disabled"; 1774 1775 simple-audio-card,cpu { 1776 sound-dai = <&i2s2>; 1777 }; 1778 simple-audio-card,codec { 1779 sound-dai = <&hdmi>; 1780 }; 1781 }; 1782 1783 hdmi: hdmi@ff940000 { 1784 compatible = "rockchip,rk3399-dw-hdmi"; 1785 reg = <0x0 0xff940000 0x0 0x20000>; 1786 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1787 clocks = <&cru PCLK_HDMI_CTRL>, 1788 <&cru SCLK_HDMI_SFR>, 1789 <&cru PLL_VPLL>, 1790 <&cru PCLK_VIO_GRF>, 1791 <&cru SCLK_HDMI_CEC>; 1792 clock-names = "iahb", "isfr", "vpll", "grf", "cec"; 1793 power-domains = <&power RK3399_PD_HDCP>; 1794 reg-io-width = <4>; 1795 rockchip,grf = <&grf>; 1796 #sound-dai-cells = <0>; 1797 status = "disabled"; 1798 1799 ports { 1800 hdmi_in: port { 1801 #address-cells = <1>; 1802 #size-cells = <0>; 1803 1804 hdmi_in_vopb: endpoint@0 { 1805 reg = <0>; 1806 remote-endpoint = <&vopb_out_hdmi>; 1807 }; 1808 hdmi_in_vopl: endpoint@1 { 1809 reg = <1>; 1810 remote-endpoint = <&vopl_out_hdmi>; 1811 }; 1812 }; 1813 }; 1814 }; 1815 1816 mipi_dsi: mipi@ff960000 { 1817 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1818 reg = <0x0 0xff960000 0x0 0x8000>; 1819 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1820 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1821 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1822 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1823 power-domains = <&power RK3399_PD_VIO>; 1824 resets = <&cru SRST_P_MIPI_DSI0>; 1825 reset-names = "apb"; 1826 rockchip,grf = <&grf>; 1827 #address-cells = <1>; 1828 #size-cells = <0>; 1829 status = "disabled"; 1830 1831 ports { 1832 #address-cells = <1>; 1833 #size-cells = <0>; 1834 1835 mipi_in: port@0 { 1836 reg = <0>; 1837 #address-cells = <1>; 1838 #size-cells = <0>; 1839 1840 mipi_in_vopb: endpoint@0 { 1841 reg = <0>; 1842 remote-endpoint = <&vopb_out_mipi>; 1843 }; 1844 mipi_in_vopl: endpoint@1 { 1845 reg = <1>; 1846 remote-endpoint = <&vopl_out_mipi>; 1847 }; 1848 }; 1849 }; 1850 }; 1851 1852 mipi_dsi1: mipi@ff968000 { 1853 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1854 reg = <0x0 0xff968000 0x0 0x8000>; 1855 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 1856 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 1857 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 1858 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1859 power-domains = <&power RK3399_PD_VIO>; 1860 resets = <&cru SRST_P_MIPI_DSI1>; 1861 reset-names = "apb"; 1862 rockchip,grf = <&grf>; 1863 #address-cells = <1>; 1864 #size-cells = <0>; 1865 status = "disabled"; 1866 1867 ports { 1868 #address-cells = <1>; 1869 #size-cells = <0>; 1870 1871 mipi1_in: port@0 { 1872 reg = <0>; 1873 #address-cells = <1>; 1874 #size-cells = <0>; 1875 1876 mipi1_in_vopb: endpoint@0 { 1877 reg = <0>; 1878 remote-endpoint = <&vopb_out_mipi1>; 1879 }; 1880 1881 mipi1_in_vopl: endpoint@1 { 1882 reg = <1>; 1883 remote-endpoint = <&vopl_out_mipi1>; 1884 }; 1885 }; 1886 }; 1887 }; 1888 1889 edp: edp@ff970000 { 1890 compatible = "rockchip,rk3399-edp"; 1891 reg = <0x0 0xff970000 0x0 0x8000>; 1892 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1893 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 1894 clock-names = "dp", "pclk", "grf"; 1895 pinctrl-names = "default"; 1896 pinctrl-0 = <&edp_hpd>; 1897 power-domains = <&power RK3399_PD_EDP>; 1898 resets = <&cru SRST_P_EDP_CTRL>; 1899 reset-names = "dp"; 1900 rockchip,grf = <&grf>; 1901 status = "disabled"; 1902 1903 ports { 1904 #address-cells = <1>; 1905 #size-cells = <0>; 1906 edp_in: port@0 { 1907 reg = <0>; 1908 #address-cells = <1>; 1909 #size-cells = <0>; 1910 1911 edp_in_vopb: endpoint@0 { 1912 reg = <0>; 1913 remote-endpoint = <&vopb_out_edp>; 1914 }; 1915 1916 edp_in_vopl: endpoint@1 { 1917 reg = <1>; 1918 remote-endpoint = <&vopl_out_edp>; 1919 }; 1920 }; 1921 }; 1922 }; 1923 1924 gpu: gpu@ff9a0000 { 1925 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1926 reg = <0x0 0xff9a0000 0x0 0x10000>; 1927 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1928 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, 1929 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 1930 interrupt-names = "job", "mmu", "gpu"; 1931 clocks = <&cru ACLK_GPU>; 1932 #cooling-cells = <2>; 1933 power-domains = <&power RK3399_PD_GPU>; 1934 status = "disabled"; 1935 }; 1936 1937 pinctrl: pinctrl { 1938 compatible = "rockchip,rk3399-pinctrl"; 1939 rockchip,grf = <&grf>; 1940 rockchip,pmu = <&pmugrf>; 1941 #address-cells = <2>; 1942 #size-cells = <2>; 1943 ranges; 1944 1945 gpio0: gpio0@ff720000 { 1946 compatible = "rockchip,gpio-bank"; 1947 reg = <0x0 0xff720000 0x0 0x100>; 1948 clocks = <&pmucru PCLK_GPIO0_PMU>; 1949 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1950 1951 gpio-controller; 1952 #gpio-cells = <0x2>; 1953 1954 interrupt-controller; 1955 #interrupt-cells = <0x2>; 1956 }; 1957 1958 gpio1: gpio1@ff730000 { 1959 compatible = "rockchip,gpio-bank"; 1960 reg = <0x0 0xff730000 0x0 0x100>; 1961 clocks = <&pmucru PCLK_GPIO1_PMU>; 1962 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1963 1964 gpio-controller; 1965 #gpio-cells = <0x2>; 1966 1967 interrupt-controller; 1968 #interrupt-cells = <0x2>; 1969 }; 1970 1971 gpio2: gpio2@ff780000 { 1972 compatible = "rockchip,gpio-bank"; 1973 reg = <0x0 0xff780000 0x0 0x100>; 1974 clocks = <&cru PCLK_GPIO2>; 1975 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1976 1977 gpio-controller; 1978 #gpio-cells = <0x2>; 1979 1980 interrupt-controller; 1981 #interrupt-cells = <0x2>; 1982 }; 1983 1984 gpio3: gpio3@ff788000 { 1985 compatible = "rockchip,gpio-bank"; 1986 reg = <0x0 0xff788000 0x0 0x100>; 1987 clocks = <&cru PCLK_GPIO3>; 1988 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1989 1990 gpio-controller; 1991 #gpio-cells = <0x2>; 1992 1993 interrupt-controller; 1994 #interrupt-cells = <0x2>; 1995 }; 1996 1997 gpio4: gpio4@ff790000 { 1998 compatible = "rockchip,gpio-bank"; 1999 reg = <0x0 0xff790000 0x0 0x100>; 2000 clocks = <&cru PCLK_GPIO4>; 2001 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 2002 2003 gpio-controller; 2004 #gpio-cells = <0x2>; 2005 2006 interrupt-controller; 2007 #interrupt-cells = <0x2>; 2008 }; 2009 2010 pcfg_pull_up: pcfg-pull-up { 2011 bias-pull-up; 2012 }; 2013 2014 pcfg_pull_down: pcfg-pull-down { 2015 bias-pull-down; 2016 }; 2017 2018 pcfg_pull_none: pcfg-pull-none { 2019 bias-disable; 2020 }; 2021 2022 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 2023 bias-disable; 2024 drive-strength = <12>; 2025 }; 2026 2027 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 2028 bias-disable; 2029 drive-strength = <13>; 2030 }; 2031 2032 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 2033 bias-disable; 2034 drive-strength = <18>; 2035 }; 2036 2037 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 2038 bias-disable; 2039 drive-strength = <20>; 2040 }; 2041 2042 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2043 bias-pull-up; 2044 drive-strength = <2>; 2045 }; 2046 2047 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2048 bias-pull-up; 2049 drive-strength = <8>; 2050 }; 2051 2052 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 2053 bias-pull-up; 2054 drive-strength = <18>; 2055 }; 2056 2057 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 2058 bias-pull-up; 2059 drive-strength = <20>; 2060 }; 2061 2062 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2063 bias-pull-down; 2064 drive-strength = <4>; 2065 }; 2066 2067 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 2068 bias-pull-down; 2069 drive-strength = <8>; 2070 }; 2071 2072 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 2073 bias-pull-down; 2074 drive-strength = <12>; 2075 }; 2076 2077 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2078 bias-pull-down; 2079 drive-strength = <18>; 2080 }; 2081 2082 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2083 bias-pull-down; 2084 drive-strength = <20>; 2085 }; 2086 2087 pcfg_output_high: pcfg-output-high { 2088 output-high; 2089 }; 2090 2091 pcfg_output_low: pcfg-output-low { 2092 output-low; 2093 }; 2094 2095 clock { 2096 clk_32k: clk-32k { 2097 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 2098 }; 2099 }; 2100 2101 edp { 2102 edp_hpd: edp-hpd { 2103 rockchip,pins = 2104 <4 RK_PC7 2 &pcfg_pull_none>; 2105 }; 2106 }; 2107 2108 gmac { 2109 rgmii_pins: rgmii-pins { 2110 rockchip,pins = 2111 /* mac_txclk */ 2112 <3 RK_PC1 1 &pcfg_pull_none_13ma>, 2113 /* mac_rxclk */ 2114 <3 RK_PB6 1 &pcfg_pull_none>, 2115 /* mac_mdio */ 2116 <3 RK_PB5 1 &pcfg_pull_none>, 2117 /* mac_txen */ 2118 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2119 /* mac_clk */ 2120 <3 RK_PB3 1 &pcfg_pull_none>, 2121 /* mac_rxdv */ 2122 <3 RK_PB1 1 &pcfg_pull_none>, 2123 /* mac_mdc */ 2124 <3 RK_PB0 1 &pcfg_pull_none>, 2125 /* mac_rxd1 */ 2126 <3 RK_PA7 1 &pcfg_pull_none>, 2127 /* mac_rxd0 */ 2128 <3 RK_PA6 1 &pcfg_pull_none>, 2129 /* mac_txd1 */ 2130 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2131 /* mac_txd0 */ 2132 <3 RK_PA4 1 &pcfg_pull_none_13ma>, 2133 /* mac_rxd3 */ 2134 <3 RK_PA3 1 &pcfg_pull_none>, 2135 /* mac_rxd2 */ 2136 <3 RK_PA2 1 &pcfg_pull_none>, 2137 /* mac_txd3 */ 2138 <3 RK_PA1 1 &pcfg_pull_none_13ma>, 2139 /* mac_txd2 */ 2140 <3 RK_PA0 1 &pcfg_pull_none_13ma>; 2141 }; 2142 2143 rmii_pins: rmii-pins { 2144 rockchip,pins = 2145 /* mac_mdio */ 2146 <3 RK_PB5 1 &pcfg_pull_none>, 2147 /* mac_txen */ 2148 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2149 /* mac_clk */ 2150 <3 RK_PB3 1 &pcfg_pull_none>, 2151 /* mac_rxer */ 2152 <3 RK_PB2 1 &pcfg_pull_none>, 2153 /* mac_rxdv */ 2154 <3 RK_PB1 1 &pcfg_pull_none>, 2155 /* mac_mdc */ 2156 <3 RK_PB0 1 &pcfg_pull_none>, 2157 /* mac_rxd1 */ 2158 <3 RK_PA7 1 &pcfg_pull_none>, 2159 /* mac_rxd0 */ 2160 <3 RK_PA6 1 &pcfg_pull_none>, 2161 /* mac_txd1 */ 2162 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2163 /* mac_txd0 */ 2164 <3 RK_PA4 1 &pcfg_pull_none_13ma>; 2165 }; 2166 }; 2167 2168 i2c0 { 2169 i2c0_xfer: i2c0-xfer { 2170 rockchip,pins = 2171 <1 RK_PB7 2 &pcfg_pull_none>, 2172 <1 RK_PC0 2 &pcfg_pull_none>; 2173 }; 2174 }; 2175 2176 i2c1 { 2177 i2c1_xfer: i2c1-xfer { 2178 rockchip,pins = 2179 <4 RK_PA2 1 &pcfg_pull_none>, 2180 <4 RK_PA1 1 &pcfg_pull_none>; 2181 }; 2182 }; 2183 2184 i2c2 { 2185 i2c2_xfer: i2c2-xfer { 2186 rockchip,pins = 2187 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 2188 <2 RK_PA0 2 &pcfg_pull_none_12ma>; 2189 }; 2190 }; 2191 2192 i2c3 { 2193 i2c3_xfer: i2c3-xfer { 2194 rockchip,pins = 2195 <4 RK_PC1 1 &pcfg_pull_none>, 2196 <4 RK_PC0 1 &pcfg_pull_none>; 2197 }; 2198 }; 2199 2200 i2c4 { 2201 i2c4_xfer: i2c4-xfer { 2202 rockchip,pins = 2203 <1 RK_PB4 1 &pcfg_pull_none>, 2204 <1 RK_PB3 1 &pcfg_pull_none>; 2205 }; 2206 }; 2207 2208 i2c5 { 2209 i2c5_xfer: i2c5-xfer { 2210 rockchip,pins = 2211 <3 RK_PB3 2 &pcfg_pull_none>, 2212 <3 RK_PB2 2 &pcfg_pull_none>; 2213 }; 2214 }; 2215 2216 i2c6 { 2217 i2c6_xfer: i2c6-xfer { 2218 rockchip,pins = 2219 <2 RK_PB2 2 &pcfg_pull_none>, 2220 <2 RK_PB1 2 &pcfg_pull_none>; 2221 }; 2222 }; 2223 2224 i2c7 { 2225 i2c7_xfer: i2c7-xfer { 2226 rockchip,pins = 2227 <2 RK_PB0 2 &pcfg_pull_none>, 2228 <2 RK_PA7 2 &pcfg_pull_none>; 2229 }; 2230 }; 2231 2232 i2c8 { 2233 i2c8_xfer: i2c8-xfer { 2234 rockchip,pins = 2235 <1 RK_PC5 1 &pcfg_pull_none>, 2236 <1 RK_PC4 1 &pcfg_pull_none>; 2237 }; 2238 }; 2239 2240 i2s0 { 2241 i2s0_2ch_bus: i2s0-2ch-bus { 2242 rockchip,pins = 2243 <3 RK_PD0 1 &pcfg_pull_none>, 2244 <3 RK_PD1 1 &pcfg_pull_none>, 2245 <3 RK_PD2 1 &pcfg_pull_none>, 2246 <3 RK_PD3 1 &pcfg_pull_none>, 2247 <3 RK_PD7 1 &pcfg_pull_none>, 2248 <4 RK_PA0 1 &pcfg_pull_none>; 2249 }; 2250 2251 i2s0_8ch_bus: i2s0-8ch-bus { 2252 rockchip,pins = 2253 <3 RK_PD0 1 &pcfg_pull_none>, 2254 <3 RK_PD1 1 &pcfg_pull_none>, 2255 <3 RK_PD2 1 &pcfg_pull_none>, 2256 <3 RK_PD3 1 &pcfg_pull_none>, 2257 <3 RK_PD4 1 &pcfg_pull_none>, 2258 <3 RK_PD5 1 &pcfg_pull_none>, 2259 <3 RK_PD6 1 &pcfg_pull_none>, 2260 <3 RK_PD7 1 &pcfg_pull_none>, 2261 <4 RK_PA0 1 &pcfg_pull_none>; 2262 }; 2263 }; 2264 2265 i2s1 { 2266 i2s1_2ch_bus: i2s1-2ch-bus { 2267 rockchip,pins = 2268 <4 RK_PA3 1 &pcfg_pull_none>, 2269 <4 RK_PA4 1 &pcfg_pull_none>, 2270 <4 RK_PA5 1 &pcfg_pull_none>, 2271 <4 RK_PA6 1 &pcfg_pull_none>, 2272 <4 RK_PA7 1 &pcfg_pull_none>; 2273 }; 2274 }; 2275 2276 sdio0 { 2277 sdio0_bus1: sdio0-bus1 { 2278 rockchip,pins = 2279 <2 RK_PC4 1 &pcfg_pull_up>; 2280 }; 2281 2282 sdio0_bus4: sdio0-bus4 { 2283 rockchip,pins = 2284 <2 RK_PC4 1 &pcfg_pull_up>, 2285 <2 RK_PC5 1 &pcfg_pull_up>, 2286 <2 RK_PC6 1 &pcfg_pull_up>, 2287 <2 RK_PC7 1 &pcfg_pull_up>; 2288 }; 2289 2290 sdio0_cmd: sdio0-cmd { 2291 rockchip,pins = 2292 <2 RK_PD0 1 &pcfg_pull_up>; 2293 }; 2294 2295 sdio0_clk: sdio0-clk { 2296 rockchip,pins = 2297 <2 RK_PD1 1 &pcfg_pull_none>; 2298 }; 2299 2300 sdio0_cd: sdio0-cd { 2301 rockchip,pins = 2302 <2 RK_PD2 1 &pcfg_pull_up>; 2303 }; 2304 2305 sdio0_pwr: sdio0-pwr { 2306 rockchip,pins = 2307 <2 RK_PD3 1 &pcfg_pull_up>; 2308 }; 2309 2310 sdio0_bkpwr: sdio0-bkpwr { 2311 rockchip,pins = 2312 <2 RK_PD4 1 &pcfg_pull_up>; 2313 }; 2314 2315 sdio0_wp: sdio0-wp { 2316 rockchip,pins = 2317 <0 RK_PA3 1 &pcfg_pull_up>; 2318 }; 2319 2320 sdio0_int: sdio0-int { 2321 rockchip,pins = 2322 <0 RK_PA4 1 &pcfg_pull_up>; 2323 }; 2324 }; 2325 2326 sdmmc { 2327 sdmmc_bus1: sdmmc-bus1 { 2328 rockchip,pins = 2329 <4 RK_PB0 1 &pcfg_pull_up>; 2330 }; 2331 2332 sdmmc_bus4: sdmmc-bus4 { 2333 rockchip,pins = 2334 <4 RK_PB0 1 &pcfg_pull_up>, 2335 <4 RK_PB1 1 &pcfg_pull_up>, 2336 <4 RK_PB2 1 &pcfg_pull_up>, 2337 <4 RK_PB3 1 &pcfg_pull_up>; 2338 }; 2339 2340 sdmmc_clk: sdmmc-clk { 2341 rockchip,pins = 2342 <4 RK_PB4 1 &pcfg_pull_none>; 2343 }; 2344 2345 sdmmc_cmd: sdmmc-cmd { 2346 rockchip,pins = 2347 <4 RK_PB5 1 &pcfg_pull_up>; 2348 }; 2349 2350 sdmmc_cd: sdmmc-cd { 2351 rockchip,pins = 2352 <0 RK_PA7 1 &pcfg_pull_up>; 2353 }; 2354 2355 sdmmc_wp: sdmmc-wp { 2356 rockchip,pins = 2357 <0 RK_PB0 1 &pcfg_pull_up>; 2358 }; 2359 }; 2360 2361 sleep { 2362 ap_pwroff: ap-pwroff { 2363 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; 2364 }; 2365 2366 ddrio_pwroff: ddrio-pwroff { 2367 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 2368 }; 2369 }; 2370 2371 spdif { 2372 spdif_bus: spdif-bus { 2373 rockchip,pins = 2374 <4 RK_PC5 1 &pcfg_pull_none>; 2375 }; 2376 2377 spdif_bus_1: spdif-bus-1 { 2378 rockchip,pins = 2379 <3 RK_PC0 3 &pcfg_pull_none>; 2380 }; 2381 }; 2382 2383 spi0 { 2384 spi0_clk: spi0-clk { 2385 rockchip,pins = 2386 <3 RK_PA6 2 &pcfg_pull_up>; 2387 }; 2388 spi0_cs0: spi0-cs0 { 2389 rockchip,pins = 2390 <3 RK_PA7 2 &pcfg_pull_up>; 2391 }; 2392 spi0_cs1: spi0-cs1 { 2393 rockchip,pins = 2394 <3 RK_PB0 2 &pcfg_pull_up>; 2395 }; 2396 spi0_tx: spi0-tx { 2397 rockchip,pins = 2398 <3 RK_PA5 2 &pcfg_pull_up>; 2399 }; 2400 spi0_rx: spi0-rx { 2401 rockchip,pins = 2402 <3 RK_PA4 2 &pcfg_pull_up>; 2403 }; 2404 }; 2405 2406 spi1 { 2407 spi1_clk: spi1-clk { 2408 rockchip,pins = 2409 <1 RK_PB1 2 &pcfg_pull_up>; 2410 }; 2411 spi1_cs0: spi1-cs0 { 2412 rockchip,pins = 2413 <1 RK_PB2 2 &pcfg_pull_up>; 2414 }; 2415 spi1_rx: spi1-rx { 2416 rockchip,pins = 2417 <1 RK_PA7 2 &pcfg_pull_up>; 2418 }; 2419 spi1_tx: spi1-tx { 2420 rockchip,pins = 2421 <1 RK_PB0 2 &pcfg_pull_up>; 2422 }; 2423 }; 2424 2425 spi2 { 2426 spi2_clk: spi2-clk { 2427 rockchip,pins = 2428 <2 RK_PB3 1 &pcfg_pull_up>; 2429 }; 2430 spi2_cs0: spi2-cs0 { 2431 rockchip,pins = 2432 <2 RK_PB4 1 &pcfg_pull_up>; 2433 }; 2434 spi2_rx: spi2-rx { 2435 rockchip,pins = 2436 <2 RK_PB1 1 &pcfg_pull_up>; 2437 }; 2438 spi2_tx: spi2-tx { 2439 rockchip,pins = 2440 <2 RK_PB2 1 &pcfg_pull_up>; 2441 }; 2442 }; 2443 2444 spi3 { 2445 spi3_clk: spi3-clk { 2446 rockchip,pins = 2447 <1 RK_PC1 1 &pcfg_pull_up>; 2448 }; 2449 spi3_cs0: spi3-cs0 { 2450 rockchip,pins = 2451 <1 RK_PC2 1 &pcfg_pull_up>; 2452 }; 2453 spi3_rx: spi3-rx { 2454 rockchip,pins = 2455 <1 RK_PB7 1 &pcfg_pull_up>; 2456 }; 2457 spi3_tx: spi3-tx { 2458 rockchip,pins = 2459 <1 RK_PC0 1 &pcfg_pull_up>; 2460 }; 2461 }; 2462 2463 spi4 { 2464 spi4_clk: spi4-clk { 2465 rockchip,pins = 2466 <3 RK_PA2 2 &pcfg_pull_up>; 2467 }; 2468 spi4_cs0: spi4-cs0 { 2469 rockchip,pins = 2470 <3 RK_PA3 2 &pcfg_pull_up>; 2471 }; 2472 spi4_rx: spi4-rx { 2473 rockchip,pins = 2474 <3 RK_PA0 2 &pcfg_pull_up>; 2475 }; 2476 spi4_tx: spi4-tx { 2477 rockchip,pins = 2478 <3 RK_PA1 2 &pcfg_pull_up>; 2479 }; 2480 }; 2481 2482 spi5 { 2483 spi5_clk: spi5-clk { 2484 rockchip,pins = 2485 <2 RK_PC6 2 &pcfg_pull_up>; 2486 }; 2487 spi5_cs0: spi5-cs0 { 2488 rockchip,pins = 2489 <2 RK_PC7 2 &pcfg_pull_up>; 2490 }; 2491 spi5_rx: spi5-rx { 2492 rockchip,pins = 2493 <2 RK_PC4 2 &pcfg_pull_up>; 2494 }; 2495 spi5_tx: spi5-tx { 2496 rockchip,pins = 2497 <2 RK_PC5 2 &pcfg_pull_up>; 2498 }; 2499 }; 2500 2501 testclk { 2502 test_clkout0: test-clkout0 { 2503 rockchip,pins = 2504 <0 RK_PA0 1 &pcfg_pull_none>; 2505 }; 2506 2507 test_clkout1: test-clkout1 { 2508 rockchip,pins = 2509 <2 RK_PD1 2 &pcfg_pull_none>; 2510 }; 2511 2512 test_clkout2: test-clkout2 { 2513 rockchip,pins = 2514 <0 RK_PB0 3 &pcfg_pull_none>; 2515 }; 2516 }; 2517 2518 tsadc { 2519 otp_pin: otp-pin { 2520 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2521 }; 2522 2523 otp_out: otp-out { 2524 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 2525 }; 2526 }; 2527 2528 uart0 { 2529 uart0_xfer: uart0-xfer { 2530 rockchip,pins = 2531 <2 RK_PC0 1 &pcfg_pull_up>, 2532 <2 RK_PC1 1 &pcfg_pull_none>; 2533 }; 2534 2535 uart0_cts: uart0-cts { 2536 rockchip,pins = 2537 <2 RK_PC2 1 &pcfg_pull_none>; 2538 }; 2539 2540 uart0_rts: uart0-rts { 2541 rockchip,pins = 2542 <2 RK_PC3 1 &pcfg_pull_none>; 2543 }; 2544 }; 2545 2546 uart1 { 2547 uart1_xfer: uart1-xfer { 2548 rockchip,pins = 2549 <3 RK_PB4 2 &pcfg_pull_up>, 2550 <3 RK_PB5 2 &pcfg_pull_none>; 2551 }; 2552 }; 2553 2554 uart2a { 2555 uart2a_xfer: uart2a-xfer { 2556 rockchip,pins = 2557 <4 RK_PB0 2 &pcfg_pull_up>, 2558 <4 RK_PB1 2 &pcfg_pull_none>; 2559 }; 2560 }; 2561 2562 uart2b { 2563 uart2b_xfer: uart2b-xfer { 2564 rockchip,pins = 2565 <4 RK_PC0 2 &pcfg_pull_up>, 2566 <4 RK_PC1 2 &pcfg_pull_none>; 2567 }; 2568 }; 2569 2570 uart2c { 2571 uart2c_xfer: uart2c-xfer { 2572 rockchip,pins = 2573 <4 RK_PC3 1 &pcfg_pull_up>, 2574 <4 RK_PC4 1 &pcfg_pull_none>; 2575 }; 2576 }; 2577 2578 uart3 { 2579 uart3_xfer: uart3-xfer { 2580 rockchip,pins = 2581 <3 RK_PB6 2 &pcfg_pull_up>, 2582 <3 RK_PB7 2 &pcfg_pull_none>; 2583 }; 2584 2585 uart3_cts: uart3-cts { 2586 rockchip,pins = 2587 <3 RK_PC0 2 &pcfg_pull_none>; 2588 }; 2589 2590 uart3_rts: uart3-rts { 2591 rockchip,pins = 2592 <3 RK_PC1 2 &pcfg_pull_none>; 2593 }; 2594 }; 2595 2596 uart4 { 2597 uart4_xfer: uart4-xfer { 2598 rockchip,pins = 2599 <1 RK_PA7 1 &pcfg_pull_up>, 2600 <1 RK_PB0 1 &pcfg_pull_none>; 2601 }; 2602 }; 2603 2604 uarthdcp { 2605 uarthdcp_xfer: uarthdcp-xfer { 2606 rockchip,pins = 2607 <4 RK_PC5 2 &pcfg_pull_up>, 2608 <4 RK_PC6 2 &pcfg_pull_none>; 2609 }; 2610 }; 2611 2612 pwm0 { 2613 pwm0_pin: pwm0-pin { 2614 rockchip,pins = 2615 <4 RK_PC2 1 &pcfg_pull_none>; 2616 }; 2617 2618 pwm0_pin_pull_down: pwm0-pin-pull-down { 2619 rockchip,pins = 2620 <4 RK_PC2 1 &pcfg_pull_down>; 2621 }; 2622 2623 vop0_pwm_pin: vop0-pwm-pin { 2624 rockchip,pins = 2625 <4 RK_PC2 2 &pcfg_pull_none>; 2626 }; 2627 2628 vop1_pwm_pin: vop1-pwm-pin { 2629 rockchip,pins = 2630 <4 RK_PC2 3 &pcfg_pull_none>; 2631 }; 2632 }; 2633 2634 pwm1 { 2635 pwm1_pin: pwm1-pin { 2636 rockchip,pins = 2637 <4 RK_PC6 1 &pcfg_pull_none>; 2638 }; 2639 2640 pwm1_pin_pull_down: pwm1-pin-pull-down { 2641 rockchip,pins = 2642 <4 RK_PC6 1 &pcfg_pull_down>; 2643 }; 2644 }; 2645 2646 pwm2 { 2647 pwm2_pin: pwm2-pin { 2648 rockchip,pins = 2649 <1 RK_PC3 1 &pcfg_pull_none>; 2650 }; 2651 2652 pwm2_pin_pull_down: pwm2-pin-pull-down { 2653 rockchip,pins = 2654 <1 RK_PC3 1 &pcfg_pull_down>; 2655 }; 2656 }; 2657 2658 pwm3a { 2659 pwm3a_pin: pwm3a-pin { 2660 rockchip,pins = 2661 <0 RK_PA6 1 &pcfg_pull_none>; 2662 }; 2663 }; 2664 2665 pwm3b { 2666 pwm3b_pin: pwm3b-pin { 2667 rockchip,pins = 2668 <1 RK_PB6 1 &pcfg_pull_none>; 2669 }; 2670 }; 2671 2672 hdmi { 2673 hdmi_i2c_xfer: hdmi-i2c-xfer { 2674 rockchip,pins = 2675 <4 RK_PC1 3 &pcfg_pull_none>, 2676 <4 RK_PC0 3 &pcfg_pull_none>; 2677 }; 2678 2679 hdmi_cec: hdmi-cec { 2680 rockchip,pins = 2681 <4 RK_PC7 1 &pcfg_pull_none>; 2682 }; 2683 }; 2684 2685 pcie { 2686 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2687 rockchip,pins = 2688 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2689 }; 2690 2691 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2692 rockchip,pins = 2693 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2694 }; 2695 }; 2696 2697 }; 2698}; 2699