1/* 2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/rk3399-cru.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46#include <dt-bindings/interrupt-controller/irq.h> 47#include <dt-bindings/pinctrl/rockchip.h> 48 49/ { 50 compatible = "rockchip,rk3399"; 51 52 interrupt-parent = <&gic>; 53 #address-cells = <2>; 54 #size-cells = <2>; 55 56 aliases { 57 serial0 = &uart0; 58 serial1 = &uart1; 59 serial2 = &uart2; 60 serial3 = &uart3; 61 serial4 = &uart4; 62 }; 63 64 cpus { 65 #address-cells = <2>; 66 #size-cells = <0>; 67 68 cpu-map { 69 cluster0 { 70 core0 { 71 cpu = <&cpu_l0>; 72 }; 73 core1 { 74 cpu = <&cpu_l1>; 75 }; 76 core2 { 77 cpu = <&cpu_l2>; 78 }; 79 core3 { 80 cpu = <&cpu_l3>; 81 }; 82 }; 83 84 cluster1 { 85 core0 { 86 cpu = <&cpu_b0>; 87 }; 88 core1 { 89 cpu = <&cpu_b1>; 90 }; 91 }; 92 }; 93 94 cpu_l0: cpu@0 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53", "arm,armv8"; 97 reg = <0x0 0x0>; 98 enable-method = "psci"; 99 #cooling-cells = <2>; /* min followed by max */ 100 clocks = <&cru ARMCLKL>; 101 }; 102 103 cpu_l1: cpu@1 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a53", "arm,armv8"; 106 reg = <0x0 0x1>; 107 enable-method = "psci"; 108 clocks = <&cru ARMCLKL>; 109 }; 110 111 cpu_l2: cpu@2 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a53", "arm,armv8"; 114 reg = <0x0 0x2>; 115 enable-method = "psci"; 116 clocks = <&cru ARMCLKL>; 117 }; 118 119 cpu_l3: cpu@3 { 120 device_type = "cpu"; 121 compatible = "arm,cortex-a53", "arm,armv8"; 122 reg = <0x0 0x3>; 123 enable-method = "psci"; 124 clocks = <&cru ARMCLKL>; 125 }; 126 127 cpu_b0: cpu@100 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a72", "arm,armv8"; 130 reg = <0x0 0x100>; 131 enable-method = "psci"; 132 #cooling-cells = <2>; /* min followed by max */ 133 clocks = <&cru ARMCLKB>; 134 }; 135 136 cpu_b1: cpu@101 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a72", "arm,armv8"; 139 reg = <0x0 0x101>; 140 enable-method = "psci"; 141 clocks = <&cru ARMCLKB>; 142 }; 143 }; 144 145 psci { 146 compatible = "arm,psci-1.0"; 147 method = "smc"; 148 }; 149 150 timer { 151 compatible = "arm,armv8-timer"; 152 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 153 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 154 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 155 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 156 }; 157 158 xin24m: xin24m { 159 compatible = "fixed-clock"; 160 clock-frequency = <24000000>; 161 clock-output-names = "xin24m"; 162 #clock-cells = <0>; 163 }; 164 165 amba { 166 compatible = "arm,amba-bus"; 167 #address-cells = <2>; 168 #size-cells = <2>; 169 ranges; 170 171 dmac_bus: dma-controller@ff6d0000 { 172 compatible = "arm,pl330", "arm,primecell"; 173 reg = <0x0 0xff6d0000 0x0 0x4000>; 174 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 176 #dma-cells = <1>; 177 clocks = <&cru ACLK_DMAC0_PERILP>; 178 clock-names = "apb_pclk"; 179 }; 180 181 dmac_peri: dma-controller@ff6e0000 { 182 compatible = "arm,pl330", "arm,primecell"; 183 reg = <0x0 0xff6e0000 0x0 0x4000>; 184 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 186 #dma-cells = <1>; 187 clocks = <&cru ACLK_DMAC1_PERILP>; 188 clock-names = "apb_pclk"; 189 }; 190 }; 191 192 sdio0: dwmmc@fe310000 { 193 compatible = "rockchip,rk3399-dw-mshc", 194 "rockchip,rk3288-dw-mshc"; 195 reg = <0x0 0xfe310000 0x0 0x4000>; 196 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 197 clock-freq-min-max = <400000 150000000>; 198 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 199 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 200 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 201 fifo-depth = <0x100>; 202 status = "disabled"; 203 }; 204 205 sdmmc: dwmmc@fe320000 { 206 compatible = "rockchip,rk3399-dw-mshc", 207 "rockchip,rk3288-dw-mshc"; 208 reg = <0x0 0xfe320000 0x0 0x4000>; 209 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 210 clock-freq-min-max = <400000 150000000>; 211 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 212 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 214 fifo-depth = <0x100>; 215 status = "disabled"; 216 }; 217 218 usb_host0_ehci: usb@fe380000 { 219 compatible = "generic-ehci"; 220 reg = <0x0 0xfe380000 0x0 0x20000>; 221 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; 223 clock-names = "hclk_host0", "hclk_host0_arb"; 224 status = "disabled"; 225 }; 226 227 usb_host0_ohci: usb@fe3a0000 { 228 compatible = "generic-ohci"; 229 reg = <0x0 0xfe3a0000 0x0 0x20000>; 230 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; 232 clock-names = "hclk_host0", "hclk_host0_arb"; 233 status = "disabled"; 234 }; 235 236 usb_host1_ehci: usb@fe3c0000 { 237 compatible = "generic-ehci"; 238 reg = <0x0 0xfe3c0000 0x0 0x20000>; 239 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; 241 clock-names = "hclk_host1", "hclk_host1_arb"; 242 status = "disabled"; 243 }; 244 245 usb_host1_ohci: usb@fe3e0000 { 246 compatible = "generic-ohci"; 247 reg = <0x0 0xfe3e0000 0x0 0x20000>; 248 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; 250 clock-names = "hclk_host1", "hclk_host1_arb"; 251 status = "disabled"; 252 }; 253 254 gic: interrupt-controller@fee00000 { 255 compatible = "arm,gic-v3"; 256 #interrupt-cells = <3>; 257 #address-cells = <2>; 258 #size-cells = <2>; 259 ranges; 260 interrupt-controller; 261 262 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 263 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 264 <0x0 0xfff00000 0 0x10000>, /* GICC */ 265 <0x0 0xfff10000 0 0x10000>, /* GICH */ 266 <0x0 0xfff20000 0 0x10000>; /* GICV */ 267 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 268 its: interrupt-controller@fee20000 { 269 compatible = "arm,gic-v3-its"; 270 msi-controller; 271 reg = <0x0 0xfee20000 0x0 0x20000>; 272 }; 273 }; 274 275 uart0: serial@ff180000 { 276 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 277 reg = <0x0 0xff180000 0x0 0x100>; 278 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 279 clock-names = "baudclk", "apb_pclk"; 280 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 281 reg-shift = <2>; 282 reg-io-width = <4>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&uart0_xfer>; 285 status = "disabled"; 286 }; 287 288 uart1: serial@ff190000 { 289 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 290 reg = <0x0 0xff190000 0x0 0x100>; 291 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 292 clock-names = "baudclk", "apb_pclk"; 293 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 294 reg-shift = <2>; 295 reg-io-width = <4>; 296 pinctrl-names = "default"; 297 pinctrl-0 = <&uart1_xfer>; 298 status = "disabled"; 299 }; 300 301 uart2: serial@ff1a0000 { 302 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 303 reg = <0x0 0xff1a0000 0x0 0x100>; 304 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 305 clock-names = "baudclk", "apb_pclk"; 306 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 307 reg-shift = <2>; 308 reg-io-width = <4>; 309 pinctrl-names = "default"; 310 pinctrl-0 = <&uart2c_xfer>; 311 status = "disabled"; 312 }; 313 314 uart3: serial@ff1b0000 { 315 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 316 reg = <0x0 0xff1b0000 0x0 0x100>; 317 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 318 clock-names = "baudclk", "apb_pclk"; 319 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 320 reg-shift = <2>; 321 reg-io-width = <4>; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&uart3_xfer>; 324 status = "disabled"; 325 }; 326 327 spi0: spi@ff1c0000 { 328 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 329 reg = <0x0 0xff1c0000 0x0 0x1000>; 330 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 331 clock-names = "spiclk", "apb_pclk"; 332 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 status = "disabled"; 338 }; 339 340 spi1: spi@ff1d0000 { 341 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 342 reg = <0x0 0xff1d0000 0x0 0x1000>; 343 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 344 clock-names = "spiclk", "apb_pclk"; 345 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 status = "disabled"; 351 }; 352 353 spi2: spi@ff1e0000 { 354 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 355 reg = <0x0 0xff1e0000 0x0 0x1000>; 356 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 357 clock-names = "spiclk", "apb_pclk"; 358 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 status = "disabled"; 364 }; 365 366 spi4: spi@ff1f0000 { 367 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 368 reg = <0x0 0xff1f0000 0x0 0x1000>; 369 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 370 clock-names = "spiclk", "apb_pclk"; 371 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 status = "disabled"; 377 }; 378 379 spi5: spi@ff200000 { 380 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 381 reg = <0x0 0xff200000 0x0 0x1000>; 382 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 383 clock-names = "spiclk", "apb_pclk"; 384 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 status = "disabled"; 390 }; 391 392 pmugrf: syscon@ff320000 { 393 compatible = "rockchip,rk3399-pmugrf", "syscon"; 394 reg = <0x0 0xff320000 0x0 0x1000>; 395 }; 396 397 spi3: spi@ff350000 { 398 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 399 reg = <0x0 0xff350000 0x0 0x1000>; 400 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 401 clock-names = "spiclk", "apb_pclk"; 402 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 status = "disabled"; 408 }; 409 410 uart4: serial@ff370000 { 411 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 412 reg = <0x0 0xff370000 0x0 0x100>; 413 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 414 clock-names = "baudclk", "apb_pclk"; 415 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 416 reg-shift = <2>; 417 reg-io-width = <4>; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&uart4_xfer>; 420 status = "disabled"; 421 }; 422 423 pwm0: pwm@ff420000 { 424 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 425 reg = <0x0 0xff420000 0x0 0x10>; 426 #pwm-cells = <3>; 427 pinctrl-names = "default"; 428 pinctrl-0 = <&pwm0_pin>; 429 clocks = <&pmucru PCLK_RKPWM_PMU>; 430 clock-names = "pwm"; 431 status = "disabled"; 432 }; 433 434 pwm1: pwm@ff420010 { 435 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 436 reg = <0x0 0xff420010 0x0 0x10>; 437 #pwm-cells = <3>; 438 pinctrl-names = "default"; 439 pinctrl-0 = <&pwm1_pin>; 440 clocks = <&pmucru PCLK_RKPWM_PMU>; 441 clock-names = "pwm"; 442 status = "disabled"; 443 }; 444 445 pwm2: pwm@ff420020 { 446 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 447 reg = <0x0 0xff420020 0x0 0x10>; 448 #pwm-cells = <3>; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&pwm2_pin>; 451 clocks = <&pmucru PCLK_RKPWM_PMU>; 452 clock-names = "pwm"; 453 status = "disabled"; 454 }; 455 456 pwm3: pwm@ff420030 { 457 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 458 reg = <0x0 0xff420030 0x0 0x10>; 459 #pwm-cells = <3>; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&pwm3a_pin>; 462 clocks = <&pmucru PCLK_RKPWM_PMU>; 463 clock-names = "pwm"; 464 status = "disabled"; 465 }; 466 467 pmucru: pmu-clock-controller@ff750000 { 468 compatible = "rockchip,rk3399-pmucru"; 469 reg = <0x0 0xff750000 0x0 0x1000>; 470 #clock-cells = <1>; 471 #reset-cells = <1>; 472 assigned-clocks = <&pmucru PLL_PPLL>; 473 assigned-clock-rates = <676000000>; 474 }; 475 476 cru: clock-controller@ff760000 { 477 compatible = "rockchip,rk3399-cru"; 478 reg = <0x0 0xff760000 0x0 0x1000>; 479 #clock-cells = <1>; 480 #reset-cells = <1>; 481 }; 482 483 grf: syscon@ff770000 { 484 compatible = "rockchip,rk3399-grf", "syscon"; 485 reg = <0x0 0xff770000 0x0 0x10000>; 486 }; 487 488 watchdog@ff840000 { 489 compatible = "snps,dw-wdt"; 490 reg = <0x0 0xff840000 0x0 0x100>; 491 clocks = <&cru PCLK_WDT>; 492 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 493 }; 494 495 spdif: spdif@ff870000 { 496 compatible = "rockchip,rk3399-spdif"; 497 reg = <0x0 0xff870000 0x0 0x1000>; 498 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 499 dmas = <&dmac_bus 7>; 500 dma-names = "tx"; 501 clock-names = "mclk", "hclk"; 502 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 503 pinctrl-names = "default"; 504 pinctrl-0 = <&spdif_bus>; 505 status = "disabled"; 506 }; 507 508 i2s0: i2s@ff880000 { 509 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 510 reg = <0x0 0xff880000 0x0 0x1000>; 511 rockchip,grf = <&grf>; 512 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 513 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 514 dma-names = "tx", "rx"; 515 clock-names = "i2s_clk", "i2s_hclk"; 516 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 517 pinctrl-names = "default"; 518 pinctrl-0 = <&i2s0_8ch_bus>; 519 status = "disabled"; 520 }; 521 522 i2s1: i2s@ff890000 { 523 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 524 reg = <0x0 0xff890000 0x0 0x1000>; 525 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 526 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 527 dma-names = "tx", "rx"; 528 clock-names = "i2s_clk", "i2s_hclk"; 529 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 530 pinctrl-names = "default"; 531 pinctrl-0 = <&i2s1_2ch_bus>; 532 status = "disabled"; 533 }; 534 535 i2s2: i2s@ff8a0000 { 536 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 537 reg = <0x0 0xff8a0000 0x0 0x1000>; 538 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 539 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 540 dma-names = "tx", "rx"; 541 clock-names = "i2s_clk", "i2s_hclk"; 542 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 543 status = "disabled"; 544 }; 545 546 pinctrl: pinctrl { 547 compatible = "rockchip,rk3399-pinctrl"; 548 rockchip,grf = <&grf>; 549 rockchip,pmu = <&pmugrf>; 550 #address-cells = <2>; 551 #size-cells = <2>; 552 ranges; 553 554 gpio0: gpio0@ff720000 { 555 compatible = "rockchip,gpio-bank"; 556 reg = <0x0 0xff720000 0x0 0x100>; 557 clocks = <&pmucru PCLK_GPIO0_PMU>; 558 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 559 560 gpio-controller; 561 #gpio-cells = <0x2>; 562 563 interrupt-controller; 564 #interrupt-cells = <0x2>; 565 }; 566 567 gpio1: gpio1@ff730000 { 568 compatible = "rockchip,gpio-bank"; 569 reg = <0x0 0xff730000 0x0 0x100>; 570 clocks = <&pmucru PCLK_GPIO1_PMU>; 571 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 572 573 gpio-controller; 574 #gpio-cells = <0x2>; 575 576 interrupt-controller; 577 #interrupt-cells = <0x2>; 578 }; 579 580 gpio2: gpio2@ff780000 { 581 compatible = "rockchip,gpio-bank"; 582 reg = <0x0 0xff780000 0x0 0x100>; 583 clocks = <&cru PCLK_GPIO2>; 584 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 585 586 gpio-controller; 587 #gpio-cells = <0x2>; 588 589 interrupt-controller; 590 #interrupt-cells = <0x2>; 591 }; 592 593 gpio3: gpio3@ff788000 { 594 compatible = "rockchip,gpio-bank"; 595 reg = <0x0 0xff788000 0x0 0x100>; 596 clocks = <&cru PCLK_GPIO3>; 597 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 598 599 gpio-controller; 600 #gpio-cells = <0x2>; 601 602 interrupt-controller; 603 #interrupt-cells = <0x2>; 604 }; 605 606 gpio4: gpio4@ff790000 { 607 compatible = "rockchip,gpio-bank"; 608 reg = <0x0 0xff790000 0x0 0x100>; 609 clocks = <&cru PCLK_GPIO4>; 610 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 611 612 gpio-controller; 613 #gpio-cells = <0x2>; 614 615 interrupt-controller; 616 #interrupt-cells = <0x2>; 617 }; 618 619 pcfg_pull_up: pcfg-pull-up { 620 bias-pull-up; 621 }; 622 623 pcfg_pull_down: pcfg-pull-down { 624 bias-pull-down; 625 }; 626 627 pcfg_pull_none: pcfg-pull-none { 628 bias-disable; 629 }; 630 631 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 632 bias-disable; 633 drive-strength = <12>; 634 }; 635 636 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 637 bias-pull-up; 638 drive-strength = <8>; 639 }; 640 641 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 642 bias-pull-down; 643 drive-strength = <4>; 644 }; 645 646 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 647 bias-pull-up; 648 drive-strength = <2>; 649 }; 650 651 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 652 bias-pull-down; 653 drive-strength = <12>; 654 }; 655 656 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 657 bias-disable; 658 drive-strength = <13>; 659 }; 660 661 i2c0 { 662 i2c0_xfer: i2c0-xfer { 663 rockchip,pins = 664 <1 15 RK_FUNC_2 &pcfg_pull_none>, 665 <1 16 RK_FUNC_2 &pcfg_pull_none>; 666 }; 667 }; 668 669 i2c1 { 670 i2c1_xfer: i2c1-xfer { 671 rockchip,pins = 672 <4 2 RK_FUNC_1 &pcfg_pull_none>, 673 <4 1 RK_FUNC_1 &pcfg_pull_none>; 674 }; 675 }; 676 677 i2c2 { 678 i2c2_xfer: i2c2-xfer { 679 rockchip,pins = 680 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 681 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; 682 }; 683 }; 684 685 i2c3 { 686 i2c3_xfer: i2c3-xfer { 687 rockchip,pins = 688 <4 17 RK_FUNC_1 &pcfg_pull_none>, 689 <4 16 RK_FUNC_1 &pcfg_pull_none>; 690 }; 691 }; 692 693 i2c4 { 694 i2c4_xfer: i2c4-xfer { 695 rockchip,pins = 696 <1 12 RK_FUNC_1 &pcfg_pull_none>, 697 <1 11 RK_FUNC_1 &pcfg_pull_none>; 698 }; 699 }; 700 701 i2c5 { 702 i2c5_xfer: i2c5-xfer { 703 rockchip,pins = 704 <3 11 RK_FUNC_2 &pcfg_pull_none>, 705 <3 10 RK_FUNC_2 &pcfg_pull_none>; 706 }; 707 }; 708 709 i2c6 { 710 i2c6_xfer: i2c6-xfer { 711 rockchip,pins = 712 <2 10 RK_FUNC_2 &pcfg_pull_none>, 713 <2 9 RK_FUNC_2 &pcfg_pull_none>; 714 }; 715 }; 716 717 i2c7 { 718 i2c7_xfer: i2c7-xfer { 719 rockchip,pins = 720 <2 8 RK_FUNC_2 &pcfg_pull_none>, 721 <2 7 RK_FUNC_2 &pcfg_pull_none>; 722 }; 723 }; 724 725 i2c8 { 726 i2c8_xfer: i2c8-xfer { 727 rockchip,pins = 728 <1 21 RK_FUNC_1 &pcfg_pull_none>, 729 <1 20 RK_FUNC_1 &pcfg_pull_none>; 730 }; 731 }; 732 733 i2s0 { 734 i2s0_8ch_bus: i2s0-8ch-bus { 735 rockchip,pins = 736 <3 24 RK_FUNC_1 &pcfg_pull_none>, 737 <3 25 RK_FUNC_1 &pcfg_pull_none>, 738 <3 26 RK_FUNC_1 &pcfg_pull_none>, 739 <3 27 RK_FUNC_1 &pcfg_pull_none>, 740 <3 28 RK_FUNC_1 &pcfg_pull_none>, 741 <3 29 RK_FUNC_1 &pcfg_pull_none>, 742 <3 30 RK_FUNC_1 &pcfg_pull_none>, 743 <3 31 RK_FUNC_1 &pcfg_pull_none>, 744 <4 0 RK_FUNC_1 &pcfg_pull_none>; 745 }; 746 }; 747 748 i2s1 { 749 i2s1_2ch_bus: i2s1-2ch-bus { 750 rockchip,pins = 751 <4 3 RK_FUNC_1 &pcfg_pull_none>, 752 <4 4 RK_FUNC_1 &pcfg_pull_none>, 753 <4 5 RK_FUNC_1 &pcfg_pull_none>, 754 <4 6 RK_FUNC_1 &pcfg_pull_none>, 755 <4 7 RK_FUNC_1 &pcfg_pull_none>; 756 }; 757 }; 758 759 spdif { 760 spdif_bus: spdif-bus { 761 rockchip,pins = 762 <4 21 RK_FUNC_1 &pcfg_pull_none>; 763 }; 764 }; 765 766 spi0 { 767 spi0_clk: spi0-clk { 768 rockchip,pins = 769 <3 6 RK_FUNC_2 &pcfg_pull_up>; 770 }; 771 spi0_cs0: spi0-cs0 { 772 rockchip,pins = 773 <3 7 RK_FUNC_2 &pcfg_pull_up>; 774 }; 775 spi0_cs1: spi0-cs1 { 776 rockchip,pins = 777 <3 8 RK_FUNC_2 &pcfg_pull_up>; 778 }; 779 spi0_tx: spi0-tx { 780 rockchip,pins = 781 <3 5 RK_FUNC_2 &pcfg_pull_up>; 782 }; 783 spi0_rx: spi0-rx { 784 rockchip,pins = 785 <3 4 RK_FUNC_2 &pcfg_pull_up>; 786 }; 787 }; 788 789 spi1 { 790 spi1_clk: spi1-clk { 791 rockchip,pins = 792 <1 9 RK_FUNC_2 &pcfg_pull_up>; 793 }; 794 spi1_cs0: spi1-cs0 { 795 rockchip,pins = 796 <1 10 RK_FUNC_2 &pcfg_pull_up>; 797 }; 798 spi1_rx: spi1-rx { 799 rockchip,pins = 800 <1 7 RK_FUNC_2 &pcfg_pull_up>; 801 }; 802 spi1_tx: spi1-tx { 803 rockchip,pins = 804 <1 8 RK_FUNC_2 &pcfg_pull_up>; 805 }; 806 }; 807 808 spi2 { 809 spi2_clk: spi2-clk { 810 rockchip,pins = 811 <2 11 RK_FUNC_1 &pcfg_pull_up>; 812 }; 813 spi2_cs0: spi2-cs0 { 814 rockchip,pins = 815 <2 12 RK_FUNC_1 &pcfg_pull_up>; 816 }; 817 spi2_rx: spi2-rx { 818 rockchip,pins = 819 <2 9 RK_FUNC_1 &pcfg_pull_up>; 820 }; 821 spi2_tx: spi2-tx { 822 rockchip,pins = 823 <2 10 RK_FUNC_1 &pcfg_pull_up>; 824 }; 825 }; 826 827 spi3 { 828 spi3_clk: spi3-clk { 829 rockchip,pins = 830 <1 17 RK_FUNC_1 &pcfg_pull_up>; 831 }; 832 spi3_cs0: spi3-cs0 { 833 rockchip,pins = 834 <1 18 RK_FUNC_1 &pcfg_pull_up>; 835 }; 836 spi3_rx: spi3-rx { 837 rockchip,pins = 838 <1 15 RK_FUNC_1 &pcfg_pull_up>; 839 }; 840 spi3_tx: spi3-tx { 841 rockchip,pins = 842 <1 16 RK_FUNC_1 &pcfg_pull_up>; 843 }; 844 }; 845 846 spi4 { 847 spi4_clk: spi4-clk { 848 rockchip,pins = 849 <3 2 RK_FUNC_2 &pcfg_pull_up>; 850 }; 851 spi4_cs0: spi4-cs0 { 852 rockchip,pins = 853 <3 3 RK_FUNC_2 &pcfg_pull_up>; 854 }; 855 spi4_rx: spi4-rx { 856 rockchip,pins = 857 <3 0 RK_FUNC_2 &pcfg_pull_up>; 858 }; 859 spi4_tx: spi4-tx { 860 rockchip,pins = 861 <3 1 RK_FUNC_2 &pcfg_pull_up>; 862 }; 863 }; 864 865 spi5 { 866 spi5_clk: spi5-clk { 867 rockchip,pins = 868 <2 22 RK_FUNC_2 &pcfg_pull_up>; 869 }; 870 spi5_cs0: spi5-cs0 { 871 rockchip,pins = 872 <2 23 RK_FUNC_2 &pcfg_pull_up>; 873 }; 874 spi5_rx: spi5-rx { 875 rockchip,pins = 876 <2 20 RK_FUNC_2 &pcfg_pull_up>; 877 }; 878 spi5_tx: spi5-tx { 879 rockchip,pins = 880 <2 21 RK_FUNC_2 &pcfg_pull_up>; 881 }; 882 }; 883 884 uart0 { 885 uart0_xfer: uart0-xfer { 886 rockchip,pins = 887 <2 16 RK_FUNC_1 &pcfg_pull_up>, 888 <2 17 RK_FUNC_1 &pcfg_pull_none>; 889 }; 890 891 uart0_cts: uart0-cts { 892 rockchip,pins = 893 <2 18 RK_FUNC_1 &pcfg_pull_none>; 894 }; 895 896 uart0_rts: uart0-rts { 897 rockchip,pins = 898 <2 19 RK_FUNC_1 &pcfg_pull_none>; 899 }; 900 }; 901 902 uart1 { 903 uart1_xfer: uart1-xfer { 904 rockchip,pins = 905 <3 12 RK_FUNC_2 &pcfg_pull_up>, 906 <3 13 RK_FUNC_2 &pcfg_pull_none>; 907 }; 908 }; 909 910 uart2a { 911 uart2a_xfer: uart2a-xfer { 912 rockchip,pins = 913 <4 8 RK_FUNC_2 &pcfg_pull_up>, 914 <4 9 RK_FUNC_2 &pcfg_pull_none>; 915 }; 916 }; 917 918 uart2b { 919 uart2b_xfer: uart2b-xfer { 920 rockchip,pins = 921 <4 16 RK_FUNC_2 &pcfg_pull_up>, 922 <4 17 RK_FUNC_2 &pcfg_pull_none>; 923 }; 924 }; 925 926 uart2c { 927 uart2c_xfer: uart2c-xfer { 928 rockchip,pins = 929 <4 19 RK_FUNC_1 &pcfg_pull_up>, 930 <4 20 RK_FUNC_1 &pcfg_pull_none>; 931 }; 932 }; 933 934 uart3 { 935 uart3_xfer: uart3-xfer { 936 rockchip,pins = 937 <3 14 RK_FUNC_2 &pcfg_pull_up>, 938 <3 15 RK_FUNC_2 &pcfg_pull_none>; 939 }; 940 941 uart3_cts: uart3-cts { 942 rockchip,pins = 943 <3 18 RK_FUNC_2 &pcfg_pull_none>; 944 }; 945 946 uart3_rts: uart3-rts { 947 rockchip,pins = 948 <3 19 RK_FUNC_2 &pcfg_pull_none>; 949 }; 950 }; 951 952 uart4 { 953 uart4_xfer: uart4-xfer { 954 rockchip,pins = 955 <1 7 RK_FUNC_1 &pcfg_pull_up>, 956 <1 8 RK_FUNC_1 &pcfg_pull_none>; 957 }; 958 }; 959 960 uarthdcp { 961 uarthdcp_xfer: uarthdcp-xfer { 962 rockchip,pins = 963 <4 21 RK_FUNC_2 &pcfg_pull_up>, 964 <4 22 RK_FUNC_2 &pcfg_pull_none>; 965 }; 966 }; 967 968 pwm0 { 969 pwm0_pin: pwm0-pin { 970 rockchip,pins = 971 <4 18 RK_FUNC_1 &pcfg_pull_none>; 972 }; 973 974 vop0_pwm_pin: vop0-pwm-pin { 975 rockchip,pins = 976 <4 18 RK_FUNC_2 &pcfg_pull_none>; 977 }; 978 }; 979 980 pwm1 { 981 pwm1_pin: pwm1-pin { 982 rockchip,pins = 983 <4 22 RK_FUNC_1 &pcfg_pull_none>; 984 }; 985 986 vop1_pwm_pin: vop1-pwm-pin { 987 rockchip,pins = 988 <4 18 RK_FUNC_3 &pcfg_pull_none>; 989 }; 990 }; 991 992 pwm2 { 993 pwm2_pin: pwm2-pin { 994 rockchip,pins = 995 <1 19 RK_FUNC_1 &pcfg_pull_none>; 996 }; 997 }; 998 999 pwm3a { 1000 pwm3a_pin: pwm3a-pin { 1001 rockchip,pins = 1002 <0 6 RK_FUNC_1 &pcfg_pull_none>; 1003 }; 1004 }; 1005 1006 pwm3b { 1007 pwm3b_pin: pwm3b-pin { 1008 rockchip,pins = 1009 <1 14 RK_FUNC_1 &pcfg_pull_none>; 1010 }; 1011 }; 1012 }; 1013}; 1014