1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 4 * Copyright (c) 2022 Radxa Limited 5 */ 6 7#include "rk3399-base.dtsi" 8 9/ { 10 cluster0_opp: opp-table-0 { 11 compatible = "operating-points-v2"; 12 opp-shared; 13 14 opp00 { 15 opp-hz = /bits/ 64 <408000000>; 16 opp-microvolt = <875000 875000 1250000>; 17 clock-latency-ns = <40000>; 18 }; 19 opp01 { 20 opp-hz = /bits/ 64 <600000000>; 21 opp-microvolt = <875000 875000 1250000>; 22 }; 23 opp02 { 24 opp-hz = /bits/ 64 <816000000>; 25 opp-microvolt = <900000 900000 1250000>; 26 }; 27 opp03 { 28 opp-hz = /bits/ 64 <1008000000>; 29 opp-microvolt = <975000 975000 1250000>; 30 }; 31 }; 32 33 cluster1_opp: opp-table-1 { 34 compatible = "operating-points-v2"; 35 opp-shared; 36 37 opp00 { 38 opp-hz = /bits/ 64 <408000000>; 39 opp-microvolt = <875000 875000 1250000>; 40 clock-latency-ns = <40000>; 41 }; 42 opp01 { 43 opp-hz = /bits/ 64 <600000000>; 44 opp-microvolt = <875000 875000 1250000>; 45 }; 46 opp02 { 47 opp-hz = /bits/ 64 <816000000>; 48 opp-microvolt = <875000 875000 1250000>; 49 }; 50 opp03 { 51 opp-hz = /bits/ 64 <1008000000>; 52 opp-microvolt = <925000 925000 1250000>; 53 }; 54 opp04 { 55 opp-hz = /bits/ 64 <1200000000>; 56 opp-microvolt = <1000000 1000000 1250000>; 57 }; 58 opp05 { 59 opp-hz = /bits/ 64 <1416000000>; 60 opp-microvolt = <1075000 1075000 1250000>; 61 }; 62 opp06 { 63 opp-hz = /bits/ 64 <1512000000>; 64 opp-microvolt = <1150000 1150000 1250000>; 65 }; 66 }; 67 68 gpu_opp_table: opp-table-2 { 69 compatible = "operating-points-v2"; 70 71 opp00 { 72 opp-hz = /bits/ 64 <200000000>; 73 opp-microvolt = <875000 875000 1150000>; 74 }; 75 opp01 { 76 opp-hz = /bits/ 64 <300000000>; 77 opp-microvolt = <875000 875000 1150000>; 78 }; 79 opp02 { 80 opp-hz = /bits/ 64 <400000000>; 81 opp-microvolt = <875000 875000 1150000>; 82 }; 83 opp03 { 84 opp-hz = /bits/ 64 <600000000>; 85 opp-microvolt = <975000 975000 1150000>; 86 }; 87 }; 88}; 89 90&cpu_l0 { 91 operating-points-v2 = <&cluster0_opp>; 92}; 93 94&cpu_l1 { 95 operating-points-v2 = <&cluster0_opp>; 96}; 97 98&cpu_l2 { 99 operating-points-v2 = <&cluster0_opp>; 100}; 101 102&cpu_l3 { 103 operating-points-v2 = <&cluster0_opp>; 104}; 105 106&cpu_b0 { 107 operating-points-v2 = <&cluster1_opp>; 108}; 109 110&cpu_b1 { 111 operating-points-v2 = <&cluster1_opp>; 112}; 113 114&gpu { 115 operating-points-v2 = <&gpu_opp_table>; 116}; 117