1*f7f8ec7dSDragan Simic// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*f7f8ec7dSDragan Simic/* 3*f7f8ec7dSDragan Simic * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 4*f7f8ec7dSDragan Simic */ 5*f7f8ec7dSDragan Simic 6*f7f8ec7dSDragan Simic#include "rk3399-base.dtsi" 7*f7f8ec7dSDragan Simic 8*f7f8ec7dSDragan Simic/ { 9*f7f8ec7dSDragan Simic cluster0_opp: opp-table-0 { 10*f7f8ec7dSDragan Simic compatible = "operating-points-v2"; 11*f7f8ec7dSDragan Simic opp-shared; 12*f7f8ec7dSDragan Simic 13*f7f8ec7dSDragan Simic opp00 { 14*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <408000000>; 15*f7f8ec7dSDragan Simic opp-microvolt = <825000 825000 1250000>; 16*f7f8ec7dSDragan Simic clock-latency-ns = <40000>; 17*f7f8ec7dSDragan Simic }; 18*f7f8ec7dSDragan Simic opp01 { 19*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <600000000>; 20*f7f8ec7dSDragan Simic opp-microvolt = <825000 825000 1250000>; 21*f7f8ec7dSDragan Simic }; 22*f7f8ec7dSDragan Simic opp02 { 23*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <816000000>; 24*f7f8ec7dSDragan Simic opp-microvolt = <850000 850000 1250000>; 25*f7f8ec7dSDragan Simic }; 26*f7f8ec7dSDragan Simic opp03 { 27*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <1008000000>; 28*f7f8ec7dSDragan Simic opp-microvolt = <925000 925000 1250000>; 29*f7f8ec7dSDragan Simic }; 30*f7f8ec7dSDragan Simic }; 31*f7f8ec7dSDragan Simic 32*f7f8ec7dSDragan Simic cluster1_opp: opp-table-1 { 33*f7f8ec7dSDragan Simic compatible = "operating-points-v2"; 34*f7f8ec7dSDragan Simic opp-shared; 35*f7f8ec7dSDragan Simic 36*f7f8ec7dSDragan Simic opp00 { 37*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <408000000>; 38*f7f8ec7dSDragan Simic opp-microvolt = <825000 825000 1250000>; 39*f7f8ec7dSDragan Simic clock-latency-ns = <40000>; 40*f7f8ec7dSDragan Simic }; 41*f7f8ec7dSDragan Simic opp01 { 42*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <600000000>; 43*f7f8ec7dSDragan Simic opp-microvolt = <825000 825000 1250000>; 44*f7f8ec7dSDragan Simic }; 45*f7f8ec7dSDragan Simic opp02 { 46*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <816000000>; 47*f7f8ec7dSDragan Simic opp-microvolt = <825000 825000 1250000>; 48*f7f8ec7dSDragan Simic }; 49*f7f8ec7dSDragan Simic opp03 { 50*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <1008000000>; 51*f7f8ec7dSDragan Simic opp-microvolt = <875000 875000 1250000>; 52*f7f8ec7dSDragan Simic }; 53*f7f8ec7dSDragan Simic opp04 { 54*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <1200000000>; 55*f7f8ec7dSDragan Simic opp-microvolt = <950000 950000 1250000>; 56*f7f8ec7dSDragan Simic }; 57*f7f8ec7dSDragan Simic opp05 { 58*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <1416000000>; 59*f7f8ec7dSDragan Simic opp-microvolt = <1025000 1025000 1250000>; 60*f7f8ec7dSDragan Simic }; 61*f7f8ec7dSDragan Simic opp06 { 62*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <1500000000>; 63*f7f8ec7dSDragan Simic opp-microvolt = <1100000 1100000 1150000>; 64*f7f8ec7dSDragan Simic }; 65*f7f8ec7dSDragan Simic }; 66*f7f8ec7dSDragan Simic 67*f7f8ec7dSDragan Simic gpu_opp_table: opp-table-2 { 68*f7f8ec7dSDragan Simic compatible = "operating-points-v2"; 69*f7f8ec7dSDragan Simic 70*f7f8ec7dSDragan Simic opp00 { 71*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <200000000>; 72*f7f8ec7dSDragan Simic opp-microvolt = <825000 825000 1150000>; 73*f7f8ec7dSDragan Simic }; 74*f7f8ec7dSDragan Simic opp01 { 75*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <297000000>; 76*f7f8ec7dSDragan Simic opp-microvolt = <825000 825000 1150000>; 77*f7f8ec7dSDragan Simic }; 78*f7f8ec7dSDragan Simic opp02 { 79*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <400000000>; 80*f7f8ec7dSDragan Simic opp-microvolt = <825000 825000 1150000>; 81*f7f8ec7dSDragan Simic }; 82*f7f8ec7dSDragan Simic opp03 { 83*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <500000000>; 84*f7f8ec7dSDragan Simic opp-microvolt = <875000 875000 1150000>; 85*f7f8ec7dSDragan Simic }; 86*f7f8ec7dSDragan Simic opp04 { 87*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <600000000>; 88*f7f8ec7dSDragan Simic opp-microvolt = <925000 925000 1150000>; 89*f7f8ec7dSDragan Simic }; 90*f7f8ec7dSDragan Simic opp05 { 91*f7f8ec7dSDragan Simic opp-hz = /bits/ 64 <800000000>; 92*f7f8ec7dSDragan Simic opp-microvolt = <1100000 1100000 1150000>; 93*f7f8ec7dSDragan Simic }; 94*f7f8ec7dSDragan Simic }; 95*f7f8ec7dSDragan Simic}; 96*f7f8ec7dSDragan Simic 97*f7f8ec7dSDragan Simic&cpu_l0 { 98*f7f8ec7dSDragan Simic operating-points-v2 = <&cluster0_opp>; 99*f7f8ec7dSDragan Simic}; 100*f7f8ec7dSDragan Simic 101*f7f8ec7dSDragan Simic&cpu_l1 { 102*f7f8ec7dSDragan Simic operating-points-v2 = <&cluster0_opp>; 103*f7f8ec7dSDragan Simic}; 104*f7f8ec7dSDragan Simic 105*f7f8ec7dSDragan Simic&cpu_l2 { 106*f7f8ec7dSDragan Simic operating-points-v2 = <&cluster0_opp>; 107*f7f8ec7dSDragan Simic}; 108*f7f8ec7dSDragan Simic 109*f7f8ec7dSDragan Simic&cpu_l3 { 110*f7f8ec7dSDragan Simic operating-points-v2 = <&cluster0_opp>; 111*f7f8ec7dSDragan Simic}; 112*f7f8ec7dSDragan Simic 113*f7f8ec7dSDragan Simic&cpu_b0 { 114*f7f8ec7dSDragan Simic operating-points-v2 = <&cluster1_opp>; 115*f7f8ec7dSDragan Simic}; 116*f7f8ec7dSDragan Simic 117*f7f8ec7dSDragan Simic&cpu_b1 { 118*f7f8ec7dSDragan Simic operating-points-v2 = <&cluster1_opp>; 119*f7f8ec7dSDragan Simic}; 120*f7f8ec7dSDragan Simic 121*f7f8ec7dSDragan Simic&gpu { 122*f7f8ec7dSDragan Simic operating-points-v2 = <&gpu_opp_table>; 123*f7f8ec7dSDragan Simic}; 124