1/* 2 * Google Gru (and derivatives) board device tree source 3 * 4 * Copyright 2016-2017 Google, Inc 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/input/input.h> 46#include "rk3399.dtsi" 47#include "rk3399-opp.dtsi" 48 49/ { 50 chosen { 51 stdout-path = "serial2:115200n8"; 52 }; 53 54 /* 55 * Power Tree 56 * 57 * In general an attempt is made to include all rails called out by 58 * the schematic as long as those rails interact in some way with 59 * the AP. AKA: 60 * - Rails that only connect to the EC (or devices that the EC talks to) 61 * are not included. 62 * - Rails _are_ included if the rails go to the AP even if the AP 63 * doesn't currently care about them / they are always on. The idea 64 * here is that it makes it easier to map to the schematic or extend 65 * later. 66 * 67 * If two rails are substantially the same from the AP's point of 68 * view, though, we won't create a full fixed regulator. We'll just 69 * put the child rail as an alias of the parent rail. Sometimes rails 70 * look the same to the AP because one of these is true: 71 * - The EC controls the enable and the EC always enables a rail as 72 * long as the AP is running. 73 * - The rails are actually connected to each other by a jumper and 74 * the distinction is just there to add clarity/flexibility to the 75 * schematic. 76 */ 77 78 ppvar_sys: ppvar-sys { 79 compatible = "regulator-fixed"; 80 regulator-name = "ppvar_sys"; 81 regulator-always-on; 82 regulator-boot-on; 83 }; 84 85 pp900_ap: pp900-ap { 86 compatible = "regulator-fixed"; 87 regulator-name = "pp900_ap"; 88 89 /* EC turns on w/ pp900_ap_en; always on for AP */ 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <900000>; 93 regulator-max-microvolt = <900000>; 94 95 vin-supply = <&ppvar_sys>; 96 }; 97 98 pp1200_lpddr: pp1200-lpddr { 99 compatible = "regulator-fixed"; 100 regulator-name = "pp1200_lpddr"; 101 102 /* EC turns on w/ lpddr_pwr_en; always on for AP */ 103 regulator-always-on; 104 regulator-boot-on; 105 regulator-min-microvolt = <1200000>; 106 regulator-max-microvolt = <1200000>; 107 108 vin-supply = <&ppvar_sys>; 109 }; 110 111 pp1800: pp1800 { 112 compatible = "regulator-fixed"; 113 regulator-name = "pp1800"; 114 115 /* Always on when ppvar_sys shows power good */ 116 regulator-always-on; 117 regulator-boot-on; 118 regulator-min-microvolt = <1800000>; 119 regulator-max-microvolt = <1800000>; 120 121 vin-supply = <&ppvar_sys>; 122 }; 123 124 pp3000: pp3000 { 125 compatible = "regulator-fixed"; 126 regulator-name = "pp3000"; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pp3000_en>; 129 130 enable-active-high; 131 gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; 132 133 regulator-always-on; 134 regulator-boot-on; 135 regulator-min-microvolt = <3000000>; 136 regulator-max-microvolt = <3000000>; 137 138 vin-supply = <&ppvar_sys>; 139 }; 140 141 pp3300: pp3300 { 142 compatible = "regulator-fixed"; 143 regulator-name = "pp3300"; 144 145 /* Always on; plain and simple */ 146 regulator-always-on; 147 regulator-boot-on; 148 regulator-min-microvolt = <3300000>; 149 regulator-max-microvolt = <3300000>; 150 151 vin-supply = <&ppvar_sys>; 152 }; 153 154 pp5000: pp5000 { 155 compatible = "regulator-fixed"; 156 regulator-name = "pp5000"; 157 158 /* EC turns on w/ pp5000_en; always on for AP */ 159 regulator-always-on; 160 regulator-boot-on; 161 regulator-min-microvolt = <5000000>; 162 regulator-max-microvolt = <5000000>; 163 164 vin-supply = <&ppvar_sys>; 165 }; 166 167 ppvar_bigcpu: ppvar-bigcpu { 168 compatible = "pwm-regulator"; 169 regulator-name = "ppvar_bigcpu"; 170 /* 171 * OVP circuit requires special handling which is not yet 172 * represented. Keep disabled for now. 173 */ 174 status = "disabled"; 175 176 pwms = <&pwm1 0 3337 0>; 177 pwm-supply = <&ppvar_sys>; 178 pwm-dutycycle-range = <100 0>; 179 pwm-dutycycle-unit = <100>; 180 181 /* EC turns on w/ ap_core_en; always on for AP */ 182 regulator-always-on; 183 regulator-boot-on; 184 regulator-min-microvolt = <798674>; 185 regulator-max-microvolt = <1302172>; 186 }; 187 188 ppvar_litcpu: ppvar-litcpu { 189 compatible = "pwm-regulator"; 190 regulator-name = "ppvar_litcpu"; 191 /* 192 * OVP circuit requires special handling which is not yet 193 * represented. Keep disabled for now. 194 */ 195 status = "disabled"; 196 197 pwms = <&pwm2 0 3337 0>; 198 pwm-supply = <&ppvar_sys>; 199 pwm-dutycycle-range = <100 0>; 200 pwm-dutycycle-unit = <100>; 201 202 /* EC turns on w/ ap_core_en; always on for AP */ 203 regulator-always-on; 204 regulator-boot-on; 205 regulator-min-microvolt = <799065>; 206 regulator-max-microvolt = <1303738>; 207 }; 208 209 ppvar_gpu: ppvar-gpu { 210 compatible = "pwm-regulator"; 211 regulator-name = "ppvar_gpu"; 212 /* 213 * OVP circuit requires special handling which is not yet 214 * represented. Keep disabled for now. 215 */ 216 status = "disabled"; 217 218 pwms = <&pwm0 0 3337 0>; 219 pwm-supply = <&ppvar_sys>; 220 pwm-dutycycle-range = <100 0>; 221 pwm-dutycycle-unit = <100>; 222 223 /* EC turns on w/ ap_core_en; always on for AP */ 224 regulator-always-on; 225 regulator-boot-on; 226 regulator-min-microvolt = <785782>; 227 regulator-max-microvolt = <1217729>; 228 }; 229 230 ppvar_centerlogic: ppvar-centerlogic { 231 compatible = "pwm-regulator"; 232 regulator-name = "ppvar_centerlogic"; 233 /* 234 * OVP circuit requires special handling which is not yet 235 * represented. Keep disabled for now. 236 */ 237 status = "disabled"; 238 239 pwms = <&pwm3 0 3337 0>; 240 pwm-supply = <&ppvar_sys>; 241 pwm-dutycycle-range = <100 0>; 242 pwm-dutycycle-unit = <100>; 243 244 /* EC turns on w/ ppvar_centerlogic_en; always on for AP */ 245 regulator-always-on; 246 regulator-boot-on; 247 regulator-min-microvolt = <800069>; 248 regulator-max-microvolt = <1049692>; 249 }; 250 251 /* Schematics call this PPVAR even though it's fixed */ 252 ppvar_logic: ppvar-logic { 253 compatible = "regulator-fixed"; 254 regulator-name = "ppvar_logic"; 255 256 /* EC turns on w/ ppvar_logic_en; always on for AP */ 257 regulator-always-on; 258 regulator-boot-on; 259 regulator-min-microvolt = <900000>; 260 regulator-max-microvolt = <900000>; 261 262 vin-supply = <&ppvar_sys>; 263 }; 264 265 /* EC turns on w/ pp900_ddrpll_en */ 266 pp900_ddrpll: pp900-ap { 267 }; 268 269 /* EC turns on w/ pp900_pcie_en */ 270 pp900_pcie: pp900-ap { 271 }; 272 273 /* EC turns on w/ pp900_pll_en */ 274 pp900_pll: pp900-ap { 275 }; 276 277 /* EC turns on w/ pp900_pmu_en */ 278 pp900_pmu: pp900-ap { 279 }; 280 281 /* EC turns on w/ pp900_usb_en */ 282 pp900_usb: pp900-ap { 283 }; 284 285 /* EC turns on w/ pp1800_s0_en_l */ 286 pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 { 287 }; 288 289 /* EC turns on w/ pp1800_avdd_en_l */ 290 pp1800_avdd: pp1800 { 291 }; 292 293 /* EC turns on w/ pp1800_lid_en_l */ 294 pp1800_lid: pp1800_mic: pp1800 { 295 }; 296 297 /* EC turns on w/ lpddr_pwr_en */ 298 pp1800_lpddr: pp1800 { 299 }; 300 301 /* EC turns on w/ pp1800_pmu_en_l */ 302 pp1800_pmu: pp1800 { 303 }; 304 305 /* EC turns on w/ pp1800_usb_en_l */ 306 pp1800_usb: pp1800 { 307 }; 308 309 pp1500_ap_io: pp1500-ap-io { 310 compatible = "regulator-fixed"; 311 regulator-name = "pp1500_ap_io"; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&pp1500_en>; 314 315 enable-active-high; 316 gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; 317 318 regulator-always-on; 319 regulator-boot-on; 320 regulator-min-microvolt = <1500000>; 321 regulator-max-microvolt = <1500000>; 322 323 vin-supply = <&pp1800>; 324 }; 325 326 pp1800_audio: pp1800-audio { 327 compatible = "regulator-fixed"; 328 regulator-name = "pp1800_audio"; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pp1800_audio_en>; 331 332 enable-active-high; 333 gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; 334 335 regulator-always-on; 336 regulator-boot-on; 337 338 vin-supply = <&pp1800>; 339 }; 340 341 /* gpio is shared with pp3300_wifi_bt */ 342 pp1800_pcie: pp1800-pcie { 343 compatible = "regulator-fixed"; 344 regulator-name = "pp1800_pcie"; 345 pinctrl-names = "default"; 346 pinctrl-0 = <&wlan_module_pd_l>; 347 348 enable-active-high; 349 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; 350 351 /* 352 * Need to wait 1ms + ramp-up time before we can power on WiFi. 353 * This has been approximated as 8ms total. 354 */ 355 regulator-enable-ramp-delay = <8000>; 356 357 vin-supply = <&pp1800>; 358 }; 359 360 /* 361 * This is a bit of a hack. The WiFi module should be reset at least 362 * 1ms after its regulators have ramped up (max rampup time is ~7ms). 363 * With some stretching of the imagination, we can call the 1.8V 364 * regulator a supply. 365 */ 366 wlan_pd_n: wlan-pd-n { 367 compatible = "regulator-fixed"; 368 regulator-name = "wlan_pd_n"; 369 370 /* Note the wlan_module_reset_l pinctrl */ 371 enable-active-high; 372 gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; 373 374 vin-supply = <&pp1800_pcie>; 375 }; 376 377 /* Always on; plain and simple */ 378 pp3000_ap: pp3000_emmc: pp3000 { 379 }; 380 381 pp3000_sd_slot: pp3000-sd-slot { 382 compatible = "regulator-fixed"; 383 regulator-name = "pp3000_sd_slot"; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&sd_slot_pwr_en>; 386 387 enable-active-high; 388 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 389 390 vin-supply = <&pp3000>; 391 }; 392 393 /* 394 * Technically, this is a small abuse of 'regulator-gpio'; this 395 * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are 396 * always on though, so it is sufficient to simply control the mux 397 * here. 398 */ 399 ppvar_sd_card_io: ppvar-sd-card-io { 400 compatible = "regulator-gpio"; 401 regulator-name = "ppvar_sd_card_io"; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; 404 405 enable-active-high; 406 enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; 407 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; 408 states = <1800000 0x1 409 3000000 0x0>; 410 411 regulator-min-microvolt = <1800000>; 412 regulator-max-microvolt = <3000000>; 413 }; 414 415 /* EC turns on w/ pp3300_trackpad_en_l */ 416 pp3300_trackpad: pp3300-trackpad { 417 }; 418 419 /* EC turns on w/ pp3300_usb_en_l */ 420 pp3300_usb: pp3300 { 421 }; 422 423 pp3300_disp: pp3300-disp { 424 compatible = "regulator-fixed"; 425 regulator-name = "pp3300_disp"; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&pp3300_disp_en>; 428 429 enable-active-high; 430 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 431 432 startup-delay-us = <2000>; 433 vin-supply = <&pp3300>; 434 }; 435 436 /* gpio is shared with pp1800_pcie and pinctrl is set there */ 437 pp3300_wifi_bt: pp3300-wifi-bt { 438 compatible = "regulator-fixed"; 439 regulator-name = "pp3300_wifi_bt"; 440 441 enable-active-high; 442 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; 443 444 vin-supply = <&pp3300>; 445 }; 446 447 /* EC turns on w/ usb_a_en */ 448 pp5000_usb_a_vbus: pp5000 { 449 }; 450 451 gpio_keys: gpio-keys { 452 compatible = "gpio-keys"; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&bt_host_wake_l>; 455 456 wake-on-bt { 457 label = "Wake-on-Bluetooth"; 458 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; 459 linux,code = <KEY_WAKEUP>; 460 wakeup-source; 461 }; 462 }; 463 464 max98357a: max98357a { 465 compatible = "maxim,max98357a"; 466 pinctrl-names = "default"; 467 pinctrl-0 = <&sdmode_en>; 468 sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 469 sdmode-delay = <2>; 470 #sound-dai-cells = <0>; 471 status = "okay"; 472 }; 473 474 sound { 475 compatible = "rockchip,rk3399-gru-sound"; 476 rockchip,cpu = <&i2s0 &i2s2>; 477 rockchip,codec = <&max98357a &headsetcodec &codec>; 478 }; 479}; 480 481/* 482 * Set some suspend operating points to avoid OVP in suspend 483 * 484 * When we go into S3 ARM Trusted Firmware will transition our PWM regulators 485 * from wherever they're at back to the "default" operating point (whatever 486 * voltage we get when we set the PWM pins to "input"). 487 * 488 * This quick transition under light load has the possibility to trigger the 489 * regulator "over voltage protection" (OVP). 490 * 491 * To make extra certain that we don't hit this OVP at suspend time, we'll 492 * transition to a voltage that's much closer to the default (~1.0 V) so that 493 * there will not be a big jump. Technically we only need to get within 200 mV 494 * of the default voltage, but the speed here should be fast enough and we need 495 * suspend/resume to be rock solid. 496 */ 497 498&cluster0_opp { 499 opp05 { 500 opp-suspend; 501 }; 502}; 503 504&cluster1_opp { 505 opp06 { 506 opp-suspend; 507 }; 508}; 509 510&cpu_l0 { 511 cpu-supply = <&ppvar_litcpu>; 512}; 513 514&cpu_l1 { 515 cpu-supply = <&ppvar_litcpu>; 516}; 517 518&cpu_l2 { 519 cpu-supply = <&ppvar_litcpu>; 520}; 521 522&cpu_l3 { 523 cpu-supply = <&ppvar_litcpu>; 524}; 525 526&cpu_b0 { 527 cpu-supply = <&ppvar_bigcpu>; 528}; 529 530&cpu_b1 { 531 cpu-supply = <&ppvar_bigcpu>; 532}; 533 534 535&cru { 536 assigned-clocks = 537 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 538 <&cru PLL_NPLL>, 539 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 540 <&cru PCLK_PERIHP>, 541 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 542 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 543 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 544 assigned-clock-rates = 545 <600000000>, <800000000>, 546 <1000000000>, 547 <150000000>, <75000000>, 548 <37500000>, 549 <100000000>, <100000000>, 550 <50000000>, <800000000>, 551 <100000000>, <50000000>; 552}; 553 554&emmc_phy { 555 status = "okay"; 556}; 557 558ap_i2c_mic: &i2c1 { 559 status = "okay"; 560 561 clock-frequency = <400000>; 562 563 /* These are relatively safe rise/fall times */ 564 i2c-scl-falling-time-ns = <50>; 565 i2c-scl-rising-time-ns = <300>; 566 567 headsetcodec: rt5514@57 { 568 compatible = "realtek,rt5514"; 569 reg = <0x57>; 570 interrupt-parent = <&gpio1>; 571 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&mic_int>; 574 realtek,dmic-init-delay = <20>; 575 wakeup-source; 576 }; 577}; 578 579ap_i2c_ts: &i2c3 { 580 status = "okay"; 581 582 clock-frequency = <400000>; 583 584 /* These are relatively safe rise/fall times */ 585 i2c-scl-falling-time-ns = <50>; 586 i2c-scl-rising-time-ns = <300>; 587}; 588 589ap_i2c_tp: &i2c5 { 590 status = "okay"; 591 592 clock-frequency = <400000>; 593 594 /* These are relatively safe rise/fall times */ 595 i2c-scl-falling-time-ns = <50>; 596 i2c-scl-rising-time-ns = <300>; 597 598 /* 599 * Note strange pullup enable. Apparently this avoids leakage but 600 * still allows us to get nice 4.7K pullups for high speed i2c 601 * transfers. Basically we want the pullup on whenever the ap is 602 * alive, so the "en" pin just gets set to output high. 603 */ 604 pinctrl-0 = <&i2c5_xfer &ap_i2c_tp_pu_en>; 605}; 606 607ap_i2c_audio: &i2c8 { 608 status = "okay"; 609 610 clock-frequency = <400000>; 611 612 /* These are relatively safe rise/fall times */ 613 i2c-scl-falling-time-ns = <50>; 614 i2c-scl-rising-time-ns = <300>; 615 616 codec: da7219@1a { 617 compatible = "dlg,da7219"; 618 reg = <0x1a>; 619 interrupt-parent = <&gpio1>; 620 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 621 clocks = <&cru SCLK_I2S_8CH_OUT>; 622 clock-names = "mclk"; 623 dlg,micbias-lvl = <2600>; 624 dlg,mic-amp-in-sel = "diff"; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&headset_int_l>; 627 VDD-supply = <&pp1800>; 628 VDDMIC-supply = <&pp3300>; 629 VDDIO-supply = <&pp1800>; 630 631 da7219_aad { 632 dlg,adc-1bit-rpt = <1>; 633 dlg,btn-avg = <4>; 634 dlg,btn-cfg = <50>; 635 dlg,mic-det-thr = <500>; 636 dlg,jack-ins-deb = <20>; 637 dlg,jack-det-rate = "32ms_64ms"; 638 dlg,jack-rem-deb = <1>; 639 640 dlg,a-d-btn-thr = <0xa>; 641 dlg,d-b-btn-thr = <0x16>; 642 dlg,b-c-btn-thr = <0x21>; 643 dlg,c-mic-btn-thr = <0x3E>; 644 }; 645 }; 646}; 647 648&i2s0 { 649 status = "okay"; 650}; 651 652&i2s2 { 653 status = "okay"; 654}; 655 656&io_domains { 657 status = "okay"; 658 659 audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */ 660 bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */ 661 gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */ 662 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */ 663}; 664 665&pcie0 { 666 status = "okay"; 667 668 ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; 669 pinctrl-names = "default"; 670 pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>; 671 vpcie3v3-supply = <&pp3300_wifi_bt>; 672 vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */ 673 vpcie0v9-supply = <&pp900_pcie>; 674 675 pci_rootport: pcie@0,0 { 676 reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>; 677 #address-cells = <3>; 678 #size-cells = <2>; 679 ranges; 680 681 mvl_wifi: wifi@0,0 { 682 compatible = "pci1b4b,2b42"; 683 reg = <0x83010000 0x0 0x00000000 0x0 0x00100000 684 0x83010000 0x0 0x00100000 0x0 0x00100000>; 685 interrupt-parent = <&gpio0>; 686 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 687 pinctrl-names = "default"; 688 pinctrl-0 = <&wlan_host_wake_l>; 689 wakeup-source; 690 }; 691 }; 692}; 693 694&pcie_phy { 695 status = "okay"; 696}; 697 698&pmu_io_domains { 699 status = "okay"; 700 701 pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */ 702}; 703 704&pwm0 { 705 status = "okay"; 706}; 707 708&pwm1 { 709 status = "okay"; 710}; 711 712&pwm2 { 713 status = "okay"; 714}; 715 716&pwm3 { 717 status = "okay"; 718}; 719 720&sdhci { 721 /* 722 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the 723 * same (or nearly the same) performance for all eMMC that are intended 724 * to be used. 725 */ 726 assigned-clock-rates = <150000000>; 727 728 bus-width = <8>; 729 mmc-hs400-1_8v; 730 mmc-hs400-enhanced-strobe; 731 non-removable; 732 status = "okay"; 733}; 734 735&sdmmc { 736 status = "okay"; 737 738 /* 739 * Note: configure "sdmmc_cd" as card detect even though it's actually 740 * hooked to ground. Because we specified "cd-gpios" below dw_mmc 741 * should be ignoring card detect anyway. Specifying the pin as 742 * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag) 743 * turned on that the system will still make sure the port is 744 * configured as SDMMC and not JTAG. 745 */ 746 pinctrl-names = "default"; 747 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio 748 &sdmmc_bus4>; 749 750 bus-width = <4>; 751 cap-mmc-highspeed; 752 cap-sd-highspeed; 753 cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 754 disable-wp; 755 sd-uhs-sdr12; 756 sd-uhs-sdr25; 757 sd-uhs-sdr50; 758 sd-uhs-sdr104; 759 vmmc-supply = <&pp3000_sd_slot>; 760 vqmmc-supply = <&ppvar_sd_card_io>; 761}; 762 763&spi1 { 764 status = "okay"; 765 766 pinctrl-names = "default", "sleep"; 767 pinctrl-1 = <&spi1_sleep>; 768 769 spiflash@0 { 770 compatible = "jedec,spi-nor"; 771 reg = <0>; 772 773 /* May run faster once verified. */ 774 spi-max-frequency = <10000000>; 775 }; 776}; 777 778&spi2 { 779 status = "okay"; 780 781 wacky_spi_audio: spi2@0 { 782 compatible = "realtek,rt5514"; 783 reg = <0>; 784 785 /* May run faster once verified. */ 786 spi-max-frequency = <10000000>; 787 }; 788}; 789 790&spi5 { 791 status = "okay"; 792 793 cros_ec: ec@0 { 794 compatible = "google,cros-ec-spi"; 795 reg = <0>; 796 interrupt-parent = <&gpio0>; 797 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&ec_ap_int_l>; 800 spi-max-frequency = <3000000>; 801 802 i2c_tunnel: i2c-tunnel { 803 compatible = "google,cros-ec-i2c-tunnel"; 804 google,remote-bus = <4>; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 }; 808 809 cros_ec_pwm: ec-pwm { 810 compatible = "google,cros-ec-pwm"; 811 #pwm-cells = <1>; 812 }; 813 }; 814}; 815 816&tsadc { 817 status = "okay"; 818 819 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 820 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 821}; 822 823&u2phy0 { 824 status = "okay"; 825}; 826 827&u2phy1 { 828 status = "okay"; 829}; 830 831&u2phy0_host { 832 status = "okay"; 833}; 834 835&u2phy1_host { 836 status = "okay"; 837}; 838 839&u2phy0_otg { 840 status = "okay"; 841}; 842 843&u2phy1_otg { 844 status = "okay"; 845}; 846 847&uart2 { 848 status = "okay"; 849}; 850 851&usb_host0_ehci { 852 status = "okay"; 853}; 854 855&usb_host0_ohci { 856 status = "okay"; 857}; 858 859&usb_host1_ehci { 860 status = "okay"; 861}; 862 863&usb_host1_ohci { 864 status = "okay"; 865}; 866 867&usbdrd3_0 { 868 status = "okay"; 869}; 870 871&usbdrd_dwc3_0 { 872 status = "okay"; 873 dr_mode = "host"; 874}; 875 876&usbdrd3_1 { 877 status = "okay"; 878}; 879 880&usbdrd_dwc3_1 { 881 status = "okay"; 882 dr_mode = "host"; 883}; 884 885#include <arm/cros-ec-keyboard.dtsi> 886#include <arm/cros-ec-sbs.dtsi> 887 888&pinctrl { 889 /* 890 * pinctrl settings for pins that have no real owners. 891 * 892 * At the moment settings are identical for S0 and S3, but if we later 893 * need to configure things differently for S3 we'll adjust here. 894 */ 895 pinctrl-names = "default"; 896 pinctrl-0 = < 897 &ap_pwroff /* AP will auto-assert this when in S3 */ 898 &clk_32k /* This pin is always 32k on gru boards */ 899 900 /* 901 * We want this driven low ASAP; firmware should help us, but 902 * we can help ourselves too. 903 */ 904 &wlan_module_reset_l 905 >; 906 907 pcfg_output_low: pcfg-output-low { 908 output-low; 909 }; 910 911 pcfg_output_high: pcfg-output-high { 912 output-high; 913 }; 914 915 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 916 bias-disable; 917 drive-strength = <8>; 918 }; 919 920 backlight-enable { 921 bl_en: bl-en { 922 rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>; 923 }; 924 }; 925 926 cros-ec { 927 ec_ap_int_l: ec-ap-int-l { 928 rockchip,pins = <RK_GPIO0 1 RK_FUNC_GPIO &pcfg_pull_up>; 929 }; 930 }; 931 932 discrete-regulators { 933 pp1500_en: pp1500-en { 934 rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO 935 &pcfg_pull_none>; 936 }; 937 938 pp1800_audio_en: pp1800-audio-en { 939 rockchip,pins = <RK_GPIO0 2 RK_FUNC_GPIO 940 &pcfg_pull_down>; 941 }; 942 943 pp3300_disp_en: pp3300-disp-en { 944 rockchip,pins = <RK_GPIO4 27 RK_FUNC_GPIO 945 &pcfg_pull_none>; 946 }; 947 948 pp3000_en: pp3000-en { 949 rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO 950 &pcfg_pull_none>; 951 }; 952 953 sd_io_pwr_en: sd-io-pwr-en { 954 rockchip,pins = <RK_GPIO2 2 RK_FUNC_GPIO 955 &pcfg_pull_none>; 956 }; 957 958 sd_pwr_1800_sel: sd-pwr-1800-sel { 959 rockchip,pins = <RK_GPIO2 28 RK_FUNC_GPIO 960 &pcfg_pull_none>; 961 }; 962 963 sd_slot_pwr_en: sd-slot-pwr-en { 964 rockchip,pins = <RK_GPIO4 29 RK_FUNC_GPIO 965 &pcfg_pull_none>; 966 }; 967 968 wlan_module_pd_l: wlan-module-pd-l { 969 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO 970 &pcfg_pull_down>; 971 }; 972 }; 973 974 codec { 975 /* Has external pullup */ 976 headset_int_l: headset-int-l { 977 rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>; 978 }; 979 980 mic_int: mic-int { 981 rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>; 982 }; 983 }; 984 985 max98357a { 986 sdmode_en: sdmode-en { 987 rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>; 988 }; 989 }; 990 991 pcie { 992 pcie_clkreqn_cpm: pci-clkreqn-cpm { 993 /* 994 * Since our pcie doesn't support ClockPM(CPM), we want 995 * to hack this as gpio, so the EP could be able to 996 * de-assert it along and make ClockPM(CPM) work. 997 */ 998 rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>; 999 }; 1000 }; 1001 1002 sdmmc { 1003 /* 1004 * We run sdmmc at max speed; bump up drive strength. 1005 * We also have external pulls, so disable the internal ones. 1006 */ 1007 sdmmc_bus4: sdmmc-bus4 { 1008 rockchip,pins = 1009 <4 8 RK_FUNC_1 &pcfg_pull_none_8ma>, 1010 <4 9 RK_FUNC_1 &pcfg_pull_none_8ma>, 1011 <4 10 RK_FUNC_1 &pcfg_pull_none_8ma>, 1012 <4 11 RK_FUNC_1 &pcfg_pull_none_8ma>; 1013 }; 1014 1015 sdmmc_clk: sdmmc-clk { 1016 rockchip,pins = 1017 <4 12 RK_FUNC_1 &pcfg_pull_none_8ma>; 1018 }; 1019 1020 sdmmc_cmd: sdmmc-cmd { 1021 rockchip,pins = 1022 <4 13 RK_FUNC_1 &pcfg_pull_none_8ma>; 1023 }; 1024 1025 /* 1026 * In our case the official card detect is hooked to ground 1027 * to avoid getting access to JTAG just by sticking something 1028 * in the SD card slot (see the force_jtag bit in the TRM). 1029 * 1030 * We still configure it as card detect because it doesn't 1031 * hurt and dw_mmc will ignore it. We make sure to disable 1032 * the pull though so we don't burn needless power. 1033 */ 1034 sdmmc_cd: sdmcc-cd { 1035 rockchip,pins = 1036 <0 7 RK_FUNC_1 &pcfg_pull_none>; 1037 }; 1038 1039 /* This is where we actually hook up CD; has external pull */ 1040 sdmmc_cd_gpio: sdmmc-cd-gpio { 1041 rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>; 1042 }; 1043 }; 1044 1045 spi1 { 1046 spi1_sleep: spi1-sleep { 1047 /* 1048 * Pull down SPI1 CLK/CS/RX/TX during suspend, to 1049 * prevent leakage. 1050 */ 1051 rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>, 1052 <1 10 RK_FUNC_GPIO &pcfg_pull_down>, 1053 <1 7 RK_FUNC_GPIO &pcfg_pull_down>, 1054 <1 8 RK_FUNC_GPIO &pcfg_pull_down>; 1055 }; 1056 }; 1057 1058 touchscreen { 1059 touch_int_l: touch-int-l { 1060 rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>; 1061 }; 1062 1063 touch_reset_l: touch-reset-l { 1064 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>; 1065 }; 1066 }; 1067 1068 trackpad { 1069 ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { 1070 rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>; 1071 }; 1072 1073 trackpad_int_l: trackpad-int-l { 1074 rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>; 1075 }; 1076 }; 1077 1078 wifi { 1079 wifi_perst_l: wifi-perst-l { 1080 rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>; 1081 }; 1082 1083 wlan_module_reset_l: wlan-module-reset-l { 1084 /* 1085 * We want this driven low ASAP (As {Soon,Strongly} As 1086 * Possible), to avoid leakage through the powered-down 1087 * WiFi. 1088 */ 1089 rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_output_low>; 1090 }; 1091 1092 bt_host_wake_l: bt-host-wake-l { 1093 /* Kevin has an external pull up, but Gru does not */ 1094 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; 1095 }; 1096 }; 1097 1098 write-protect { 1099 ap_fw_wp: ap-fw-wp { 1100 rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>; 1101 }; 1102 }; 1103}; 1104