1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 i2c0 = &i2c0; 31 i2c1 = &i2c1; 32 i2c2 = &i2c2; 33 i2c3 = &i2c3; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 reg = <0x0 0x0>; 44 clocks = <&cru ARMCLK>; 45 #cooling-cells = <2>; 46 cpu-idle-states = <&CPU_SLEEP>; 47 dynamic-power-coefficient = <120>; 48 enable-method = "psci"; 49 operating-points-v2 = <&cpu0_opp_table>; 50 i-cache-size = <0x8000>; 51 i-cache-line-size = <64>; 52 i-cache-sets = <256>; 53 d-cache-size = <0x8000>; 54 d-cache-line-size = <64>; 55 d-cache-sets = <128>; 56 next-level-cache = <&l2_cache>; 57 }; 58 59 cpu1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0 0x1>; 63 clocks = <&cru ARMCLK>; 64 #cooling-cells = <2>; 65 cpu-idle-states = <&CPU_SLEEP>; 66 dynamic-power-coefficient = <120>; 67 enable-method = "psci"; 68 operating-points-v2 = <&cpu0_opp_table>; 69 i-cache-size = <0x8000>; 70 i-cache-line-size = <64>; 71 i-cache-sets = <256>; 72 d-cache-size = <0x8000>; 73 d-cache-line-size = <64>; 74 d-cache-sets = <128>; 75 next-level-cache = <&l2_cache>; 76 }; 77 78 cpu2: cpu@2 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x2>; 82 clocks = <&cru ARMCLK>; 83 #cooling-cells = <2>; 84 cpu-idle-states = <&CPU_SLEEP>; 85 dynamic-power-coefficient = <120>; 86 enable-method = "psci"; 87 operating-points-v2 = <&cpu0_opp_table>; 88 i-cache-size = <0x8000>; 89 i-cache-line-size = <64>; 90 i-cache-sets = <256>; 91 d-cache-size = <0x8000>; 92 d-cache-line-size = <64>; 93 d-cache-sets = <128>; 94 next-level-cache = <&l2_cache>; 95 }; 96 97 cpu3: cpu@3 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53"; 100 reg = <0x0 0x3>; 101 clocks = <&cru ARMCLK>; 102 #cooling-cells = <2>; 103 cpu-idle-states = <&CPU_SLEEP>; 104 dynamic-power-coefficient = <120>; 105 enable-method = "psci"; 106 operating-points-v2 = <&cpu0_opp_table>; 107 i-cache-size = <0x8000>; 108 i-cache-line-size = <64>; 109 i-cache-sets = <256>; 110 d-cache-size = <0x8000>; 111 d-cache-line-size = <64>; 112 d-cache-sets = <128>; 113 next-level-cache = <&l2_cache>; 114 }; 115 116 idle-states { 117 entry-method = "psci"; 118 119 CPU_SLEEP: cpu-sleep { 120 compatible = "arm,idle-state"; 121 local-timer-stop; 122 arm,psci-suspend-param = <0x0010000>; 123 entry-latency-us = <120>; 124 exit-latency-us = <250>; 125 min-residency-us = <900>; 126 }; 127 }; 128 129 l2_cache: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 cache-size = <0x40000>; 134 cache-line-size = <64>; 135 cache-sets = <256>; 136 }; 137 }; 138 139 cpu0_opp_table: opp-table-0 { 140 compatible = "operating-points-v2"; 141 opp-shared; 142 143 opp-408000000 { 144 opp-hz = /bits/ 64 <408000000>; 145 opp-microvolt = <950000>; 146 clock-latency-ns = <40000>; 147 opp-suspend; 148 }; 149 opp-600000000 { 150 opp-hz = /bits/ 64 <600000000>; 151 opp-microvolt = <950000>; 152 clock-latency-ns = <40000>; 153 }; 154 opp-816000000 { 155 opp-hz = /bits/ 64 <816000000>; 156 opp-microvolt = <1000000>; 157 clock-latency-ns = <40000>; 158 }; 159 opp-1008000000 { 160 opp-hz = /bits/ 64 <1008000000>; 161 opp-microvolt = <1100000>; 162 clock-latency-ns = <40000>; 163 }; 164 opp-1200000000 { 165 opp-hz = /bits/ 64 <1200000000>; 166 opp-microvolt = <1225000>; 167 clock-latency-ns = <40000>; 168 }; 169 opp-1296000000 { 170 opp-hz = /bits/ 64 <1296000000>; 171 opp-microvolt = <1300000>; 172 clock-latency-ns = <40000>; 173 }; 174 }; 175 176 analog_sound: analog-sound { 177 compatible = "simple-audio-card"; 178 simple-audio-card,format = "i2s"; 179 simple-audio-card,mclk-fs = <256>; 180 simple-audio-card,name = "Analog"; 181 status = "disabled"; 182 183 simple-audio-card,cpu { 184 sound-dai = <&i2s1>; 185 }; 186 187 simple-audio-card,codec { 188 sound-dai = <&codec>; 189 }; 190 }; 191 192 arm-pmu { 193 compatible = "arm,cortex-a53-pmu"; 194 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 198 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 199 }; 200 201 display_subsystem: display-subsystem { 202 compatible = "rockchip,display-subsystem"; 203 ports = <&vop_out>; 204 }; 205 206 hdmi_sound: hdmi-sound { 207 compatible = "simple-audio-card"; 208 simple-audio-card,format = "i2s"; 209 simple-audio-card,mclk-fs = <128>; 210 simple-audio-card,name = "HDMI"; 211 status = "disabled"; 212 213 simple-audio-card,cpu { 214 sound-dai = <&i2s0>; 215 }; 216 217 simple-audio-card,codec { 218 sound-dai = <&hdmi>; 219 }; 220 }; 221 222 psci { 223 compatible = "arm,psci-1.0", "arm,psci-0.2"; 224 method = "smc"; 225 }; 226 227 timer { 228 compatible = "arm,armv8-timer"; 229 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 230 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 231 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 232 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 233 }; 234 235 xin24m: xin24m { 236 compatible = "fixed-clock"; 237 #clock-cells = <0>; 238 clock-frequency = <24000000>; 239 clock-output-names = "xin24m"; 240 }; 241 242 i2s0: i2s@ff000000 { 243 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 244 reg = <0x0 0xff000000 0x0 0x1000>; 245 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 247 clock-names = "i2s_clk", "i2s_hclk"; 248 dmas = <&dmac 11>, <&dmac 12>; 249 dma-names = "tx", "rx"; 250 #sound-dai-cells = <0>; 251 status = "disabled"; 252 }; 253 254 i2s1: i2s@ff010000 { 255 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 256 reg = <0x0 0xff010000 0x0 0x1000>; 257 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 259 clock-names = "i2s_clk", "i2s_hclk"; 260 dmas = <&dmac 14>, <&dmac 15>; 261 dma-names = "tx", "rx"; 262 #sound-dai-cells = <0>; 263 status = "disabled"; 264 }; 265 266 i2s2: i2s@ff020000 { 267 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 268 reg = <0x0 0xff020000 0x0 0x1000>; 269 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 271 clock-names = "i2s_clk", "i2s_hclk"; 272 dmas = <&dmac 0>, <&dmac 1>; 273 dma-names = "tx", "rx"; 274 #sound-dai-cells = <0>; 275 status = "disabled"; 276 }; 277 278 spdif: spdif@ff030000 { 279 compatible = "rockchip,rk3328-spdif"; 280 reg = <0x0 0xff030000 0x0 0x1000>; 281 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 283 clock-names = "mclk", "hclk"; 284 dmas = <&dmac 10>; 285 dma-names = "tx"; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&spdifm2_tx>; 288 #sound-dai-cells = <0>; 289 status = "disabled"; 290 }; 291 292 pdm: pdm@ff040000 { 293 compatible = "rockchip,pdm"; 294 reg = <0x0 0xff040000 0x0 0x1000>; 295 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 296 clock-names = "pdm_clk", "pdm_hclk"; 297 dmas = <&dmac 16>; 298 dma-names = "rx"; 299 pinctrl-names = "default", "sleep"; 300 pinctrl-0 = <&pdmm0_clk 301 &pdmm0_sdi0 302 &pdmm0_sdi1 303 &pdmm0_sdi2 304 &pdmm0_sdi3>; 305 pinctrl-1 = <&pdmm0_clk_sleep 306 &pdmm0_sdi0_sleep 307 &pdmm0_sdi1_sleep 308 &pdmm0_sdi2_sleep 309 &pdmm0_sdi3_sleep>; 310 status = "disabled"; 311 }; 312 313 grf: syscon@ff100000 { 314 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 315 reg = <0x0 0xff100000 0x0 0x1000>; 316 317 io_domains: io-domains { 318 compatible = "rockchip,rk3328-io-voltage-domain"; 319 status = "disabled"; 320 }; 321 322 grf_gpio: gpio { 323 compatible = "rockchip,rk3328-grf-gpio"; 324 gpio-controller; 325 #gpio-cells = <2>; 326 }; 327 328 power: power-controller { 329 compatible = "rockchip,rk3328-power-controller"; 330 #power-domain-cells = <1>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 334 power-domain@RK3328_PD_GPU { 335 reg = <RK3328_PD_GPU>; 336 clocks = <&cru ACLK_GPU>; 337 #power-domain-cells = <0>; 338 }; 339 power-domain@RK3328_PD_HEVC { 340 reg = <RK3328_PD_HEVC>; 341 clocks = <&cru SCLK_VENC_CORE>; 342 #power-domain-cells = <0>; 343 }; 344 power-domain@RK3328_PD_VIDEO { 345 reg = <RK3328_PD_VIDEO>; 346 clocks = <&cru ACLK_RKVDEC>, 347 <&cru HCLK_RKVDEC>, 348 <&cru SCLK_VDEC_CABAC>, 349 <&cru SCLK_VDEC_CORE>; 350 #power-domain-cells = <0>; 351 }; 352 power-domain@RK3328_PD_VPU { 353 reg = <RK3328_PD_VPU>; 354 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 355 #power-domain-cells = <0>; 356 }; 357 }; 358 359 reboot-mode { 360 compatible = "syscon-reboot-mode"; 361 offset = <0x5c8>; 362 mode-normal = <BOOT_NORMAL>; 363 mode-recovery = <BOOT_RECOVERY>; 364 mode-bootloader = <BOOT_FASTBOOT>; 365 mode-loader = <BOOT_BL_DOWNLOAD>; 366 }; 367 }; 368 369 uart0: serial@ff110000 { 370 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 371 reg = <0x0 0xff110000 0x0 0x100>; 372 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 374 clock-names = "baudclk", "apb_pclk"; 375 dmas = <&dmac 2>, <&dmac 3>; 376 dma-names = "tx", "rx"; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 379 reg-io-width = <4>; 380 reg-shift = <2>; 381 status = "disabled"; 382 }; 383 384 uart1: serial@ff120000 { 385 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 386 reg = <0x0 0xff120000 0x0 0x100>; 387 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 389 clock-names = "baudclk", "apb_pclk"; 390 dmas = <&dmac 4>, <&dmac 5>; 391 dma-names = "tx", "rx"; 392 pinctrl-names = "default"; 393 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 394 reg-io-width = <4>; 395 reg-shift = <2>; 396 status = "disabled"; 397 }; 398 399 uart2: serial@ff130000 { 400 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 401 reg = <0x0 0xff130000 0x0 0x100>; 402 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 404 clock-names = "baudclk", "apb_pclk"; 405 dmas = <&dmac 6>, <&dmac 7>; 406 dma-names = "tx", "rx"; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&uart2m1_xfer>; 409 reg-io-width = <4>; 410 reg-shift = <2>; 411 status = "disabled"; 412 }; 413 414 i2c0: i2c@ff150000 { 415 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 416 reg = <0x0 0xff150000 0x0 0x1000>; 417 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 421 clock-names = "i2c", "pclk"; 422 pinctrl-names = "default"; 423 pinctrl-0 = <&i2c0_xfer>; 424 status = "disabled"; 425 }; 426 427 i2c1: i2c@ff160000 { 428 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 429 reg = <0x0 0xff160000 0x0 0x1000>; 430 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 434 clock-names = "i2c", "pclk"; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&i2c1_xfer>; 437 status = "disabled"; 438 }; 439 440 i2c2: i2c@ff170000 { 441 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 442 reg = <0x0 0xff170000 0x0 0x1000>; 443 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 447 clock-names = "i2c", "pclk"; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&i2c2_xfer>; 450 status = "disabled"; 451 }; 452 453 i2c3: i2c@ff180000 { 454 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 455 reg = <0x0 0xff180000 0x0 0x1000>; 456 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 460 clock-names = "i2c", "pclk"; 461 pinctrl-names = "default"; 462 pinctrl-0 = <&i2c3_xfer>; 463 status = "disabled"; 464 }; 465 466 spi0: spi@ff190000 { 467 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 468 reg = <0x0 0xff190000 0x0 0x1000>; 469 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 473 clock-names = "spiclk", "apb_pclk"; 474 dmas = <&dmac 8>, <&dmac 9>; 475 dma-names = "tx", "rx"; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 478 status = "disabled"; 479 }; 480 481 wdt: watchdog@ff1a0000 { 482 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; 483 reg = <0x0 0xff1a0000 0x0 0x100>; 484 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&cru PCLK_WDT>; 486 }; 487 488 pwm0: pwm@ff1b0000 { 489 compatible = "rockchip,rk3328-pwm"; 490 reg = <0x0 0xff1b0000 0x0 0x10>; 491 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 492 clock-names = "pwm", "pclk"; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&pwm0_pin>; 495 #pwm-cells = <3>; 496 status = "disabled"; 497 }; 498 499 pwm1: pwm@ff1b0010 { 500 compatible = "rockchip,rk3328-pwm"; 501 reg = <0x0 0xff1b0010 0x0 0x10>; 502 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 503 clock-names = "pwm", "pclk"; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&pwm1_pin>; 506 #pwm-cells = <3>; 507 status = "disabled"; 508 }; 509 510 pwm2: pwm@ff1b0020 { 511 compatible = "rockchip,rk3328-pwm"; 512 reg = <0x0 0xff1b0020 0x0 0x10>; 513 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 514 clock-names = "pwm", "pclk"; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&pwm2_pin>; 517 #pwm-cells = <3>; 518 status = "disabled"; 519 }; 520 521 pwm3: pwm@ff1b0030 { 522 compatible = "rockchip,rk3328-pwm"; 523 reg = <0x0 0xff1b0030 0x0 0x10>; 524 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 525 clock-names = "pwm", "pclk"; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&pwmir_pin>; 528 #pwm-cells = <3>; 529 status = "disabled"; 530 }; 531 532 dmac: dma-controller@ff1f0000 { 533 compatible = "arm,pl330", "arm,primecell"; 534 reg = <0x0 0xff1f0000 0x0 0x4000>; 535 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 537 arm,pl330-periph-burst; 538 clocks = <&cru ACLK_DMAC>; 539 clock-names = "apb_pclk"; 540 #dma-cells = <1>; 541 }; 542 543 thermal-zones { 544 soc_thermal: soc-thermal { 545 polling-delay-passive = <20>; 546 polling-delay = <1000>; 547 sustainable-power = <1000>; 548 549 thermal-sensors = <&tsadc 0>; 550 551 trips { 552 threshold: trip-point0 { 553 temperature = <70000>; 554 hysteresis = <2000>; 555 type = "passive"; 556 }; 557 target: trip-point1 { 558 temperature = <85000>; 559 hysteresis = <2000>; 560 type = "passive"; 561 }; 562 soc_crit: soc-crit { 563 temperature = <95000>; 564 hysteresis = <2000>; 565 type = "critical"; 566 }; 567 }; 568 569 cooling-maps { 570 map0 { 571 trip = <&target>; 572 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 573 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 574 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 575 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 576 contribution = <4096>; 577 }; 578 map1 { 579 trip = <&target>; 580 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 581 contribution = <4096>; 582 }; 583 }; 584 }; 585 }; 586 587 tsadc: tsadc@ff250000 { 588 compatible = "rockchip,rk3328-tsadc"; 589 reg = <0x0 0xff250000 0x0 0x100>; 590 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 591 assigned-clocks = <&cru SCLK_TSADC>; 592 assigned-clock-rates = <50000>; 593 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 594 clock-names = "tsadc", "apb_pclk"; 595 pinctrl-names = "init", "default", "sleep"; 596 pinctrl-0 = <&otp_pin>; 597 pinctrl-1 = <&otp_out>; 598 pinctrl-2 = <&otp_pin>; 599 resets = <&cru SRST_TSADC>; 600 reset-names = "tsadc-apb"; 601 rockchip,grf = <&grf>; 602 rockchip,hw-tshut-temp = <100000>; 603 #thermal-sensor-cells = <1>; 604 status = "disabled"; 605 }; 606 607 efuse: efuse@ff260000 { 608 compatible = "rockchip,rk3328-efuse"; 609 reg = <0x0 0xff260000 0x0 0x50>; 610 #address-cells = <1>; 611 #size-cells = <1>; 612 clocks = <&cru SCLK_EFUSE>; 613 clock-names = "pclk_efuse"; 614 rockchip,efuse-size = <0x20>; 615 616 /* Data cells */ 617 efuse_id: id@7 { 618 reg = <0x07 0x10>; 619 }; 620 cpu_leakage: cpu-leakage@17 { 621 reg = <0x17 0x1>; 622 }; 623 logic_leakage: logic-leakage@19 { 624 reg = <0x19 0x1>; 625 }; 626 efuse_cpu_version: cpu-version@1a { 627 reg = <0x1a 0x1>; 628 bits = <3 3>; 629 }; 630 }; 631 632 saradc: adc@ff280000 { 633 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 634 reg = <0x0 0xff280000 0x0 0x100>; 635 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 636 #io-channel-cells = <1>; 637 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 638 clock-names = "saradc", "apb_pclk"; 639 resets = <&cru SRST_SARADC_P>; 640 reset-names = "saradc-apb"; 641 status = "disabled"; 642 }; 643 644 gpu: gpu@ff300000 { 645 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 646 reg = <0x0 0xff300000 0x0 0x30000>; 647 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 654 interrupt-names = "gp", 655 "gpmmu", 656 "pp", 657 "pp0", 658 "ppmmu0", 659 "pp1", 660 "ppmmu1"; 661 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 662 clock-names = "bus", "core"; 663 operating-points-v2 = <&gpu_opp_table>; 664 power-domains = <&power RK3328_PD_GPU>; 665 resets = <&cru SRST_GPU_A>; 666 #cooling-cells = <2>; 667 }; 668 669 gpu_opp_table: opp-table-gpu { 670 compatible = "operating-points-v2"; 671 672 opp-200000000 { 673 opp-hz = /bits/ 64 <200000000>; 674 opp-microvolt = <1075000>; 675 }; 676 677 opp-300000000 { 678 opp-hz = /bits/ 64 <300000000>; 679 opp-microvolt = <1075000>; 680 }; 681 682 opp-400000000 { 683 opp-hz = /bits/ 64 <400000000>; 684 opp-microvolt = <1075000>; 685 }; 686 687 opp-500000000 { 688 /* causes stability issues */ 689 opp-hz = /bits/ 64 <500000000>; 690 opp-microvolt = <1150000>; 691 status = "disabled"; 692 }; 693 }; 694 695 h265e_mmu: iommu@ff330200 { 696 compatible = "rockchip,iommu"; 697 reg = <0x0 0xff330200 0 0x100>; 698 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 700 clock-names = "aclk", "iface"; 701 #iommu-cells = <0>; 702 status = "disabled"; 703 }; 704 705 vepu_mmu: iommu@ff340800 { 706 compatible = "rockchip,iommu"; 707 reg = <0x0 0xff340800 0x0 0x40>; 708 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 710 clock-names = "aclk", "iface"; 711 #iommu-cells = <0>; 712 status = "disabled"; 713 }; 714 715 vpu: video-codec@ff350000 { 716 compatible = "rockchip,rk3328-vpu"; 717 reg = <0x0 0xff350000 0x0 0x800>; 718 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 719 interrupt-names = "vdpu"; 720 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 721 clock-names = "aclk", "hclk"; 722 iommus = <&vpu_mmu>; 723 power-domains = <&power RK3328_PD_VPU>; 724 }; 725 726 vpu_mmu: iommu@ff350800 { 727 compatible = "rockchip,iommu"; 728 reg = <0x0 0xff350800 0x0 0x40>; 729 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 731 clock-names = "aclk", "iface"; 732 #iommu-cells = <0>; 733 power-domains = <&power RK3328_PD_VPU>; 734 }; 735 736 vdec: video-codec@ff360000 { 737 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; 738 reg = <0x0 0xff360000 0x0 0x480>; 739 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, 741 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; 742 clock-names = "axi", "ahb", "cabac", "core"; 743 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, 744 <&cru SCLK_VDEC_CORE>; 745 assigned-clock-rates = <400000000>, <400000000>, <300000000>; 746 iommus = <&vdec_mmu>; 747 power-domains = <&power RK3328_PD_VIDEO>; 748 }; 749 750 vdec_mmu: iommu@ff360480 { 751 compatible = "rockchip,iommu"; 752 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 753 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 755 clock-names = "aclk", "iface"; 756 #iommu-cells = <0>; 757 power-domains = <&power RK3328_PD_VIDEO>; 758 }; 759 760 vop: vop@ff370000 { 761 compatible = "rockchip,rk3328-vop"; 762 reg = <0x0 0xff370000 0x0 0x3efc>; 763 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 765 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 766 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 767 reset-names = "axi", "ahb", "dclk"; 768 iommus = <&vop_mmu>; 769 status = "disabled"; 770 771 vop_out: port { 772 vop_out_hdmi: endpoint { 773 remote-endpoint = <&hdmi_in_vop>; 774 }; 775 }; 776 }; 777 778 vop_mmu: iommu@ff373f00 { 779 compatible = "rockchip,iommu"; 780 reg = <0x0 0xff373f00 0x0 0x100>; 781 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 782 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 783 clock-names = "aclk", "iface"; 784 #iommu-cells = <0>; 785 status = "disabled"; 786 }; 787 788 hdmi: hdmi@ff3c0000 { 789 compatible = "rockchip,rk3328-dw-hdmi"; 790 reg = <0x0 0xff3c0000 0x0 0x20000>; 791 reg-io-width = <4>; 792 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&cru PCLK_HDMI>, 794 <&cru SCLK_HDMI_SFC>, 795 <&cru SCLK_RTC32K>; 796 clock-names = "iahb", 797 "isfr", 798 "cec"; 799 phys = <&hdmiphy>; 800 phy-names = "hdmi"; 801 pinctrl-names = "default"; 802 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 803 rockchip,grf = <&grf>; 804 #sound-dai-cells = <0>; 805 status = "disabled"; 806 807 ports { 808 #address-cells = <1>; 809 #size-cells = <0>; 810 811 hdmi_in: port@0 { 812 reg = <0>; 813 814 hdmi_in_vop: endpoint { 815 remote-endpoint = <&vop_out_hdmi>; 816 }; 817 }; 818 819 hdmi_out: port@1 { 820 reg = <1>; 821 }; 822 }; 823 }; 824 825 codec: codec@ff410000 { 826 compatible = "rockchip,rk3328-codec"; 827 reg = <0x0 0xff410000 0x0 0x1000>; 828 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 829 clock-names = "pclk", "mclk"; 830 rockchip,grf = <&grf>; 831 #sound-dai-cells = <0>; 832 status = "disabled"; 833 }; 834 835 hdmiphy: phy@ff430000 { 836 compatible = "rockchip,rk3328-hdmi-phy"; 837 reg = <0x0 0xff430000 0x0 0x10000>; 838 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 840 clock-names = "sysclk", "refoclk", "refpclk"; 841 clock-output-names = "hdmi_phy"; 842 #clock-cells = <0>; 843 nvmem-cells = <&efuse_cpu_version>; 844 nvmem-cell-names = "cpu-version"; 845 #phy-cells = <0>; 846 status = "disabled"; 847 }; 848 849 cru: clock-controller@ff440000 { 850 compatible = "rockchip,rk3328-cru"; 851 reg = <0x0 0xff440000 0x0 0x1000>; 852 clocks = <&xin24m>; 853 clock-names = "xin24m"; 854 rockchip,grf = <&grf>; 855 #clock-cells = <1>; 856 #reset-cells = <1>; 857 assigned-clocks = 858 /* 859 * CPLL should run at 1200, but that is to high for 860 * the initial dividers of most of its children. 861 * We need set cpll child clk div first, 862 * and then set the cpll frequency. 863 */ 864 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 865 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 866 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 867 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 868 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 869 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 870 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 871 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 872 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 873 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 874 <&cru SCLK_WIFI>, <&cru ARMCLK>, 875 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 876 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 877 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 878 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 879 <&cru SCLK_RTC32K>; 880 assigned-clock-parents = 881 <&cru HDMIPHY>, <&cru PLL_APLL>, 882 <&cru PLL_GPLL>, <&xin24m>, 883 <&xin24m>, <&xin24m>; 884 assigned-clock-rates = 885 <0>, <61440000>, 886 <0>, <24000000>, 887 <24000000>, <24000000>, 888 <15000000>, <15000000>, 889 <300000000>, <100000000>, 890 <400000000>, <100000000>, 891 <50000000>, <100000000>, 892 <100000000>, <100000000>, 893 <50000000>, <50000000>, 894 <50000000>, <50000000>, 895 <24000000>, <600000000>, 896 <491520000>, <1200000000>, 897 <150000000>, <75000000>, 898 <75000000>, <150000000>, 899 <75000000>, <75000000>, 900 <32768>; 901 }; 902 903 usb2phy_grf: syscon@ff450000 { 904 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 905 "simple-mfd"; 906 reg = <0x0 0xff450000 0x0 0x10000>; 907 #address-cells = <1>; 908 #size-cells = <1>; 909 910 u2phy: usb2phy@100 { 911 compatible = "rockchip,rk3328-usb2phy"; 912 reg = <0x100 0x10>; 913 clocks = <&xin24m>; 914 clock-names = "phyclk"; 915 clock-output-names = "usb480m_phy"; 916 #clock-cells = <0>; 917 assigned-clocks = <&cru USB480M>; 918 assigned-clock-parents = <&u2phy>; 919 status = "disabled"; 920 921 u2phy_otg: otg-port { 922 #phy-cells = <0>; 923 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 926 interrupt-names = "otg-bvalid", "otg-id", 927 "linestate"; 928 status = "disabled"; 929 }; 930 931 u2phy_host: host-port { 932 #phy-cells = <0>; 933 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 934 interrupt-names = "linestate"; 935 status = "disabled"; 936 }; 937 }; 938 }; 939 940 sdmmc: mmc@ff500000 { 941 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 942 reg = <0x0 0xff500000 0x0 0x4000>; 943 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 945 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 946 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 947 fifo-depth = <0x100>; 948 max-frequency = <150000000>; 949 resets = <&cru SRST_MMC0>; 950 reset-names = "reset"; 951 status = "disabled"; 952 }; 953 954 sdio: mmc@ff510000 { 955 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 956 reg = <0x0 0xff510000 0x0 0x4000>; 957 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 959 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 960 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 961 fifo-depth = <0x100>; 962 max-frequency = <150000000>; 963 resets = <&cru SRST_SDIO>; 964 reset-names = "reset"; 965 status = "disabled"; 966 }; 967 968 emmc: mmc@ff520000 { 969 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 970 reg = <0x0 0xff520000 0x0 0x4000>; 971 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 973 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 974 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 975 fifo-depth = <0x100>; 976 max-frequency = <150000000>; 977 resets = <&cru SRST_EMMC>; 978 reset-names = "reset"; 979 status = "disabled"; 980 }; 981 982 gmac2io: ethernet@ff540000 { 983 compatible = "rockchip,rk3328-gmac"; 984 reg = <0x0 0xff540000 0x0 0x10000>; 985 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 986 interrupt-names = "macirq"; 987 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 988 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 989 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 990 <&cru PCLK_MAC2IO>; 991 clock-names = "stmmaceth", "mac_clk_rx", 992 "mac_clk_tx", "clk_mac_ref", 993 "clk_mac_refout", "aclk_mac", 994 "pclk_mac"; 995 resets = <&cru SRST_GMAC2IO_A>; 996 reset-names = "stmmaceth"; 997 rockchip,grf = <&grf>; 998 tx-fifo-depth = <2048>; 999 rx-fifo-depth = <4096>; 1000 snps,txpbl = <0x4>; 1001 status = "disabled"; 1002 }; 1003 1004 gmac2phy: ethernet@ff550000 { 1005 compatible = "rockchip,rk3328-gmac"; 1006 reg = <0x0 0xff550000 0x0 0x10000>; 1007 rockchip,grf = <&grf>; 1008 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1009 interrupt-names = "macirq"; 1010 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 1011 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 1012 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 1013 <&cru SCLK_MAC2PHY_OUT>; 1014 clock-names = "stmmaceth", "mac_clk_rx", 1015 "mac_clk_tx", "clk_mac_ref", 1016 "aclk_mac", "pclk_mac", 1017 "clk_macphy"; 1018 resets = <&cru SRST_GMAC2PHY_A>; 1019 reset-names = "stmmaceth"; 1020 phy-mode = "rmii"; 1021 phy-handle = <&phy>; 1022 tx-fifo-depth = <2048>; 1023 rx-fifo-depth = <4096>; 1024 snps,txpbl = <0x4>; 1025 clock_in_out = "output"; 1026 status = "disabled"; 1027 1028 mdio { 1029 compatible = "snps,dwmac-mdio"; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 1033 phy: ethernet-phy@0 { 1034 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 1035 reg = <0>; 1036 clocks = <&cru SCLK_MAC2PHY_OUT>; 1037 resets = <&cru SRST_MACPHY>; 1038 pinctrl-names = "default"; 1039 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 1040 phy-is-integrated; 1041 }; 1042 }; 1043 }; 1044 1045 usb20_otg: usb@ff580000 { 1046 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 1047 "snps,dwc2"; 1048 reg = <0x0 0xff580000 0x0 0x40000>; 1049 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1050 clocks = <&cru HCLK_OTG>; 1051 clock-names = "otg"; 1052 dr_mode = "otg"; 1053 g-np-tx-fifo-size = <16>; 1054 g-rx-fifo-size = <280>; 1055 g-tx-fifo-size = <256 128 128 64 32 16>; 1056 phys = <&u2phy_otg>; 1057 phy-names = "usb2-phy"; 1058 status = "disabled"; 1059 }; 1060 1061 usb_host0_ehci: usb@ff5c0000 { 1062 compatible = "generic-ehci"; 1063 reg = <0x0 0xff5c0000 0x0 0x10000>; 1064 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&cru HCLK_HOST0>, <&u2phy>; 1066 phys = <&u2phy_host>; 1067 phy-names = "usb"; 1068 status = "disabled"; 1069 }; 1070 1071 usb_host0_ohci: usb@ff5d0000 { 1072 compatible = "generic-ohci"; 1073 reg = <0x0 0xff5d0000 0x0 0x10000>; 1074 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&cru HCLK_HOST0>, <&u2phy>; 1076 phys = <&u2phy_host>; 1077 phy-names = "usb"; 1078 status = "disabled"; 1079 }; 1080 1081 sdmmc_ext: mmc@ff5f0000 { 1082 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 1083 reg = <0x0 0xff5f0000 0x0 0x4000>; 1084 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1085 clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, 1086 <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; 1087 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1088 fifo-depth = <0x100>; 1089 max-frequency = <150000000>; 1090 resets = <&cru SRST_SDMMCEXT>; 1091 reset-names = "reset"; 1092 status = "disabled"; 1093 }; 1094 1095 usbdrd3: usb@ff600000 { 1096 compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; 1097 reg = <0x0 0xff600000 0x0 0x100000>; 1098 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 1100 <&cru ACLK_USB3OTG>; 1101 clock-names = "ref_clk", "suspend_clk", 1102 "bus_clk"; 1103 dr_mode = "otg"; 1104 phy_type = "utmi_wide"; 1105 snps,dis-del-phy-power-chg-quirk; 1106 snps,dis_enblslpm_quirk; 1107 snps,dis-tx-ipgap-linecheck-quirk; 1108 snps,dis-u2-freeclk-exists-quirk; 1109 snps,dis_u2_susphy_quirk; 1110 snps,dis_u3_susphy_quirk; 1111 status = "disabled"; 1112 }; 1113 1114 gic: interrupt-controller@ff811000 { 1115 compatible = "arm,gic-400"; 1116 #interrupt-cells = <3>; 1117 #address-cells = <0>; 1118 interrupt-controller; 1119 reg = <0x0 0xff811000 0 0x1000>, 1120 <0x0 0xff812000 0 0x2000>, 1121 <0x0 0xff814000 0 0x2000>, 1122 <0x0 0xff816000 0 0x2000>; 1123 interrupts = <GIC_PPI 9 1124 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1125 }; 1126 1127 crypto: crypto@ff060000 { 1128 compatible = "rockchip,rk3328-crypto"; 1129 reg = <0x0 0xff060000 0x0 0x4000>; 1130 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1131 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>, 1132 <&cru SCLK_CRYPTO>; 1133 clock-names = "hclk_master", "hclk_slave", "sclk"; 1134 resets = <&cru SRST_CRYPTO>; 1135 reset-names = "crypto-rst"; 1136 }; 1137 1138 pinctrl: pinctrl { 1139 compatible = "rockchip,rk3328-pinctrl"; 1140 rockchip,grf = <&grf>; 1141 #address-cells = <2>; 1142 #size-cells = <2>; 1143 ranges; 1144 1145 gpio0: gpio@ff210000 { 1146 compatible = "rockchip,gpio-bank"; 1147 reg = <0x0 0xff210000 0x0 0x100>; 1148 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1149 clocks = <&cru PCLK_GPIO0>; 1150 1151 gpio-controller; 1152 #gpio-cells = <2>; 1153 1154 interrupt-controller; 1155 #interrupt-cells = <2>; 1156 }; 1157 1158 gpio1: gpio@ff220000 { 1159 compatible = "rockchip,gpio-bank"; 1160 reg = <0x0 0xff220000 0x0 0x100>; 1161 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1162 clocks = <&cru PCLK_GPIO1>; 1163 1164 gpio-controller; 1165 #gpio-cells = <2>; 1166 1167 interrupt-controller; 1168 #interrupt-cells = <2>; 1169 }; 1170 1171 gpio2: gpio@ff230000 { 1172 compatible = "rockchip,gpio-bank"; 1173 reg = <0x0 0xff230000 0x0 0x100>; 1174 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1175 clocks = <&cru PCLK_GPIO2>; 1176 1177 gpio-controller; 1178 #gpio-cells = <2>; 1179 1180 interrupt-controller; 1181 #interrupt-cells = <2>; 1182 }; 1183 1184 gpio3: gpio@ff240000 { 1185 compatible = "rockchip,gpio-bank"; 1186 reg = <0x0 0xff240000 0x0 0x100>; 1187 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&cru PCLK_GPIO3>; 1189 1190 gpio-controller; 1191 #gpio-cells = <2>; 1192 1193 interrupt-controller; 1194 #interrupt-cells = <2>; 1195 }; 1196 1197 pcfg_pull_up: pcfg-pull-up { 1198 bias-pull-up; 1199 }; 1200 1201 pcfg_pull_down: pcfg-pull-down { 1202 bias-pull-down; 1203 }; 1204 1205 pcfg_pull_none: pcfg-pull-none { 1206 bias-disable; 1207 }; 1208 1209 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1210 bias-disable; 1211 drive-strength = <2>; 1212 }; 1213 1214 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1215 bias-pull-up; 1216 drive-strength = <2>; 1217 }; 1218 1219 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1220 bias-pull-up; 1221 drive-strength = <4>; 1222 }; 1223 1224 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1225 bias-disable; 1226 drive-strength = <4>; 1227 }; 1228 1229 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1230 bias-pull-down; 1231 drive-strength = <4>; 1232 }; 1233 1234 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1235 bias-disable; 1236 drive-strength = <8>; 1237 }; 1238 1239 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1240 bias-pull-up; 1241 drive-strength = <8>; 1242 }; 1243 1244 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1245 bias-disable; 1246 drive-strength = <12>; 1247 }; 1248 1249 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1250 bias-pull-up; 1251 drive-strength = <12>; 1252 }; 1253 1254 pcfg_output_high: pcfg-output-high { 1255 output-high; 1256 }; 1257 1258 pcfg_output_low: pcfg-output-low { 1259 output-low; 1260 }; 1261 1262 pcfg_input_high: pcfg-input-high { 1263 bias-pull-up; 1264 input-enable; 1265 }; 1266 1267 pcfg_input: pcfg-input { 1268 input-enable; 1269 }; 1270 1271 i2c0 { 1272 i2c0_xfer: i2c0-xfer { 1273 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1274 <2 RK_PD1 1 &pcfg_pull_none>; 1275 }; 1276 }; 1277 1278 i2c1 { 1279 i2c1_xfer: i2c1-xfer { 1280 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1281 <2 RK_PA5 2 &pcfg_pull_none>; 1282 }; 1283 }; 1284 1285 i2c2 { 1286 i2c2_xfer: i2c2-xfer { 1287 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1288 <2 RK_PB6 1 &pcfg_pull_none>; 1289 }; 1290 }; 1291 1292 i2c3 { 1293 i2c3_xfer: i2c3-xfer { 1294 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1295 <0 RK_PA6 2 &pcfg_pull_none>; 1296 }; 1297 i2c3_pins: i2c3-pins { 1298 rockchip,pins = 1299 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1300 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1301 }; 1302 }; 1303 1304 hdmi_i2c { 1305 hdmii2c_xfer: hdmii2c-xfer { 1306 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1307 <0 RK_PA6 1 &pcfg_pull_none>; 1308 }; 1309 }; 1310 1311 pdm-0 { 1312 pdmm0_clk: pdmm0-clk { 1313 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1314 }; 1315 1316 pdmm0_fsync: pdmm0-fsync { 1317 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1318 }; 1319 1320 pdmm0_sdi0: pdmm0-sdi0 { 1321 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1322 }; 1323 1324 pdmm0_sdi1: pdmm0-sdi1 { 1325 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1326 }; 1327 1328 pdmm0_sdi2: pdmm0-sdi2 { 1329 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1330 }; 1331 1332 pdmm0_sdi3: pdmm0-sdi3 { 1333 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1334 }; 1335 1336 pdmm0_clk_sleep: pdmm0-clk-sleep { 1337 rockchip,pins = 1338 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1339 }; 1340 1341 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1342 rockchip,pins = 1343 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1344 }; 1345 1346 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1347 rockchip,pins = 1348 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1349 }; 1350 1351 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1352 rockchip,pins = 1353 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1354 }; 1355 1356 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1357 rockchip,pins = 1358 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1359 }; 1360 1361 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1362 rockchip,pins = 1363 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1364 }; 1365 }; 1366 1367 tsadc { 1368 otp_pin: otp-pin { 1369 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1370 }; 1371 1372 otp_out: otp-out { 1373 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1374 }; 1375 }; 1376 1377 uart0 { 1378 uart0_xfer: uart0-xfer { 1379 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1380 <1 RK_PB0 1 &pcfg_pull_up>; 1381 }; 1382 1383 uart0_cts: uart0-cts { 1384 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1385 }; 1386 1387 uart0_rts: uart0-rts { 1388 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1389 }; 1390 1391 uart0_rts_pin: uart0-rts-pin { 1392 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1393 }; 1394 }; 1395 1396 uart1 { 1397 uart1_xfer: uart1-xfer { 1398 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, 1399 <3 RK_PA6 4 &pcfg_pull_up>; 1400 }; 1401 1402 uart1_cts: uart1-cts { 1403 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1404 }; 1405 1406 uart1_rts: uart1-rts { 1407 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1408 }; 1409 1410 uart1_rts_pin: uart1-rts-pin { 1411 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1412 }; 1413 }; 1414 1415 uart2-0 { 1416 uart2m0_xfer: uart2m0-xfer { 1417 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, 1418 <1 RK_PA1 2 &pcfg_pull_up>; 1419 }; 1420 }; 1421 1422 uart2-1 { 1423 uart2m1_xfer: uart2m1-xfer { 1424 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 1425 <2 RK_PA1 1 &pcfg_pull_up>; 1426 }; 1427 }; 1428 1429 spi0-0 { 1430 spi0m0_clk: spi0m0-clk { 1431 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1432 }; 1433 1434 spi0m0_cs0: spi0m0-cs0 { 1435 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1436 }; 1437 1438 spi0m0_tx: spi0m0-tx { 1439 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1440 }; 1441 1442 spi0m0_rx: spi0m0-rx { 1443 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1444 }; 1445 1446 spi0m0_cs1: spi0m0-cs1 { 1447 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1448 }; 1449 }; 1450 1451 spi0-1 { 1452 spi0m1_clk: spi0m1-clk { 1453 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1454 }; 1455 1456 spi0m1_cs0: spi0m1-cs0 { 1457 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1458 }; 1459 1460 spi0m1_tx: spi0m1-tx { 1461 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1462 }; 1463 1464 spi0m1_rx: spi0m1-rx { 1465 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1466 }; 1467 1468 spi0m1_cs1: spi0m1-cs1 { 1469 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1470 }; 1471 }; 1472 1473 spi0-2 { 1474 spi0m2_clk: spi0m2-clk { 1475 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1476 }; 1477 1478 spi0m2_cs0: spi0m2-cs0 { 1479 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1480 }; 1481 1482 spi0m2_tx: spi0m2-tx { 1483 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1484 }; 1485 1486 spi0m2_rx: spi0m2-rx { 1487 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1488 }; 1489 }; 1490 1491 i2s1 { 1492 i2s1_mclk: i2s1-mclk { 1493 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1494 }; 1495 1496 i2s1_sclk: i2s1-sclk { 1497 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1498 }; 1499 1500 i2s1_lrckrx: i2s1-lrckrx { 1501 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1502 }; 1503 1504 i2s1_lrcktx: i2s1-lrcktx { 1505 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1506 }; 1507 1508 i2s1_sdi: i2s1-sdi { 1509 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1510 }; 1511 1512 i2s1_sdo: i2s1-sdo { 1513 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1514 }; 1515 1516 i2s1_sdio1: i2s1-sdio1 { 1517 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1518 }; 1519 1520 i2s1_sdio2: i2s1-sdio2 { 1521 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1522 }; 1523 1524 i2s1_sdio3: i2s1-sdio3 { 1525 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1526 }; 1527 1528 i2s1_sleep: i2s1-sleep { 1529 rockchip,pins = 1530 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1531 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1532 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1533 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1534 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1535 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1536 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1537 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1538 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1539 }; 1540 }; 1541 1542 i2s2-0 { 1543 i2s2m0_mclk: i2s2m0-mclk { 1544 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1545 }; 1546 1547 i2s2m0_sclk: i2s2m0-sclk { 1548 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1549 }; 1550 1551 i2s2m0_lrckrx: i2s2m0-lrckrx { 1552 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1553 }; 1554 1555 i2s2m0_lrcktx: i2s2m0-lrcktx { 1556 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1557 }; 1558 1559 i2s2m0_sdi: i2s2m0-sdi { 1560 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1561 }; 1562 1563 i2s2m0_sdo: i2s2m0-sdo { 1564 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1565 }; 1566 1567 i2s2m0_sleep: i2s2m0-sleep { 1568 rockchip,pins = 1569 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1570 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1571 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1572 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1573 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1574 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1575 }; 1576 }; 1577 1578 i2s2-1 { 1579 i2s2m1_mclk: i2s2m1-mclk { 1580 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1581 }; 1582 1583 i2s2m1_sclk: i2s2m1-sclk { 1584 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1585 }; 1586 1587 i2s2m1_lrckrx: i2sm1-lrckrx { 1588 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1589 }; 1590 1591 i2s2m1_lrcktx: i2s2m1-lrcktx { 1592 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1593 }; 1594 1595 i2s2m1_sdi: i2s2m1-sdi { 1596 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1597 }; 1598 1599 i2s2m1_sdo: i2s2m1-sdo { 1600 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1601 }; 1602 1603 i2s2m1_sleep: i2s2m1-sleep { 1604 rockchip,pins = 1605 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1606 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1607 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1608 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1609 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1610 }; 1611 }; 1612 1613 spdif-0 { 1614 spdifm0_tx: spdifm0-tx { 1615 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1616 }; 1617 }; 1618 1619 spdif-1 { 1620 spdifm1_tx: spdifm1-tx { 1621 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1622 }; 1623 }; 1624 1625 spdif-2 { 1626 spdifm2_tx: spdifm2-tx { 1627 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1628 }; 1629 }; 1630 1631 sdmmc0-0 { 1632 sdmmc0m0_pwren: sdmmc0m0-pwren { 1633 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1634 }; 1635 1636 sdmmc0m0_pin: sdmmc0m0-pin { 1637 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1638 }; 1639 }; 1640 1641 sdmmc0-1 { 1642 sdmmc0m1_pwren: sdmmc0m1-pwren { 1643 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1644 }; 1645 1646 sdmmc0m1_pin: sdmmc0m1-pin { 1647 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1648 }; 1649 }; 1650 1651 sdmmc0 { 1652 sdmmc0_clk: sdmmc0-clk { 1653 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1654 }; 1655 1656 sdmmc0_cmd: sdmmc0-cmd { 1657 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1658 }; 1659 1660 sdmmc0_dectn: sdmmc0-dectn { 1661 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1662 }; 1663 1664 sdmmc0_wrprt: sdmmc0-wrprt { 1665 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1666 }; 1667 1668 sdmmc0_bus1: sdmmc0-bus1 { 1669 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1670 }; 1671 1672 sdmmc0_bus4: sdmmc0-bus4 { 1673 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1674 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1675 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1676 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1677 }; 1678 1679 sdmmc0_pins: sdmmc0-pins { 1680 rockchip,pins = 1681 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1682 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1683 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1684 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1685 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1686 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1687 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1688 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1689 }; 1690 }; 1691 1692 sdmmc0ext { 1693 sdmmc0ext_clk: sdmmc0ext-clk { 1694 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1695 }; 1696 1697 sdmmc0ext_cmd: sdmmc0ext-cmd { 1698 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1699 }; 1700 1701 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1702 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1703 }; 1704 1705 sdmmc0ext_dectn: sdmmc0ext-dectn { 1706 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1707 }; 1708 1709 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1710 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1711 }; 1712 1713 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1714 rockchip,pins = 1715 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1716 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1717 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1718 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1719 }; 1720 1721 sdmmc0ext_pins: sdmmc0ext-pins { 1722 rockchip,pins = 1723 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1724 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1725 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1726 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1727 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1728 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1729 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1730 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1731 }; 1732 }; 1733 1734 sdmmc1 { 1735 sdmmc1_clk: sdmmc1-clk { 1736 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1737 }; 1738 1739 sdmmc1_cmd: sdmmc1-cmd { 1740 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1741 }; 1742 1743 sdmmc1_pwren: sdmmc1-pwren { 1744 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1745 }; 1746 1747 sdmmc1_wrprt: sdmmc1-wrprt { 1748 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1749 }; 1750 1751 sdmmc1_dectn: sdmmc1-dectn { 1752 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1753 }; 1754 1755 sdmmc1_bus1: sdmmc1-bus1 { 1756 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1757 }; 1758 1759 sdmmc1_bus4: sdmmc1-bus4 { 1760 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1761 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1762 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1763 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1764 }; 1765 1766 sdmmc1_pins: sdmmc1-pins { 1767 rockchip,pins = 1768 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1769 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1770 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1771 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1772 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1773 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1774 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1775 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1776 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1777 }; 1778 }; 1779 1780 emmc { 1781 emmc_clk: emmc-clk { 1782 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1783 }; 1784 1785 emmc_cmd: emmc-cmd { 1786 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1787 }; 1788 1789 emmc_pwren: emmc-pwren { 1790 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1791 }; 1792 1793 emmc_rstnout: emmc-rstnout { 1794 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1795 }; 1796 1797 emmc_bus1: emmc-bus1 { 1798 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1799 }; 1800 1801 emmc_bus4: emmc-bus4 { 1802 rockchip,pins = 1803 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1804 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1805 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1806 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1807 }; 1808 1809 emmc_bus8: emmc-bus8 { 1810 rockchip,pins = 1811 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1812 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1813 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1814 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1815 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1816 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1817 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1818 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1819 }; 1820 }; 1821 1822 pwm0 { 1823 pwm0_pin: pwm0-pin { 1824 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1825 }; 1826 }; 1827 1828 pwm1 { 1829 pwm1_pin: pwm1-pin { 1830 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1831 }; 1832 }; 1833 1834 pwm2 { 1835 pwm2_pin: pwm2-pin { 1836 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1837 }; 1838 }; 1839 1840 pwmir { 1841 pwmir_pin: pwmir-pin { 1842 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1843 }; 1844 }; 1845 1846 gmac-1 { 1847 rgmiim1_pins: rgmiim1-pins { 1848 rockchip,pins = 1849 /* mac_txclk */ 1850 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1851 /* mac_rxclk */ 1852 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1853 /* mac_mdio */ 1854 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1855 /* mac_txen */ 1856 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1857 /* mac_clk */ 1858 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1859 /* mac_rxdv */ 1860 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1861 /* mac_mdc */ 1862 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1863 /* mac_rxd1 */ 1864 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1865 /* mac_rxd0 */ 1866 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1867 /* mac_txd1 */ 1868 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1869 /* mac_txd0 */ 1870 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1871 /* mac_rxd3 */ 1872 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1873 /* mac_rxd2 */ 1874 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1875 /* mac_txd3 */ 1876 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1877 /* mac_txd2 */ 1878 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1879 1880 /* mac_txclk */ 1881 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1882 /* mac_txen */ 1883 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1884 /* mac_clk */ 1885 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1886 /* mac_txd1 */ 1887 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1888 /* mac_txd0 */ 1889 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1890 /* mac_txd3 */ 1891 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1892 /* mac_txd2 */ 1893 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1894 }; 1895 1896 rmiim1_pins: rmiim1-pins { 1897 rockchip,pins = 1898 /* mac_mdio */ 1899 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1900 /* mac_txen */ 1901 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1902 /* mac_clk */ 1903 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1904 /* mac_rxer */ 1905 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1906 /* mac_rxdv */ 1907 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1908 /* mac_mdc */ 1909 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1910 /* mac_rxd1 */ 1911 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1912 /* mac_rxd0 */ 1913 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1914 /* mac_txd1 */ 1915 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1916 /* mac_txd0 */ 1917 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1918 1919 /* mac_mdio */ 1920 <0 RK_PB3 1 &pcfg_pull_none>, 1921 /* mac_txen */ 1922 <0 RK_PB4 1 &pcfg_pull_none>, 1923 /* mac_clk */ 1924 <0 RK_PD0 1 &pcfg_pull_none>, 1925 /* mac_mdc */ 1926 <0 RK_PC3 1 &pcfg_pull_none>, 1927 /* mac_txd1 */ 1928 <0 RK_PC0 1 &pcfg_pull_none>, 1929 /* mac_txd0 */ 1930 <0 RK_PC1 1 &pcfg_pull_none>; 1931 }; 1932 }; 1933 1934 gmac2phy { 1935 fephyled_speed10: fephyled-speed10 { 1936 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1937 }; 1938 1939 fephyled_duplex: fephyled-duplex { 1940 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1941 }; 1942 1943 fephyled_rxm1: fephyled-rxm1 { 1944 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1945 }; 1946 1947 fephyled_txm1: fephyled-txm1 { 1948 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1949 }; 1950 1951 fephyled_linkm1: fephyled-linkm1 { 1952 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1953 }; 1954 }; 1955 1956 tsadc_pin { 1957 tsadc_int: tsadc-int { 1958 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1959 }; 1960 tsadc_pin: tsadc-pin { 1961 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1962 }; 1963 }; 1964 1965 hdmi_pin { 1966 hdmi_cec: hdmi-cec { 1967 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1968 }; 1969 1970 hdmi_hpd: hdmi-hpd { 1971 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1972 }; 1973 }; 1974 1975 cif-0 { 1976 dvp_d2d9_m0:dvp-d2d9-m0 { 1977 rockchip,pins = 1978 /* cif_d0 */ 1979 <3 RK_PA4 2 &pcfg_pull_none>, 1980 /* cif_d1 */ 1981 <3 RK_PA5 2 &pcfg_pull_none>, 1982 /* cif_d2 */ 1983 <3 RK_PA6 2 &pcfg_pull_none>, 1984 /* cif_d3 */ 1985 <3 RK_PA7 2 &pcfg_pull_none>, 1986 /* cif_d4 */ 1987 <3 RK_PB0 2 &pcfg_pull_none>, 1988 /* cif_d5m0 */ 1989 <3 RK_PB1 2 &pcfg_pull_none>, 1990 /* cif_d6m0 */ 1991 <3 RK_PB2 2 &pcfg_pull_none>, 1992 /* cif_d7m0 */ 1993 <3 RK_PB3 2 &pcfg_pull_none>, 1994 /* cif_href */ 1995 <3 RK_PA1 2 &pcfg_pull_none>, 1996 /* cif_vsync */ 1997 <3 RK_PA0 2 &pcfg_pull_none>, 1998 /* cif_clkoutm0 */ 1999 <3 RK_PA3 2 &pcfg_pull_none>, 2000 /* cif_clkin */ 2001 <3 RK_PA2 2 &pcfg_pull_none>; 2002 }; 2003 }; 2004 2005 cif-1 { 2006 dvp_d2d9_m1:dvp-d2d9-m1 { 2007 rockchip,pins = 2008 /* cif_d0 */ 2009 <3 RK_PA4 2 &pcfg_pull_none>, 2010 /* cif_d1 */ 2011 <3 RK_PA5 2 &pcfg_pull_none>, 2012 /* cif_d2 */ 2013 <3 RK_PA6 2 &pcfg_pull_none>, 2014 /* cif_d3 */ 2015 <3 RK_PA7 2 &pcfg_pull_none>, 2016 /* cif_d4 */ 2017 <3 RK_PB0 2 &pcfg_pull_none>, 2018 /* cif_d5m1 */ 2019 <2 RK_PC0 4 &pcfg_pull_none>, 2020 /* cif_d6m1 */ 2021 <2 RK_PC1 4 &pcfg_pull_none>, 2022 /* cif_d7m1 */ 2023 <2 RK_PC2 4 &pcfg_pull_none>, 2024 /* cif_href */ 2025 <3 RK_PA1 2 &pcfg_pull_none>, 2026 /* cif_vsync */ 2027 <3 RK_PA0 2 &pcfg_pull_none>, 2028 /* cif_clkoutm1 */ 2029 <2 RK_PB7 4 &pcfg_pull_none>, 2030 /* cif_clkin */ 2031 <3 RK_PA2 2 &pcfg_pull_none>; 2032 }; 2033 }; 2034 }; 2035}; 2036