1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 i2c0 = &i2c0; 31 i2c1 = &i2c1; 32 i2c2 = &i2c2; 33 i2c3 = &i2c3; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 reg = <0x0 0x0>; 44 clocks = <&cru ARMCLK>; 45 #cooling-cells = <2>; 46 cpu-idle-states = <&CPU_SLEEP>; 47 dynamic-power-coefficient = <120>; 48 enable-method = "psci"; 49 operating-points-v2 = <&cpu0_opp_table>; 50 i-cache-size = <0x8000>; 51 i-cache-line-size = <64>; 52 i-cache-sets = <256>; 53 d-cache-size = <0x8000>; 54 d-cache-line-size = <64>; 55 d-cache-sets = <128>; 56 next-level-cache = <&l2_cache>; 57 }; 58 59 cpu1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0 0x1>; 63 clocks = <&cru ARMCLK>; 64 #cooling-cells = <2>; 65 cpu-idle-states = <&CPU_SLEEP>; 66 dynamic-power-coefficient = <120>; 67 enable-method = "psci"; 68 operating-points-v2 = <&cpu0_opp_table>; 69 i-cache-size = <0x8000>; 70 i-cache-line-size = <64>; 71 i-cache-sets = <256>; 72 d-cache-size = <0x8000>; 73 d-cache-line-size = <64>; 74 d-cache-sets = <128>; 75 next-level-cache = <&l2_cache>; 76 }; 77 78 cpu2: cpu@2 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x2>; 82 clocks = <&cru ARMCLK>; 83 #cooling-cells = <2>; 84 cpu-idle-states = <&CPU_SLEEP>; 85 dynamic-power-coefficient = <120>; 86 enable-method = "psci"; 87 operating-points-v2 = <&cpu0_opp_table>; 88 i-cache-size = <0x8000>; 89 i-cache-line-size = <64>; 90 i-cache-sets = <256>; 91 d-cache-size = <0x8000>; 92 d-cache-line-size = <64>; 93 d-cache-sets = <128>; 94 next-level-cache = <&l2_cache>; 95 }; 96 97 cpu3: cpu@3 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53"; 100 reg = <0x0 0x3>; 101 clocks = <&cru ARMCLK>; 102 #cooling-cells = <2>; 103 cpu-idle-states = <&CPU_SLEEP>; 104 dynamic-power-coefficient = <120>; 105 enable-method = "psci"; 106 operating-points-v2 = <&cpu0_opp_table>; 107 i-cache-size = <0x8000>; 108 i-cache-line-size = <64>; 109 i-cache-sets = <256>; 110 d-cache-size = <0x8000>; 111 d-cache-line-size = <64>; 112 d-cache-sets = <128>; 113 next-level-cache = <&l2_cache>; 114 }; 115 116 idle-states { 117 entry-method = "psci"; 118 119 CPU_SLEEP: cpu-sleep { 120 compatible = "arm,idle-state"; 121 local-timer-stop; 122 arm,psci-suspend-param = <0x0010000>; 123 entry-latency-us = <120>; 124 exit-latency-us = <250>; 125 min-residency-us = <900>; 126 }; 127 }; 128 129 l2_cache: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 cache-size = <0x40000>; 134 cache-line-size = <64>; 135 cache-sets = <256>; 136 }; 137 }; 138 139 cpu0_opp_table: opp-table-0 { 140 compatible = "operating-points-v2"; 141 opp-shared; 142 143 opp-408000000 { 144 opp-hz = /bits/ 64 <408000000>; 145 opp-microvolt = <950000>; 146 clock-latency-ns = <40000>; 147 opp-suspend; 148 }; 149 opp-600000000 { 150 opp-hz = /bits/ 64 <600000000>; 151 opp-microvolt = <950000>; 152 clock-latency-ns = <40000>; 153 }; 154 opp-816000000 { 155 opp-hz = /bits/ 64 <816000000>; 156 opp-microvolt = <1000000>; 157 clock-latency-ns = <40000>; 158 }; 159 opp-1008000000 { 160 opp-hz = /bits/ 64 <1008000000>; 161 opp-microvolt = <1100000>; 162 clock-latency-ns = <40000>; 163 }; 164 opp-1200000000 { 165 opp-hz = /bits/ 64 <1200000000>; 166 opp-microvolt = <1225000>; 167 clock-latency-ns = <40000>; 168 }; 169 opp-1296000000 { 170 opp-hz = /bits/ 64 <1296000000>; 171 opp-microvolt = <1300000>; 172 clock-latency-ns = <40000>; 173 }; 174 }; 175 176 analog_sound: analog-sound { 177 compatible = "simple-audio-card"; 178 simple-audio-card,format = "i2s"; 179 simple-audio-card,mclk-fs = <256>; 180 simple-audio-card,name = "Analog"; 181 status = "disabled"; 182 183 simple-audio-card,cpu { 184 sound-dai = <&i2s1>; 185 }; 186 187 simple-audio-card,codec { 188 sound-dai = <&codec>; 189 }; 190 }; 191 192 arm-pmu { 193 compatible = "arm,cortex-a53-pmu"; 194 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 198 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 199 }; 200 201 display_subsystem: display-subsystem { 202 compatible = "rockchip,display-subsystem"; 203 ports = <&vop_out>; 204 }; 205 206 hdmi_sound: hdmi-sound { 207 compatible = "simple-audio-card"; 208 simple-audio-card,format = "i2s"; 209 simple-audio-card,mclk-fs = <128>; 210 simple-audio-card,name = "HDMI"; 211 status = "disabled"; 212 213 simple-audio-card,cpu { 214 sound-dai = <&i2s0>; 215 }; 216 217 simple-audio-card,codec { 218 sound-dai = <&hdmi>; 219 }; 220 }; 221 222 psci { 223 compatible = "arm,psci-1.0", "arm,psci-0.2"; 224 method = "smc"; 225 }; 226 227 timer { 228 compatible = "arm,armv8-timer"; 229 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 230 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 231 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 232 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 233 }; 234 235 xin24m: xin24m { 236 compatible = "fixed-clock"; 237 #clock-cells = <0>; 238 clock-frequency = <24000000>; 239 clock-output-names = "xin24m"; 240 }; 241 242 i2s0: i2s@ff000000 { 243 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 244 reg = <0x0 0xff000000 0x0 0x1000>; 245 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 247 clock-names = "i2s_clk", "i2s_hclk"; 248 dmas = <&dmac 11>, <&dmac 12>; 249 dma-names = "tx", "rx"; 250 #sound-dai-cells = <0>; 251 status = "disabled"; 252 }; 253 254 i2s1: i2s@ff010000 { 255 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 256 reg = <0x0 0xff010000 0x0 0x1000>; 257 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 259 clock-names = "i2s_clk", "i2s_hclk"; 260 dmas = <&dmac 14>, <&dmac 15>; 261 dma-names = "tx", "rx"; 262 #sound-dai-cells = <0>; 263 status = "disabled"; 264 }; 265 266 i2s2: i2s@ff020000 { 267 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 268 reg = <0x0 0xff020000 0x0 0x1000>; 269 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 271 clock-names = "i2s_clk", "i2s_hclk"; 272 dmas = <&dmac 0>, <&dmac 1>; 273 dma-names = "tx", "rx"; 274 #sound-dai-cells = <0>; 275 status = "disabled"; 276 }; 277 278 spdif: spdif@ff030000 { 279 compatible = "rockchip,rk3328-spdif"; 280 reg = <0x0 0xff030000 0x0 0x1000>; 281 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 283 clock-names = "mclk", "hclk"; 284 dmas = <&dmac 10>; 285 dma-names = "tx"; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&spdifm2_tx>; 288 #sound-dai-cells = <0>; 289 status = "disabled"; 290 }; 291 292 pdm: pdm@ff040000 { 293 compatible = "rockchip,pdm"; 294 reg = <0x0 0xff040000 0x0 0x1000>; 295 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 296 clock-names = "pdm_clk", "pdm_hclk"; 297 dmas = <&dmac 16>; 298 dma-names = "rx"; 299 pinctrl-names = "default", "sleep"; 300 pinctrl-0 = <&pdmm0_clk 301 &pdmm0_sdi0 302 &pdmm0_sdi1 303 &pdmm0_sdi2 304 &pdmm0_sdi3>; 305 pinctrl-1 = <&pdmm0_clk_sleep 306 &pdmm0_sdi0_sleep 307 &pdmm0_sdi1_sleep 308 &pdmm0_sdi2_sleep 309 &pdmm0_sdi3_sleep>; 310 status = "disabled"; 311 }; 312 313 grf: syscon@ff100000 { 314 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 315 reg = <0x0 0xff100000 0x0 0x1000>; 316 317 io_domains: io-domains { 318 compatible = "rockchip,rk3328-io-voltage-domain"; 319 status = "disabled"; 320 }; 321 322 grf_gpio: gpio { 323 compatible = "rockchip,rk3328-grf-gpio"; 324 gpio-controller; 325 #gpio-cells = <2>; 326 }; 327 328 power: power-controller { 329 compatible = "rockchip,rk3328-power-controller"; 330 #power-domain-cells = <1>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 334 power-domain@RK3328_PD_HEVC { 335 reg = <RK3328_PD_HEVC>; 336 #power-domain-cells = <0>; 337 }; 338 power-domain@RK3328_PD_VIDEO { 339 reg = <RK3328_PD_VIDEO>; 340 clocks = <&cru ACLK_RKVDEC>, 341 <&cru HCLK_RKVDEC>, 342 <&cru SCLK_VDEC_CABAC>, 343 <&cru SCLK_VDEC_CORE>; 344 #power-domain-cells = <0>; 345 }; 346 power-domain@RK3328_PD_VPU { 347 reg = <RK3328_PD_VPU>; 348 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 349 #power-domain-cells = <0>; 350 }; 351 }; 352 353 reboot-mode { 354 compatible = "syscon-reboot-mode"; 355 offset = <0x5c8>; 356 mode-normal = <BOOT_NORMAL>; 357 mode-recovery = <BOOT_RECOVERY>; 358 mode-bootloader = <BOOT_FASTBOOT>; 359 mode-loader = <BOOT_BL_DOWNLOAD>; 360 }; 361 }; 362 363 uart0: serial@ff110000 { 364 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 365 reg = <0x0 0xff110000 0x0 0x100>; 366 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 368 clock-names = "baudclk", "apb_pclk"; 369 dmas = <&dmac 2>, <&dmac 3>; 370 dma-names = "tx", "rx"; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 373 reg-io-width = <4>; 374 reg-shift = <2>; 375 status = "disabled"; 376 }; 377 378 uart1: serial@ff120000 { 379 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 380 reg = <0x0 0xff120000 0x0 0x100>; 381 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 383 clock-names = "baudclk", "apb_pclk"; 384 dmas = <&dmac 4>, <&dmac 5>; 385 dma-names = "tx", "rx"; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 388 reg-io-width = <4>; 389 reg-shift = <2>; 390 status = "disabled"; 391 }; 392 393 uart2: serial@ff130000 { 394 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 395 reg = <0x0 0xff130000 0x0 0x100>; 396 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 398 clock-names = "baudclk", "apb_pclk"; 399 dmas = <&dmac 6>, <&dmac 7>; 400 dma-names = "tx", "rx"; 401 pinctrl-names = "default"; 402 pinctrl-0 = <&uart2m1_xfer>; 403 reg-io-width = <4>; 404 reg-shift = <2>; 405 status = "disabled"; 406 }; 407 408 i2c0: i2c@ff150000 { 409 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 410 reg = <0x0 0xff150000 0x0 0x1000>; 411 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 415 clock-names = "i2c", "pclk"; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&i2c0_xfer>; 418 status = "disabled"; 419 }; 420 421 i2c1: i2c@ff160000 { 422 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 423 reg = <0x0 0xff160000 0x0 0x1000>; 424 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 428 clock-names = "i2c", "pclk"; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&i2c1_xfer>; 431 status = "disabled"; 432 }; 433 434 i2c2: i2c@ff170000 { 435 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 436 reg = <0x0 0xff170000 0x0 0x1000>; 437 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 441 clock-names = "i2c", "pclk"; 442 pinctrl-names = "default"; 443 pinctrl-0 = <&i2c2_xfer>; 444 status = "disabled"; 445 }; 446 447 i2c3: i2c@ff180000 { 448 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 449 reg = <0x0 0xff180000 0x0 0x1000>; 450 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 454 clock-names = "i2c", "pclk"; 455 pinctrl-names = "default"; 456 pinctrl-0 = <&i2c3_xfer>; 457 status = "disabled"; 458 }; 459 460 spi0: spi@ff190000 { 461 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 462 reg = <0x0 0xff190000 0x0 0x1000>; 463 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 467 clock-names = "spiclk", "apb_pclk"; 468 dmas = <&dmac 8>, <&dmac 9>; 469 dma-names = "tx", "rx"; 470 pinctrl-names = "default"; 471 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 472 status = "disabled"; 473 }; 474 475 wdt: watchdog@ff1a0000 { 476 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; 477 reg = <0x0 0xff1a0000 0x0 0x100>; 478 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&cru PCLK_WDT>; 480 }; 481 482 pwm0: pwm@ff1b0000 { 483 compatible = "rockchip,rk3328-pwm"; 484 reg = <0x0 0xff1b0000 0x0 0x10>; 485 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 486 clock-names = "pwm", "pclk"; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&pwm0_pin>; 489 #pwm-cells = <3>; 490 status = "disabled"; 491 }; 492 493 pwm1: pwm@ff1b0010 { 494 compatible = "rockchip,rk3328-pwm"; 495 reg = <0x0 0xff1b0010 0x0 0x10>; 496 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 497 clock-names = "pwm", "pclk"; 498 pinctrl-names = "default"; 499 pinctrl-0 = <&pwm1_pin>; 500 #pwm-cells = <3>; 501 status = "disabled"; 502 }; 503 504 pwm2: pwm@ff1b0020 { 505 compatible = "rockchip,rk3328-pwm"; 506 reg = <0x0 0xff1b0020 0x0 0x10>; 507 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 508 clock-names = "pwm", "pclk"; 509 pinctrl-names = "default"; 510 pinctrl-0 = <&pwm2_pin>; 511 #pwm-cells = <3>; 512 status = "disabled"; 513 }; 514 515 pwm3: pwm@ff1b0030 { 516 compatible = "rockchip,rk3328-pwm"; 517 reg = <0x0 0xff1b0030 0x0 0x10>; 518 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 519 clock-names = "pwm", "pclk"; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&pwmir_pin>; 522 #pwm-cells = <3>; 523 status = "disabled"; 524 }; 525 526 dmac: dma-controller@ff1f0000 { 527 compatible = "arm,pl330", "arm,primecell"; 528 reg = <0x0 0xff1f0000 0x0 0x4000>; 529 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 531 arm,pl330-periph-burst; 532 clocks = <&cru ACLK_DMAC>; 533 clock-names = "apb_pclk"; 534 #dma-cells = <1>; 535 }; 536 537 thermal-zones { 538 soc_thermal: soc-thermal { 539 polling-delay-passive = <20>; 540 polling-delay = <1000>; 541 sustainable-power = <1000>; 542 543 thermal-sensors = <&tsadc 0>; 544 545 trips { 546 threshold: trip-point0 { 547 temperature = <70000>; 548 hysteresis = <2000>; 549 type = "passive"; 550 }; 551 target: trip-point1 { 552 temperature = <85000>; 553 hysteresis = <2000>; 554 type = "passive"; 555 }; 556 soc_crit: soc-crit { 557 temperature = <95000>; 558 hysteresis = <2000>; 559 type = "critical"; 560 }; 561 }; 562 563 cooling-maps { 564 map0 { 565 trip = <&target>; 566 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 567 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 568 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 569 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 570 contribution = <4096>; 571 }; 572 }; 573 }; 574 575 }; 576 577 tsadc: tsadc@ff250000 { 578 compatible = "rockchip,rk3328-tsadc"; 579 reg = <0x0 0xff250000 0x0 0x100>; 580 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 581 assigned-clocks = <&cru SCLK_TSADC>; 582 assigned-clock-rates = <50000>; 583 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 584 clock-names = "tsadc", "apb_pclk"; 585 pinctrl-names = "init", "default", "sleep"; 586 pinctrl-0 = <&otp_pin>; 587 pinctrl-1 = <&otp_out>; 588 pinctrl-2 = <&otp_pin>; 589 resets = <&cru SRST_TSADC>; 590 reset-names = "tsadc-apb"; 591 rockchip,grf = <&grf>; 592 rockchip,hw-tshut-temp = <100000>; 593 #thermal-sensor-cells = <1>; 594 status = "disabled"; 595 }; 596 597 efuse: efuse@ff260000 { 598 compatible = "rockchip,rk3328-efuse"; 599 reg = <0x0 0xff260000 0x0 0x50>; 600 #address-cells = <1>; 601 #size-cells = <1>; 602 clocks = <&cru SCLK_EFUSE>; 603 clock-names = "pclk_efuse"; 604 rockchip,efuse-size = <0x20>; 605 606 /* Data cells */ 607 efuse_id: id@7 { 608 reg = <0x07 0x10>; 609 }; 610 cpu_leakage: cpu-leakage@17 { 611 reg = <0x17 0x1>; 612 }; 613 logic_leakage: logic-leakage@19 { 614 reg = <0x19 0x1>; 615 }; 616 efuse_cpu_version: cpu-version@1a { 617 reg = <0x1a 0x1>; 618 bits = <3 3>; 619 }; 620 }; 621 622 saradc: adc@ff280000 { 623 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 624 reg = <0x0 0xff280000 0x0 0x100>; 625 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 626 #io-channel-cells = <1>; 627 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 628 clock-names = "saradc", "apb_pclk"; 629 resets = <&cru SRST_SARADC_P>; 630 reset-names = "saradc-apb"; 631 status = "disabled"; 632 }; 633 634 gpu: gpu@ff300000 { 635 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 636 reg = <0x0 0xff300000 0x0 0x30000>; 637 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 644 interrupt-names = "gp", 645 "gpmmu", 646 "pp", 647 "pp0", 648 "ppmmu0", 649 "pp1", 650 "ppmmu1"; 651 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 652 clock-names = "bus", "core"; 653 resets = <&cru SRST_GPU_A>; 654 }; 655 656 h265e_mmu: iommu@ff330200 { 657 compatible = "rockchip,iommu"; 658 reg = <0x0 0xff330200 0 0x100>; 659 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 661 clock-names = "aclk", "iface"; 662 #iommu-cells = <0>; 663 status = "disabled"; 664 }; 665 666 vepu_mmu: iommu@ff340800 { 667 compatible = "rockchip,iommu"; 668 reg = <0x0 0xff340800 0x0 0x40>; 669 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 671 clock-names = "aclk", "iface"; 672 #iommu-cells = <0>; 673 status = "disabled"; 674 }; 675 676 vpu: video-codec@ff350000 { 677 compatible = "rockchip,rk3328-vpu"; 678 reg = <0x0 0xff350000 0x0 0x800>; 679 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 680 interrupt-names = "vdpu"; 681 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 682 clock-names = "aclk", "hclk"; 683 iommus = <&vpu_mmu>; 684 power-domains = <&power RK3328_PD_VPU>; 685 }; 686 687 vpu_mmu: iommu@ff350800 { 688 compatible = "rockchip,iommu"; 689 reg = <0x0 0xff350800 0x0 0x40>; 690 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 692 clock-names = "aclk", "iface"; 693 #iommu-cells = <0>; 694 power-domains = <&power RK3328_PD_VPU>; 695 }; 696 697 vdec: video-codec@ff360000 { 698 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; 699 reg = <0x0 0xff360000 0x0 0x480>; 700 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, 702 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; 703 clock-names = "axi", "ahb", "cabac", "core"; 704 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, 705 <&cru SCLK_VDEC_CORE>; 706 assigned-clock-rates = <400000000>, <400000000>, <300000000>; 707 iommus = <&vdec_mmu>; 708 power-domains = <&power RK3328_PD_VIDEO>; 709 }; 710 711 vdec_mmu: iommu@ff360480 { 712 compatible = "rockchip,iommu"; 713 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 714 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 716 clock-names = "aclk", "iface"; 717 #iommu-cells = <0>; 718 power-domains = <&power RK3328_PD_VIDEO>; 719 }; 720 721 vop: vop@ff370000 { 722 compatible = "rockchip,rk3328-vop"; 723 reg = <0x0 0xff370000 0x0 0x3efc>; 724 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 726 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 727 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 728 reset-names = "axi", "ahb", "dclk"; 729 iommus = <&vop_mmu>; 730 status = "disabled"; 731 732 vop_out: port { 733 #address-cells = <1>; 734 #size-cells = <0>; 735 736 vop_out_hdmi: endpoint@0 { 737 reg = <0>; 738 remote-endpoint = <&hdmi_in_vop>; 739 }; 740 }; 741 }; 742 743 vop_mmu: iommu@ff373f00 { 744 compatible = "rockchip,iommu"; 745 reg = <0x0 0xff373f00 0x0 0x100>; 746 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 748 clock-names = "aclk", "iface"; 749 #iommu-cells = <0>; 750 status = "disabled"; 751 }; 752 753 hdmi: hdmi@ff3c0000 { 754 compatible = "rockchip,rk3328-dw-hdmi"; 755 reg = <0x0 0xff3c0000 0x0 0x20000>; 756 reg-io-width = <4>; 757 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&cru PCLK_HDMI>, 759 <&cru SCLK_HDMI_SFC>, 760 <&cru SCLK_RTC32K>; 761 clock-names = "iahb", 762 "isfr", 763 "cec"; 764 phys = <&hdmiphy>; 765 phy-names = "hdmi"; 766 pinctrl-names = "default"; 767 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 768 rockchip,grf = <&grf>; 769 #sound-dai-cells = <0>; 770 status = "disabled"; 771 772 ports { 773 #address-cells = <1>; 774 #size-cells = <0>; 775 776 hdmi_in: port@0 { 777 reg = <0>; 778 779 hdmi_in_vop: endpoint { 780 remote-endpoint = <&vop_out_hdmi>; 781 }; 782 }; 783 784 hdmi_out: port@1 { 785 reg = <1>; 786 }; 787 }; 788 }; 789 790 codec: codec@ff410000 { 791 compatible = "rockchip,rk3328-codec"; 792 reg = <0x0 0xff410000 0x0 0x1000>; 793 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 794 clock-names = "pclk", "mclk"; 795 rockchip,grf = <&grf>; 796 #sound-dai-cells = <0>; 797 status = "disabled"; 798 }; 799 800 hdmiphy: phy@ff430000 { 801 compatible = "rockchip,rk3328-hdmi-phy"; 802 reg = <0x0 0xff430000 0x0 0x10000>; 803 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 805 clock-names = "sysclk", "refoclk", "refpclk"; 806 clock-output-names = "hdmi_phy"; 807 #clock-cells = <0>; 808 nvmem-cells = <&efuse_cpu_version>; 809 nvmem-cell-names = "cpu-version"; 810 #phy-cells = <0>; 811 status = "disabled"; 812 }; 813 814 cru: clock-controller@ff440000 { 815 compatible = "rockchip,rk3328-cru"; 816 reg = <0x0 0xff440000 0x0 0x1000>; 817 clocks = <&xin24m>; 818 clock-names = "xin24m"; 819 rockchip,grf = <&grf>; 820 #clock-cells = <1>; 821 #reset-cells = <1>; 822 assigned-clocks = 823 /* 824 * CPLL should run at 1200, but that is to high for 825 * the initial dividers of most of its children. 826 * We need set cpll child clk div first, 827 * and then set the cpll frequency. 828 */ 829 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 830 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 831 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 832 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 833 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 834 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 835 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 836 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 837 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 838 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 839 <&cru SCLK_WIFI>, <&cru ARMCLK>, 840 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 841 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 842 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 843 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 844 <&cru SCLK_RTC32K>; 845 assigned-clock-parents = 846 <&cru HDMIPHY>, <&cru PLL_APLL>, 847 <&cru PLL_GPLL>, <&xin24m>, 848 <&xin24m>, <&xin24m>; 849 assigned-clock-rates = 850 <0>, <61440000>, 851 <0>, <24000000>, 852 <24000000>, <24000000>, 853 <15000000>, <15000000>, 854 <300000000>, <100000000>, 855 <400000000>, <100000000>, 856 <50000000>, <100000000>, 857 <100000000>, <100000000>, 858 <50000000>, <50000000>, 859 <50000000>, <50000000>, 860 <24000000>, <600000000>, 861 <491520000>, <1200000000>, 862 <150000000>, <75000000>, 863 <75000000>, <150000000>, 864 <75000000>, <75000000>, 865 <32768>; 866 }; 867 868 usb2phy_grf: syscon@ff450000 { 869 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 870 "simple-mfd"; 871 reg = <0x0 0xff450000 0x0 0x10000>; 872 #address-cells = <1>; 873 #size-cells = <1>; 874 875 u2phy: usb2phy@100 { 876 compatible = "rockchip,rk3328-usb2phy"; 877 reg = <0x100 0x10>; 878 clocks = <&xin24m>; 879 clock-names = "phyclk"; 880 clock-output-names = "usb480m_phy"; 881 #clock-cells = <0>; 882 assigned-clocks = <&cru USB480M>; 883 assigned-clock-parents = <&u2phy>; 884 status = "disabled"; 885 886 u2phy_otg: otg-port { 887 #phy-cells = <0>; 888 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 891 interrupt-names = "otg-bvalid", "otg-id", 892 "linestate"; 893 status = "disabled"; 894 }; 895 896 u2phy_host: host-port { 897 #phy-cells = <0>; 898 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 899 interrupt-names = "linestate"; 900 status = "disabled"; 901 }; 902 }; 903 }; 904 905 sdmmc: mmc@ff500000 { 906 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 907 reg = <0x0 0xff500000 0x0 0x4000>; 908 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 910 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 911 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 912 fifo-depth = <0x100>; 913 max-frequency = <150000000>; 914 resets = <&cru SRST_MMC0>; 915 reset-names = "reset"; 916 status = "disabled"; 917 }; 918 919 sdio: mmc@ff510000 { 920 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 921 reg = <0x0 0xff510000 0x0 0x4000>; 922 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 923 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 924 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 925 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 926 fifo-depth = <0x100>; 927 max-frequency = <150000000>; 928 resets = <&cru SRST_SDIO>; 929 reset-names = "reset"; 930 status = "disabled"; 931 }; 932 933 emmc: mmc@ff520000 { 934 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 935 reg = <0x0 0xff520000 0x0 0x4000>; 936 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 938 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 939 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 940 fifo-depth = <0x100>; 941 max-frequency = <150000000>; 942 resets = <&cru SRST_EMMC>; 943 reset-names = "reset"; 944 status = "disabled"; 945 }; 946 947 gmac2io: ethernet@ff540000 { 948 compatible = "rockchip,rk3328-gmac"; 949 reg = <0x0 0xff540000 0x0 0x10000>; 950 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 951 interrupt-names = "macirq"; 952 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 953 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 954 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 955 <&cru PCLK_MAC2IO>; 956 clock-names = "stmmaceth", "mac_clk_rx", 957 "mac_clk_tx", "clk_mac_ref", 958 "clk_mac_refout", "aclk_mac", 959 "pclk_mac"; 960 resets = <&cru SRST_GMAC2IO_A>; 961 reset-names = "stmmaceth"; 962 rockchip,grf = <&grf>; 963 tx-fifo-depth = <2048>; 964 rx-fifo-depth = <4096>; 965 snps,txpbl = <0x4>; 966 status = "disabled"; 967 }; 968 969 gmac2phy: ethernet@ff550000 { 970 compatible = "rockchip,rk3328-gmac"; 971 reg = <0x0 0xff550000 0x0 0x10000>; 972 rockchip,grf = <&grf>; 973 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 974 interrupt-names = "macirq"; 975 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 976 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 977 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 978 <&cru SCLK_MAC2PHY_OUT>; 979 clock-names = "stmmaceth", "mac_clk_rx", 980 "mac_clk_tx", "clk_mac_ref", 981 "aclk_mac", "pclk_mac", 982 "clk_macphy"; 983 resets = <&cru SRST_GMAC2PHY_A>; 984 reset-names = "stmmaceth"; 985 phy-mode = "rmii"; 986 phy-handle = <&phy>; 987 tx-fifo-depth = <2048>; 988 rx-fifo-depth = <4096>; 989 snps,txpbl = <0x4>; 990 clock_in_out = "output"; 991 status = "disabled"; 992 993 mdio { 994 compatible = "snps,dwmac-mdio"; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 998 phy: ethernet-phy@0 { 999 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 1000 reg = <0>; 1001 clocks = <&cru SCLK_MAC2PHY_OUT>; 1002 resets = <&cru SRST_MACPHY>; 1003 pinctrl-names = "default"; 1004 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 1005 phy-is-integrated; 1006 }; 1007 }; 1008 }; 1009 1010 usb20_otg: usb@ff580000 { 1011 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 1012 "snps,dwc2"; 1013 reg = <0x0 0xff580000 0x0 0x40000>; 1014 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&cru HCLK_OTG>; 1016 clock-names = "otg"; 1017 dr_mode = "otg"; 1018 g-np-tx-fifo-size = <16>; 1019 g-rx-fifo-size = <280>; 1020 g-tx-fifo-size = <256 128 128 64 32 16>; 1021 phys = <&u2phy_otg>; 1022 phy-names = "usb2-phy"; 1023 status = "disabled"; 1024 }; 1025 1026 usb_host0_ehci: usb@ff5c0000 { 1027 compatible = "generic-ehci"; 1028 reg = <0x0 0xff5c0000 0x0 0x10000>; 1029 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1030 clocks = <&cru HCLK_HOST0>, <&u2phy>; 1031 phys = <&u2phy_host>; 1032 phy-names = "usb"; 1033 status = "disabled"; 1034 }; 1035 1036 usb_host0_ohci: usb@ff5d0000 { 1037 compatible = "generic-ohci"; 1038 reg = <0x0 0xff5d0000 0x0 0x10000>; 1039 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1040 clocks = <&cru HCLK_HOST0>, <&u2phy>; 1041 phys = <&u2phy_host>; 1042 phy-names = "usb"; 1043 status = "disabled"; 1044 }; 1045 1046 sdmmc_ext: mmc@ff5f0000 { 1047 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 1048 reg = <0x0 0xff5f0000 0x0 0x4000>; 1049 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1050 clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, 1051 <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; 1052 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1053 fifo-depth = <0x100>; 1054 max-frequency = <150000000>; 1055 resets = <&cru SRST_SDMMCEXT>; 1056 reset-names = "reset"; 1057 status = "disabled"; 1058 }; 1059 1060 usbdrd3: usb@ff600000 { 1061 compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; 1062 reg = <0x0 0xff600000 0x0 0x100000>; 1063 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 1065 <&cru ACLK_USB3OTG>; 1066 clock-names = "ref_clk", "suspend_clk", 1067 "bus_clk"; 1068 dr_mode = "otg"; 1069 phy_type = "utmi_wide"; 1070 snps,dis-del-phy-power-chg-quirk; 1071 snps,dis_enblslpm_quirk; 1072 snps,dis-tx-ipgap-linecheck-quirk; 1073 snps,dis-u2-freeclk-exists-quirk; 1074 snps,dis_u2_susphy_quirk; 1075 snps,dis_u3_susphy_quirk; 1076 status = "disabled"; 1077 }; 1078 1079 gic: interrupt-controller@ff811000 { 1080 compatible = "arm,gic-400"; 1081 #interrupt-cells = <3>; 1082 #address-cells = <0>; 1083 interrupt-controller; 1084 reg = <0x0 0xff811000 0 0x1000>, 1085 <0x0 0xff812000 0 0x2000>, 1086 <0x0 0xff814000 0 0x2000>, 1087 <0x0 0xff816000 0 0x2000>; 1088 interrupts = <GIC_PPI 9 1089 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1090 }; 1091 1092 crypto: crypto@ff060000 { 1093 compatible = "rockchip,rk3328-crypto"; 1094 reg = <0x0 0xff060000 0x0 0x4000>; 1095 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>, 1097 <&cru SCLK_CRYPTO>; 1098 clock-names = "hclk_master", "hclk_slave", "sclk"; 1099 resets = <&cru SRST_CRYPTO>; 1100 reset-names = "crypto-rst"; 1101 }; 1102 1103 pinctrl: pinctrl { 1104 compatible = "rockchip,rk3328-pinctrl"; 1105 rockchip,grf = <&grf>; 1106 #address-cells = <2>; 1107 #size-cells = <2>; 1108 ranges; 1109 1110 gpio0: gpio@ff210000 { 1111 compatible = "rockchip,gpio-bank"; 1112 reg = <0x0 0xff210000 0x0 0x100>; 1113 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1114 clocks = <&cru PCLK_GPIO0>; 1115 1116 gpio-controller; 1117 #gpio-cells = <2>; 1118 1119 interrupt-controller; 1120 #interrupt-cells = <2>; 1121 }; 1122 1123 gpio1: gpio@ff220000 { 1124 compatible = "rockchip,gpio-bank"; 1125 reg = <0x0 0xff220000 0x0 0x100>; 1126 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1127 clocks = <&cru PCLK_GPIO1>; 1128 1129 gpio-controller; 1130 #gpio-cells = <2>; 1131 1132 interrupt-controller; 1133 #interrupt-cells = <2>; 1134 }; 1135 1136 gpio2: gpio@ff230000 { 1137 compatible = "rockchip,gpio-bank"; 1138 reg = <0x0 0xff230000 0x0 0x100>; 1139 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1140 clocks = <&cru PCLK_GPIO2>; 1141 1142 gpio-controller; 1143 #gpio-cells = <2>; 1144 1145 interrupt-controller; 1146 #interrupt-cells = <2>; 1147 }; 1148 1149 gpio3: gpio@ff240000 { 1150 compatible = "rockchip,gpio-bank"; 1151 reg = <0x0 0xff240000 0x0 0x100>; 1152 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1153 clocks = <&cru PCLK_GPIO3>; 1154 1155 gpio-controller; 1156 #gpio-cells = <2>; 1157 1158 interrupt-controller; 1159 #interrupt-cells = <2>; 1160 }; 1161 1162 pcfg_pull_up: pcfg-pull-up { 1163 bias-pull-up; 1164 }; 1165 1166 pcfg_pull_down: pcfg-pull-down { 1167 bias-pull-down; 1168 }; 1169 1170 pcfg_pull_none: pcfg-pull-none { 1171 bias-disable; 1172 }; 1173 1174 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1175 bias-disable; 1176 drive-strength = <2>; 1177 }; 1178 1179 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1180 bias-pull-up; 1181 drive-strength = <2>; 1182 }; 1183 1184 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1185 bias-pull-up; 1186 drive-strength = <4>; 1187 }; 1188 1189 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1190 bias-disable; 1191 drive-strength = <4>; 1192 }; 1193 1194 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1195 bias-pull-down; 1196 drive-strength = <4>; 1197 }; 1198 1199 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1200 bias-disable; 1201 drive-strength = <8>; 1202 }; 1203 1204 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1205 bias-pull-up; 1206 drive-strength = <8>; 1207 }; 1208 1209 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1210 bias-disable; 1211 drive-strength = <12>; 1212 }; 1213 1214 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1215 bias-pull-up; 1216 drive-strength = <12>; 1217 }; 1218 1219 pcfg_output_high: pcfg-output-high { 1220 output-high; 1221 }; 1222 1223 pcfg_output_low: pcfg-output-low { 1224 output-low; 1225 }; 1226 1227 pcfg_input_high: pcfg-input-high { 1228 bias-pull-up; 1229 input-enable; 1230 }; 1231 1232 pcfg_input: pcfg-input { 1233 input-enable; 1234 }; 1235 1236 i2c0 { 1237 i2c0_xfer: i2c0-xfer { 1238 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1239 <2 RK_PD1 1 &pcfg_pull_none>; 1240 }; 1241 }; 1242 1243 i2c1 { 1244 i2c1_xfer: i2c1-xfer { 1245 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1246 <2 RK_PA5 2 &pcfg_pull_none>; 1247 }; 1248 }; 1249 1250 i2c2 { 1251 i2c2_xfer: i2c2-xfer { 1252 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1253 <2 RK_PB6 1 &pcfg_pull_none>; 1254 }; 1255 }; 1256 1257 i2c3 { 1258 i2c3_xfer: i2c3-xfer { 1259 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1260 <0 RK_PA6 2 &pcfg_pull_none>; 1261 }; 1262 i2c3_pins: i2c3-pins { 1263 rockchip,pins = 1264 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1265 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1266 }; 1267 }; 1268 1269 hdmi_i2c { 1270 hdmii2c_xfer: hdmii2c-xfer { 1271 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1272 <0 RK_PA6 1 &pcfg_pull_none>; 1273 }; 1274 }; 1275 1276 pdm-0 { 1277 pdmm0_clk: pdmm0-clk { 1278 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1279 }; 1280 1281 pdmm0_fsync: pdmm0-fsync { 1282 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1283 }; 1284 1285 pdmm0_sdi0: pdmm0-sdi0 { 1286 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1287 }; 1288 1289 pdmm0_sdi1: pdmm0-sdi1 { 1290 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1291 }; 1292 1293 pdmm0_sdi2: pdmm0-sdi2 { 1294 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1295 }; 1296 1297 pdmm0_sdi3: pdmm0-sdi3 { 1298 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1299 }; 1300 1301 pdmm0_clk_sleep: pdmm0-clk-sleep { 1302 rockchip,pins = 1303 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1304 }; 1305 1306 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1307 rockchip,pins = 1308 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1309 }; 1310 1311 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1312 rockchip,pins = 1313 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1314 }; 1315 1316 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1317 rockchip,pins = 1318 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1319 }; 1320 1321 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1322 rockchip,pins = 1323 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1324 }; 1325 1326 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1327 rockchip,pins = 1328 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1329 }; 1330 }; 1331 1332 tsadc { 1333 otp_pin: otp-pin { 1334 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1335 }; 1336 1337 otp_out: otp-out { 1338 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1339 }; 1340 }; 1341 1342 uart0 { 1343 uart0_xfer: uart0-xfer { 1344 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1345 <1 RK_PB0 1 &pcfg_pull_up>; 1346 }; 1347 1348 uart0_cts: uart0-cts { 1349 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1350 }; 1351 1352 uart0_rts: uart0-rts { 1353 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1354 }; 1355 1356 uart0_rts_pin: uart0-rts-pin { 1357 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1358 }; 1359 }; 1360 1361 uart1 { 1362 uart1_xfer: uart1-xfer { 1363 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, 1364 <3 RK_PA6 4 &pcfg_pull_up>; 1365 }; 1366 1367 uart1_cts: uart1-cts { 1368 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1369 }; 1370 1371 uart1_rts: uart1-rts { 1372 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1373 }; 1374 1375 uart1_rts_pin: uart1-rts-pin { 1376 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1377 }; 1378 }; 1379 1380 uart2-0 { 1381 uart2m0_xfer: uart2m0-xfer { 1382 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, 1383 <1 RK_PA1 2 &pcfg_pull_up>; 1384 }; 1385 }; 1386 1387 uart2-1 { 1388 uart2m1_xfer: uart2m1-xfer { 1389 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 1390 <2 RK_PA1 1 &pcfg_pull_up>; 1391 }; 1392 }; 1393 1394 spi0-0 { 1395 spi0m0_clk: spi0m0-clk { 1396 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1397 }; 1398 1399 spi0m0_cs0: spi0m0-cs0 { 1400 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1401 }; 1402 1403 spi0m0_tx: spi0m0-tx { 1404 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1405 }; 1406 1407 spi0m0_rx: spi0m0-rx { 1408 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1409 }; 1410 1411 spi0m0_cs1: spi0m0-cs1 { 1412 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1413 }; 1414 }; 1415 1416 spi0-1 { 1417 spi0m1_clk: spi0m1-clk { 1418 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1419 }; 1420 1421 spi0m1_cs0: spi0m1-cs0 { 1422 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1423 }; 1424 1425 spi0m1_tx: spi0m1-tx { 1426 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1427 }; 1428 1429 spi0m1_rx: spi0m1-rx { 1430 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1431 }; 1432 1433 spi0m1_cs1: spi0m1-cs1 { 1434 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1435 }; 1436 }; 1437 1438 spi0-2 { 1439 spi0m2_clk: spi0m2-clk { 1440 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1441 }; 1442 1443 spi0m2_cs0: spi0m2-cs0 { 1444 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1445 }; 1446 1447 spi0m2_tx: spi0m2-tx { 1448 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1449 }; 1450 1451 spi0m2_rx: spi0m2-rx { 1452 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1453 }; 1454 }; 1455 1456 i2s1 { 1457 i2s1_mclk: i2s1-mclk { 1458 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1459 }; 1460 1461 i2s1_sclk: i2s1-sclk { 1462 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1463 }; 1464 1465 i2s1_lrckrx: i2s1-lrckrx { 1466 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1467 }; 1468 1469 i2s1_lrcktx: i2s1-lrcktx { 1470 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1471 }; 1472 1473 i2s1_sdi: i2s1-sdi { 1474 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1475 }; 1476 1477 i2s1_sdo: i2s1-sdo { 1478 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1479 }; 1480 1481 i2s1_sdio1: i2s1-sdio1 { 1482 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1483 }; 1484 1485 i2s1_sdio2: i2s1-sdio2 { 1486 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1487 }; 1488 1489 i2s1_sdio3: i2s1-sdio3 { 1490 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1491 }; 1492 1493 i2s1_sleep: i2s1-sleep { 1494 rockchip,pins = 1495 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1496 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1497 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1498 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1499 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1500 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1501 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1502 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1503 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1504 }; 1505 }; 1506 1507 i2s2-0 { 1508 i2s2m0_mclk: i2s2m0-mclk { 1509 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1510 }; 1511 1512 i2s2m0_sclk: i2s2m0-sclk { 1513 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1514 }; 1515 1516 i2s2m0_lrckrx: i2s2m0-lrckrx { 1517 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1518 }; 1519 1520 i2s2m0_lrcktx: i2s2m0-lrcktx { 1521 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1522 }; 1523 1524 i2s2m0_sdi: i2s2m0-sdi { 1525 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1526 }; 1527 1528 i2s2m0_sdo: i2s2m0-sdo { 1529 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1530 }; 1531 1532 i2s2m0_sleep: i2s2m0-sleep { 1533 rockchip,pins = 1534 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1535 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1536 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1537 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1538 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1539 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1540 }; 1541 }; 1542 1543 i2s2-1 { 1544 i2s2m1_mclk: i2s2m1-mclk { 1545 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1546 }; 1547 1548 i2s2m1_sclk: i2s2m1-sclk { 1549 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1550 }; 1551 1552 i2s2m1_lrckrx: i2sm1-lrckrx { 1553 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1554 }; 1555 1556 i2s2m1_lrcktx: i2s2m1-lrcktx { 1557 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1558 }; 1559 1560 i2s2m1_sdi: i2s2m1-sdi { 1561 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1562 }; 1563 1564 i2s2m1_sdo: i2s2m1-sdo { 1565 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1566 }; 1567 1568 i2s2m1_sleep: i2s2m1-sleep { 1569 rockchip,pins = 1570 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1571 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1572 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1573 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1574 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1575 }; 1576 }; 1577 1578 spdif-0 { 1579 spdifm0_tx: spdifm0-tx { 1580 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1581 }; 1582 }; 1583 1584 spdif-1 { 1585 spdifm1_tx: spdifm1-tx { 1586 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1587 }; 1588 }; 1589 1590 spdif-2 { 1591 spdifm2_tx: spdifm2-tx { 1592 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1593 }; 1594 }; 1595 1596 sdmmc0-0 { 1597 sdmmc0m0_pwren: sdmmc0m0-pwren { 1598 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1599 }; 1600 1601 sdmmc0m0_pin: sdmmc0m0-pin { 1602 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1603 }; 1604 }; 1605 1606 sdmmc0-1 { 1607 sdmmc0m1_pwren: sdmmc0m1-pwren { 1608 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1609 }; 1610 1611 sdmmc0m1_pin: sdmmc0m1-pin { 1612 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1613 }; 1614 }; 1615 1616 sdmmc0 { 1617 sdmmc0_clk: sdmmc0-clk { 1618 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1619 }; 1620 1621 sdmmc0_cmd: sdmmc0-cmd { 1622 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1623 }; 1624 1625 sdmmc0_dectn: sdmmc0-dectn { 1626 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1627 }; 1628 1629 sdmmc0_wrprt: sdmmc0-wrprt { 1630 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1631 }; 1632 1633 sdmmc0_bus1: sdmmc0-bus1 { 1634 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1635 }; 1636 1637 sdmmc0_bus4: sdmmc0-bus4 { 1638 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1639 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1640 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1641 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1642 }; 1643 1644 sdmmc0_pins: sdmmc0-pins { 1645 rockchip,pins = 1646 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1647 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1648 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1649 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1650 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1651 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1652 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1653 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1654 }; 1655 }; 1656 1657 sdmmc0ext { 1658 sdmmc0ext_clk: sdmmc0ext-clk { 1659 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1660 }; 1661 1662 sdmmc0ext_cmd: sdmmc0ext-cmd { 1663 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1664 }; 1665 1666 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1667 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1668 }; 1669 1670 sdmmc0ext_dectn: sdmmc0ext-dectn { 1671 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1672 }; 1673 1674 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1675 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1676 }; 1677 1678 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1679 rockchip,pins = 1680 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1681 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1682 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1683 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1684 }; 1685 1686 sdmmc0ext_pins: sdmmc0ext-pins { 1687 rockchip,pins = 1688 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1689 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1690 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1691 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1692 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1693 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1694 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1695 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1696 }; 1697 }; 1698 1699 sdmmc1 { 1700 sdmmc1_clk: sdmmc1-clk { 1701 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1702 }; 1703 1704 sdmmc1_cmd: sdmmc1-cmd { 1705 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1706 }; 1707 1708 sdmmc1_pwren: sdmmc1-pwren { 1709 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1710 }; 1711 1712 sdmmc1_wrprt: sdmmc1-wrprt { 1713 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1714 }; 1715 1716 sdmmc1_dectn: sdmmc1-dectn { 1717 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1718 }; 1719 1720 sdmmc1_bus1: sdmmc1-bus1 { 1721 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1722 }; 1723 1724 sdmmc1_bus4: sdmmc1-bus4 { 1725 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1726 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1727 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1728 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1729 }; 1730 1731 sdmmc1_pins: sdmmc1-pins { 1732 rockchip,pins = 1733 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1734 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1735 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1736 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1737 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1738 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1739 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1740 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1741 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1742 }; 1743 }; 1744 1745 emmc { 1746 emmc_clk: emmc-clk { 1747 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1748 }; 1749 1750 emmc_cmd: emmc-cmd { 1751 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1752 }; 1753 1754 emmc_pwren: emmc-pwren { 1755 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1756 }; 1757 1758 emmc_rstnout: emmc-rstnout { 1759 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1760 }; 1761 1762 emmc_bus1: emmc-bus1 { 1763 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1764 }; 1765 1766 emmc_bus4: emmc-bus4 { 1767 rockchip,pins = 1768 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1769 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1770 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1771 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1772 }; 1773 1774 emmc_bus8: emmc-bus8 { 1775 rockchip,pins = 1776 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1777 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1778 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1779 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1780 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1781 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1782 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1783 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1784 }; 1785 }; 1786 1787 pwm0 { 1788 pwm0_pin: pwm0-pin { 1789 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1790 }; 1791 }; 1792 1793 pwm1 { 1794 pwm1_pin: pwm1-pin { 1795 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1796 }; 1797 }; 1798 1799 pwm2 { 1800 pwm2_pin: pwm2-pin { 1801 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1802 }; 1803 }; 1804 1805 pwmir { 1806 pwmir_pin: pwmir-pin { 1807 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1808 }; 1809 }; 1810 1811 gmac-1 { 1812 rgmiim1_pins: rgmiim1-pins { 1813 rockchip,pins = 1814 /* mac_txclk */ 1815 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1816 /* mac_rxclk */ 1817 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1818 /* mac_mdio */ 1819 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1820 /* mac_txen */ 1821 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1822 /* mac_clk */ 1823 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1824 /* mac_rxdv */ 1825 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1826 /* mac_mdc */ 1827 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1828 /* mac_rxd1 */ 1829 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1830 /* mac_rxd0 */ 1831 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1832 /* mac_txd1 */ 1833 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1834 /* mac_txd0 */ 1835 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1836 /* mac_rxd3 */ 1837 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1838 /* mac_rxd2 */ 1839 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1840 /* mac_txd3 */ 1841 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1842 /* mac_txd2 */ 1843 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1844 1845 /* mac_txclk */ 1846 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1847 /* mac_txen */ 1848 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1849 /* mac_clk */ 1850 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1851 /* mac_txd1 */ 1852 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1853 /* mac_txd0 */ 1854 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1855 /* mac_txd3 */ 1856 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1857 /* mac_txd2 */ 1858 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1859 }; 1860 1861 rmiim1_pins: rmiim1-pins { 1862 rockchip,pins = 1863 /* mac_mdio */ 1864 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1865 /* mac_txen */ 1866 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1867 /* mac_clk */ 1868 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1869 /* mac_rxer */ 1870 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1871 /* mac_rxdv */ 1872 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1873 /* mac_mdc */ 1874 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1875 /* mac_rxd1 */ 1876 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1877 /* mac_rxd0 */ 1878 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1879 /* mac_txd1 */ 1880 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1881 /* mac_txd0 */ 1882 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1883 1884 /* mac_mdio */ 1885 <0 RK_PB3 1 &pcfg_pull_none>, 1886 /* mac_txen */ 1887 <0 RK_PB4 1 &pcfg_pull_none>, 1888 /* mac_clk */ 1889 <0 RK_PD0 1 &pcfg_pull_none>, 1890 /* mac_mdc */ 1891 <0 RK_PC3 1 &pcfg_pull_none>, 1892 /* mac_txd1 */ 1893 <0 RK_PC0 1 &pcfg_pull_none>, 1894 /* mac_txd0 */ 1895 <0 RK_PC1 1 &pcfg_pull_none>; 1896 }; 1897 }; 1898 1899 gmac2phy { 1900 fephyled_speed10: fephyled-speed10 { 1901 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1902 }; 1903 1904 fephyled_duplex: fephyled-duplex { 1905 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1906 }; 1907 1908 fephyled_rxm1: fephyled-rxm1 { 1909 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1910 }; 1911 1912 fephyled_txm1: fephyled-txm1 { 1913 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1914 }; 1915 1916 fephyled_linkm1: fephyled-linkm1 { 1917 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1918 }; 1919 }; 1920 1921 tsadc_pin { 1922 tsadc_int: tsadc-int { 1923 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1924 }; 1925 tsadc_pin: tsadc-pin { 1926 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1927 }; 1928 }; 1929 1930 hdmi_pin { 1931 hdmi_cec: hdmi-cec { 1932 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1933 }; 1934 1935 hdmi_hpd: hdmi-hpd { 1936 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1937 }; 1938 }; 1939 1940 cif-0 { 1941 dvp_d2d9_m0:dvp-d2d9-m0 { 1942 rockchip,pins = 1943 /* cif_d0 */ 1944 <3 RK_PA4 2 &pcfg_pull_none>, 1945 /* cif_d1 */ 1946 <3 RK_PA5 2 &pcfg_pull_none>, 1947 /* cif_d2 */ 1948 <3 RK_PA6 2 &pcfg_pull_none>, 1949 /* cif_d3 */ 1950 <3 RK_PA7 2 &pcfg_pull_none>, 1951 /* cif_d4 */ 1952 <3 RK_PB0 2 &pcfg_pull_none>, 1953 /* cif_d5m0 */ 1954 <3 RK_PB1 2 &pcfg_pull_none>, 1955 /* cif_d6m0 */ 1956 <3 RK_PB2 2 &pcfg_pull_none>, 1957 /* cif_d7m0 */ 1958 <3 RK_PB3 2 &pcfg_pull_none>, 1959 /* cif_href */ 1960 <3 RK_PA1 2 &pcfg_pull_none>, 1961 /* cif_vsync */ 1962 <3 RK_PA0 2 &pcfg_pull_none>, 1963 /* cif_clkoutm0 */ 1964 <3 RK_PA3 2 &pcfg_pull_none>, 1965 /* cif_clkin */ 1966 <3 RK_PA2 2 &pcfg_pull_none>; 1967 }; 1968 }; 1969 1970 cif-1 { 1971 dvp_d2d9_m1:dvp-d2d9-m1 { 1972 rockchip,pins = 1973 /* cif_d0 */ 1974 <3 RK_PA4 2 &pcfg_pull_none>, 1975 /* cif_d1 */ 1976 <3 RK_PA5 2 &pcfg_pull_none>, 1977 /* cif_d2 */ 1978 <3 RK_PA6 2 &pcfg_pull_none>, 1979 /* cif_d3 */ 1980 <3 RK_PA7 2 &pcfg_pull_none>, 1981 /* cif_d4 */ 1982 <3 RK_PB0 2 &pcfg_pull_none>, 1983 /* cif_d5m1 */ 1984 <2 RK_PC0 4 &pcfg_pull_none>, 1985 /* cif_d6m1 */ 1986 <2 RK_PC1 4 &pcfg_pull_none>, 1987 /* cif_d7m1 */ 1988 <2 RK_PC2 4 &pcfg_pull_none>, 1989 /* cif_href */ 1990 <3 RK_PA1 2 &pcfg_pull_none>, 1991 /* cif_vsync */ 1992 <3 RK_PA0 2 &pcfg_pull_none>, 1993 /* cif_clkoutm1 */ 1994 <2 RK_PB7 4 &pcfg_pull_none>, 1995 /* cif_clkin */ 1996 <3 RK_PA2 2 &pcfg_pull_none>; 1997 }; 1998 }; 1999 }; 2000}; 2001