1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 i2c0 = &i2c0; 31 i2c1 = &i2c1; 32 i2c2 = &i2c2; 33 i2c3 = &i2c3; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 reg = <0x0 0x0>; 44 clocks = <&cru ARMCLK>; 45 #cooling-cells = <2>; 46 cpu-idle-states = <&CPU_SLEEP>; 47 dynamic-power-coefficient = <120>; 48 enable-method = "psci"; 49 operating-points-v2 = <&cpu0_opp_table>; 50 i-cache-size = <0x8000>; 51 i-cache-line-size = <64>; 52 i-cache-sets = <256>; 53 d-cache-size = <0x8000>; 54 d-cache-line-size = <64>; 55 d-cache-sets = <128>; 56 next-level-cache = <&l2_cache>; 57 }; 58 59 cpu1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0 0x1>; 63 clocks = <&cru ARMCLK>; 64 #cooling-cells = <2>; 65 cpu-idle-states = <&CPU_SLEEP>; 66 dynamic-power-coefficient = <120>; 67 enable-method = "psci"; 68 operating-points-v2 = <&cpu0_opp_table>; 69 i-cache-size = <0x8000>; 70 i-cache-line-size = <64>; 71 i-cache-sets = <256>; 72 d-cache-size = <0x8000>; 73 d-cache-line-size = <64>; 74 d-cache-sets = <128>; 75 next-level-cache = <&l2_cache>; 76 }; 77 78 cpu2: cpu@2 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x2>; 82 clocks = <&cru ARMCLK>; 83 #cooling-cells = <2>; 84 cpu-idle-states = <&CPU_SLEEP>; 85 dynamic-power-coefficient = <120>; 86 enable-method = "psci"; 87 operating-points-v2 = <&cpu0_opp_table>; 88 i-cache-size = <0x8000>; 89 i-cache-line-size = <64>; 90 i-cache-sets = <256>; 91 d-cache-size = <0x8000>; 92 d-cache-line-size = <64>; 93 d-cache-sets = <128>; 94 next-level-cache = <&l2_cache>; 95 }; 96 97 cpu3: cpu@3 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53"; 100 reg = <0x0 0x3>; 101 clocks = <&cru ARMCLK>; 102 #cooling-cells = <2>; 103 cpu-idle-states = <&CPU_SLEEP>; 104 dynamic-power-coefficient = <120>; 105 enable-method = "psci"; 106 operating-points-v2 = <&cpu0_opp_table>; 107 i-cache-size = <0x8000>; 108 i-cache-line-size = <64>; 109 i-cache-sets = <256>; 110 d-cache-size = <0x8000>; 111 d-cache-line-size = <64>; 112 d-cache-sets = <128>; 113 next-level-cache = <&l2_cache>; 114 }; 115 116 idle-states { 117 entry-method = "psci"; 118 119 CPU_SLEEP: cpu-sleep { 120 compatible = "arm,idle-state"; 121 local-timer-stop; 122 arm,psci-suspend-param = <0x0010000>; 123 entry-latency-us = <120>; 124 exit-latency-us = <250>; 125 min-residency-us = <900>; 126 }; 127 }; 128 129 l2_cache: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 cache-size = <0x40000>; 134 cache-line-size = <64>; 135 cache-sets = <256>; 136 }; 137 }; 138 139 cpu0_opp_table: opp-table-0 { 140 compatible = "operating-points-v2"; 141 opp-shared; 142 143 opp-408000000 { 144 opp-hz = /bits/ 64 <408000000>; 145 opp-microvolt = <950000>; 146 clock-latency-ns = <40000>; 147 opp-suspend; 148 }; 149 opp-600000000 { 150 opp-hz = /bits/ 64 <600000000>; 151 opp-microvolt = <950000>; 152 clock-latency-ns = <40000>; 153 }; 154 opp-816000000 { 155 opp-hz = /bits/ 64 <816000000>; 156 opp-microvolt = <1000000>; 157 clock-latency-ns = <40000>; 158 }; 159 opp-1008000000 { 160 opp-hz = /bits/ 64 <1008000000>; 161 opp-microvolt = <1100000>; 162 clock-latency-ns = <40000>; 163 }; 164 opp-1200000000 { 165 opp-hz = /bits/ 64 <1200000000>; 166 opp-microvolt = <1225000>; 167 clock-latency-ns = <40000>; 168 }; 169 opp-1296000000 { 170 opp-hz = /bits/ 64 <1296000000>; 171 opp-microvolt = <1300000>; 172 clock-latency-ns = <40000>; 173 }; 174 }; 175 176 analog_sound: analog-sound { 177 compatible = "simple-audio-card"; 178 simple-audio-card,format = "i2s"; 179 simple-audio-card,mclk-fs = <256>; 180 simple-audio-card,name = "Analog"; 181 status = "disabled"; 182 183 simple-audio-card,cpu { 184 sound-dai = <&i2s1>; 185 }; 186 187 simple-audio-card,codec { 188 sound-dai = <&codec>; 189 }; 190 }; 191 192 arm-pmu { 193 compatible = "arm,cortex-a53-pmu"; 194 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 198 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 199 }; 200 201 display_subsystem: display-subsystem { 202 compatible = "rockchip,display-subsystem"; 203 ports = <&vop_out>; 204 }; 205 206 hdmi_sound: hdmi-sound { 207 compatible = "simple-audio-card"; 208 simple-audio-card,format = "i2s"; 209 simple-audio-card,mclk-fs = <128>; 210 simple-audio-card,name = "HDMI"; 211 status = "disabled"; 212 213 simple-audio-card,cpu { 214 sound-dai = <&i2s0>; 215 }; 216 217 simple-audio-card,codec { 218 sound-dai = <&hdmi>; 219 }; 220 }; 221 222 psci { 223 compatible = "arm,psci-1.0", "arm,psci-0.2"; 224 method = "smc"; 225 }; 226 227 timer { 228 compatible = "arm,armv8-timer"; 229 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 230 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 231 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 232 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 233 }; 234 235 xin24m: xin24m { 236 compatible = "fixed-clock"; 237 #clock-cells = <0>; 238 clock-frequency = <24000000>; 239 clock-output-names = "xin24m"; 240 }; 241 242 i2s0: i2s@ff000000 { 243 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 244 reg = <0x0 0xff000000 0x0 0x1000>; 245 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 247 clock-names = "i2s_clk", "i2s_hclk"; 248 dmas = <&dmac 11>, <&dmac 12>; 249 dma-names = "tx", "rx"; 250 #sound-dai-cells = <0>; 251 status = "disabled"; 252 }; 253 254 i2s1: i2s@ff010000 { 255 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 256 reg = <0x0 0xff010000 0x0 0x1000>; 257 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 259 clock-names = "i2s_clk", "i2s_hclk"; 260 dmas = <&dmac 14>, <&dmac 15>; 261 dma-names = "tx", "rx"; 262 #sound-dai-cells = <0>; 263 status = "disabled"; 264 }; 265 266 i2s2: i2s@ff020000 { 267 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 268 reg = <0x0 0xff020000 0x0 0x1000>; 269 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 271 clock-names = "i2s_clk", "i2s_hclk"; 272 dmas = <&dmac 0>, <&dmac 1>; 273 dma-names = "tx", "rx"; 274 #sound-dai-cells = <0>; 275 status = "disabled"; 276 }; 277 278 spdif: spdif@ff030000 { 279 compatible = "rockchip,rk3328-spdif"; 280 reg = <0x0 0xff030000 0x0 0x1000>; 281 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 283 clock-names = "mclk", "hclk"; 284 dmas = <&dmac 10>; 285 dma-names = "tx"; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&spdifm2_tx>; 288 #sound-dai-cells = <0>; 289 status = "disabled"; 290 }; 291 292 pdm: pdm@ff040000 { 293 compatible = "rockchip,pdm"; 294 reg = <0x0 0xff040000 0x0 0x1000>; 295 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 296 clock-names = "pdm_clk", "pdm_hclk"; 297 dmas = <&dmac 16>; 298 dma-names = "rx"; 299 pinctrl-names = "default", "sleep"; 300 pinctrl-0 = <&pdmm0_clk 301 &pdmm0_sdi0 302 &pdmm0_sdi1 303 &pdmm0_sdi2 304 &pdmm0_sdi3>; 305 pinctrl-1 = <&pdmm0_clk_sleep 306 &pdmm0_sdi0_sleep 307 &pdmm0_sdi1_sleep 308 &pdmm0_sdi2_sleep 309 &pdmm0_sdi3_sleep>; 310 status = "disabled"; 311 }; 312 313 grf: syscon@ff100000 { 314 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 315 reg = <0x0 0xff100000 0x0 0x1000>; 316 317 io_domains: io-domains { 318 compatible = "rockchip,rk3328-io-voltage-domain"; 319 status = "disabled"; 320 }; 321 322 grf_gpio: gpio { 323 compatible = "rockchip,rk3328-grf-gpio"; 324 gpio-controller; 325 #gpio-cells = <2>; 326 }; 327 328 power: power-controller { 329 compatible = "rockchip,rk3328-power-controller"; 330 #power-domain-cells = <1>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 334 power-domain@RK3328_PD_HEVC { 335 reg = <RK3328_PD_HEVC>; 336 clocks = <&cru SCLK_VENC_CORE>; 337 #power-domain-cells = <0>; 338 }; 339 power-domain@RK3328_PD_VIDEO { 340 reg = <RK3328_PD_VIDEO>; 341 clocks = <&cru ACLK_RKVDEC>, 342 <&cru HCLK_RKVDEC>, 343 <&cru SCLK_VDEC_CABAC>, 344 <&cru SCLK_VDEC_CORE>; 345 #power-domain-cells = <0>; 346 }; 347 power-domain@RK3328_PD_VPU { 348 reg = <RK3328_PD_VPU>; 349 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 350 #power-domain-cells = <0>; 351 }; 352 }; 353 354 reboot-mode { 355 compatible = "syscon-reboot-mode"; 356 offset = <0x5c8>; 357 mode-normal = <BOOT_NORMAL>; 358 mode-recovery = <BOOT_RECOVERY>; 359 mode-bootloader = <BOOT_FASTBOOT>; 360 mode-loader = <BOOT_BL_DOWNLOAD>; 361 }; 362 }; 363 364 uart0: serial@ff110000 { 365 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 366 reg = <0x0 0xff110000 0x0 0x100>; 367 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 369 clock-names = "baudclk", "apb_pclk"; 370 dmas = <&dmac 2>, <&dmac 3>; 371 dma-names = "tx", "rx"; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 374 reg-io-width = <4>; 375 reg-shift = <2>; 376 status = "disabled"; 377 }; 378 379 uart1: serial@ff120000 { 380 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 381 reg = <0x0 0xff120000 0x0 0x100>; 382 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 384 clock-names = "baudclk", "apb_pclk"; 385 dmas = <&dmac 4>, <&dmac 5>; 386 dma-names = "tx", "rx"; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 389 reg-io-width = <4>; 390 reg-shift = <2>; 391 status = "disabled"; 392 }; 393 394 uart2: serial@ff130000 { 395 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 396 reg = <0x0 0xff130000 0x0 0x100>; 397 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 399 clock-names = "baudclk", "apb_pclk"; 400 dmas = <&dmac 6>, <&dmac 7>; 401 dma-names = "tx", "rx"; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&uart2m1_xfer>; 404 reg-io-width = <4>; 405 reg-shift = <2>; 406 status = "disabled"; 407 }; 408 409 i2c0: i2c@ff150000 { 410 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 411 reg = <0x0 0xff150000 0x0 0x1000>; 412 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 416 clock-names = "i2c", "pclk"; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&i2c0_xfer>; 419 status = "disabled"; 420 }; 421 422 i2c1: i2c@ff160000 { 423 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 424 reg = <0x0 0xff160000 0x0 0x1000>; 425 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 429 clock-names = "i2c", "pclk"; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&i2c1_xfer>; 432 status = "disabled"; 433 }; 434 435 i2c2: i2c@ff170000 { 436 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 437 reg = <0x0 0xff170000 0x0 0x1000>; 438 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 442 clock-names = "i2c", "pclk"; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&i2c2_xfer>; 445 status = "disabled"; 446 }; 447 448 i2c3: i2c@ff180000 { 449 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 450 reg = <0x0 0xff180000 0x0 0x1000>; 451 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 455 clock-names = "i2c", "pclk"; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&i2c3_xfer>; 458 status = "disabled"; 459 }; 460 461 spi0: spi@ff190000 { 462 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 463 reg = <0x0 0xff190000 0x0 0x1000>; 464 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 468 clock-names = "spiclk", "apb_pclk"; 469 dmas = <&dmac 8>, <&dmac 9>; 470 dma-names = "tx", "rx"; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 473 status = "disabled"; 474 }; 475 476 wdt: watchdog@ff1a0000 { 477 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; 478 reg = <0x0 0xff1a0000 0x0 0x100>; 479 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&cru PCLK_WDT>; 481 }; 482 483 pwm0: pwm@ff1b0000 { 484 compatible = "rockchip,rk3328-pwm"; 485 reg = <0x0 0xff1b0000 0x0 0x10>; 486 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 487 clock-names = "pwm", "pclk"; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&pwm0_pin>; 490 #pwm-cells = <3>; 491 status = "disabled"; 492 }; 493 494 pwm1: pwm@ff1b0010 { 495 compatible = "rockchip,rk3328-pwm"; 496 reg = <0x0 0xff1b0010 0x0 0x10>; 497 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 498 clock-names = "pwm", "pclk"; 499 pinctrl-names = "default"; 500 pinctrl-0 = <&pwm1_pin>; 501 #pwm-cells = <3>; 502 status = "disabled"; 503 }; 504 505 pwm2: pwm@ff1b0020 { 506 compatible = "rockchip,rk3328-pwm"; 507 reg = <0x0 0xff1b0020 0x0 0x10>; 508 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 509 clock-names = "pwm", "pclk"; 510 pinctrl-names = "default"; 511 pinctrl-0 = <&pwm2_pin>; 512 #pwm-cells = <3>; 513 status = "disabled"; 514 }; 515 516 pwm3: pwm@ff1b0030 { 517 compatible = "rockchip,rk3328-pwm"; 518 reg = <0x0 0xff1b0030 0x0 0x10>; 519 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 520 clock-names = "pwm", "pclk"; 521 pinctrl-names = "default"; 522 pinctrl-0 = <&pwmir_pin>; 523 #pwm-cells = <3>; 524 status = "disabled"; 525 }; 526 527 dmac: dma-controller@ff1f0000 { 528 compatible = "arm,pl330", "arm,primecell"; 529 reg = <0x0 0xff1f0000 0x0 0x4000>; 530 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 532 arm,pl330-periph-burst; 533 clocks = <&cru ACLK_DMAC>; 534 clock-names = "apb_pclk"; 535 #dma-cells = <1>; 536 }; 537 538 thermal-zones { 539 soc_thermal: soc-thermal { 540 polling-delay-passive = <20>; 541 polling-delay = <1000>; 542 sustainable-power = <1000>; 543 544 thermal-sensors = <&tsadc 0>; 545 546 trips { 547 threshold: trip-point0 { 548 temperature = <70000>; 549 hysteresis = <2000>; 550 type = "passive"; 551 }; 552 target: trip-point1 { 553 temperature = <85000>; 554 hysteresis = <2000>; 555 type = "passive"; 556 }; 557 soc_crit: soc-crit { 558 temperature = <95000>; 559 hysteresis = <2000>; 560 type = "critical"; 561 }; 562 }; 563 564 cooling-maps { 565 map0 { 566 trip = <&target>; 567 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 568 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 569 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 570 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 571 contribution = <4096>; 572 }; 573 }; 574 }; 575 576 }; 577 578 tsadc: tsadc@ff250000 { 579 compatible = "rockchip,rk3328-tsadc"; 580 reg = <0x0 0xff250000 0x0 0x100>; 581 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 582 assigned-clocks = <&cru SCLK_TSADC>; 583 assigned-clock-rates = <50000>; 584 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 585 clock-names = "tsadc", "apb_pclk"; 586 pinctrl-names = "init", "default", "sleep"; 587 pinctrl-0 = <&otp_pin>; 588 pinctrl-1 = <&otp_out>; 589 pinctrl-2 = <&otp_pin>; 590 resets = <&cru SRST_TSADC>; 591 reset-names = "tsadc-apb"; 592 rockchip,grf = <&grf>; 593 rockchip,hw-tshut-temp = <100000>; 594 #thermal-sensor-cells = <1>; 595 status = "disabled"; 596 }; 597 598 efuse: efuse@ff260000 { 599 compatible = "rockchip,rk3328-efuse"; 600 reg = <0x0 0xff260000 0x0 0x50>; 601 #address-cells = <1>; 602 #size-cells = <1>; 603 clocks = <&cru SCLK_EFUSE>; 604 clock-names = "pclk_efuse"; 605 rockchip,efuse-size = <0x20>; 606 607 /* Data cells */ 608 efuse_id: id@7 { 609 reg = <0x07 0x10>; 610 }; 611 cpu_leakage: cpu-leakage@17 { 612 reg = <0x17 0x1>; 613 }; 614 logic_leakage: logic-leakage@19 { 615 reg = <0x19 0x1>; 616 }; 617 efuse_cpu_version: cpu-version@1a { 618 reg = <0x1a 0x1>; 619 bits = <3 3>; 620 }; 621 }; 622 623 saradc: adc@ff280000 { 624 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 625 reg = <0x0 0xff280000 0x0 0x100>; 626 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 627 #io-channel-cells = <1>; 628 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 629 clock-names = "saradc", "apb_pclk"; 630 resets = <&cru SRST_SARADC_P>; 631 reset-names = "saradc-apb"; 632 status = "disabled"; 633 }; 634 635 gpu: gpu@ff300000 { 636 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 637 reg = <0x0 0xff300000 0x0 0x30000>; 638 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 645 interrupt-names = "gp", 646 "gpmmu", 647 "pp", 648 "pp0", 649 "ppmmu0", 650 "pp1", 651 "ppmmu1"; 652 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 653 clock-names = "bus", "core"; 654 resets = <&cru SRST_GPU_A>; 655 }; 656 657 h265e_mmu: iommu@ff330200 { 658 compatible = "rockchip,iommu"; 659 reg = <0x0 0xff330200 0 0x100>; 660 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 662 clock-names = "aclk", "iface"; 663 #iommu-cells = <0>; 664 status = "disabled"; 665 }; 666 667 vepu_mmu: iommu@ff340800 { 668 compatible = "rockchip,iommu"; 669 reg = <0x0 0xff340800 0x0 0x40>; 670 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 672 clock-names = "aclk", "iface"; 673 #iommu-cells = <0>; 674 status = "disabled"; 675 }; 676 677 vpu: video-codec@ff350000 { 678 compatible = "rockchip,rk3328-vpu"; 679 reg = <0x0 0xff350000 0x0 0x800>; 680 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 681 interrupt-names = "vdpu"; 682 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 683 clock-names = "aclk", "hclk"; 684 iommus = <&vpu_mmu>; 685 power-domains = <&power RK3328_PD_VPU>; 686 }; 687 688 vpu_mmu: iommu@ff350800 { 689 compatible = "rockchip,iommu"; 690 reg = <0x0 0xff350800 0x0 0x40>; 691 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 693 clock-names = "aclk", "iface"; 694 #iommu-cells = <0>; 695 power-domains = <&power RK3328_PD_VPU>; 696 }; 697 698 vdec: video-codec@ff360000 { 699 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; 700 reg = <0x0 0xff360000 0x0 0x480>; 701 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, 703 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; 704 clock-names = "axi", "ahb", "cabac", "core"; 705 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, 706 <&cru SCLK_VDEC_CORE>; 707 assigned-clock-rates = <400000000>, <400000000>, <300000000>; 708 iommus = <&vdec_mmu>; 709 power-domains = <&power RK3328_PD_VIDEO>; 710 }; 711 712 vdec_mmu: iommu@ff360480 { 713 compatible = "rockchip,iommu"; 714 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 715 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 717 clock-names = "aclk", "iface"; 718 #iommu-cells = <0>; 719 power-domains = <&power RK3328_PD_VIDEO>; 720 }; 721 722 vop: vop@ff370000 { 723 compatible = "rockchip,rk3328-vop"; 724 reg = <0x0 0xff370000 0x0 0x3efc>; 725 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 727 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 728 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 729 reset-names = "axi", "ahb", "dclk"; 730 iommus = <&vop_mmu>; 731 status = "disabled"; 732 733 vop_out: port { 734 #address-cells = <1>; 735 #size-cells = <0>; 736 737 vop_out_hdmi: endpoint@0 { 738 reg = <0>; 739 remote-endpoint = <&hdmi_in_vop>; 740 }; 741 }; 742 }; 743 744 vop_mmu: iommu@ff373f00 { 745 compatible = "rockchip,iommu"; 746 reg = <0x0 0xff373f00 0x0 0x100>; 747 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 749 clock-names = "aclk", "iface"; 750 #iommu-cells = <0>; 751 status = "disabled"; 752 }; 753 754 hdmi: hdmi@ff3c0000 { 755 compatible = "rockchip,rk3328-dw-hdmi"; 756 reg = <0x0 0xff3c0000 0x0 0x20000>; 757 reg-io-width = <4>; 758 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&cru PCLK_HDMI>, 760 <&cru SCLK_HDMI_SFC>, 761 <&cru SCLK_RTC32K>; 762 clock-names = "iahb", 763 "isfr", 764 "cec"; 765 phys = <&hdmiphy>; 766 phy-names = "hdmi"; 767 pinctrl-names = "default"; 768 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 769 rockchip,grf = <&grf>; 770 #sound-dai-cells = <0>; 771 status = "disabled"; 772 773 ports { 774 #address-cells = <1>; 775 #size-cells = <0>; 776 777 hdmi_in: port@0 { 778 reg = <0>; 779 780 hdmi_in_vop: endpoint { 781 remote-endpoint = <&vop_out_hdmi>; 782 }; 783 }; 784 785 hdmi_out: port@1 { 786 reg = <1>; 787 }; 788 }; 789 }; 790 791 codec: codec@ff410000 { 792 compatible = "rockchip,rk3328-codec"; 793 reg = <0x0 0xff410000 0x0 0x1000>; 794 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 795 clock-names = "pclk", "mclk"; 796 rockchip,grf = <&grf>; 797 #sound-dai-cells = <0>; 798 status = "disabled"; 799 }; 800 801 hdmiphy: phy@ff430000 { 802 compatible = "rockchip,rk3328-hdmi-phy"; 803 reg = <0x0 0xff430000 0x0 0x10000>; 804 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 806 clock-names = "sysclk", "refoclk", "refpclk"; 807 clock-output-names = "hdmi_phy"; 808 #clock-cells = <0>; 809 nvmem-cells = <&efuse_cpu_version>; 810 nvmem-cell-names = "cpu-version"; 811 #phy-cells = <0>; 812 status = "disabled"; 813 }; 814 815 cru: clock-controller@ff440000 { 816 compatible = "rockchip,rk3328-cru"; 817 reg = <0x0 0xff440000 0x0 0x1000>; 818 clocks = <&xin24m>; 819 clock-names = "xin24m"; 820 rockchip,grf = <&grf>; 821 #clock-cells = <1>; 822 #reset-cells = <1>; 823 assigned-clocks = 824 /* 825 * CPLL should run at 1200, but that is to high for 826 * the initial dividers of most of its children. 827 * We need set cpll child clk div first, 828 * and then set the cpll frequency. 829 */ 830 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 831 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 832 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 833 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 834 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 835 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 836 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 837 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 838 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 839 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 840 <&cru SCLK_WIFI>, <&cru ARMCLK>, 841 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 842 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 843 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 844 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 845 <&cru SCLK_RTC32K>; 846 assigned-clock-parents = 847 <&cru HDMIPHY>, <&cru PLL_APLL>, 848 <&cru PLL_GPLL>, <&xin24m>, 849 <&xin24m>, <&xin24m>; 850 assigned-clock-rates = 851 <0>, <61440000>, 852 <0>, <24000000>, 853 <24000000>, <24000000>, 854 <15000000>, <15000000>, 855 <300000000>, <100000000>, 856 <400000000>, <100000000>, 857 <50000000>, <100000000>, 858 <100000000>, <100000000>, 859 <50000000>, <50000000>, 860 <50000000>, <50000000>, 861 <24000000>, <600000000>, 862 <491520000>, <1200000000>, 863 <150000000>, <75000000>, 864 <75000000>, <150000000>, 865 <75000000>, <75000000>, 866 <32768>; 867 }; 868 869 usb2phy_grf: syscon@ff450000 { 870 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 871 "simple-mfd"; 872 reg = <0x0 0xff450000 0x0 0x10000>; 873 #address-cells = <1>; 874 #size-cells = <1>; 875 876 u2phy: usb2phy@100 { 877 compatible = "rockchip,rk3328-usb2phy"; 878 reg = <0x100 0x10>; 879 clocks = <&xin24m>; 880 clock-names = "phyclk"; 881 clock-output-names = "usb480m_phy"; 882 #clock-cells = <0>; 883 assigned-clocks = <&cru USB480M>; 884 assigned-clock-parents = <&u2phy>; 885 status = "disabled"; 886 887 u2phy_otg: otg-port { 888 #phy-cells = <0>; 889 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 892 interrupt-names = "otg-bvalid", "otg-id", 893 "linestate"; 894 status = "disabled"; 895 }; 896 897 u2phy_host: host-port { 898 #phy-cells = <0>; 899 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 900 interrupt-names = "linestate"; 901 status = "disabled"; 902 }; 903 }; 904 }; 905 906 sdmmc: mmc@ff500000 { 907 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 908 reg = <0x0 0xff500000 0x0 0x4000>; 909 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 910 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 911 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 912 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 913 fifo-depth = <0x100>; 914 max-frequency = <150000000>; 915 resets = <&cru SRST_MMC0>; 916 reset-names = "reset"; 917 status = "disabled"; 918 }; 919 920 sdio: mmc@ff510000 { 921 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 922 reg = <0x0 0xff510000 0x0 0x4000>; 923 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 925 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 926 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 927 fifo-depth = <0x100>; 928 max-frequency = <150000000>; 929 resets = <&cru SRST_SDIO>; 930 reset-names = "reset"; 931 status = "disabled"; 932 }; 933 934 emmc: mmc@ff520000 { 935 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 936 reg = <0x0 0xff520000 0x0 0x4000>; 937 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 939 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 940 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 941 fifo-depth = <0x100>; 942 max-frequency = <150000000>; 943 resets = <&cru SRST_EMMC>; 944 reset-names = "reset"; 945 status = "disabled"; 946 }; 947 948 gmac2io: ethernet@ff540000 { 949 compatible = "rockchip,rk3328-gmac"; 950 reg = <0x0 0xff540000 0x0 0x10000>; 951 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 952 interrupt-names = "macirq"; 953 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 954 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 955 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 956 <&cru PCLK_MAC2IO>; 957 clock-names = "stmmaceth", "mac_clk_rx", 958 "mac_clk_tx", "clk_mac_ref", 959 "clk_mac_refout", "aclk_mac", 960 "pclk_mac"; 961 resets = <&cru SRST_GMAC2IO_A>; 962 reset-names = "stmmaceth"; 963 rockchip,grf = <&grf>; 964 tx-fifo-depth = <2048>; 965 rx-fifo-depth = <4096>; 966 snps,txpbl = <0x4>; 967 status = "disabled"; 968 }; 969 970 gmac2phy: ethernet@ff550000 { 971 compatible = "rockchip,rk3328-gmac"; 972 reg = <0x0 0xff550000 0x0 0x10000>; 973 rockchip,grf = <&grf>; 974 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 975 interrupt-names = "macirq"; 976 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 977 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 978 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 979 <&cru SCLK_MAC2PHY_OUT>; 980 clock-names = "stmmaceth", "mac_clk_rx", 981 "mac_clk_tx", "clk_mac_ref", 982 "aclk_mac", "pclk_mac", 983 "clk_macphy"; 984 resets = <&cru SRST_GMAC2PHY_A>; 985 reset-names = "stmmaceth"; 986 phy-mode = "rmii"; 987 phy-handle = <&phy>; 988 tx-fifo-depth = <2048>; 989 rx-fifo-depth = <4096>; 990 snps,txpbl = <0x4>; 991 clock_in_out = "output"; 992 status = "disabled"; 993 994 mdio { 995 compatible = "snps,dwmac-mdio"; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 999 phy: ethernet-phy@0 { 1000 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 1001 reg = <0>; 1002 clocks = <&cru SCLK_MAC2PHY_OUT>; 1003 resets = <&cru SRST_MACPHY>; 1004 pinctrl-names = "default"; 1005 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 1006 phy-is-integrated; 1007 }; 1008 }; 1009 }; 1010 1011 usb20_otg: usb@ff580000 { 1012 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 1013 "snps,dwc2"; 1014 reg = <0x0 0xff580000 0x0 0x40000>; 1015 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&cru HCLK_OTG>; 1017 clock-names = "otg"; 1018 dr_mode = "otg"; 1019 g-np-tx-fifo-size = <16>; 1020 g-rx-fifo-size = <280>; 1021 g-tx-fifo-size = <256 128 128 64 32 16>; 1022 phys = <&u2phy_otg>; 1023 phy-names = "usb2-phy"; 1024 status = "disabled"; 1025 }; 1026 1027 usb_host0_ehci: usb@ff5c0000 { 1028 compatible = "generic-ehci"; 1029 reg = <0x0 0xff5c0000 0x0 0x10000>; 1030 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&cru HCLK_HOST0>, <&u2phy>; 1032 phys = <&u2phy_host>; 1033 phy-names = "usb"; 1034 status = "disabled"; 1035 }; 1036 1037 usb_host0_ohci: usb@ff5d0000 { 1038 compatible = "generic-ohci"; 1039 reg = <0x0 0xff5d0000 0x0 0x10000>; 1040 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&cru HCLK_HOST0>, <&u2phy>; 1042 phys = <&u2phy_host>; 1043 phy-names = "usb"; 1044 status = "disabled"; 1045 }; 1046 1047 sdmmc_ext: mmc@ff5f0000 { 1048 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 1049 reg = <0x0 0xff5f0000 0x0 0x4000>; 1050 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, 1052 <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; 1053 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1054 fifo-depth = <0x100>; 1055 max-frequency = <150000000>; 1056 resets = <&cru SRST_SDMMCEXT>; 1057 reset-names = "reset"; 1058 status = "disabled"; 1059 }; 1060 1061 usbdrd3: usb@ff600000 { 1062 compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; 1063 reg = <0x0 0xff600000 0x0 0x100000>; 1064 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 1066 <&cru ACLK_USB3OTG>; 1067 clock-names = "ref_clk", "suspend_clk", 1068 "bus_clk"; 1069 dr_mode = "otg"; 1070 phy_type = "utmi_wide"; 1071 snps,dis-del-phy-power-chg-quirk; 1072 snps,dis_enblslpm_quirk; 1073 snps,dis-tx-ipgap-linecheck-quirk; 1074 snps,dis-u2-freeclk-exists-quirk; 1075 snps,dis_u2_susphy_quirk; 1076 snps,dis_u3_susphy_quirk; 1077 status = "disabled"; 1078 }; 1079 1080 gic: interrupt-controller@ff811000 { 1081 compatible = "arm,gic-400"; 1082 #interrupt-cells = <3>; 1083 #address-cells = <0>; 1084 interrupt-controller; 1085 reg = <0x0 0xff811000 0 0x1000>, 1086 <0x0 0xff812000 0 0x2000>, 1087 <0x0 0xff814000 0 0x2000>, 1088 <0x0 0xff816000 0 0x2000>; 1089 interrupts = <GIC_PPI 9 1090 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1091 }; 1092 1093 crypto: crypto@ff060000 { 1094 compatible = "rockchip,rk3328-crypto"; 1095 reg = <0x0 0xff060000 0x0 0x4000>; 1096 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1097 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>, 1098 <&cru SCLK_CRYPTO>; 1099 clock-names = "hclk_master", "hclk_slave", "sclk"; 1100 resets = <&cru SRST_CRYPTO>; 1101 reset-names = "crypto-rst"; 1102 }; 1103 1104 pinctrl: pinctrl { 1105 compatible = "rockchip,rk3328-pinctrl"; 1106 rockchip,grf = <&grf>; 1107 #address-cells = <2>; 1108 #size-cells = <2>; 1109 ranges; 1110 1111 gpio0: gpio@ff210000 { 1112 compatible = "rockchip,gpio-bank"; 1113 reg = <0x0 0xff210000 0x0 0x100>; 1114 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1115 clocks = <&cru PCLK_GPIO0>; 1116 1117 gpio-controller; 1118 #gpio-cells = <2>; 1119 1120 interrupt-controller; 1121 #interrupt-cells = <2>; 1122 }; 1123 1124 gpio1: gpio@ff220000 { 1125 compatible = "rockchip,gpio-bank"; 1126 reg = <0x0 0xff220000 0x0 0x100>; 1127 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1128 clocks = <&cru PCLK_GPIO1>; 1129 1130 gpio-controller; 1131 #gpio-cells = <2>; 1132 1133 interrupt-controller; 1134 #interrupt-cells = <2>; 1135 }; 1136 1137 gpio2: gpio@ff230000 { 1138 compatible = "rockchip,gpio-bank"; 1139 reg = <0x0 0xff230000 0x0 0x100>; 1140 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1141 clocks = <&cru PCLK_GPIO2>; 1142 1143 gpio-controller; 1144 #gpio-cells = <2>; 1145 1146 interrupt-controller; 1147 #interrupt-cells = <2>; 1148 }; 1149 1150 gpio3: gpio@ff240000 { 1151 compatible = "rockchip,gpio-bank"; 1152 reg = <0x0 0xff240000 0x0 0x100>; 1153 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1154 clocks = <&cru PCLK_GPIO3>; 1155 1156 gpio-controller; 1157 #gpio-cells = <2>; 1158 1159 interrupt-controller; 1160 #interrupt-cells = <2>; 1161 }; 1162 1163 pcfg_pull_up: pcfg-pull-up { 1164 bias-pull-up; 1165 }; 1166 1167 pcfg_pull_down: pcfg-pull-down { 1168 bias-pull-down; 1169 }; 1170 1171 pcfg_pull_none: pcfg-pull-none { 1172 bias-disable; 1173 }; 1174 1175 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1176 bias-disable; 1177 drive-strength = <2>; 1178 }; 1179 1180 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1181 bias-pull-up; 1182 drive-strength = <2>; 1183 }; 1184 1185 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1186 bias-pull-up; 1187 drive-strength = <4>; 1188 }; 1189 1190 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1191 bias-disable; 1192 drive-strength = <4>; 1193 }; 1194 1195 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1196 bias-pull-down; 1197 drive-strength = <4>; 1198 }; 1199 1200 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1201 bias-disable; 1202 drive-strength = <8>; 1203 }; 1204 1205 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1206 bias-pull-up; 1207 drive-strength = <8>; 1208 }; 1209 1210 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1211 bias-disable; 1212 drive-strength = <12>; 1213 }; 1214 1215 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1216 bias-pull-up; 1217 drive-strength = <12>; 1218 }; 1219 1220 pcfg_output_high: pcfg-output-high { 1221 output-high; 1222 }; 1223 1224 pcfg_output_low: pcfg-output-low { 1225 output-low; 1226 }; 1227 1228 pcfg_input_high: pcfg-input-high { 1229 bias-pull-up; 1230 input-enable; 1231 }; 1232 1233 pcfg_input: pcfg-input { 1234 input-enable; 1235 }; 1236 1237 i2c0 { 1238 i2c0_xfer: i2c0-xfer { 1239 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1240 <2 RK_PD1 1 &pcfg_pull_none>; 1241 }; 1242 }; 1243 1244 i2c1 { 1245 i2c1_xfer: i2c1-xfer { 1246 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1247 <2 RK_PA5 2 &pcfg_pull_none>; 1248 }; 1249 }; 1250 1251 i2c2 { 1252 i2c2_xfer: i2c2-xfer { 1253 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1254 <2 RK_PB6 1 &pcfg_pull_none>; 1255 }; 1256 }; 1257 1258 i2c3 { 1259 i2c3_xfer: i2c3-xfer { 1260 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1261 <0 RK_PA6 2 &pcfg_pull_none>; 1262 }; 1263 i2c3_pins: i2c3-pins { 1264 rockchip,pins = 1265 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1266 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1267 }; 1268 }; 1269 1270 hdmi_i2c { 1271 hdmii2c_xfer: hdmii2c-xfer { 1272 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1273 <0 RK_PA6 1 &pcfg_pull_none>; 1274 }; 1275 }; 1276 1277 pdm-0 { 1278 pdmm0_clk: pdmm0-clk { 1279 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1280 }; 1281 1282 pdmm0_fsync: pdmm0-fsync { 1283 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1284 }; 1285 1286 pdmm0_sdi0: pdmm0-sdi0 { 1287 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1288 }; 1289 1290 pdmm0_sdi1: pdmm0-sdi1 { 1291 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1292 }; 1293 1294 pdmm0_sdi2: pdmm0-sdi2 { 1295 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1296 }; 1297 1298 pdmm0_sdi3: pdmm0-sdi3 { 1299 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1300 }; 1301 1302 pdmm0_clk_sleep: pdmm0-clk-sleep { 1303 rockchip,pins = 1304 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1305 }; 1306 1307 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1308 rockchip,pins = 1309 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1310 }; 1311 1312 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1313 rockchip,pins = 1314 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1315 }; 1316 1317 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1318 rockchip,pins = 1319 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1320 }; 1321 1322 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1323 rockchip,pins = 1324 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1325 }; 1326 1327 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1328 rockchip,pins = 1329 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1330 }; 1331 }; 1332 1333 tsadc { 1334 otp_pin: otp-pin { 1335 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1336 }; 1337 1338 otp_out: otp-out { 1339 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1340 }; 1341 }; 1342 1343 uart0 { 1344 uart0_xfer: uart0-xfer { 1345 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1346 <1 RK_PB0 1 &pcfg_pull_up>; 1347 }; 1348 1349 uart0_cts: uart0-cts { 1350 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1351 }; 1352 1353 uart0_rts: uart0-rts { 1354 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1355 }; 1356 1357 uart0_rts_pin: uart0-rts-pin { 1358 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1359 }; 1360 }; 1361 1362 uart1 { 1363 uart1_xfer: uart1-xfer { 1364 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, 1365 <3 RK_PA6 4 &pcfg_pull_up>; 1366 }; 1367 1368 uart1_cts: uart1-cts { 1369 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1370 }; 1371 1372 uart1_rts: uart1-rts { 1373 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1374 }; 1375 1376 uart1_rts_pin: uart1-rts-pin { 1377 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1378 }; 1379 }; 1380 1381 uart2-0 { 1382 uart2m0_xfer: uart2m0-xfer { 1383 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, 1384 <1 RK_PA1 2 &pcfg_pull_up>; 1385 }; 1386 }; 1387 1388 uart2-1 { 1389 uart2m1_xfer: uart2m1-xfer { 1390 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 1391 <2 RK_PA1 1 &pcfg_pull_up>; 1392 }; 1393 }; 1394 1395 spi0-0 { 1396 spi0m0_clk: spi0m0-clk { 1397 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1398 }; 1399 1400 spi0m0_cs0: spi0m0-cs0 { 1401 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1402 }; 1403 1404 spi0m0_tx: spi0m0-tx { 1405 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1406 }; 1407 1408 spi0m0_rx: spi0m0-rx { 1409 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1410 }; 1411 1412 spi0m0_cs1: spi0m0-cs1 { 1413 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1414 }; 1415 }; 1416 1417 spi0-1 { 1418 spi0m1_clk: spi0m1-clk { 1419 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1420 }; 1421 1422 spi0m1_cs0: spi0m1-cs0 { 1423 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1424 }; 1425 1426 spi0m1_tx: spi0m1-tx { 1427 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1428 }; 1429 1430 spi0m1_rx: spi0m1-rx { 1431 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1432 }; 1433 1434 spi0m1_cs1: spi0m1-cs1 { 1435 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1436 }; 1437 }; 1438 1439 spi0-2 { 1440 spi0m2_clk: spi0m2-clk { 1441 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1442 }; 1443 1444 spi0m2_cs0: spi0m2-cs0 { 1445 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1446 }; 1447 1448 spi0m2_tx: spi0m2-tx { 1449 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1450 }; 1451 1452 spi0m2_rx: spi0m2-rx { 1453 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1454 }; 1455 }; 1456 1457 i2s1 { 1458 i2s1_mclk: i2s1-mclk { 1459 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1460 }; 1461 1462 i2s1_sclk: i2s1-sclk { 1463 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1464 }; 1465 1466 i2s1_lrckrx: i2s1-lrckrx { 1467 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1468 }; 1469 1470 i2s1_lrcktx: i2s1-lrcktx { 1471 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1472 }; 1473 1474 i2s1_sdi: i2s1-sdi { 1475 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1476 }; 1477 1478 i2s1_sdo: i2s1-sdo { 1479 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1480 }; 1481 1482 i2s1_sdio1: i2s1-sdio1 { 1483 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1484 }; 1485 1486 i2s1_sdio2: i2s1-sdio2 { 1487 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1488 }; 1489 1490 i2s1_sdio3: i2s1-sdio3 { 1491 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1492 }; 1493 1494 i2s1_sleep: i2s1-sleep { 1495 rockchip,pins = 1496 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1497 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1498 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1499 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1500 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1501 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1502 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1503 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1504 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1505 }; 1506 }; 1507 1508 i2s2-0 { 1509 i2s2m0_mclk: i2s2m0-mclk { 1510 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1511 }; 1512 1513 i2s2m0_sclk: i2s2m0-sclk { 1514 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1515 }; 1516 1517 i2s2m0_lrckrx: i2s2m0-lrckrx { 1518 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1519 }; 1520 1521 i2s2m0_lrcktx: i2s2m0-lrcktx { 1522 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1523 }; 1524 1525 i2s2m0_sdi: i2s2m0-sdi { 1526 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1527 }; 1528 1529 i2s2m0_sdo: i2s2m0-sdo { 1530 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1531 }; 1532 1533 i2s2m0_sleep: i2s2m0-sleep { 1534 rockchip,pins = 1535 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1536 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1537 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1538 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1539 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1540 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1541 }; 1542 }; 1543 1544 i2s2-1 { 1545 i2s2m1_mclk: i2s2m1-mclk { 1546 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1547 }; 1548 1549 i2s2m1_sclk: i2s2m1-sclk { 1550 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1551 }; 1552 1553 i2s2m1_lrckrx: i2sm1-lrckrx { 1554 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1555 }; 1556 1557 i2s2m1_lrcktx: i2s2m1-lrcktx { 1558 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1559 }; 1560 1561 i2s2m1_sdi: i2s2m1-sdi { 1562 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1563 }; 1564 1565 i2s2m1_sdo: i2s2m1-sdo { 1566 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1567 }; 1568 1569 i2s2m1_sleep: i2s2m1-sleep { 1570 rockchip,pins = 1571 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1572 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1573 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1574 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1575 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1576 }; 1577 }; 1578 1579 spdif-0 { 1580 spdifm0_tx: spdifm0-tx { 1581 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1582 }; 1583 }; 1584 1585 spdif-1 { 1586 spdifm1_tx: spdifm1-tx { 1587 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1588 }; 1589 }; 1590 1591 spdif-2 { 1592 spdifm2_tx: spdifm2-tx { 1593 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1594 }; 1595 }; 1596 1597 sdmmc0-0 { 1598 sdmmc0m0_pwren: sdmmc0m0-pwren { 1599 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1600 }; 1601 1602 sdmmc0m0_pin: sdmmc0m0-pin { 1603 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1604 }; 1605 }; 1606 1607 sdmmc0-1 { 1608 sdmmc0m1_pwren: sdmmc0m1-pwren { 1609 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1610 }; 1611 1612 sdmmc0m1_pin: sdmmc0m1-pin { 1613 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1614 }; 1615 }; 1616 1617 sdmmc0 { 1618 sdmmc0_clk: sdmmc0-clk { 1619 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1620 }; 1621 1622 sdmmc0_cmd: sdmmc0-cmd { 1623 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1624 }; 1625 1626 sdmmc0_dectn: sdmmc0-dectn { 1627 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1628 }; 1629 1630 sdmmc0_wrprt: sdmmc0-wrprt { 1631 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1632 }; 1633 1634 sdmmc0_bus1: sdmmc0-bus1 { 1635 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1636 }; 1637 1638 sdmmc0_bus4: sdmmc0-bus4 { 1639 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1640 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1641 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1642 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1643 }; 1644 1645 sdmmc0_pins: sdmmc0-pins { 1646 rockchip,pins = 1647 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1648 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1649 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1650 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1651 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1652 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1653 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1654 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1655 }; 1656 }; 1657 1658 sdmmc0ext { 1659 sdmmc0ext_clk: sdmmc0ext-clk { 1660 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1661 }; 1662 1663 sdmmc0ext_cmd: sdmmc0ext-cmd { 1664 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1665 }; 1666 1667 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1668 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1669 }; 1670 1671 sdmmc0ext_dectn: sdmmc0ext-dectn { 1672 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1673 }; 1674 1675 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1676 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1677 }; 1678 1679 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1680 rockchip,pins = 1681 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1682 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1683 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1684 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1685 }; 1686 1687 sdmmc0ext_pins: sdmmc0ext-pins { 1688 rockchip,pins = 1689 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1690 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1691 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1692 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1693 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1694 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1695 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1696 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1697 }; 1698 }; 1699 1700 sdmmc1 { 1701 sdmmc1_clk: sdmmc1-clk { 1702 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1703 }; 1704 1705 sdmmc1_cmd: sdmmc1-cmd { 1706 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1707 }; 1708 1709 sdmmc1_pwren: sdmmc1-pwren { 1710 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1711 }; 1712 1713 sdmmc1_wrprt: sdmmc1-wrprt { 1714 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1715 }; 1716 1717 sdmmc1_dectn: sdmmc1-dectn { 1718 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1719 }; 1720 1721 sdmmc1_bus1: sdmmc1-bus1 { 1722 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1723 }; 1724 1725 sdmmc1_bus4: sdmmc1-bus4 { 1726 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1727 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1728 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1729 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1730 }; 1731 1732 sdmmc1_pins: sdmmc1-pins { 1733 rockchip,pins = 1734 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1735 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1736 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1737 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1738 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1739 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1740 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1741 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1742 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1743 }; 1744 }; 1745 1746 emmc { 1747 emmc_clk: emmc-clk { 1748 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1749 }; 1750 1751 emmc_cmd: emmc-cmd { 1752 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1753 }; 1754 1755 emmc_pwren: emmc-pwren { 1756 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1757 }; 1758 1759 emmc_rstnout: emmc-rstnout { 1760 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1761 }; 1762 1763 emmc_bus1: emmc-bus1 { 1764 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1765 }; 1766 1767 emmc_bus4: emmc-bus4 { 1768 rockchip,pins = 1769 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1770 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1771 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1772 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1773 }; 1774 1775 emmc_bus8: emmc-bus8 { 1776 rockchip,pins = 1777 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1778 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1779 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1780 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1781 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1782 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1783 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1784 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1785 }; 1786 }; 1787 1788 pwm0 { 1789 pwm0_pin: pwm0-pin { 1790 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1791 }; 1792 }; 1793 1794 pwm1 { 1795 pwm1_pin: pwm1-pin { 1796 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1797 }; 1798 }; 1799 1800 pwm2 { 1801 pwm2_pin: pwm2-pin { 1802 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1803 }; 1804 }; 1805 1806 pwmir { 1807 pwmir_pin: pwmir-pin { 1808 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1809 }; 1810 }; 1811 1812 gmac-1 { 1813 rgmiim1_pins: rgmiim1-pins { 1814 rockchip,pins = 1815 /* mac_txclk */ 1816 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1817 /* mac_rxclk */ 1818 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1819 /* mac_mdio */ 1820 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1821 /* mac_txen */ 1822 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1823 /* mac_clk */ 1824 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1825 /* mac_rxdv */ 1826 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1827 /* mac_mdc */ 1828 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1829 /* mac_rxd1 */ 1830 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1831 /* mac_rxd0 */ 1832 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1833 /* mac_txd1 */ 1834 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1835 /* mac_txd0 */ 1836 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1837 /* mac_rxd3 */ 1838 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1839 /* mac_rxd2 */ 1840 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1841 /* mac_txd3 */ 1842 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1843 /* mac_txd2 */ 1844 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1845 1846 /* mac_txclk */ 1847 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1848 /* mac_txen */ 1849 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1850 /* mac_clk */ 1851 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1852 /* mac_txd1 */ 1853 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1854 /* mac_txd0 */ 1855 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1856 /* mac_txd3 */ 1857 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1858 /* mac_txd2 */ 1859 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1860 }; 1861 1862 rmiim1_pins: rmiim1-pins { 1863 rockchip,pins = 1864 /* mac_mdio */ 1865 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1866 /* mac_txen */ 1867 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1868 /* mac_clk */ 1869 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1870 /* mac_rxer */ 1871 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1872 /* mac_rxdv */ 1873 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1874 /* mac_mdc */ 1875 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1876 /* mac_rxd1 */ 1877 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1878 /* mac_rxd0 */ 1879 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1880 /* mac_txd1 */ 1881 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1882 /* mac_txd0 */ 1883 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1884 1885 /* mac_mdio */ 1886 <0 RK_PB3 1 &pcfg_pull_none>, 1887 /* mac_txen */ 1888 <0 RK_PB4 1 &pcfg_pull_none>, 1889 /* mac_clk */ 1890 <0 RK_PD0 1 &pcfg_pull_none>, 1891 /* mac_mdc */ 1892 <0 RK_PC3 1 &pcfg_pull_none>, 1893 /* mac_txd1 */ 1894 <0 RK_PC0 1 &pcfg_pull_none>, 1895 /* mac_txd0 */ 1896 <0 RK_PC1 1 &pcfg_pull_none>; 1897 }; 1898 }; 1899 1900 gmac2phy { 1901 fephyled_speed10: fephyled-speed10 { 1902 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1903 }; 1904 1905 fephyled_duplex: fephyled-duplex { 1906 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1907 }; 1908 1909 fephyled_rxm1: fephyled-rxm1 { 1910 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1911 }; 1912 1913 fephyled_txm1: fephyled-txm1 { 1914 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1915 }; 1916 1917 fephyled_linkm1: fephyled-linkm1 { 1918 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1919 }; 1920 }; 1921 1922 tsadc_pin { 1923 tsadc_int: tsadc-int { 1924 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1925 }; 1926 tsadc_pin: tsadc-pin { 1927 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1928 }; 1929 }; 1930 1931 hdmi_pin { 1932 hdmi_cec: hdmi-cec { 1933 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1934 }; 1935 1936 hdmi_hpd: hdmi-hpd { 1937 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1938 }; 1939 }; 1940 1941 cif-0 { 1942 dvp_d2d9_m0:dvp-d2d9-m0 { 1943 rockchip,pins = 1944 /* cif_d0 */ 1945 <3 RK_PA4 2 &pcfg_pull_none>, 1946 /* cif_d1 */ 1947 <3 RK_PA5 2 &pcfg_pull_none>, 1948 /* cif_d2 */ 1949 <3 RK_PA6 2 &pcfg_pull_none>, 1950 /* cif_d3 */ 1951 <3 RK_PA7 2 &pcfg_pull_none>, 1952 /* cif_d4 */ 1953 <3 RK_PB0 2 &pcfg_pull_none>, 1954 /* cif_d5m0 */ 1955 <3 RK_PB1 2 &pcfg_pull_none>, 1956 /* cif_d6m0 */ 1957 <3 RK_PB2 2 &pcfg_pull_none>, 1958 /* cif_d7m0 */ 1959 <3 RK_PB3 2 &pcfg_pull_none>, 1960 /* cif_href */ 1961 <3 RK_PA1 2 &pcfg_pull_none>, 1962 /* cif_vsync */ 1963 <3 RK_PA0 2 &pcfg_pull_none>, 1964 /* cif_clkoutm0 */ 1965 <3 RK_PA3 2 &pcfg_pull_none>, 1966 /* cif_clkin */ 1967 <3 RK_PA2 2 &pcfg_pull_none>; 1968 }; 1969 }; 1970 1971 cif-1 { 1972 dvp_d2d9_m1:dvp-d2d9-m1 { 1973 rockchip,pins = 1974 /* cif_d0 */ 1975 <3 RK_PA4 2 &pcfg_pull_none>, 1976 /* cif_d1 */ 1977 <3 RK_PA5 2 &pcfg_pull_none>, 1978 /* cif_d2 */ 1979 <3 RK_PA6 2 &pcfg_pull_none>, 1980 /* cif_d3 */ 1981 <3 RK_PA7 2 &pcfg_pull_none>, 1982 /* cif_d4 */ 1983 <3 RK_PB0 2 &pcfg_pull_none>, 1984 /* cif_d5m1 */ 1985 <2 RK_PC0 4 &pcfg_pull_none>, 1986 /* cif_d6m1 */ 1987 <2 RK_PC1 4 &pcfg_pull_none>, 1988 /* cif_d7m1 */ 1989 <2 RK_PC2 4 &pcfg_pull_none>, 1990 /* cif_href */ 1991 <3 RK_PA1 2 &pcfg_pull_none>, 1992 /* cif_vsync */ 1993 <3 RK_PA0 2 &pcfg_pull_none>, 1994 /* cif_clkoutm1 */ 1995 <2 RK_PB7 4 &pcfg_pull_none>, 1996 /* cif_clkin */ 1997 <3 RK_PA2 2 &pcfg_pull_none>; 1998 }; 1999 }; 2000 }; 2001}; 2002