1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 i2c0 = &i2c0; 31 i2c1 = &i2c1; 32 i2c2 = &i2c2; 33 i2c3 = &i2c3; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 reg = <0x0 0x0>; 44 clocks = <&cru ARMCLK>; 45 #cooling-cells = <2>; 46 cpu-idle-states = <&CPU_SLEEP>; 47 dynamic-power-coefficient = <120>; 48 enable-method = "psci"; 49 next-level-cache = <&l2>; 50 operating-points-v2 = <&cpu0_opp_table>; 51 }; 52 53 cpu1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x0 0x1>; 57 clocks = <&cru ARMCLK>; 58 #cooling-cells = <2>; 59 cpu-idle-states = <&CPU_SLEEP>; 60 dynamic-power-coefficient = <120>; 61 enable-method = "psci"; 62 next-level-cache = <&l2>; 63 operating-points-v2 = <&cpu0_opp_table>; 64 }; 65 66 cpu2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a53"; 69 reg = <0x0 0x2>; 70 clocks = <&cru ARMCLK>; 71 #cooling-cells = <2>; 72 cpu-idle-states = <&CPU_SLEEP>; 73 dynamic-power-coefficient = <120>; 74 enable-method = "psci"; 75 next-level-cache = <&l2>; 76 operating-points-v2 = <&cpu0_opp_table>; 77 }; 78 79 cpu3: cpu@3 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53"; 82 reg = <0x0 0x3>; 83 clocks = <&cru ARMCLK>; 84 #cooling-cells = <2>; 85 cpu-idle-states = <&CPU_SLEEP>; 86 dynamic-power-coefficient = <120>; 87 enable-method = "psci"; 88 next-level-cache = <&l2>; 89 operating-points-v2 = <&cpu0_opp_table>; 90 }; 91 92 idle-states { 93 entry-method = "psci"; 94 95 CPU_SLEEP: cpu-sleep { 96 compatible = "arm,idle-state"; 97 local-timer-stop; 98 arm,psci-suspend-param = <0x0010000>; 99 entry-latency-us = <120>; 100 exit-latency-us = <250>; 101 min-residency-us = <900>; 102 }; 103 }; 104 105 l2: l2-cache0 { 106 compatible = "cache"; 107 cache-level = <2>; 108 cache-unified; 109 }; 110 }; 111 112 cpu0_opp_table: opp-table-0 { 113 compatible = "operating-points-v2"; 114 opp-shared; 115 116 opp-408000000 { 117 opp-hz = /bits/ 64 <408000000>; 118 opp-microvolt = <950000>; 119 clock-latency-ns = <40000>; 120 opp-suspend; 121 }; 122 opp-600000000 { 123 opp-hz = /bits/ 64 <600000000>; 124 opp-microvolt = <950000>; 125 clock-latency-ns = <40000>; 126 }; 127 opp-816000000 { 128 opp-hz = /bits/ 64 <816000000>; 129 opp-microvolt = <1000000>; 130 clock-latency-ns = <40000>; 131 }; 132 opp-1008000000 { 133 opp-hz = /bits/ 64 <1008000000>; 134 opp-microvolt = <1100000>; 135 clock-latency-ns = <40000>; 136 }; 137 opp-1200000000 { 138 opp-hz = /bits/ 64 <1200000000>; 139 opp-microvolt = <1225000>; 140 clock-latency-ns = <40000>; 141 }; 142 opp-1296000000 { 143 opp-hz = /bits/ 64 <1296000000>; 144 opp-microvolt = <1300000>; 145 clock-latency-ns = <40000>; 146 }; 147 }; 148 149 analog_sound: analog-sound { 150 compatible = "simple-audio-card"; 151 simple-audio-card,format = "i2s"; 152 simple-audio-card,mclk-fs = <256>; 153 simple-audio-card,name = "Analog"; 154 status = "disabled"; 155 156 simple-audio-card,cpu { 157 sound-dai = <&i2s1>; 158 }; 159 160 simple-audio-card,codec { 161 sound-dai = <&codec>; 162 }; 163 }; 164 165 arm-pmu { 166 compatible = "arm,cortex-a53-pmu"; 167 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 171 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 172 }; 173 174 display_subsystem: display-subsystem { 175 compatible = "rockchip,display-subsystem"; 176 ports = <&vop_out>; 177 }; 178 179 hdmi_sound: hdmi-sound { 180 compatible = "simple-audio-card"; 181 simple-audio-card,format = "i2s"; 182 simple-audio-card,mclk-fs = <128>; 183 simple-audio-card,name = "HDMI"; 184 status = "disabled"; 185 186 simple-audio-card,cpu { 187 sound-dai = <&i2s0>; 188 }; 189 190 simple-audio-card,codec { 191 sound-dai = <&hdmi>; 192 }; 193 }; 194 195 psci { 196 compatible = "arm,psci-1.0", "arm,psci-0.2"; 197 method = "smc"; 198 }; 199 200 timer { 201 compatible = "arm,armv8-timer"; 202 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 203 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 204 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 205 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 206 }; 207 208 xin24m: xin24m { 209 compatible = "fixed-clock"; 210 #clock-cells = <0>; 211 clock-frequency = <24000000>; 212 clock-output-names = "xin24m"; 213 }; 214 215 i2s0: i2s@ff000000 { 216 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 217 reg = <0x0 0xff000000 0x0 0x1000>; 218 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 220 clock-names = "i2s_clk", "i2s_hclk"; 221 dmas = <&dmac 11>, <&dmac 12>; 222 dma-names = "tx", "rx"; 223 #sound-dai-cells = <0>; 224 status = "disabled"; 225 }; 226 227 i2s1: i2s@ff010000 { 228 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 229 reg = <0x0 0xff010000 0x0 0x1000>; 230 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 232 clock-names = "i2s_clk", "i2s_hclk"; 233 dmas = <&dmac 14>, <&dmac 15>; 234 dma-names = "tx", "rx"; 235 #sound-dai-cells = <0>; 236 status = "disabled"; 237 }; 238 239 i2s2: i2s@ff020000 { 240 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 241 reg = <0x0 0xff020000 0x0 0x1000>; 242 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 244 clock-names = "i2s_clk", "i2s_hclk"; 245 dmas = <&dmac 0>, <&dmac 1>; 246 dma-names = "tx", "rx"; 247 #sound-dai-cells = <0>; 248 status = "disabled"; 249 }; 250 251 spdif: spdif@ff030000 { 252 compatible = "rockchip,rk3328-spdif"; 253 reg = <0x0 0xff030000 0x0 0x1000>; 254 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 256 clock-names = "mclk", "hclk"; 257 dmas = <&dmac 10>; 258 dma-names = "tx"; 259 pinctrl-names = "default"; 260 pinctrl-0 = <&spdifm2_tx>; 261 #sound-dai-cells = <0>; 262 status = "disabled"; 263 }; 264 265 pdm: pdm@ff040000 { 266 compatible = "rockchip,pdm"; 267 reg = <0x0 0xff040000 0x0 0x1000>; 268 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 269 clock-names = "pdm_clk", "pdm_hclk"; 270 dmas = <&dmac 16>; 271 dma-names = "rx"; 272 pinctrl-names = "default", "sleep"; 273 pinctrl-0 = <&pdmm0_clk 274 &pdmm0_sdi0 275 &pdmm0_sdi1 276 &pdmm0_sdi2 277 &pdmm0_sdi3>; 278 pinctrl-1 = <&pdmm0_clk_sleep 279 &pdmm0_sdi0_sleep 280 &pdmm0_sdi1_sleep 281 &pdmm0_sdi2_sleep 282 &pdmm0_sdi3_sleep>; 283 status = "disabled"; 284 }; 285 286 grf: syscon@ff100000 { 287 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 288 reg = <0x0 0xff100000 0x0 0x1000>; 289 290 io_domains: io-domains { 291 compatible = "rockchip,rk3328-io-voltage-domain"; 292 status = "disabled"; 293 }; 294 295 grf_gpio: gpio { 296 compatible = "rockchip,rk3328-grf-gpio"; 297 gpio-controller; 298 #gpio-cells = <2>; 299 }; 300 301 power: power-controller { 302 compatible = "rockchip,rk3328-power-controller"; 303 #power-domain-cells = <1>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 307 power-domain@RK3328_PD_HEVC { 308 reg = <RK3328_PD_HEVC>; 309 #power-domain-cells = <0>; 310 }; 311 power-domain@RK3328_PD_VIDEO { 312 reg = <RK3328_PD_VIDEO>; 313 clocks = <&cru ACLK_RKVDEC>, 314 <&cru HCLK_RKVDEC>, 315 <&cru SCLK_VDEC_CABAC>, 316 <&cru SCLK_VDEC_CORE>; 317 #power-domain-cells = <0>; 318 }; 319 power-domain@RK3328_PD_VPU { 320 reg = <RK3328_PD_VPU>; 321 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 322 #power-domain-cells = <0>; 323 }; 324 }; 325 326 reboot-mode { 327 compatible = "syscon-reboot-mode"; 328 offset = <0x5c8>; 329 mode-normal = <BOOT_NORMAL>; 330 mode-recovery = <BOOT_RECOVERY>; 331 mode-bootloader = <BOOT_FASTBOOT>; 332 mode-loader = <BOOT_BL_DOWNLOAD>; 333 }; 334 }; 335 336 uart0: serial@ff110000 { 337 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 338 reg = <0x0 0xff110000 0x0 0x100>; 339 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 341 clock-names = "baudclk", "apb_pclk"; 342 dmas = <&dmac 2>, <&dmac 3>; 343 dma-names = "tx", "rx"; 344 pinctrl-names = "default"; 345 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 346 reg-io-width = <4>; 347 reg-shift = <2>; 348 status = "disabled"; 349 }; 350 351 uart1: serial@ff120000 { 352 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 353 reg = <0x0 0xff120000 0x0 0x100>; 354 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 356 clock-names = "baudclk", "apb_pclk"; 357 dmas = <&dmac 4>, <&dmac 5>; 358 dma-names = "tx", "rx"; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 361 reg-io-width = <4>; 362 reg-shift = <2>; 363 status = "disabled"; 364 }; 365 366 uart2: serial@ff130000 { 367 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 368 reg = <0x0 0xff130000 0x0 0x100>; 369 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 371 clock-names = "baudclk", "apb_pclk"; 372 dmas = <&dmac 6>, <&dmac 7>; 373 dma-names = "tx", "rx"; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&uart2m1_xfer>; 376 reg-io-width = <4>; 377 reg-shift = <2>; 378 status = "disabled"; 379 }; 380 381 i2c0: i2c@ff150000 { 382 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 383 reg = <0x0 0xff150000 0x0 0x1000>; 384 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 388 clock-names = "i2c", "pclk"; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&i2c0_xfer>; 391 status = "disabled"; 392 }; 393 394 i2c1: i2c@ff160000 { 395 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 396 reg = <0x0 0xff160000 0x0 0x1000>; 397 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 401 clock-names = "i2c", "pclk"; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&i2c1_xfer>; 404 status = "disabled"; 405 }; 406 407 i2c2: i2c@ff170000 { 408 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 409 reg = <0x0 0xff170000 0x0 0x1000>; 410 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 414 clock-names = "i2c", "pclk"; 415 pinctrl-names = "default"; 416 pinctrl-0 = <&i2c2_xfer>; 417 status = "disabled"; 418 }; 419 420 i2c3: i2c@ff180000 { 421 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 422 reg = <0x0 0xff180000 0x0 0x1000>; 423 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 427 clock-names = "i2c", "pclk"; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&i2c3_xfer>; 430 status = "disabled"; 431 }; 432 433 spi0: spi@ff190000 { 434 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 435 reg = <0x0 0xff190000 0x0 0x1000>; 436 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 440 clock-names = "spiclk", "apb_pclk"; 441 dmas = <&dmac 8>, <&dmac 9>; 442 dma-names = "tx", "rx"; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 445 status = "disabled"; 446 }; 447 448 wdt: watchdog@ff1a0000 { 449 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; 450 reg = <0x0 0xff1a0000 0x0 0x100>; 451 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&cru PCLK_WDT>; 453 }; 454 455 pwm0: pwm@ff1b0000 { 456 compatible = "rockchip,rk3328-pwm"; 457 reg = <0x0 0xff1b0000 0x0 0x10>; 458 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 459 clock-names = "pwm", "pclk"; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&pwm0_pin>; 462 #pwm-cells = <3>; 463 status = "disabled"; 464 }; 465 466 pwm1: pwm@ff1b0010 { 467 compatible = "rockchip,rk3328-pwm"; 468 reg = <0x0 0xff1b0010 0x0 0x10>; 469 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 470 clock-names = "pwm", "pclk"; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&pwm1_pin>; 473 #pwm-cells = <3>; 474 status = "disabled"; 475 }; 476 477 pwm2: pwm@ff1b0020 { 478 compatible = "rockchip,rk3328-pwm"; 479 reg = <0x0 0xff1b0020 0x0 0x10>; 480 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 481 clock-names = "pwm", "pclk"; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&pwm2_pin>; 484 #pwm-cells = <3>; 485 status = "disabled"; 486 }; 487 488 pwm3: pwm@ff1b0030 { 489 compatible = "rockchip,rk3328-pwm"; 490 reg = <0x0 0xff1b0030 0x0 0x10>; 491 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 493 clock-names = "pwm", "pclk"; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&pwmir_pin>; 496 #pwm-cells = <3>; 497 status = "disabled"; 498 }; 499 500 dmac: dma-controller@ff1f0000 { 501 compatible = "arm,pl330", "arm,primecell"; 502 reg = <0x0 0xff1f0000 0x0 0x4000>; 503 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 505 arm,pl330-periph-burst; 506 clocks = <&cru ACLK_DMAC>; 507 clock-names = "apb_pclk"; 508 #dma-cells = <1>; 509 }; 510 511 thermal-zones { 512 soc_thermal: soc-thermal { 513 polling-delay-passive = <20>; 514 polling-delay = <1000>; 515 sustainable-power = <1000>; 516 517 thermal-sensors = <&tsadc 0>; 518 519 trips { 520 threshold: trip-point0 { 521 temperature = <70000>; 522 hysteresis = <2000>; 523 type = "passive"; 524 }; 525 target: trip-point1 { 526 temperature = <85000>; 527 hysteresis = <2000>; 528 type = "passive"; 529 }; 530 soc_crit: soc-crit { 531 temperature = <95000>; 532 hysteresis = <2000>; 533 type = "critical"; 534 }; 535 }; 536 537 cooling-maps { 538 map0 { 539 trip = <&target>; 540 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 541 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 542 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 543 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 544 contribution = <4096>; 545 }; 546 }; 547 }; 548 549 }; 550 551 tsadc: tsadc@ff250000 { 552 compatible = "rockchip,rk3328-tsadc"; 553 reg = <0x0 0xff250000 0x0 0x100>; 554 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 555 assigned-clocks = <&cru SCLK_TSADC>; 556 assigned-clock-rates = <50000>; 557 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 558 clock-names = "tsadc", "apb_pclk"; 559 pinctrl-names = "init", "default", "sleep"; 560 pinctrl-0 = <&otp_pin>; 561 pinctrl-1 = <&otp_out>; 562 pinctrl-2 = <&otp_pin>; 563 resets = <&cru SRST_TSADC>; 564 reset-names = "tsadc-apb"; 565 rockchip,grf = <&grf>; 566 rockchip,hw-tshut-temp = <100000>; 567 #thermal-sensor-cells = <1>; 568 status = "disabled"; 569 }; 570 571 efuse: efuse@ff260000 { 572 compatible = "rockchip,rk3328-efuse"; 573 reg = <0x0 0xff260000 0x0 0x50>; 574 #address-cells = <1>; 575 #size-cells = <1>; 576 clocks = <&cru SCLK_EFUSE>; 577 clock-names = "pclk_efuse"; 578 rockchip,efuse-size = <0x20>; 579 580 /* Data cells */ 581 efuse_id: id@7 { 582 reg = <0x07 0x10>; 583 }; 584 cpu_leakage: cpu-leakage@17 { 585 reg = <0x17 0x1>; 586 }; 587 logic_leakage: logic-leakage@19 { 588 reg = <0x19 0x1>; 589 }; 590 efuse_cpu_version: cpu-version@1a { 591 reg = <0x1a 0x1>; 592 bits = <3 3>; 593 }; 594 }; 595 596 saradc: adc@ff280000 { 597 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 598 reg = <0x0 0xff280000 0x0 0x100>; 599 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 600 #io-channel-cells = <1>; 601 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 602 clock-names = "saradc", "apb_pclk"; 603 resets = <&cru SRST_SARADC_P>; 604 reset-names = "saradc-apb"; 605 status = "disabled"; 606 }; 607 608 gpu: gpu@ff300000 { 609 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 610 reg = <0x0 0xff300000 0x0 0x30000>; 611 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 618 interrupt-names = "gp", 619 "gpmmu", 620 "pp", 621 "pp0", 622 "ppmmu0", 623 "pp1", 624 "ppmmu1"; 625 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 626 clock-names = "bus", "core"; 627 resets = <&cru SRST_GPU_A>; 628 }; 629 630 h265e_mmu: iommu@ff330200 { 631 compatible = "rockchip,iommu"; 632 reg = <0x0 0xff330200 0 0x100>; 633 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 635 clock-names = "aclk", "iface"; 636 #iommu-cells = <0>; 637 status = "disabled"; 638 }; 639 640 vepu_mmu: iommu@ff340800 { 641 compatible = "rockchip,iommu"; 642 reg = <0x0 0xff340800 0x0 0x40>; 643 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 645 clock-names = "aclk", "iface"; 646 #iommu-cells = <0>; 647 status = "disabled"; 648 }; 649 650 vpu: video-codec@ff350000 { 651 compatible = "rockchip,rk3328-vpu"; 652 reg = <0x0 0xff350000 0x0 0x800>; 653 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 654 interrupt-names = "vdpu"; 655 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 656 clock-names = "aclk", "hclk"; 657 iommus = <&vpu_mmu>; 658 power-domains = <&power RK3328_PD_VPU>; 659 }; 660 661 vpu_mmu: iommu@ff350800 { 662 compatible = "rockchip,iommu"; 663 reg = <0x0 0xff350800 0x0 0x40>; 664 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 666 clock-names = "aclk", "iface"; 667 #iommu-cells = <0>; 668 power-domains = <&power RK3328_PD_VPU>; 669 }; 670 671 vdec: video-codec@ff360000 { 672 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; 673 reg = <0x0 0xff360000 0x0 0x480>; 674 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, 676 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; 677 clock-names = "axi", "ahb", "cabac", "core"; 678 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, 679 <&cru SCLK_VDEC_CORE>; 680 assigned-clock-rates = <400000000>, <400000000>, <300000000>; 681 iommus = <&vdec_mmu>; 682 power-domains = <&power RK3328_PD_VIDEO>; 683 }; 684 685 vdec_mmu: iommu@ff360480 { 686 compatible = "rockchip,iommu"; 687 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 688 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 690 clock-names = "aclk", "iface"; 691 #iommu-cells = <0>; 692 power-domains = <&power RK3328_PD_VIDEO>; 693 }; 694 695 vop: vop@ff370000 { 696 compatible = "rockchip,rk3328-vop"; 697 reg = <0x0 0xff370000 0x0 0x3efc>; 698 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 700 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 701 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 702 reset-names = "axi", "ahb", "dclk"; 703 iommus = <&vop_mmu>; 704 status = "disabled"; 705 706 vop_out: port { 707 #address-cells = <1>; 708 #size-cells = <0>; 709 710 vop_out_hdmi: endpoint@0 { 711 reg = <0>; 712 remote-endpoint = <&hdmi_in_vop>; 713 }; 714 }; 715 }; 716 717 vop_mmu: iommu@ff373f00 { 718 compatible = "rockchip,iommu"; 719 reg = <0x0 0xff373f00 0x0 0x100>; 720 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 722 clock-names = "aclk", "iface"; 723 #iommu-cells = <0>; 724 status = "disabled"; 725 }; 726 727 hdmi: hdmi@ff3c0000 { 728 compatible = "rockchip,rk3328-dw-hdmi"; 729 reg = <0x0 0xff3c0000 0x0 0x20000>; 730 reg-io-width = <4>; 731 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&cru PCLK_HDMI>, 734 <&cru SCLK_HDMI_SFC>, 735 <&cru SCLK_RTC32K>; 736 clock-names = "iahb", 737 "isfr", 738 "cec"; 739 phys = <&hdmiphy>; 740 phy-names = "hdmi"; 741 pinctrl-names = "default"; 742 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 743 rockchip,grf = <&grf>; 744 #sound-dai-cells = <0>; 745 status = "disabled"; 746 747 ports { 748 hdmi_in: port { 749 hdmi_in_vop: endpoint { 750 remote-endpoint = <&vop_out_hdmi>; 751 }; 752 }; 753 }; 754 }; 755 756 codec: codec@ff410000 { 757 compatible = "rockchip,rk3328-codec"; 758 reg = <0x0 0xff410000 0x0 0x1000>; 759 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 760 clock-names = "pclk", "mclk"; 761 rockchip,grf = <&grf>; 762 #sound-dai-cells = <0>; 763 status = "disabled"; 764 }; 765 766 hdmiphy: phy@ff430000 { 767 compatible = "rockchip,rk3328-hdmi-phy"; 768 reg = <0x0 0xff430000 0x0 0x10000>; 769 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 771 clock-names = "sysclk", "refoclk", "refpclk"; 772 clock-output-names = "hdmi_phy"; 773 #clock-cells = <0>; 774 nvmem-cells = <&efuse_cpu_version>; 775 nvmem-cell-names = "cpu-version"; 776 #phy-cells = <0>; 777 status = "disabled"; 778 }; 779 780 cru: clock-controller@ff440000 { 781 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 782 reg = <0x0 0xff440000 0x0 0x1000>; 783 rockchip,grf = <&grf>; 784 #clock-cells = <1>; 785 #reset-cells = <1>; 786 assigned-clocks = 787 /* 788 * CPLL should run at 1200, but that is to high for 789 * the initial dividers of most of its children. 790 * We need set cpll child clk div first, 791 * and then set the cpll frequency. 792 */ 793 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 794 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 795 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 796 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 797 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 798 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 799 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 800 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 801 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 802 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 803 <&cru SCLK_WIFI>, <&cru ARMCLK>, 804 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 805 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 806 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 807 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 808 <&cru SCLK_RTC32K>; 809 assigned-clock-parents = 810 <&cru HDMIPHY>, <&cru PLL_APLL>, 811 <&cru PLL_GPLL>, <&xin24m>, 812 <&xin24m>, <&xin24m>; 813 assigned-clock-rates = 814 <0>, <61440000>, 815 <0>, <24000000>, 816 <24000000>, <24000000>, 817 <15000000>, <15000000>, 818 <100000000>, <100000000>, 819 <100000000>, <100000000>, 820 <50000000>, <100000000>, 821 <100000000>, <100000000>, 822 <50000000>, <50000000>, 823 <50000000>, <50000000>, 824 <24000000>, <600000000>, 825 <491520000>, <1200000000>, 826 <150000000>, <75000000>, 827 <75000000>, <150000000>, 828 <75000000>, <75000000>, 829 <32768>; 830 }; 831 832 usb2phy_grf: syscon@ff450000 { 833 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 834 "simple-mfd"; 835 reg = <0x0 0xff450000 0x0 0x10000>; 836 #address-cells = <1>; 837 #size-cells = <1>; 838 839 u2phy: usb2phy@100 { 840 compatible = "rockchip,rk3328-usb2phy"; 841 reg = <0x100 0x10>; 842 clocks = <&xin24m>; 843 clock-names = "phyclk"; 844 clock-output-names = "usb480m_phy"; 845 #clock-cells = <0>; 846 assigned-clocks = <&cru USB480M>; 847 assigned-clock-parents = <&u2phy>; 848 status = "disabled"; 849 850 u2phy_otg: otg-port { 851 #phy-cells = <0>; 852 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 855 interrupt-names = "otg-bvalid", "otg-id", 856 "linestate"; 857 status = "disabled"; 858 }; 859 860 u2phy_host: host-port { 861 #phy-cells = <0>; 862 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 863 interrupt-names = "linestate"; 864 status = "disabled"; 865 }; 866 }; 867 }; 868 869 sdmmc: mmc@ff500000 { 870 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 871 reg = <0x0 0xff500000 0x0 0x4000>; 872 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 874 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 875 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 876 fifo-depth = <0x100>; 877 max-frequency = <150000000>; 878 status = "disabled"; 879 }; 880 881 sdio: mmc@ff510000 { 882 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 883 reg = <0x0 0xff510000 0x0 0x4000>; 884 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 886 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 887 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 888 fifo-depth = <0x100>; 889 max-frequency = <150000000>; 890 status = "disabled"; 891 }; 892 893 emmc: mmc@ff520000 { 894 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 895 reg = <0x0 0xff520000 0x0 0x4000>; 896 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 898 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 899 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 900 fifo-depth = <0x100>; 901 max-frequency = <150000000>; 902 status = "disabled"; 903 }; 904 905 gmac2io: ethernet@ff540000 { 906 compatible = "rockchip,rk3328-gmac"; 907 reg = <0x0 0xff540000 0x0 0x10000>; 908 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 909 interrupt-names = "macirq"; 910 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 911 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 912 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 913 <&cru PCLK_MAC2IO>; 914 clock-names = "stmmaceth", "mac_clk_rx", 915 "mac_clk_tx", "clk_mac_ref", 916 "clk_mac_refout", "aclk_mac", 917 "pclk_mac"; 918 resets = <&cru SRST_GMAC2IO_A>; 919 reset-names = "stmmaceth"; 920 rockchip,grf = <&grf>; 921 tx-fifo-depth = <2048>; 922 rx-fifo-depth = <4096>; 923 snps,txpbl = <0x4>; 924 status = "disabled"; 925 }; 926 927 gmac2phy: ethernet@ff550000 { 928 compatible = "rockchip,rk3328-gmac"; 929 reg = <0x0 0xff550000 0x0 0x10000>; 930 rockchip,grf = <&grf>; 931 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 932 interrupt-names = "macirq"; 933 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 934 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 935 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 936 <&cru SCLK_MAC2PHY_OUT>; 937 clock-names = "stmmaceth", "mac_clk_rx", 938 "mac_clk_tx", "clk_mac_ref", 939 "aclk_mac", "pclk_mac", 940 "clk_macphy"; 941 resets = <&cru SRST_GMAC2PHY_A>; 942 reset-names = "stmmaceth"; 943 phy-mode = "rmii"; 944 phy-handle = <&phy>; 945 tx-fifo-depth = <2048>; 946 rx-fifo-depth = <4096>; 947 snps,txpbl = <0x4>; 948 clock_in_out = "output"; 949 status = "disabled"; 950 951 mdio { 952 compatible = "snps,dwmac-mdio"; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 956 phy: ethernet-phy@0 { 957 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 958 reg = <0>; 959 clocks = <&cru SCLK_MAC2PHY_OUT>; 960 resets = <&cru SRST_MACPHY>; 961 pinctrl-names = "default"; 962 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 963 phy-is-integrated; 964 }; 965 }; 966 }; 967 968 usb20_otg: usb@ff580000 { 969 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 970 "snps,dwc2"; 971 reg = <0x0 0xff580000 0x0 0x40000>; 972 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&cru HCLK_OTG>; 974 clock-names = "otg"; 975 dr_mode = "otg"; 976 g-np-tx-fifo-size = <16>; 977 g-rx-fifo-size = <280>; 978 g-tx-fifo-size = <256 128 128 64 32 16>; 979 phys = <&u2phy_otg>; 980 phy-names = "usb2-phy"; 981 status = "disabled"; 982 }; 983 984 usb_host0_ehci: usb@ff5c0000 { 985 compatible = "generic-ehci"; 986 reg = <0x0 0xff5c0000 0x0 0x10000>; 987 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&cru HCLK_HOST0>, <&u2phy>; 989 phys = <&u2phy_host>; 990 phy-names = "usb"; 991 status = "disabled"; 992 }; 993 994 usb_host0_ohci: usb@ff5d0000 { 995 compatible = "generic-ohci"; 996 reg = <0x0 0xff5d0000 0x0 0x10000>; 997 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&cru HCLK_HOST0>, <&u2phy>; 999 phys = <&u2phy_host>; 1000 phy-names = "usb"; 1001 status = "disabled"; 1002 }; 1003 1004 usbdrd3: usb@ff600000 { 1005 compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; 1006 reg = <0x0 0xff600000 0x0 0x100000>; 1007 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 1009 <&cru ACLK_USB3OTG>; 1010 clock-names = "ref_clk", "suspend_clk", 1011 "bus_clk"; 1012 dr_mode = "otg"; 1013 phy_type = "utmi_wide"; 1014 snps,dis-del-phy-power-chg-quirk; 1015 snps,dis_enblslpm_quirk; 1016 snps,dis-tx-ipgap-linecheck-quirk; 1017 snps,dis-u2-freeclk-exists-quirk; 1018 snps,dis_u2_susphy_quirk; 1019 snps,dis_u3_susphy_quirk; 1020 status = "disabled"; 1021 }; 1022 1023 gic: interrupt-controller@ff811000 { 1024 compatible = "arm,gic-400"; 1025 #interrupt-cells = <3>; 1026 #address-cells = <0>; 1027 interrupt-controller; 1028 reg = <0x0 0xff811000 0 0x1000>, 1029 <0x0 0xff812000 0 0x2000>, 1030 <0x0 0xff814000 0 0x2000>, 1031 <0x0 0xff816000 0 0x2000>; 1032 interrupts = <GIC_PPI 9 1033 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1034 }; 1035 1036 crypto: crypto@ff060000 { 1037 compatible = "rockchip,rk3328-crypto"; 1038 reg = <0x0 0xff060000 0x0 0x4000>; 1039 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1040 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>, 1041 <&cru SCLK_CRYPTO>; 1042 clock-names = "hclk_master", "hclk_slave", "sclk"; 1043 resets = <&cru SRST_CRYPTO>; 1044 reset-names = "crypto-rst"; 1045 }; 1046 1047 pinctrl: pinctrl { 1048 compatible = "rockchip,rk3328-pinctrl"; 1049 rockchip,grf = <&grf>; 1050 #address-cells = <2>; 1051 #size-cells = <2>; 1052 ranges; 1053 1054 gpio0: gpio@ff210000 { 1055 compatible = "rockchip,gpio-bank"; 1056 reg = <0x0 0xff210000 0x0 0x100>; 1057 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1058 clocks = <&cru PCLK_GPIO0>; 1059 1060 gpio-controller; 1061 #gpio-cells = <2>; 1062 1063 interrupt-controller; 1064 #interrupt-cells = <2>; 1065 }; 1066 1067 gpio1: gpio@ff220000 { 1068 compatible = "rockchip,gpio-bank"; 1069 reg = <0x0 0xff220000 0x0 0x100>; 1070 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1071 clocks = <&cru PCLK_GPIO1>; 1072 1073 gpio-controller; 1074 #gpio-cells = <2>; 1075 1076 interrupt-controller; 1077 #interrupt-cells = <2>; 1078 }; 1079 1080 gpio2: gpio@ff230000 { 1081 compatible = "rockchip,gpio-bank"; 1082 reg = <0x0 0xff230000 0x0 0x100>; 1083 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1084 clocks = <&cru PCLK_GPIO2>; 1085 1086 gpio-controller; 1087 #gpio-cells = <2>; 1088 1089 interrupt-controller; 1090 #interrupt-cells = <2>; 1091 }; 1092 1093 gpio3: gpio@ff240000 { 1094 compatible = "rockchip,gpio-bank"; 1095 reg = <0x0 0xff240000 0x0 0x100>; 1096 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1097 clocks = <&cru PCLK_GPIO3>; 1098 1099 gpio-controller; 1100 #gpio-cells = <2>; 1101 1102 interrupt-controller; 1103 #interrupt-cells = <2>; 1104 }; 1105 1106 pcfg_pull_up: pcfg-pull-up { 1107 bias-pull-up; 1108 }; 1109 1110 pcfg_pull_down: pcfg-pull-down { 1111 bias-pull-down; 1112 }; 1113 1114 pcfg_pull_none: pcfg-pull-none { 1115 bias-disable; 1116 }; 1117 1118 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1119 bias-disable; 1120 drive-strength = <2>; 1121 }; 1122 1123 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1124 bias-pull-up; 1125 drive-strength = <2>; 1126 }; 1127 1128 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1129 bias-pull-up; 1130 drive-strength = <4>; 1131 }; 1132 1133 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1134 bias-disable; 1135 drive-strength = <4>; 1136 }; 1137 1138 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1139 bias-pull-down; 1140 drive-strength = <4>; 1141 }; 1142 1143 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1144 bias-disable; 1145 drive-strength = <8>; 1146 }; 1147 1148 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1149 bias-pull-up; 1150 drive-strength = <8>; 1151 }; 1152 1153 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1154 bias-disable; 1155 drive-strength = <12>; 1156 }; 1157 1158 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1159 bias-pull-up; 1160 drive-strength = <12>; 1161 }; 1162 1163 pcfg_output_high: pcfg-output-high { 1164 output-high; 1165 }; 1166 1167 pcfg_output_low: pcfg-output-low { 1168 output-low; 1169 }; 1170 1171 pcfg_input_high: pcfg-input-high { 1172 bias-pull-up; 1173 input-enable; 1174 }; 1175 1176 pcfg_input: pcfg-input { 1177 input-enable; 1178 }; 1179 1180 i2c0 { 1181 i2c0_xfer: i2c0-xfer { 1182 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1183 <2 RK_PD1 1 &pcfg_pull_none>; 1184 }; 1185 }; 1186 1187 i2c1 { 1188 i2c1_xfer: i2c1-xfer { 1189 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1190 <2 RK_PA5 2 &pcfg_pull_none>; 1191 }; 1192 }; 1193 1194 i2c2 { 1195 i2c2_xfer: i2c2-xfer { 1196 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1197 <2 RK_PB6 1 &pcfg_pull_none>; 1198 }; 1199 }; 1200 1201 i2c3 { 1202 i2c3_xfer: i2c3-xfer { 1203 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1204 <0 RK_PA6 2 &pcfg_pull_none>; 1205 }; 1206 i2c3_pins: i2c3-pins { 1207 rockchip,pins = 1208 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1209 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1210 }; 1211 }; 1212 1213 hdmi_i2c { 1214 hdmii2c_xfer: hdmii2c-xfer { 1215 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1216 <0 RK_PA6 1 &pcfg_pull_none>; 1217 }; 1218 }; 1219 1220 pdm-0 { 1221 pdmm0_clk: pdmm0-clk { 1222 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1223 }; 1224 1225 pdmm0_fsync: pdmm0-fsync { 1226 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1227 }; 1228 1229 pdmm0_sdi0: pdmm0-sdi0 { 1230 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1231 }; 1232 1233 pdmm0_sdi1: pdmm0-sdi1 { 1234 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1235 }; 1236 1237 pdmm0_sdi2: pdmm0-sdi2 { 1238 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1239 }; 1240 1241 pdmm0_sdi3: pdmm0-sdi3 { 1242 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1243 }; 1244 1245 pdmm0_clk_sleep: pdmm0-clk-sleep { 1246 rockchip,pins = 1247 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1248 }; 1249 1250 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1251 rockchip,pins = 1252 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1253 }; 1254 1255 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1256 rockchip,pins = 1257 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1258 }; 1259 1260 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1261 rockchip,pins = 1262 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1263 }; 1264 1265 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1266 rockchip,pins = 1267 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1268 }; 1269 1270 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1271 rockchip,pins = 1272 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1273 }; 1274 }; 1275 1276 tsadc { 1277 otp_pin: otp-pin { 1278 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1279 }; 1280 1281 otp_out: otp-out { 1282 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1283 }; 1284 }; 1285 1286 uart0 { 1287 uart0_xfer: uart0-xfer { 1288 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1289 <1 RK_PB0 1 &pcfg_pull_up>; 1290 }; 1291 1292 uart0_cts: uart0-cts { 1293 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1294 }; 1295 1296 uart0_rts: uart0-rts { 1297 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1298 }; 1299 1300 uart0_rts_pin: uart0-rts-pin { 1301 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1302 }; 1303 }; 1304 1305 uart1 { 1306 uart1_xfer: uart1-xfer { 1307 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, 1308 <3 RK_PA6 4 &pcfg_pull_up>; 1309 }; 1310 1311 uart1_cts: uart1-cts { 1312 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1313 }; 1314 1315 uart1_rts: uart1-rts { 1316 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1317 }; 1318 1319 uart1_rts_pin: uart1-rts-pin { 1320 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1321 }; 1322 }; 1323 1324 uart2-0 { 1325 uart2m0_xfer: uart2m0-xfer { 1326 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, 1327 <1 RK_PA1 2 &pcfg_pull_up>; 1328 }; 1329 }; 1330 1331 uart2-1 { 1332 uart2m1_xfer: uart2m1-xfer { 1333 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 1334 <2 RK_PA1 1 &pcfg_pull_up>; 1335 }; 1336 }; 1337 1338 spi0-0 { 1339 spi0m0_clk: spi0m0-clk { 1340 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1341 }; 1342 1343 spi0m0_cs0: spi0m0-cs0 { 1344 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1345 }; 1346 1347 spi0m0_tx: spi0m0-tx { 1348 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1349 }; 1350 1351 spi0m0_rx: spi0m0-rx { 1352 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1353 }; 1354 1355 spi0m0_cs1: spi0m0-cs1 { 1356 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1357 }; 1358 }; 1359 1360 spi0-1 { 1361 spi0m1_clk: spi0m1-clk { 1362 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1363 }; 1364 1365 spi0m1_cs0: spi0m1-cs0 { 1366 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1367 }; 1368 1369 spi0m1_tx: spi0m1-tx { 1370 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1371 }; 1372 1373 spi0m1_rx: spi0m1-rx { 1374 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1375 }; 1376 1377 spi0m1_cs1: spi0m1-cs1 { 1378 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1379 }; 1380 }; 1381 1382 spi0-2 { 1383 spi0m2_clk: spi0m2-clk { 1384 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1385 }; 1386 1387 spi0m2_cs0: spi0m2-cs0 { 1388 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1389 }; 1390 1391 spi0m2_tx: spi0m2-tx { 1392 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1393 }; 1394 1395 spi0m2_rx: spi0m2-rx { 1396 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1397 }; 1398 }; 1399 1400 i2s1 { 1401 i2s1_mclk: i2s1-mclk { 1402 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1403 }; 1404 1405 i2s1_sclk: i2s1-sclk { 1406 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1407 }; 1408 1409 i2s1_lrckrx: i2s1-lrckrx { 1410 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1411 }; 1412 1413 i2s1_lrcktx: i2s1-lrcktx { 1414 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1415 }; 1416 1417 i2s1_sdi: i2s1-sdi { 1418 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1419 }; 1420 1421 i2s1_sdo: i2s1-sdo { 1422 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1423 }; 1424 1425 i2s1_sdio1: i2s1-sdio1 { 1426 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1427 }; 1428 1429 i2s1_sdio2: i2s1-sdio2 { 1430 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1431 }; 1432 1433 i2s1_sdio3: i2s1-sdio3 { 1434 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1435 }; 1436 1437 i2s1_sleep: i2s1-sleep { 1438 rockchip,pins = 1439 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1440 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1441 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1442 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1443 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1444 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1445 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1446 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1447 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1448 }; 1449 }; 1450 1451 i2s2-0 { 1452 i2s2m0_mclk: i2s2m0-mclk { 1453 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1454 }; 1455 1456 i2s2m0_sclk: i2s2m0-sclk { 1457 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1458 }; 1459 1460 i2s2m0_lrckrx: i2s2m0-lrckrx { 1461 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1462 }; 1463 1464 i2s2m0_lrcktx: i2s2m0-lrcktx { 1465 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1466 }; 1467 1468 i2s2m0_sdi: i2s2m0-sdi { 1469 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1470 }; 1471 1472 i2s2m0_sdo: i2s2m0-sdo { 1473 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1474 }; 1475 1476 i2s2m0_sleep: i2s2m0-sleep { 1477 rockchip,pins = 1478 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1479 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1480 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1481 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1482 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1483 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1484 }; 1485 }; 1486 1487 i2s2-1 { 1488 i2s2m1_mclk: i2s2m1-mclk { 1489 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1490 }; 1491 1492 i2s2m1_sclk: i2s2m1-sclk { 1493 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1494 }; 1495 1496 i2s2m1_lrckrx: i2sm1-lrckrx { 1497 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1498 }; 1499 1500 i2s2m1_lrcktx: i2s2m1-lrcktx { 1501 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1502 }; 1503 1504 i2s2m1_sdi: i2s2m1-sdi { 1505 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1506 }; 1507 1508 i2s2m1_sdo: i2s2m1-sdo { 1509 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1510 }; 1511 1512 i2s2m1_sleep: i2s2m1-sleep { 1513 rockchip,pins = 1514 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1515 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1516 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1517 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1518 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1519 }; 1520 }; 1521 1522 spdif-0 { 1523 spdifm0_tx: spdifm0-tx { 1524 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1525 }; 1526 }; 1527 1528 spdif-1 { 1529 spdifm1_tx: spdifm1-tx { 1530 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1531 }; 1532 }; 1533 1534 spdif-2 { 1535 spdifm2_tx: spdifm2-tx { 1536 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1537 }; 1538 }; 1539 1540 sdmmc0-0 { 1541 sdmmc0m0_pwren: sdmmc0m0-pwren { 1542 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1543 }; 1544 1545 sdmmc0m0_pin: sdmmc0m0-pin { 1546 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1547 }; 1548 }; 1549 1550 sdmmc0-1 { 1551 sdmmc0m1_pwren: sdmmc0m1-pwren { 1552 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1553 }; 1554 1555 sdmmc0m1_pin: sdmmc0m1-pin { 1556 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1557 }; 1558 }; 1559 1560 sdmmc0 { 1561 sdmmc0_clk: sdmmc0-clk { 1562 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1563 }; 1564 1565 sdmmc0_cmd: sdmmc0-cmd { 1566 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1567 }; 1568 1569 sdmmc0_dectn: sdmmc0-dectn { 1570 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1571 }; 1572 1573 sdmmc0_wrprt: sdmmc0-wrprt { 1574 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1575 }; 1576 1577 sdmmc0_bus1: sdmmc0-bus1 { 1578 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1579 }; 1580 1581 sdmmc0_bus4: sdmmc0-bus4 { 1582 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1583 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1584 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1585 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1586 }; 1587 1588 sdmmc0_pins: sdmmc0-pins { 1589 rockchip,pins = 1590 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1591 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1592 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1593 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1594 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1595 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1596 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1597 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1598 }; 1599 }; 1600 1601 sdmmc0ext { 1602 sdmmc0ext_clk: sdmmc0ext-clk { 1603 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1604 }; 1605 1606 sdmmc0ext_cmd: sdmmc0ext-cmd { 1607 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1608 }; 1609 1610 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1611 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1612 }; 1613 1614 sdmmc0ext_dectn: sdmmc0ext-dectn { 1615 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1616 }; 1617 1618 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1619 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1620 }; 1621 1622 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1623 rockchip,pins = 1624 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1625 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1626 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1627 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1628 }; 1629 1630 sdmmc0ext_pins: sdmmc0ext-pins { 1631 rockchip,pins = 1632 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1633 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1634 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1635 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1636 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1637 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1638 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1639 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1640 }; 1641 }; 1642 1643 sdmmc1 { 1644 sdmmc1_clk: sdmmc1-clk { 1645 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1646 }; 1647 1648 sdmmc1_cmd: sdmmc1-cmd { 1649 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1650 }; 1651 1652 sdmmc1_pwren: sdmmc1-pwren { 1653 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1654 }; 1655 1656 sdmmc1_wrprt: sdmmc1-wrprt { 1657 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1658 }; 1659 1660 sdmmc1_dectn: sdmmc1-dectn { 1661 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1662 }; 1663 1664 sdmmc1_bus1: sdmmc1-bus1 { 1665 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1666 }; 1667 1668 sdmmc1_bus4: sdmmc1-bus4 { 1669 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1670 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1671 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1672 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1673 }; 1674 1675 sdmmc1_pins: sdmmc1-pins { 1676 rockchip,pins = 1677 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1678 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1679 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1680 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1681 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1682 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1683 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1684 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1685 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1686 }; 1687 }; 1688 1689 emmc { 1690 emmc_clk: emmc-clk { 1691 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1692 }; 1693 1694 emmc_cmd: emmc-cmd { 1695 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1696 }; 1697 1698 emmc_pwren: emmc-pwren { 1699 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1700 }; 1701 1702 emmc_rstnout: emmc-rstnout { 1703 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1704 }; 1705 1706 emmc_bus1: emmc-bus1 { 1707 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1708 }; 1709 1710 emmc_bus4: emmc-bus4 { 1711 rockchip,pins = 1712 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1713 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1714 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1715 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1716 }; 1717 1718 emmc_bus8: emmc-bus8 { 1719 rockchip,pins = 1720 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1721 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1722 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1723 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1724 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1725 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1726 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1727 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1728 }; 1729 }; 1730 1731 pwm0 { 1732 pwm0_pin: pwm0-pin { 1733 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1734 }; 1735 }; 1736 1737 pwm1 { 1738 pwm1_pin: pwm1-pin { 1739 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1740 }; 1741 }; 1742 1743 pwm2 { 1744 pwm2_pin: pwm2-pin { 1745 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1746 }; 1747 }; 1748 1749 pwmir { 1750 pwmir_pin: pwmir-pin { 1751 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1752 }; 1753 }; 1754 1755 gmac-1 { 1756 rgmiim1_pins: rgmiim1-pins { 1757 rockchip,pins = 1758 /* mac_txclk */ 1759 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1760 /* mac_rxclk */ 1761 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1762 /* mac_mdio */ 1763 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1764 /* mac_txen */ 1765 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1766 /* mac_clk */ 1767 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1768 /* mac_rxdv */ 1769 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1770 /* mac_mdc */ 1771 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1772 /* mac_rxd1 */ 1773 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1774 /* mac_rxd0 */ 1775 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1776 /* mac_txd1 */ 1777 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1778 /* mac_txd0 */ 1779 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1780 /* mac_rxd3 */ 1781 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1782 /* mac_rxd2 */ 1783 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1784 /* mac_txd3 */ 1785 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1786 /* mac_txd2 */ 1787 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1788 1789 /* mac_txclk */ 1790 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1791 /* mac_txen */ 1792 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1793 /* mac_clk */ 1794 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1795 /* mac_txd1 */ 1796 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1797 /* mac_txd0 */ 1798 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1799 /* mac_txd3 */ 1800 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1801 /* mac_txd2 */ 1802 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1803 }; 1804 1805 rmiim1_pins: rmiim1-pins { 1806 rockchip,pins = 1807 /* mac_mdio */ 1808 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1809 /* mac_txen */ 1810 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1811 /* mac_clk */ 1812 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1813 /* mac_rxer */ 1814 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1815 /* mac_rxdv */ 1816 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1817 /* mac_mdc */ 1818 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1819 /* mac_rxd1 */ 1820 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1821 /* mac_rxd0 */ 1822 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1823 /* mac_txd1 */ 1824 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1825 /* mac_txd0 */ 1826 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1827 1828 /* mac_mdio */ 1829 <0 RK_PB3 1 &pcfg_pull_none>, 1830 /* mac_txen */ 1831 <0 RK_PB4 1 &pcfg_pull_none>, 1832 /* mac_clk */ 1833 <0 RK_PD0 1 &pcfg_pull_none>, 1834 /* mac_mdc */ 1835 <0 RK_PC3 1 &pcfg_pull_none>, 1836 /* mac_txd1 */ 1837 <0 RK_PC0 1 &pcfg_pull_none>, 1838 /* mac_txd0 */ 1839 <0 RK_PC1 1 &pcfg_pull_none>; 1840 }; 1841 }; 1842 1843 gmac2phy { 1844 fephyled_speed10: fephyled-speed10 { 1845 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1846 }; 1847 1848 fephyled_duplex: fephyled-duplex { 1849 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1850 }; 1851 1852 fephyled_rxm1: fephyled-rxm1 { 1853 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1854 }; 1855 1856 fephyled_txm1: fephyled-txm1 { 1857 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1858 }; 1859 1860 fephyled_linkm1: fephyled-linkm1 { 1861 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1862 }; 1863 }; 1864 1865 tsadc_pin { 1866 tsadc_int: tsadc-int { 1867 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1868 }; 1869 tsadc_pin: tsadc-pin { 1870 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1871 }; 1872 }; 1873 1874 hdmi_pin { 1875 hdmi_cec: hdmi-cec { 1876 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1877 }; 1878 1879 hdmi_hpd: hdmi-hpd { 1880 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1881 }; 1882 }; 1883 1884 cif-0 { 1885 dvp_d2d9_m0:dvp-d2d9-m0 { 1886 rockchip,pins = 1887 /* cif_d0 */ 1888 <3 RK_PA4 2 &pcfg_pull_none>, 1889 /* cif_d1 */ 1890 <3 RK_PA5 2 &pcfg_pull_none>, 1891 /* cif_d2 */ 1892 <3 RK_PA6 2 &pcfg_pull_none>, 1893 /* cif_d3 */ 1894 <3 RK_PA7 2 &pcfg_pull_none>, 1895 /* cif_d4 */ 1896 <3 RK_PB0 2 &pcfg_pull_none>, 1897 /* cif_d5m0 */ 1898 <3 RK_PB1 2 &pcfg_pull_none>, 1899 /* cif_d6m0 */ 1900 <3 RK_PB2 2 &pcfg_pull_none>, 1901 /* cif_d7m0 */ 1902 <3 RK_PB3 2 &pcfg_pull_none>, 1903 /* cif_href */ 1904 <3 RK_PA1 2 &pcfg_pull_none>, 1905 /* cif_vsync */ 1906 <3 RK_PA0 2 &pcfg_pull_none>, 1907 /* cif_clkoutm0 */ 1908 <3 RK_PA3 2 &pcfg_pull_none>, 1909 /* cif_clkin */ 1910 <3 RK_PA2 2 &pcfg_pull_none>; 1911 }; 1912 }; 1913 1914 cif-1 { 1915 dvp_d2d9_m1:dvp-d2d9-m1 { 1916 rockchip,pins = 1917 /* cif_d0 */ 1918 <3 RK_PA4 2 &pcfg_pull_none>, 1919 /* cif_d1 */ 1920 <3 RK_PA5 2 &pcfg_pull_none>, 1921 /* cif_d2 */ 1922 <3 RK_PA6 2 &pcfg_pull_none>, 1923 /* cif_d3 */ 1924 <3 RK_PA7 2 &pcfg_pull_none>, 1925 /* cif_d4 */ 1926 <3 RK_PB0 2 &pcfg_pull_none>, 1927 /* cif_d5m1 */ 1928 <2 RK_PC0 4 &pcfg_pull_none>, 1929 /* cif_d6m1 */ 1930 <2 RK_PC1 4 &pcfg_pull_none>, 1931 /* cif_d7m1 */ 1932 <2 RK_PC2 4 &pcfg_pull_none>, 1933 /* cif_href */ 1934 <3 RK_PA1 2 &pcfg_pull_none>, 1935 /* cif_vsync */ 1936 <3 RK_PA0 2 &pcfg_pull_none>, 1937 /* cif_clkoutm1 */ 1938 <2 RK_PB7 4 &pcfg_pull_none>, 1939 /* cif_clkin */ 1940 <3 RK_PA2 2 &pcfg_pull_none>; 1941 }; 1942 }; 1943 }; 1944}; 1945