1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2021 T-Chip Intelligent Technology Co., Ltd 3 4/dts-v1/; 5 6#include <dt-bindings/input/input.h> 7#include "rk3328-roc.dtsi" 8 9/ { 10 model = "Firefly ROC-RK3328-PC"; 11 compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328"; 12 13 adc-keys { 14 compatible = "adc-keys"; 15 io-channels = <&saradc 0>; 16 io-channel-names = "buttons"; 17 keyup-threshold-microvolt = <1750000>; 18 19 /* This button is unpopulated out of the factory. */ 20 button-recovery { 21 label = "Recovery"; 22 linux,code = <KEY_VENDOR>; 23 press-threshold-microvolt = <10000>; 24 }; 25 }; 26 27 ir-receiver { 28 compatible = "gpio-ir-receiver"; 29 gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; 30 linux,rc-map-name = "rc-khadas"; 31 pinctrl-names = "default"; 32 pinctrl-0 = <&ir_int>; 33 }; 34 35 sdio_pwrseq: sdio-pwrseq { 36 compatible = "mmc-pwrseq-simple"; 37 pinctrl-names = "default"; 38 pinctrl-0 = <&wifi_en>, <&wifi_host_wake>; 39 reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; 40 }; 41}; 42 43&codec { 44 mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; 45}; 46 47&gpu { 48 mali-supply = <&vdd_logic>; 49}; 50 51&pinctrl { 52 ir { 53 ir_int: ir-int { 54 rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 55 }; 56 }; 57 58 sdmmcio { 59 sdio_per_pin: sdio-per-pin { 60 rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; 61 }; 62 }; 63 64 wifi { 65 wifi_en: wifi-en { 66 rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 67 }; 68 69 wifi_host_wake: wifi-host-wake { 70 rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>; 71 }; 72 73 bt_rst: bt-rst { 74 rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 75 }; 76 77 bt_en: bt-en { 78 rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 79 }; 80 }; 81}; 82 83&pmic_int_l { 84 rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; 85}; 86 87&rk805 { 88 interrupt-parent = <&gpio0>; 89 interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; 90}; 91 92&saradc { 93 vref-supply = <&vcc_18>; 94 status = "okay"; 95}; 96 97&usb20_host_drv { 98 rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; 99}; 100 101&vcc_host1_5v { 102 gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; 103}; 104 105&vcc_sdio { 106 gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&sdio_per_pin>; 109}; 110