1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2021 T-Chip Intelligent Technology Co., Ltd 3 4/dts-v1/; 5 6#include <dt-bindings/input/input.h> 7 8#include "rk3328-roc-cc.dts" 9 10/ { 11 model = "Firefly ROC-RK3328-PC"; 12 compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328"; 13 14 adc-keys { 15 compatible = "adc-keys"; 16 io-channels = <&saradc 0>; 17 io-channel-names = "buttons"; 18 keyup-threshold-microvolt = <1750000>; 19 20 /* This button is unpopulated out of the factory. */ 21 button-recovery { 22 label = "Recovery"; 23 linux,code = <KEY_VENDOR>; 24 press-threshold-microvolt = <10000>; 25 }; 26 }; 27 28 ir-receiver { 29 compatible = "gpio-ir-receiver"; 30 gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; 31 linux,rc-map-name = "rc-khadas"; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&ir_int>; 34 }; 35 36 sdio_pwrseq: sdio-pwrseq { 37 compatible = "mmc-pwrseq-simple"; 38 pinctrl-names = "default"; 39 pinctrl-0 = <&wifi_en>, <&wifi_host_wake>; 40 reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; 41 }; 42}; 43 44&codec { 45 mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; 46}; 47 48&gpu { 49 mali-supply = <&vdd_logic>; 50}; 51 52&pinctrl { 53 ir { 54 ir_int: ir-int { 55 rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 56 }; 57 }; 58 59 sdmmcio { 60 sdio_per_pin: sdio-per-pin { 61 rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; 62 }; 63 }; 64 65 wifi { 66 wifi_en: wifi-en { 67 rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 68 }; 69 70 wifi_host_wake: wifi-host-wake { 71 rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>; 72 }; 73 74 bt_rst: bt-rst { 75 rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 76 }; 77 78 bt_en: bt-en { 79 rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 80 }; 81 }; 82}; 83 84&pmic_int_l { 85 rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; 86}; 87 88&rk805 { 89 interrupt-parent = <&gpio0>; 90 interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; 91}; 92 93&saradc { 94 vref-supply = <&vcc_18>; 95 status = "okay"; 96}; 97 98&usb20_host_drv { 99 rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; 100}; 101 102&vcc_host1_5v { 103 gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; 104}; 105 106&vcc_sdio { 107 gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; 108 pinctrl-names = "default"; 109 pinctrl-0 = <&sdio_per_pin>; 110}; 111