1*f3c6526dSDragan Simic// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2*f3c6526dSDragan Simic/* 3*f3c6526dSDragan Simic * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. 4*f3c6526dSDragan Simic * (http://www.friendlyarm.com) 5*f3c6526dSDragan Simic * 6*f3c6526dSDragan Simic * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com> 7*f3c6526dSDragan Simic */ 8*f3c6526dSDragan Simic 9*f3c6526dSDragan Simic/dts-v1/; 10*f3c6526dSDragan Simic 11*f3c6526dSDragan Simic#include "rk3328-nanopi-r2.dtsi" 12*f3c6526dSDragan Simic 13*f3c6526dSDragan Simic&gmac2io { 14*f3c6526dSDragan Simic phy-handle = <&yt8521s>; 15*f3c6526dSDragan Simic tx_delay = <0x22>; 16*f3c6526dSDragan Simic rx_delay = <0x12>; 17*f3c6526dSDragan Simic status = "okay"; 18*f3c6526dSDragan Simic 19*f3c6526dSDragan Simic mdio { 20*f3c6526dSDragan Simic yt8521s: ethernet-phy@3 { 21*f3c6526dSDragan Simic compatible = "ethernet-phy-ieee802.3-c22"; 22*f3c6526dSDragan Simic reg = <3>; 23*f3c6526dSDragan Simic 24*f3c6526dSDragan Simic motorcomm,clk-out-frequency-hz = <125000000>; 25*f3c6526dSDragan Simic motorcomm,keep-pll-enabled; 26*f3c6526dSDragan Simic motorcomm,auto-sleep-disabled; 27*f3c6526dSDragan Simic 28*f3c6526dSDragan Simic pinctrl-0 = <ð_phy_reset_pin>; 29*f3c6526dSDragan Simic pinctrl-names = "default"; 30*f3c6526dSDragan Simic reset-assert-us = <10000>; 31*f3c6526dSDragan Simic reset-deassert-us = <50000>; 32*f3c6526dSDragan Simic reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; 33*f3c6526dSDragan Simic }; 34*f3c6526dSDragan Simic }; 35*f3c6526dSDragan Simic}; 36