1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7#include <dt-bindings/clock/rk3308-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3308"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 gpio4 = &gpio4; 28 i2c0 = &i2c0; 29 i2c1 = &i2c1; 30 i2c2 = &i2c2; 31 i2c3 = &i2c3; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 spi0 = &spi0; 38 spi1 = &spi1; 39 spi2 = &spi2; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 cpu0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a35"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 clocks = <&cru ARMCLK>; 52 #cooling-cells = <2>; 53 dynamic-power-coefficient = <90>; 54 operating-points-v2 = <&cpu0_opp_table>; 55 cpu-idle-states = <&CPU_SLEEP>; 56 next-level-cache = <&l2>; 57 }; 58 59 cpu1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a35"; 62 reg = <0x0 0x1>; 63 enable-method = "psci"; 64 operating-points-v2 = <&cpu0_opp_table>; 65 cpu-idle-states = <&CPU_SLEEP>; 66 next-level-cache = <&l2>; 67 }; 68 69 cpu2: cpu@2 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a35"; 72 reg = <0x0 0x2>; 73 enable-method = "psci"; 74 operating-points-v2 = <&cpu0_opp_table>; 75 cpu-idle-states = <&CPU_SLEEP>; 76 next-level-cache = <&l2>; 77 }; 78 79 cpu3: cpu@3 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a35"; 82 reg = <0x0 0x3>; 83 enable-method = "psci"; 84 operating-points-v2 = <&cpu0_opp_table>; 85 cpu-idle-states = <&CPU_SLEEP>; 86 next-level-cache = <&l2>; 87 }; 88 89 idle-states { 90 entry-method = "psci"; 91 92 CPU_SLEEP: cpu-sleep { 93 compatible = "arm,idle-state"; 94 local-timer-stop; 95 arm,psci-suspend-param = <0x0010000>; 96 entry-latency-us = <120>; 97 exit-latency-us = <250>; 98 min-residency-us = <900>; 99 }; 100 }; 101 102 l2: l2-cache { 103 compatible = "cache"; 104 cache-level = <2>; 105 cache-unified; 106 }; 107 }; 108 109 cpu0_opp_table: opp-table-0 { 110 compatible = "operating-points-v2"; 111 opp-shared; 112 113 opp-408000000 { 114 opp-hz = /bits/ 64 <408000000>; 115 opp-microvolt = <950000 950000 1340000>; 116 clock-latency-ns = <40000>; 117 opp-suspend; 118 }; 119 opp-600000000 { 120 opp-hz = /bits/ 64 <600000000>; 121 opp-microvolt = <950000 950000 1340000>; 122 clock-latency-ns = <40000>; 123 }; 124 opp-816000000 { 125 opp-hz = /bits/ 64 <816000000>; 126 opp-microvolt = <1025000 1025000 1340000>; 127 clock-latency-ns = <40000>; 128 }; 129 opp-1008000000 { 130 opp-hz = /bits/ 64 <1008000000>; 131 opp-microvolt = <1125000 1125000 1340000>; 132 clock-latency-ns = <40000>; 133 }; 134 }; 135 136 arm-pmu { 137 compatible = "arm,cortex-a35-pmu"; 138 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 142 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 143 }; 144 145 mac_clkin: external-mac-clock { 146 compatible = "fixed-clock"; 147 clock-frequency = <50000000>; 148 clock-output-names = "mac_clkin"; 149 #clock-cells = <0>; 150 }; 151 152 psci { 153 compatible = "arm,psci-1.0"; 154 method = "smc"; 155 }; 156 157 timer { 158 compatible = "arm,armv8-timer"; 159 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 160 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 161 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 162 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 163 }; 164 165 xin24m: xin24m { 166 compatible = "fixed-clock"; 167 #clock-cells = <0>; 168 clock-frequency = <24000000>; 169 clock-output-names = "xin24m"; 170 }; 171 172 grf: grf@ff000000 { 173 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 174 reg = <0x0 0xff000000 0x0 0x08000>; 175 176 reboot-mode { 177 compatible = "syscon-reboot-mode"; 178 offset = <0x500>; 179 mode-bootloader = <BOOT_BL_DOWNLOAD>; 180 mode-loader = <BOOT_BL_DOWNLOAD>; 181 mode-normal = <BOOT_NORMAL>; 182 mode-recovery = <BOOT_RECOVERY>; 183 mode-fastboot = <BOOT_FASTBOOT>; 184 }; 185 }; 186 187 usb2phy_grf: syscon@ff008000 { 188 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd"; 189 reg = <0x0 0xff008000 0x0 0x4000>; 190 #address-cells = <1>; 191 #size-cells = <1>; 192 193 u2phy: usb2phy@100 { 194 compatible = "rockchip,rk3308-usb2phy"; 195 reg = <0x100 0x10>; 196 assigned-clocks = <&cru USB480M>; 197 assigned-clock-parents = <&u2phy>; 198 clocks = <&cru SCLK_USBPHY_REF>; 199 clock-names = "phyclk"; 200 clock-output-names = "usb480m_phy"; 201 #clock-cells = <0>; 202 status = "disabled"; 203 204 u2phy_otg: otg-port { 205 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 208 interrupt-names = "otg-bvalid", "otg-id", 209 "linestate"; 210 #phy-cells = <0>; 211 status = "disabled"; 212 }; 213 214 u2phy_host: host-port { 215 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 216 interrupt-names = "linestate"; 217 #phy-cells = <0>; 218 status = "disabled"; 219 }; 220 }; 221 }; 222 223 detect_grf: syscon@ff00b000 { 224 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; 225 reg = <0x0 0xff00b000 0x0 0x1000>; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 }; 229 230 core_grf: syscon@ff00c000 { 231 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd"; 232 reg = <0x0 0xff00c000 0x0 0x1000>; 233 #address-cells = <1>; 234 #size-cells = <1>; 235 }; 236 237 i2c0: i2c@ff040000 { 238 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 239 reg = <0x0 0xff040000 0x0 0x1000>; 240 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 241 clock-names = "i2c", "pclk"; 242 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&i2c0_xfer>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 status = "disabled"; 248 }; 249 250 i2c1: i2c@ff050000 { 251 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 252 reg = <0x0 0xff050000 0x0 0x1000>; 253 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 254 clock-names = "i2c", "pclk"; 255 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&i2c1_xfer>; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 status = "disabled"; 261 }; 262 263 i2c2: i2c@ff060000 { 264 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 265 reg = <0x0 0xff060000 0x0 0x1000>; 266 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 267 clock-names = "i2c", "pclk"; 268 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 269 pinctrl-names = "default"; 270 pinctrl-0 = <&i2c2_xfer>; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 status = "disabled"; 274 }; 275 276 i2c3: i2c@ff070000 { 277 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 278 reg = <0x0 0xff070000 0x0 0x1000>; 279 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 280 clock-names = "i2c", "pclk"; 281 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&i2c3m0_xfer>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 status = "disabled"; 287 }; 288 289 wdt: watchdog@ff080000 { 290 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt"; 291 reg = <0x0 0xff080000 0x0 0x100>; 292 clocks = <&cru PCLK_WDT>; 293 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 294 status = "disabled"; 295 }; 296 297 uart0: serial@ff0a0000 { 298 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 299 reg = <0x0 0xff0a0000 0x0 0x100>; 300 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 302 clock-names = "baudclk", "apb_pclk"; 303 reg-shift = <2>; 304 reg-io-width = <4>; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 307 status = "disabled"; 308 }; 309 310 uart1: serial@ff0b0000 { 311 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 312 reg = <0x0 0xff0b0000 0x0 0x100>; 313 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 315 clock-names = "baudclk", "apb_pclk"; 316 reg-shift = <2>; 317 reg-io-width = <4>; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 320 status = "disabled"; 321 }; 322 323 uart2: serial@ff0c0000 { 324 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 325 reg = <0x0 0xff0c0000 0x0 0x100>; 326 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 328 clock-names = "baudclk", "apb_pclk"; 329 reg-shift = <2>; 330 reg-io-width = <4>; 331 pinctrl-names = "default"; 332 pinctrl-0 = <&uart2m0_xfer>; 333 status = "disabled"; 334 }; 335 336 uart3: serial@ff0d0000 { 337 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 338 reg = <0x0 0xff0d0000 0x0 0x100>; 339 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 341 clock-names = "baudclk", "apb_pclk"; 342 reg-shift = <2>; 343 reg-io-width = <4>; 344 pinctrl-names = "default"; 345 pinctrl-0 = <&uart3_xfer>; 346 status = "disabled"; 347 }; 348 349 uart4: serial@ff0e0000 { 350 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 351 reg = <0x0 0xff0e0000 0x0 0x100>; 352 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 354 clock-names = "baudclk", "apb_pclk"; 355 reg-shift = <2>; 356 reg-io-width = <4>; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 359 status = "disabled"; 360 }; 361 362 spi0: spi@ff120000 { 363 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 364 reg = <0x0 0xff120000 0x0 0x1000>; 365 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 369 clock-names = "spiclk", "apb_pclk"; 370 dmas = <&dmac0 0>, <&dmac0 1>; 371 dma-names = "tx", "rx"; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; 374 status = "disabled"; 375 }; 376 377 spi1: spi@ff130000 { 378 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 379 reg = <0x0 0xff130000 0x0 0x1000>; 380 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 384 clock-names = "spiclk", "apb_pclk"; 385 dmas = <&dmac0 2>, <&dmac0 3>; 386 dma-names = "tx", "rx"; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; 389 status = "disabled"; 390 }; 391 392 spi2: spi@ff140000 { 393 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 394 reg = <0x0 0xff140000 0x0 0x1000>; 395 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 399 clock-names = "spiclk", "apb_pclk"; 400 dmas = <&dmac1 16>, <&dmac1 17>; 401 dma-names = "tx", "rx"; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; 404 status = "disabled"; 405 }; 406 407 pwm8: pwm@ff160000 { 408 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 409 reg = <0x0 0xff160000 0x0 0x10>; 410 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 411 clock-names = "pwm", "pclk"; 412 pinctrl-names = "default"; 413 pinctrl-0 = <&pwm8_pin>; 414 #pwm-cells = <3>; 415 status = "disabled"; 416 }; 417 418 pwm9: pwm@ff160010 { 419 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 420 reg = <0x0 0xff160010 0x0 0x10>; 421 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 422 clock-names = "pwm", "pclk"; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&pwm9_pin>; 425 #pwm-cells = <3>; 426 status = "disabled"; 427 }; 428 429 pwm10: pwm@ff160020 { 430 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 431 reg = <0x0 0xff160020 0x0 0x10>; 432 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 433 clock-names = "pwm", "pclk"; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&pwm10_pin>; 436 #pwm-cells = <3>; 437 status = "disabled"; 438 }; 439 440 pwm11: pwm@ff160030 { 441 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 442 reg = <0x0 0xff160030 0x0 0x10>; 443 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 444 clock-names = "pwm", "pclk"; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&pwm11_pin>; 447 #pwm-cells = <3>; 448 status = "disabled"; 449 }; 450 451 pwm4: pwm@ff170000 { 452 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 453 reg = <0x0 0xff170000 0x0 0x10>; 454 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 455 clock-names = "pwm", "pclk"; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&pwm4_pin>; 458 #pwm-cells = <3>; 459 status = "disabled"; 460 }; 461 462 pwm5: pwm@ff170010 { 463 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 464 reg = <0x0 0xff170010 0x0 0x10>; 465 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 466 clock-names = "pwm", "pclk"; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pwm5_pin>; 469 #pwm-cells = <3>; 470 status = "disabled"; 471 }; 472 473 pwm6: pwm@ff170020 { 474 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 475 reg = <0x0 0xff170020 0x0 0x10>; 476 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 477 clock-names = "pwm", "pclk"; 478 pinctrl-names = "default"; 479 pinctrl-0 = <&pwm6_pin>; 480 #pwm-cells = <3>; 481 status = "disabled"; 482 }; 483 484 pwm7: pwm@ff170030 { 485 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 486 reg = <0x0 0xff170030 0x0 0x10>; 487 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 488 clock-names = "pwm", "pclk"; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&pwm7_pin>; 491 #pwm-cells = <3>; 492 status = "disabled"; 493 }; 494 495 pwm0: pwm@ff180000 { 496 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 497 reg = <0x0 0xff180000 0x0 0x10>; 498 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 499 clock-names = "pwm", "pclk"; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&pwm0_pin>; 502 #pwm-cells = <3>; 503 status = "disabled"; 504 }; 505 506 pwm1: pwm@ff180010 { 507 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 508 reg = <0x0 0xff180010 0x0 0x10>; 509 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 510 clock-names = "pwm", "pclk"; 511 pinctrl-names = "default"; 512 pinctrl-0 = <&pwm1_pin>; 513 #pwm-cells = <3>; 514 status = "disabled"; 515 }; 516 517 pwm2: pwm@ff180020 { 518 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 519 reg = <0x0 0xff180020 0x0 0x10>; 520 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 521 clock-names = "pwm", "pclk"; 522 pinctrl-names = "default"; 523 pinctrl-0 = <&pwm2_pin>; 524 #pwm-cells = <3>; 525 status = "disabled"; 526 }; 527 528 pwm3: pwm@ff180030 { 529 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 530 reg = <0x0 0xff180030 0x0 0x10>; 531 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 532 clock-names = "pwm", "pclk"; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&pwm3_pin>; 535 #pwm-cells = <3>; 536 status = "disabled"; 537 }; 538 539 rktimer: rktimer@ff1a0000 { 540 compatible = "rockchip,rk3288-timer"; 541 reg = <0x0 0xff1a0000 0x0 0x20>; 542 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 544 clock-names = "pclk", "timer"; 545 }; 546 547 saradc: saradc@ff1e0000 { 548 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 549 reg = <0x0 0xff1e0000 0x0 0x100>; 550 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 552 clock-names = "saradc", "apb_pclk"; 553 #io-channel-cells = <1>; 554 resets = <&cru SRST_SARADC_P>; 555 reset-names = "saradc-apb"; 556 status = "disabled"; 557 }; 558 559 dmac0: dma-controller@ff2c0000 { 560 compatible = "arm,pl330", "arm,primecell"; 561 reg = <0x0 0xff2c0000 0x0 0x4000>; 562 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 564 arm,pl330-periph-burst; 565 clocks = <&cru ACLK_DMAC0>; 566 clock-names = "apb_pclk"; 567 #dma-cells = <1>; 568 }; 569 570 dmac1: dma-controller@ff2d0000 { 571 compatible = "arm,pl330", "arm,primecell"; 572 reg = <0x0 0xff2d0000 0x0 0x4000>; 573 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 575 arm,pl330-periph-burst; 576 clocks = <&cru ACLK_DMAC1>; 577 clock-names = "apb_pclk"; 578 #dma-cells = <1>; 579 }; 580 581 /* 582 * - can be clock producer or consumer 583 * - up to 8 capture channels and 2 playback channels 584 * - connected internally to audio codec 585 */ 586 i2s_8ch_2: i2s@ff320000 { 587 compatible = "rockchip,rk3308-i2s-tdm"; 588 reg = <0x0 0xff320000 0x0 0x1000>; 589 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 590 clock-names = "mclk_tx", "mclk_rx", "hclk"; 591 clocks = <&cru SCLK_I2S2_8CH_TX>, 592 <&cru SCLK_I2S2_8CH_RX>, 593 <&cru HCLK_I2S2_8CH>; 594 dmas = <&dmac1 5>, <&dmac1 4>; 595 dma-names = "rx", "tx"; 596 resets = <&cru SRST_I2S2_8CH_TX_M>, <&cru SRST_I2S2_8CH_RX_M>; 597 reset-names = "tx-m", "rx-m"; 598 rockchip,grf = <&grf>; 599 status = "disabled"; 600 }; 601 602 /* 603 * - can be clock consumer only 604 * - up to 4 capture channels, no playback 605 * - connected internally to audio codec 606 */ 607 i2s_8ch_3: i2s@ff330000 { 608 compatible = "rockchip,rk3308-i2s-tdm"; 609 reg = <0x0 0xff330000 0x0 0x1000>; 610 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 611 clock-names = "mclk_tx", "mclk_rx", "hclk"; 612 clocks = <&cru SCLK_I2S3_8CH_TX>, 613 <&cru SCLK_I2S3_8CH_RX>, 614 <&cru HCLK_I2S3_8CH>; 615 dmas = <&dmac1 7>; 616 dma-names = "rx"; 617 resets = <&cru SRST_I2S3_8CH_TX_M>, <&cru SRST_I2S3_8CH_RX_M>; 618 reset-names = "tx-m", "rx-m"; 619 rockchip,grf = <&grf>; 620 status = "disabled"; 621 }; 622 623 i2s_2ch_0: i2s@ff350000 { 624 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 625 reg = <0x0 0xff350000 0x0 0x1000>; 626 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>; 628 clock-names = "i2s_clk", "i2s_hclk"; 629 dmas = <&dmac1 8>, <&dmac1 9>; 630 dma-names = "tx", "rx"; 631 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>; 632 reset-names = "reset-m", "reset-h"; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&i2s_2ch_0_sclk 635 &i2s_2ch_0_lrck 636 &i2s_2ch_0_sdi 637 &i2s_2ch_0_sdo>; 638 status = "disabled"; 639 }; 640 641 i2s_2ch_1: i2s@ff360000 { 642 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 643 reg = <0x0 0xff360000 0x0 0x1000>; 644 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; 646 clock-names = "i2s_clk", "i2s_hclk"; 647 dmas = <&dmac1 11>; 648 dma-names = "rx"; 649 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>; 650 reset-names = "reset-m", "reset-h"; 651 status = "disabled"; 652 }; 653 654 spdif_tx: spdif-tx@ff3a0000 { 655 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif"; 656 reg = <0x0 0xff3a0000 0x0 0x1000>; 657 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; 659 clock-names = "mclk", "hclk"; 660 dmas = <&dmac1 13>; 661 dma-names = "tx"; 662 pinctrl-names = "default"; 663 pinctrl-0 = <&spdif_out>; 664 status = "disabled"; 665 }; 666 667 usb20_otg: usb@ff400000 { 668 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", 669 "snps,dwc2"; 670 reg = <0x0 0xff400000 0x0 0x40000>; 671 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&cru HCLK_OTG>; 673 clock-names = "otg"; 674 dr_mode = "otg"; 675 g-np-tx-fifo-size = <16>; 676 g-rx-fifo-size = <280>; 677 g-tx-fifo-size = <256 128 128 64 32 16>; 678 phys = <&u2phy_otg>; 679 phy-names = "usb2-phy"; 680 status = "disabled"; 681 }; 682 683 usb_host_ehci: usb@ff440000 { 684 compatible = "generic-ehci"; 685 reg = <0x0 0xff440000 0x0 0x10000>; 686 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; 688 phys = <&u2phy_host>; 689 phy-names = "usb"; 690 status = "disabled"; 691 }; 692 693 usb_host_ohci: usb@ff450000 { 694 compatible = "generic-ohci"; 695 reg = <0x0 0xff450000 0x0 0x10000>; 696 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; 698 phys = <&u2phy_host>; 699 phy-names = "usb"; 700 status = "disabled"; 701 }; 702 703 sdmmc: mmc@ff480000 { 704 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 705 reg = <0x0 0xff480000 0x0 0x4000>; 706 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 707 bus-width = <4>; 708 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 709 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 710 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 711 fifo-depth = <0x100>; 712 max-frequency = <150000000>; 713 pinctrl-names = "default"; 714 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 715 status = "disabled"; 716 }; 717 718 emmc: mmc@ff490000 { 719 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 720 reg = <0x0 0xff490000 0x0 0x4000>; 721 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 722 bus-width = <8>; 723 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 724 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 725 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 726 fifo-depth = <0x100>; 727 max-frequency = <150000000>; 728 status = "disabled"; 729 }; 730 731 sdio: mmc@ff4a0000 { 732 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 733 reg = <0x0 0xff4a0000 0x0 0x4000>; 734 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 735 bus-width = <4>; 736 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 737 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 738 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 739 fifo-depth = <0x100>; 740 max-frequency = <150000000>; 741 pinctrl-names = "default"; 742 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 743 status = "disabled"; 744 }; 745 746 nfc: nand-controller@ff4b0000 { 747 compatible = "rockchip,rk3308-nfc", 748 "rockchip,rv1108-nfc"; 749 reg = <0x0 0xff4b0000 0x0 0x4000>; 750 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 752 clock-names = "ahb", "nfc"; 753 assigned-clocks = <&cru SCLK_NANDC>; 754 assigned-clock-rates = <150000000>; 755 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 756 &flash_rdn &flash_rdy &flash_wrn>; 757 pinctrl-names = "default"; 758 status = "disabled"; 759 }; 760 761 gmac: ethernet@ff4e0000 { 762 compatible = "rockchip,rk3308-gmac"; 763 reg = <0x0 0xff4e0000 0x0 0x10000>; 764 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 765 interrupt-names = "macirq"; 766 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, 767 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, 768 <&cru SCLK_MAC>, <&cru ACLK_MAC>, 769 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; 770 clock-names = "stmmaceth", "mac_clk_rx", 771 "mac_clk_tx", "clk_mac_ref", 772 "clk_mac_refout", "aclk_mac", 773 "pclk_mac", "clk_mac_speed"; 774 phy-mode = "rmii"; 775 pinctrl-names = "default"; 776 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 777 resets = <&cru SRST_MAC_A>; 778 reset-names = "stmmaceth"; 779 rockchip,grf = <&grf>; 780 status = "disabled"; 781 }; 782 783 sfc: spi@ff4c0000 { 784 compatible = "rockchip,sfc"; 785 reg = <0x0 0xff4c0000 0x0 0x4000>; 786 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 788 clock-names = "clk_sfc", "hclk_sfc"; 789 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; 790 pinctrl-names = "default"; 791 status = "disabled"; 792 }; 793 794 cru: clock-controller@ff500000 { 795 compatible = "rockchip,rk3308-cru"; 796 reg = <0x0 0xff500000 0x0 0x1000>; 797 clocks = <&xin24m>; 798 clock-names = "xin24m"; 799 rockchip,grf = <&grf>; 800 #clock-cells = <1>; 801 #reset-cells = <1>; 802 assigned-clocks = <&cru SCLK_RTC32K>; 803 assigned-clock-rates = <32768>; 804 }; 805 806 codec: codec@ff560000 { 807 compatible = "rockchip,rk3308-codec"; 808 reg = <0x0 0xff560000 0x0 0x10000>; 809 rockchip,grf = <&grf>; 810 clock-names = "mclk_tx", "mclk_rx", "hclk"; 811 clocks = <&cru SCLK_I2S2_8CH_TX_OUT>, 812 <&cru SCLK_I2S2_8CH_RX_OUT>, 813 <&cru PCLK_ACODEC>; 814 reset-names = "codec"; 815 resets = <&cru SRST_ACODEC_P>; 816 #sound-dai-cells = <0>; 817 status = "disabled"; 818 }; 819 820 gic: interrupt-controller@ff580000 { 821 compatible = "arm,gic-400"; 822 reg = <0x0 0xff581000 0x0 0x1000>, 823 <0x0 0xff582000 0x0 0x2000>, 824 <0x0 0xff584000 0x0 0x2000>, 825 <0x0 0xff586000 0x0 0x2000>; 826 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 827 #interrupt-cells = <3>; 828 interrupt-controller; 829 #address-cells = <0>; 830 }; 831 832 sram: sram@fff80000 { 833 compatible = "mmio-sram"; 834 reg = <0x0 0xfff80000 0x0 0x40000>; 835 ranges = <0 0x0 0xfff80000 0x40000>; 836 #address-cells = <1>; 837 #size-cells = <1>; 838 839 /* reserved for ddr dvfs and system suspend/resume */ 840 ddr-sram@0 { 841 reg = <0x0 0x8000>; 842 }; 843 844 /* reserved for vad audio buffer */ 845 vad_sram: vad-sram@8000 { 846 reg = <0x8000 0x38000>; 847 }; 848 }; 849 850 pinctrl: pinctrl { 851 compatible = "rockchip,rk3308-pinctrl"; 852 rockchip,grf = <&grf>; 853 #address-cells = <2>; 854 #size-cells = <2>; 855 ranges; 856 857 gpio0: gpio@ff220000 { 858 compatible = "rockchip,gpio-bank"; 859 reg = <0x0 0xff220000 0x0 0x100>; 860 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&cru PCLK_GPIO0>; 862 gpio-controller; 863 #gpio-cells = <2>; 864 interrupt-controller; 865 #interrupt-cells = <2>; 866 }; 867 868 gpio1: gpio@ff230000 { 869 compatible = "rockchip,gpio-bank"; 870 reg = <0x0 0xff230000 0x0 0x100>; 871 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 872 clocks = <&cru PCLK_GPIO1>; 873 gpio-controller; 874 #gpio-cells = <2>; 875 interrupt-controller; 876 #interrupt-cells = <2>; 877 }; 878 879 gpio2: gpio@ff240000 { 880 compatible = "rockchip,gpio-bank"; 881 reg = <0x0 0xff240000 0x0 0x100>; 882 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&cru PCLK_GPIO2>; 884 gpio-controller; 885 #gpio-cells = <2>; 886 interrupt-controller; 887 #interrupt-cells = <2>; 888 }; 889 890 gpio3: gpio@ff250000 { 891 compatible = "rockchip,gpio-bank"; 892 reg = <0x0 0xff250000 0x0 0x100>; 893 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 894 clocks = <&cru PCLK_GPIO3>; 895 gpio-controller; 896 #gpio-cells = <2>; 897 interrupt-controller; 898 #interrupt-cells = <2>; 899 }; 900 901 gpio4: gpio@ff260000 { 902 compatible = "rockchip,gpio-bank"; 903 reg = <0x0 0xff260000 0x0 0x100>; 904 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&cru PCLK_GPIO4>; 906 gpio-controller; 907 #gpio-cells = <2>; 908 interrupt-controller; 909 #interrupt-cells = <2>; 910 }; 911 912 pcfg_pull_up: pcfg-pull-up { 913 bias-pull-up; 914 }; 915 916 pcfg_pull_down: pcfg-pull-down { 917 bias-pull-down; 918 }; 919 920 pcfg_pull_none: pcfg-pull-none { 921 bias-disable; 922 }; 923 924 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 925 bias-disable; 926 drive-strength = <2>; 927 }; 928 929 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 930 bias-pull-up; 931 drive-strength = <2>; 932 }; 933 934 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 935 bias-pull-up; 936 drive-strength = <4>; 937 }; 938 939 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 940 bias-disable; 941 drive-strength = <4>; 942 }; 943 944 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 945 bias-pull-down; 946 drive-strength = <4>; 947 }; 948 949 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 950 bias-disable; 951 drive-strength = <8>; 952 }; 953 954 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 955 bias-pull-up; 956 drive-strength = <8>; 957 }; 958 959 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 960 bias-disable; 961 drive-strength = <12>; 962 }; 963 964 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 965 bias-pull-up; 966 drive-strength = <12>; 967 }; 968 969 pcfg_pull_none_smt: pcfg-pull-none-smt { 970 bias-disable; 971 input-schmitt-enable; 972 }; 973 974 pcfg_output_high: pcfg-output-high { 975 output-high; 976 }; 977 978 pcfg_output_low: pcfg-output-low { 979 output-low; 980 }; 981 982 pcfg_input_high: pcfg-input-high { 983 bias-pull-up; 984 input-enable; 985 }; 986 987 pcfg_input: pcfg-input { 988 input-enable; 989 }; 990 991 emmc { 992 emmc_clk: emmc-clk { 993 rockchip,pins = 994 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 995 }; 996 997 emmc_cmd: emmc-cmd { 998 rockchip,pins = 999 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 1000 }; 1001 1002 emmc_pwren: emmc-pwren { 1003 rockchip,pins = 1004 <3 RK_PB3 2 &pcfg_pull_none>; 1005 }; 1006 1007 emmc_rstn: emmc-rstn { 1008 rockchip,pins = 1009 <3 RK_PB2 2 &pcfg_pull_none>; 1010 }; 1011 1012 emmc_bus1: emmc-bus1 { 1013 rockchip,pins = 1014 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 1015 }; 1016 1017 emmc_bus4: emmc-bus4 { 1018 rockchip,pins = 1019 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 1020 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 1021 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 1022 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 1023 }; 1024 1025 emmc_bus8: emmc-bus8 { 1026 rockchip,pins = 1027 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 1028 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 1029 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 1030 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 1031 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 1032 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 1033 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 1034 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 1035 }; 1036 }; 1037 1038 flash { 1039 flash_csn0: flash-csn0 { 1040 rockchip,pins = 1041 <3 RK_PB5 1 &pcfg_pull_none>; 1042 }; 1043 1044 flash_rdy: flash-rdy { 1045 rockchip,pins = 1046 <3 RK_PB4 1 &pcfg_pull_none>; 1047 }; 1048 1049 flash_ale: flash-ale { 1050 rockchip,pins = 1051 <3 RK_PB3 1 &pcfg_pull_none>; 1052 }; 1053 1054 flash_cle: flash-cle { 1055 rockchip,pins = 1056 <3 RK_PB1 1 &pcfg_pull_none>; 1057 }; 1058 1059 flash_wrn: flash-wrn { 1060 rockchip,pins = 1061 <3 RK_PB0 1 &pcfg_pull_none>; 1062 }; 1063 1064 flash_rdn: flash-rdn { 1065 rockchip,pins = 1066 <3 RK_PB2 1 &pcfg_pull_none>; 1067 }; 1068 1069 flash_bus8: flash-bus8 { 1070 rockchip,pins = 1071 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 1072 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 1073 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 1074 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 1075 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 1076 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 1077 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 1078 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 1079 }; 1080 }; 1081 1082 sfc { 1083 sfc_bus4: sfc-bus4 { 1084 rockchip,pins = 1085 <3 RK_PA0 3 &pcfg_pull_none>, 1086 <3 RK_PA1 3 &pcfg_pull_none>, 1087 <3 RK_PA2 3 &pcfg_pull_none>, 1088 <3 RK_PA3 3 &pcfg_pull_none>; 1089 }; 1090 1091 sfc_bus2: sfc-bus2 { 1092 rockchip,pins = 1093 <3 RK_PA0 3 &pcfg_pull_none>, 1094 <3 RK_PA1 3 &pcfg_pull_none>; 1095 }; 1096 1097 sfc_cs0: sfc-cs0 { 1098 rockchip,pins = 1099 <3 RK_PA4 3 &pcfg_pull_none>; 1100 }; 1101 1102 sfc_clk: sfc-clk { 1103 rockchip,pins = 1104 <3 RK_PA5 3 &pcfg_pull_none>; 1105 }; 1106 }; 1107 1108 gmac { 1109 rmii_pins: rmii-pins { 1110 rockchip,pins = 1111 /* mac_txen */ 1112 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 1113 /* mac_txd1 */ 1114 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 1115 /* mac_txd0 */ 1116 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 1117 /* mac_rxd0 */ 1118 <1 RK_PC4 3 &pcfg_pull_none>, 1119 /* mac_rxd1 */ 1120 <1 RK_PC5 3 &pcfg_pull_none>, 1121 /* mac_rxer */ 1122 <1 RK_PB7 3 &pcfg_pull_none>, 1123 /* mac_rxdv */ 1124 <1 RK_PC0 3 &pcfg_pull_none>, 1125 /* mac_mdio */ 1126 <1 RK_PB6 3 &pcfg_pull_none>, 1127 /* mac_mdc */ 1128 <1 RK_PB5 3 &pcfg_pull_none>; 1129 }; 1130 1131 mac_refclk_12ma: mac-refclk-12ma { 1132 rockchip,pins = 1133 <1 RK_PB4 3 &pcfg_pull_none_12ma>; 1134 }; 1135 1136 mac_refclk: mac-refclk { 1137 rockchip,pins = 1138 <1 RK_PB4 3 &pcfg_pull_none>; 1139 }; 1140 }; 1141 1142 gmac-m1 { 1143 rmiim1_pins: rmiim1-pins { 1144 rockchip,pins = 1145 /* mac_txen */ 1146 <4 RK_PB7 2 &pcfg_pull_none_12ma>, 1147 /* mac_txd1 */ 1148 <4 RK_PA5 2 &pcfg_pull_none_12ma>, 1149 /* mac_txd0 */ 1150 <4 RK_PA4 2 &pcfg_pull_none_12ma>, 1151 /* mac_rxd0 */ 1152 <4 RK_PA2 2 &pcfg_pull_none>, 1153 /* mac_rxd1 */ 1154 <4 RK_PA3 2 &pcfg_pull_none>, 1155 /* mac_rxer */ 1156 <4 RK_PA0 2 &pcfg_pull_none>, 1157 /* mac_rxdv */ 1158 <4 RK_PA1 2 &pcfg_pull_none>, 1159 /* mac_mdio */ 1160 <4 RK_PB6 2 &pcfg_pull_none>, 1161 /* mac_mdc */ 1162 <4 RK_PB5 2 &pcfg_pull_none>; 1163 }; 1164 1165 macm1_refclk_12ma: macm1-refclk-12ma { 1166 rockchip,pins = 1167 <4 RK_PB4 2 &pcfg_pull_none_12ma>; 1168 }; 1169 1170 macm1_refclk: macm1-refclk { 1171 rockchip,pins = 1172 <4 RK_PB4 2 &pcfg_pull_none>; 1173 }; 1174 }; 1175 1176 i2c0 { 1177 i2c0_xfer: i2c0-xfer { 1178 rockchip,pins = 1179 <1 RK_PD0 2 &pcfg_pull_none_smt>, 1180 <1 RK_PD1 2 &pcfg_pull_none_smt>; 1181 }; 1182 }; 1183 1184 i2c1 { 1185 i2c1_xfer: i2c1-xfer { 1186 rockchip,pins = 1187 <0 RK_PB3 1 &pcfg_pull_none_smt>, 1188 <0 RK_PB4 1 &pcfg_pull_none_smt>; 1189 }; 1190 }; 1191 1192 i2c2 { 1193 i2c2_xfer: i2c2-xfer { 1194 rockchip,pins = 1195 <2 RK_PA2 3 &pcfg_pull_none_smt>, 1196 <2 RK_PA3 3 &pcfg_pull_none_smt>; 1197 }; 1198 }; 1199 1200 i2c3-m0 { 1201 i2c3m0_xfer: i2c3m0-xfer { 1202 rockchip,pins = 1203 <0 RK_PB7 2 &pcfg_pull_none_smt>, 1204 <0 RK_PC0 2 &pcfg_pull_none_smt>; 1205 }; 1206 }; 1207 1208 i2c3-m1 { 1209 i2c3m1_xfer: i2c3m1-xfer { 1210 rockchip,pins = 1211 <3 RK_PB4 2 &pcfg_pull_none_smt>, 1212 <3 RK_PB5 2 &pcfg_pull_none_smt>; 1213 }; 1214 }; 1215 1216 i2c3-m2 { 1217 i2c3m2_xfer: i2c3m2-xfer { 1218 rockchip,pins = 1219 <2 RK_PA1 3 &pcfg_pull_none_smt>, 1220 <2 RK_PA0 3 &pcfg_pull_none_smt>; 1221 }; 1222 }; 1223 1224 i2s_2ch_0 { 1225 i2s_2ch_0_mclk: i2s-2ch-0-mclk { 1226 rockchip,pins = 1227 <4 RK_PB4 1 &pcfg_pull_none>; 1228 }; 1229 1230 i2s_2ch_0_sclk: i2s-2ch-0-sclk { 1231 rockchip,pins = 1232 <4 RK_PB5 1 &pcfg_pull_none>; 1233 }; 1234 1235 i2s_2ch_0_lrck: i2s-2ch-0-lrck { 1236 rockchip,pins = 1237 <4 RK_PB6 1 &pcfg_pull_none>; 1238 }; 1239 1240 i2s_2ch_0_sdo: i2s-2ch-0-sdo { 1241 rockchip,pins = 1242 <4 RK_PB7 1 &pcfg_pull_none>; 1243 }; 1244 1245 i2s_2ch_0_sdi: i2s-2ch-0-sdi { 1246 rockchip,pins = 1247 <4 RK_PC0 1 &pcfg_pull_none>; 1248 }; 1249 }; 1250 1251 i2s_8ch_0 { 1252 i2s_8ch_0_mclk: i2s-8ch-0-mclk { 1253 rockchip,pins = 1254 <2 RK_PA4 1 &pcfg_pull_none>; 1255 }; 1256 1257 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { 1258 rockchip,pins = 1259 <2 RK_PA5 1 &pcfg_pull_none>; 1260 }; 1261 1262 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { 1263 rockchip,pins = 1264 <2 RK_PA6 1 &pcfg_pull_none>; 1265 }; 1266 1267 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { 1268 rockchip,pins = 1269 <2 RK_PA7 1 &pcfg_pull_none>; 1270 }; 1271 1272 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { 1273 rockchip,pins = 1274 <2 RK_PB0 1 &pcfg_pull_none>; 1275 }; 1276 1277 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { 1278 rockchip,pins = 1279 <2 RK_PB1 1 &pcfg_pull_none>; 1280 }; 1281 1282 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { 1283 rockchip,pins = 1284 <2 RK_PB2 1 &pcfg_pull_none>; 1285 }; 1286 1287 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { 1288 rockchip,pins = 1289 <2 RK_PB3 1 &pcfg_pull_none>; 1290 }; 1291 1292 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { 1293 rockchip,pins = 1294 <2 RK_PB4 1 &pcfg_pull_none>; 1295 }; 1296 1297 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { 1298 rockchip,pins = 1299 <2 RK_PB5 1 &pcfg_pull_none>; 1300 }; 1301 1302 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 { 1303 rockchip,pins = 1304 <2 RK_PB6 1 &pcfg_pull_none>; 1305 }; 1306 1307 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 { 1308 rockchip,pins = 1309 <2 RK_PB7 1 &pcfg_pull_none>; 1310 }; 1311 1312 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 { 1313 rockchip,pins = 1314 <2 RK_PC0 1 &pcfg_pull_none>; 1315 }; 1316 }; 1317 1318 i2s_8ch_1_m0 { 1319 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { 1320 rockchip,pins = 1321 <1 RK_PA2 2 &pcfg_pull_none>; 1322 }; 1323 1324 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { 1325 rockchip,pins = 1326 <1 RK_PA3 2 &pcfg_pull_none>; 1327 }; 1328 1329 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { 1330 rockchip,pins = 1331 <1 RK_PA4 2 &pcfg_pull_none>; 1332 }; 1333 1334 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { 1335 rockchip,pins = 1336 <1 RK_PA5 2 &pcfg_pull_none>; 1337 }; 1338 1339 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { 1340 rockchip,pins = 1341 <1 RK_PA6 2 &pcfg_pull_none>; 1342 }; 1343 1344 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { 1345 rockchip,pins = 1346 <1 RK_PA7 2 &pcfg_pull_none>; 1347 }; 1348 1349 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 { 1350 rockchip,pins = 1351 <1 RK_PB0 2 &pcfg_pull_none>; 1352 }; 1353 1354 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 { 1355 rockchip,pins = 1356 <1 RK_PB1 2 &pcfg_pull_none>; 1357 }; 1358 1359 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 { 1360 rockchip,pins = 1361 <1 RK_PB2 2 &pcfg_pull_none>; 1362 }; 1363 1364 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 { 1365 rockchip,pins = 1366 <1 RK_PB3 2 &pcfg_pull_none>; 1367 }; 1368 }; 1369 1370 i2s_8ch_1_m1 { 1371 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { 1372 rockchip,pins = 1373 <1 RK_PB4 2 &pcfg_pull_none>; 1374 }; 1375 1376 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { 1377 rockchip,pins = 1378 <1 RK_PB5 2 &pcfg_pull_none>; 1379 }; 1380 1381 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { 1382 rockchip,pins = 1383 <1 RK_PB6 2 &pcfg_pull_none>; 1384 }; 1385 1386 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { 1387 rockchip,pins = 1388 <1 RK_PB7 2 &pcfg_pull_none>; 1389 }; 1390 1391 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { 1392 rockchip,pins = 1393 <1 RK_PC0 2 &pcfg_pull_none>; 1394 }; 1395 1396 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { 1397 rockchip,pins = 1398 <1 RK_PC1 2 &pcfg_pull_none>; 1399 }; 1400 1401 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 { 1402 rockchip,pins = 1403 <1 RK_PC2 2 &pcfg_pull_none>; 1404 }; 1405 1406 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 { 1407 rockchip,pins = 1408 <1 RK_PC3 2 &pcfg_pull_none>; 1409 }; 1410 1411 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 { 1412 rockchip,pins = 1413 <1 RK_PC4 2 &pcfg_pull_none>; 1414 }; 1415 1416 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 { 1417 rockchip,pins = 1418 <1 RK_PC5 2 &pcfg_pull_none>; 1419 }; 1420 }; 1421 1422 pdm_m0 { 1423 pdm_m0_clk: pdm-m0-clk { 1424 rockchip,pins = 1425 <1 RK_PA4 3 &pcfg_pull_none>; 1426 }; 1427 1428 pdm_m0_sdi0: pdm-m0-sdi0 { 1429 rockchip,pins = 1430 <1 RK_PB3 3 &pcfg_pull_none>; 1431 }; 1432 1433 pdm_m0_sdi1: pdm-m0-sdi1 { 1434 rockchip,pins = 1435 <1 RK_PB2 3 &pcfg_pull_none>; 1436 }; 1437 1438 pdm_m0_sdi2: pdm-m0-sdi2 { 1439 rockchip,pins = 1440 <1 RK_PB1 3 &pcfg_pull_none>; 1441 }; 1442 1443 pdm_m0_sdi3: pdm-m0-sdi3 { 1444 rockchip,pins = 1445 <1 RK_PB0 3 &pcfg_pull_none>; 1446 }; 1447 }; 1448 1449 pdm_m1 { 1450 pdm_m1_clk: pdm-m1-clk { 1451 rockchip,pins = 1452 <1 RK_PB6 4 &pcfg_pull_none>; 1453 }; 1454 1455 pdm_m1_sdi0: pdm-m1-sdi0 { 1456 rockchip,pins = 1457 <1 RK_PC5 4 &pcfg_pull_none>; 1458 }; 1459 1460 pdm_m1_sdi1: pdm-m1-sdi1 { 1461 rockchip,pins = 1462 <1 RK_PC4 4 &pcfg_pull_none>; 1463 }; 1464 1465 pdm_m1_sdi2: pdm-m1-sdi2 { 1466 rockchip,pins = 1467 <1 RK_PC3 4 &pcfg_pull_none>; 1468 }; 1469 1470 pdm_m1_sdi3: pdm-m1-sdi3 { 1471 rockchip,pins = 1472 <1 RK_PC2 4 &pcfg_pull_none>; 1473 }; 1474 }; 1475 1476 pdm_m2 { 1477 pdm_m2_clkm: pdm-m2-clkm { 1478 rockchip,pins = 1479 <2 RK_PA4 3 &pcfg_pull_none>; 1480 }; 1481 1482 pdm_m2_clk: pdm-m2-clk { 1483 rockchip,pins = 1484 <2 RK_PA6 2 &pcfg_pull_none>; 1485 }; 1486 1487 pdm_m2_sdi0: pdm-m2-sdi0 { 1488 rockchip,pins = 1489 <2 RK_PB5 2 &pcfg_pull_none>; 1490 }; 1491 1492 pdm_m2_sdi1: pdm-m2-sdi1 { 1493 rockchip,pins = 1494 <2 RK_PB6 2 &pcfg_pull_none>; 1495 }; 1496 1497 pdm_m2_sdi2: pdm-m2-sdi2 { 1498 rockchip,pins = 1499 <2 RK_PB7 2 &pcfg_pull_none>; 1500 }; 1501 1502 pdm_m2_sdi3: pdm-m2-sdi3 { 1503 rockchip,pins = 1504 <2 RK_PC0 2 &pcfg_pull_none>; 1505 }; 1506 }; 1507 1508 pwm0 { 1509 pwm0_pin: pwm0-pin { 1510 rockchip,pins = 1511 <0 RK_PB5 1 &pcfg_pull_none>; 1512 }; 1513 1514 pwm0_pin_pull_down: pwm0-pin-pull-down { 1515 rockchip,pins = 1516 <0 RK_PB5 1 &pcfg_pull_down>; 1517 }; 1518 }; 1519 1520 pwm1 { 1521 pwm1_pin: pwm1-pin { 1522 rockchip,pins = 1523 <0 RK_PB6 1 &pcfg_pull_none>; 1524 }; 1525 1526 pwm1_pin_pull_down: pwm1-pin-pull-down { 1527 rockchip,pins = 1528 <0 RK_PB6 1 &pcfg_pull_down>; 1529 }; 1530 }; 1531 1532 pwm2 { 1533 pwm2_pin: pwm2-pin { 1534 rockchip,pins = 1535 <0 RK_PB7 1 &pcfg_pull_none>; 1536 }; 1537 1538 pwm2_pin_pull_down: pwm2-pin-pull-down { 1539 rockchip,pins = 1540 <0 RK_PB7 1 &pcfg_pull_down>; 1541 }; 1542 }; 1543 1544 pwm3 { 1545 pwm3_pin: pwm3-pin { 1546 rockchip,pins = 1547 <0 RK_PC0 1 &pcfg_pull_none>; 1548 }; 1549 1550 pwm3_pin_pull_down: pwm3-pin-pull-down { 1551 rockchip,pins = 1552 <0 RK_PC0 1 &pcfg_pull_down>; 1553 }; 1554 }; 1555 1556 pwm4 { 1557 pwm4_pin: pwm4-pin { 1558 rockchip,pins = 1559 <0 RK_PA1 2 &pcfg_pull_none>; 1560 }; 1561 1562 pwm4_pin_pull_down: pwm4-pin-pull-down { 1563 rockchip,pins = 1564 <0 RK_PA1 2 &pcfg_pull_down>; 1565 }; 1566 }; 1567 1568 pwm5 { 1569 pwm5_pin: pwm5-pin { 1570 rockchip,pins = 1571 <0 RK_PC1 2 &pcfg_pull_none>; 1572 }; 1573 1574 pwm5_pin_pull_down: pwm5-pin-pull-down { 1575 rockchip,pins = 1576 <0 RK_PC1 2 &pcfg_pull_down>; 1577 }; 1578 }; 1579 1580 pwm6 { 1581 pwm6_pin: pwm6-pin { 1582 rockchip,pins = 1583 <0 RK_PC2 2 &pcfg_pull_none>; 1584 }; 1585 1586 pwm6_pin_pull_down: pwm6-pin-pull-down { 1587 rockchip,pins = 1588 <0 RK_PC2 2 &pcfg_pull_down>; 1589 }; 1590 }; 1591 1592 pwm7 { 1593 pwm7_pin: pwm7-pin { 1594 rockchip,pins = 1595 <2 RK_PB0 2 &pcfg_pull_none>; 1596 }; 1597 1598 pwm7_pin_pull_down: pwm7-pin-pull-down { 1599 rockchip,pins = 1600 <2 RK_PB0 2 &pcfg_pull_down>; 1601 }; 1602 }; 1603 1604 pwm8 { 1605 pwm8_pin: pwm8-pin { 1606 rockchip,pins = 1607 <2 RK_PB2 2 &pcfg_pull_none>; 1608 }; 1609 1610 pwm8_pin_pull_down: pwm8-pin-pull-down { 1611 rockchip,pins = 1612 <2 RK_PB2 2 &pcfg_pull_down>; 1613 }; 1614 }; 1615 1616 pwm9 { 1617 pwm9_pin: pwm9-pin { 1618 rockchip,pins = 1619 <2 RK_PB3 2 &pcfg_pull_none>; 1620 }; 1621 1622 pwm9_pin_pull_down: pwm9-pin-pull-down { 1623 rockchip,pins = 1624 <2 RK_PB3 2 &pcfg_pull_down>; 1625 }; 1626 }; 1627 1628 pwm10 { 1629 pwm10_pin: pwm10-pin { 1630 rockchip,pins = 1631 <2 RK_PB4 2 &pcfg_pull_none>; 1632 }; 1633 1634 pwm10_pin_pull_down: pwm10-pin-pull-down { 1635 rockchip,pins = 1636 <2 RK_PB4 2 &pcfg_pull_down>; 1637 }; 1638 }; 1639 1640 pwm11 { 1641 pwm11_pin: pwm11-pin { 1642 rockchip,pins = 1643 <2 RK_PC0 4 &pcfg_pull_none>; 1644 }; 1645 1646 pwm11_pin_pull_down: pwm11-pin-pull-down { 1647 rockchip,pins = 1648 <2 RK_PC0 4 &pcfg_pull_down>; 1649 }; 1650 }; 1651 1652 rtc { 1653 rtc_32k: rtc-32k { 1654 rockchip,pins = 1655 <0 RK_PC3 1 &pcfg_pull_none>; 1656 }; 1657 }; 1658 1659 sdmmc { 1660 sdmmc_clk: sdmmc-clk { 1661 rockchip,pins = 1662 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 1663 }; 1664 1665 sdmmc_cmd: sdmmc-cmd { 1666 rockchip,pins = 1667 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 1668 }; 1669 1670 sdmmc_det: sdmmc-det { 1671 rockchip,pins = 1672 <0 RK_PA3 1 &pcfg_pull_up_4ma>; 1673 }; 1674 1675 sdmmc_pwren: sdmmc-pwren { 1676 rockchip,pins = 1677 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 1678 }; 1679 1680 sdmmc_bus1: sdmmc-bus1 { 1681 rockchip,pins = 1682 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 1683 }; 1684 1685 sdmmc_bus4: sdmmc-bus4 { 1686 rockchip,pins = 1687 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 1688 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 1689 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 1690 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 1691 }; 1692 }; 1693 1694 sdio { 1695 sdio_clk: sdio-clk { 1696 rockchip,pins = 1697 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 1698 }; 1699 1700 sdio_cmd: sdio-cmd { 1701 rockchip,pins = 1702 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 1703 }; 1704 1705 sdio_pwren: sdio-pwren { 1706 rockchip,pins = 1707 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 1708 }; 1709 1710 sdio_wrpt: sdio-wrpt { 1711 rockchip,pins = 1712 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 1713 }; 1714 1715 sdio_intn: sdio-intn { 1716 rockchip,pins = 1717 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 1718 }; 1719 1720 sdio_bus1: sdio-bus1 { 1721 rockchip,pins = 1722 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 1723 }; 1724 1725 sdio_bus4: sdio-bus4 { 1726 rockchip,pins = 1727 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 1728 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 1729 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 1730 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 1731 }; 1732 }; 1733 1734 spdif_in { 1735 spdif_in: spdif-in { 1736 rockchip,pins = 1737 <0 RK_PC2 1 &pcfg_pull_none>; 1738 }; 1739 }; 1740 1741 spdif_out { 1742 spdif_out: spdif-out { 1743 rockchip,pins = 1744 <0 RK_PC1 1 &pcfg_pull_none>; 1745 }; 1746 }; 1747 1748 spi0 { 1749 spi0_clk: spi0-clk { 1750 rockchip,pins = 1751 <2 RK_PA2 2 &pcfg_pull_up_4ma>; 1752 }; 1753 1754 spi0_csn0: spi0-csn0 { 1755 rockchip,pins = 1756 <2 RK_PA3 2 &pcfg_pull_up_4ma>; 1757 }; 1758 1759 spi0_miso: spi0-miso { 1760 rockchip,pins = 1761 <2 RK_PA0 2 &pcfg_pull_up_4ma>; 1762 }; 1763 1764 spi0_mosi: spi0-mosi { 1765 rockchip,pins = 1766 <2 RK_PA1 2 &pcfg_pull_up_4ma>; 1767 }; 1768 }; 1769 1770 spi1 { 1771 spi1_clk: spi1-clk { 1772 rockchip,pins = 1773 <3 RK_PB3 3 &pcfg_pull_up_4ma>; 1774 }; 1775 1776 spi1_csn0: spi1-csn0 { 1777 rockchip,pins = 1778 <3 RK_PB5 3 &pcfg_pull_up_4ma>; 1779 }; 1780 1781 spi1_miso: spi1-miso { 1782 rockchip,pins = 1783 <3 RK_PB2 3 &pcfg_pull_up_4ma>; 1784 }; 1785 1786 spi1_mosi: spi1-mosi { 1787 rockchip,pins = 1788 <3 RK_PB4 3 &pcfg_pull_up_4ma>; 1789 }; 1790 }; 1791 1792 spi1-m1 { 1793 spi1m1_miso: spi1m1-miso { 1794 rockchip,pins = 1795 <2 RK_PA4 2 &pcfg_pull_up_4ma>; 1796 }; 1797 1798 spi1m1_mosi: spi1m1-mosi { 1799 rockchip,pins = 1800 <2 RK_PA5 2 &pcfg_pull_up_4ma>; 1801 }; 1802 1803 spi1m1_clk: spi1m1-clk { 1804 rockchip,pins = 1805 <2 RK_PA7 2 &pcfg_pull_up_4ma>; 1806 }; 1807 1808 spi1m1_csn0: spi1m1-csn0 { 1809 rockchip,pins = 1810 <2 RK_PB1 2 &pcfg_pull_up_4ma>; 1811 }; 1812 }; 1813 1814 spi2 { 1815 spi2_clk: spi2-clk { 1816 rockchip,pins = 1817 <1 RK_PD0 3 &pcfg_pull_up_4ma>; 1818 }; 1819 1820 spi2_csn0: spi2-csn0 { 1821 rockchip,pins = 1822 <1 RK_PD1 3 &pcfg_pull_up_4ma>; 1823 }; 1824 1825 spi2_miso: spi2-miso { 1826 rockchip,pins = 1827 <1 RK_PC6 3 &pcfg_pull_up_4ma>; 1828 }; 1829 1830 spi2_mosi: spi2-mosi { 1831 rockchip,pins = 1832 <1 RK_PC7 3 &pcfg_pull_up_4ma>; 1833 }; 1834 }; 1835 1836 tsadc { 1837 tsadc_otp_pin: tsadc-otp-pin { 1838 rockchip,pins = 1839 <0 RK_PB2 0 &pcfg_pull_none>; 1840 }; 1841 1842 tsadc_otp_out: tsadc-otp-out { 1843 rockchip,pins = 1844 <0 RK_PB2 1 &pcfg_pull_none>; 1845 }; 1846 }; 1847 1848 uart0 { 1849 uart0_xfer: uart0-xfer { 1850 rockchip,pins = 1851 <2 RK_PA1 1 &pcfg_pull_up>, 1852 <2 RK_PA0 1 &pcfg_pull_up>; 1853 }; 1854 1855 uart0_cts: uart0-cts { 1856 rockchip,pins = 1857 <2 RK_PA2 1 &pcfg_pull_none>; 1858 }; 1859 1860 uart0_rts: uart0-rts { 1861 rockchip,pins = 1862 <2 RK_PA3 1 &pcfg_pull_none>; 1863 }; 1864 1865 uart0_rts_pin: uart0-rts-pin { 1866 rockchip,pins = 1867 <2 RK_PA3 0 &pcfg_pull_none>; 1868 }; 1869 }; 1870 1871 uart1 { 1872 uart1_xfer: uart1-xfer { 1873 rockchip,pins = 1874 <1 RK_PD1 1 &pcfg_pull_up>, 1875 <1 RK_PD0 1 &pcfg_pull_up>; 1876 }; 1877 1878 uart1_cts: uart1-cts { 1879 rockchip,pins = 1880 <1 RK_PC6 1 &pcfg_pull_none>; 1881 }; 1882 1883 uart1_rts: uart1-rts { 1884 rockchip,pins = 1885 <1 RK_PC7 1 &pcfg_pull_none>; 1886 }; 1887 }; 1888 1889 uart2-m0 { 1890 uart2m0_xfer: uart2m0-xfer { 1891 rockchip,pins = 1892 <1 RK_PC7 2 &pcfg_pull_up>, 1893 <1 RK_PC6 2 &pcfg_pull_up>; 1894 }; 1895 }; 1896 1897 uart2-m1 { 1898 uart2m1_xfer: uart2m1-xfer { 1899 rockchip,pins = 1900 <4 RK_PD3 2 &pcfg_pull_up>, 1901 <4 RK_PD2 2 &pcfg_pull_up>; 1902 }; 1903 }; 1904 1905 uart3 { 1906 uart3_xfer: uart3-xfer { 1907 rockchip,pins = 1908 <3 RK_PB5 4 &pcfg_pull_up>, 1909 <3 RK_PB4 4 &pcfg_pull_up>; 1910 }; 1911 }; 1912 1913 uart3-m1 { 1914 uart3m1_xfer: uart3m1-xfer { 1915 rockchip,pins = 1916 <0 RK_PC2 3 &pcfg_pull_up>, 1917 <0 RK_PC1 3 &pcfg_pull_up>; 1918 }; 1919 }; 1920 1921 uart4 { 1922 uart4_xfer: uart4-xfer { 1923 rockchip,pins = 1924 <4 RK_PB1 1 &pcfg_pull_up>, 1925 <4 RK_PB0 1 &pcfg_pull_up>; 1926 }; 1927 1928 uart4_cts: uart4-cts { 1929 rockchip,pins = 1930 <4 RK_PA6 1 &pcfg_pull_none>; 1931 }; 1932 1933 uart4_rts: uart4-rts { 1934 rockchip,pins = 1935 <4 RK_PA7 1 &pcfg_pull_none>; 1936 }; 1937 1938 uart4_rts_pin: uart4-rts-pin { 1939 rockchip,pins = 1940 <4 RK_PA7 0 &pcfg_pull_none>; 1941 }; 1942 }; 1943 }; 1944}; 1945