xref: /linux/arch/arm64/boot/dts/renesas/ulcb.dtsi (revision fc2d791a43d3880496d1c729b8bd74d2c19cb4e7) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car Gen3 ULCB board
4 *
5 * Copyright (C) 2016 Renesas Electronics Corp.
6 * Copyright (C) 2016 Cogent Embedded, Inc.
7 *
8 * Sample Audio settings:
9 *
10 *	> amixer set "DVC Out" 1%
11 *	> amixer set "DVC In"  20%
12 */
13
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/input/input.h>
16
17/ {
18	model = "Renesas R-Car Gen3 ULCB board";
19
20	aliases {
21		i2c0 = &i2c0;
22		i2c1 = &i2c1;
23		i2c2 = &i2c2;
24		i2c3 = &i2c3;
25		i2c4 = &i2c4;
26		i2c5 = &i2c5;
27		i2c6 = &i2c6;
28		i2c7 = &i2c_dvfs;
29		serial0 = &scif2;
30		ethernet0 = &avb;
31		mmc0 = &sdhi2;
32		mmc1 = &sdhi0;
33	};
34
35	chosen {
36		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
37		stdout-path = "serial0:115200n8";
38	};
39
40	audio_clkout: audio-clkout {
41		/*
42		 * This is same as <&rcar_sound 0>
43		 * but needed to avoid cs2000/rcar_sound probe dead-lock
44		 */
45		compatible = "fixed-clock";
46		#clock-cells = <0>;
47		clock-frequency = <12288000>;
48	};
49
50	pcie_usb_refclk: clk-x24 {
51		compatible = "fixed-clock";
52		#clock-cells = <0>;
53		clock-frequency = <25000000>;
54	};
55
56	hdmi0-out {
57		compatible = "hdmi-connector";
58		type = "a";
59
60		port {
61			hdmi0_con: endpoint {
62				remote-endpoint = <&rcar_dw_hdmi0_out>;
63			};
64		};
65	};
66
67	keyboard {
68		compatible = "gpio-keys";
69
70		key-1 {
71			linux,code = <KEY_1>;
72			label = "SW3";
73			wakeup-source;
74			debounce-interval = <20>;
75			gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
76		};
77	};
78
79	leds {
80		compatible = "gpio-leds";
81
82		led5 {
83			gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
84		};
85		led6 {
86			gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
87		};
88	};
89
90	reg_1p8v: regulator-1p8v {
91		compatible = "regulator-fixed";
92		regulator-name = "fixed-1.8V";
93		regulator-min-microvolt = <1800000>;
94		regulator-max-microvolt = <1800000>;
95		regulator-boot-on;
96		regulator-always-on;
97	};
98
99	reg_3p3v: regulator-3p3v {
100		compatible = "regulator-fixed";
101		regulator-name = "fixed-3.3V";
102		regulator-min-microvolt = <3300000>;
103		regulator-max-microvolt = <3300000>;
104		regulator-boot-on;
105		regulator-always-on;
106	};
107
108	vcc_sdhi0: regulator-vcc-sdhi0 {
109		compatible = "regulator-fixed";
110
111		regulator-name = "SDHI0 Vcc";
112		regulator-min-microvolt = <3300000>;
113		regulator-max-microvolt = <3300000>;
114
115		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
116		enable-active-high;
117	};
118
119	vccq_sdhi0: regulator-vccq-sdhi0 {
120		compatible = "regulator-gpio";
121
122		regulator-name = "SDHI0 VccQ";
123		regulator-min-microvolt = <1800000>;
124		regulator-max-microvolt = <3300000>;
125
126		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
127		gpios-states = <1>;
128		states = <3300000 1>, <1800000 0>;
129	};
130
131	x12_clk: x12 {
132		compatible = "fixed-clock";
133		#clock-cells = <0>;
134		clock-frequency = <24576000>;
135	};
136
137	x23_clk: x23-clock {
138		compatible = "fixed-clock";
139		#clock-cells = <0>;
140		clock-frequency = <25000000>;
141	};
142};
143
144&a57_0 {
145	cpu-supply = <&dvfs>;
146};
147
148&audio_clk_a {
149	clock-frequency = <22579200>;
150};
151
152&avb {
153	pinctrl-0 = <&avb_pins>;
154	pinctrl-names = "default";
155	phy-handle = <&phy0>;
156	tx-internal-delay-ps = <2000>;
157	status = "okay";
158
159	phy0: ethernet-phy@0 {
160		compatible = "ethernet-phy-id0022.1622",
161			     "ethernet-phy-ieee802.3-c22";
162		rxc-skew-ps = <1500>;
163		reg = <0>;
164		interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
165		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
166	};
167};
168
169&du {
170	status = "okay";
171};
172
173&ehci1 {
174	status = "okay";
175};
176
177&extal_clk {
178	clock-frequency = <16666666>;
179};
180
181&extalr_clk {
182	clock-frequency = <32768>;
183};
184
185&hdmi0 {
186	status = "okay";
187
188	ports {
189		port@1 {
190			reg = <1>;
191			rcar_dw_hdmi0_out: endpoint {
192				remote-endpoint = <&hdmi0_con>;
193			};
194		};
195		port@2 {
196			reg = <2>;
197		};
198	};
199};
200
201&i2c2 {
202	pinctrl-0 = <&i2c2_pins>;
203	pinctrl-names = "default";
204
205	status = "okay";
206
207	clock-frequency = <100000>;
208
209	ak4613: codec@10 {
210		compatible = "asahi-kasei,ak4613";
211		reg = <0x10>;
212		clocks = <&rcar_sound 3>;
213
214		asahi-kasei,in1-single-end;
215		asahi-kasei,in2-single-end;
216		asahi-kasei,out1-single-end;
217		asahi-kasei,out2-single-end;
218		asahi-kasei,out3-single-end;
219		asahi-kasei,out4-single-end;
220		asahi-kasei,out5-single-end;
221		asahi-kasei,out6-single-end;
222	};
223
224	cs2000: clk-multiplier@4f {
225		#clock-cells = <0>;
226		compatible = "cirrus,cs2000-cp";
227		reg = <0x4f>;
228		clocks = <&audio_clkout>, <&x12_clk>;
229		clock-names = "clk_in", "ref_clk";
230
231		assigned-clocks = <&cs2000>;
232		assigned-clock-rates = <24576000>; /* 1/1 divide */
233	};
234};
235
236&i2c4 {
237	status = "okay";
238
239	clock-frequency = <400000>;
240
241	pcie_usb_clk: clk@68 {
242		compatible = "renesas,9fgv0841";
243		reg = <0x68>;
244		clocks = <&pcie_usb_refclk>;
245		#clock-cells = <1>;
246	};
247
248	versaclock5: clock-generator@6a {
249		compatible = "idt,5p49v5925";
250		reg = <0x6a>;
251		#clock-cells = <1>;
252		clocks = <&x23_clk>;
253		clock-names = "xin";
254		idt,shutdown = <0>;
255		idt,output-enable-active = <1>;
256	};
257};
258
259&i2c_dvfs {
260	bootph-all;
261	status = "okay";
262
263	clock-frequency = <400000>;
264
265	pmic: pmic@30 {
266		pinctrl-0 = <&irq0_pins>;
267		pinctrl-names = "default";
268
269		compatible = "rohm,bd9571mwv";
270		reg = <0x30>;
271		interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_LOW>;
272		interrupt-controller;
273		#interrupt-cells = <2>;
274		gpio-controller;
275		#gpio-cells = <2>;
276		rohm,ddr-backup-power = <0xf>;
277		rohm,rstbmode-pulse;
278
279		regulators {
280			dvfs: dvfs {
281				regulator-name = "dvfs";
282				regulator-min-microvolt = <750000>;
283				regulator-max-microvolt = <1030000>;
284				regulator-boot-on;
285				regulator-always-on;
286			};
287		};
288	};
289
290	eeprom@50 {
291		compatible = "rohm,br24t01", "atmel,24c01";
292		reg = <0x50>;
293		pagesize = <8>;
294		bootph-all;
295	};
296};
297
298&ohci1 {
299	status = "okay";
300};
301
302&pfc {
303	pinctrl-0 = <&scif_clk_pins>;
304	pinctrl-names = "default";
305
306	avb_pins: avb {
307		mux {
308			groups = "avb_link", "avb_mdio", "avb_mii";
309			function = "avb";
310		};
311
312		pins_mdio {
313			groups = "avb_mdio";
314			drive-strength = <24>;
315		};
316
317		pins_mii_tx {
318			pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
319			       "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
320			drive-strength = <12>;
321		};
322	};
323
324	i2c2_pins: i2c2 {
325		groups = "i2c2_a";
326		function = "i2c2";
327	};
328
329	irq0_pins: irq0 {
330		groups = "intc_ex_irq0";
331		function = "intc_ex";
332	};
333
334	scif2_pins: scif2 {
335		groups = "scif2_data_a";
336		function = "scif2";
337	};
338
339	scif_clk_pins: scif_clk {
340		groups = "scif_clk_a";
341		function = "scif_clk";
342	};
343
344	sdhi0_pins: sd0 {
345		groups = "sdhi0_data4", "sdhi0_ctrl";
346		function = "sdhi0";
347		power-source = <3300>;
348	};
349
350	sdhi0_pins_uhs: sd0_uhs {
351		groups = "sdhi0_data4", "sdhi0_ctrl";
352		function = "sdhi0";
353		power-source = <1800>;
354	};
355
356	sdhi2_pins: sd2 {
357		groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
358		function = "sdhi2";
359		power-source = <1800>;
360	};
361
362	sound_pins: sound {
363		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
364		function = "ssi";
365	};
366
367	sound_clk_pins: sound-clk {
368		groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
369			 "audio_clkout_a", "audio_clkout3_a";
370		function = "audio_clk";
371	};
372
373	usb1_pins: usb1 {
374		groups = "usb1";
375		function = "usb1";
376	};
377};
378
379&rcar_sound {
380	pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
381	pinctrl-names = "default";
382
383	/* audio_clkout0/1/2/3 */
384	#clock-cells = <1>;
385	clock-frequency = <12288000 11289600>;
386
387	status = "okay";
388
389	/* update <audio_clk_b> to <cs2000> */
390	clocks = <&cpg CPG_MOD 1005>,
391		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
392		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
393		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
394		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
395		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
396		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
397		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
398		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
399		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
400		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
401		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
402		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
403		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
404		 <&audio_clk_a>, <&cs2000>,
405		 <&audio_clk_c>,
406		 <&cpg CPG_MOD 922>;
407};
408
409&rpc {
410	/* Left disabled.  To be enabled by firmware when unlocked. */
411
412	flash@0 {
413		compatible = "cypress,hyperflash", "cfi-flash";
414		reg = <0>;
415
416		partitions {
417			compatible = "fixed-partitions";
418			#address-cells = <1>;
419			#size-cells = <1>;
420
421			bootparam@0 {
422				reg = <0x00000000 0x040000>;
423				read-only;
424			};
425			bl2@40000 {
426				reg = <0x00040000 0x140000>;
427				read-only;
428			};
429			cert-header-sa6@180000 {
430				reg = <0x00180000 0x040000>;
431				read-only;
432			};
433			bl31@1c0000 {
434				reg = <0x001c0000 0x040000>;
435				read-only;
436			};
437			tee@200000 {
438				reg = <0x00200000 0x440000>;
439				read-only;
440			};
441			uboot@640000 {
442				reg = <0x00640000 0x100000>;
443				read-only;
444			};
445			dtb@740000 {
446				reg = <0x00740000 0x080000>;
447			};
448			kernel@7c0000 {
449				reg = <0x007c0000 0x1400000>;
450			};
451			user@1bc0000 {
452				reg = <0x01bc0000 0x2440000>;
453			};
454		};
455	};
456};
457
458&rwdt {
459	timeout-sec = <60>;
460	status = "okay";
461};
462
463&scif2 {
464	pinctrl-0 = <&scif2_pins>;
465	pinctrl-names = "default";
466	bootph-all;
467
468	status = "okay";
469};
470
471&scif_clk {
472	clock-frequency = <14745600>;
473};
474
475&sdhi0 {
476	pinctrl-0 = <&sdhi0_pins>;
477	pinctrl-1 = <&sdhi0_pins_uhs>;
478	pinctrl-names = "default", "state_uhs";
479
480	vmmc-supply = <&vcc_sdhi0>;
481	vqmmc-supply = <&vccq_sdhi0>;
482	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
483	bus-width = <4>;
484	sd-uhs-sdr50;
485	sd-uhs-sdr104;
486	status = "okay";
487};
488
489&sdhi2 {
490	/* used for on-board 8bit eMMC */
491	pinctrl-0 = <&sdhi2_pins>;
492	pinctrl-1 = <&sdhi2_pins>;
493	pinctrl-names = "default", "state_uhs";
494
495	vmmc-supply = <&reg_3p3v>;
496	vqmmc-supply = <&reg_1p8v>;
497	bus-width = <8>;
498	mmc-hs200-1_8v;
499	mmc-hs400-1_8v;
500	no-sd;
501	no-sdio;
502	non-removable;
503	full-pwr-cycle-in-suspend;
504	status = "okay";
505};
506
507&ssi1 {
508	shared-pin;
509};
510
511/* Firmware should reserve it but sadly doesn't */
512&swdt {
513	status = "reserved";
514};
515
516&usb2_phy1 {
517	pinctrl-0 = <&usb1_pins>;
518	pinctrl-names = "default";
519
520	status = "okay";
521};
522
523
524/*
525 * For sound-test.
526 *
527 * We can switch Audio Card for testing
528 *
529 * #include "ulcb-simple-audio-card.dtsi"
530 * #include "ulcb-simple-audio-card-mix+split.dtsi"
531 * #include "ulcb-audio-graph-card.dtsi"
532 * #include "ulcb-audio-graph-card-mix+split.dtsi"
533 * #include "ulcb-audio-graph-card2-mix+split.dtsi"
534 */
535#include "ulcb-audio-graph-card2.dtsi"
536