xref: /linux/arch/arm64/boot/dts/renesas/salvator-xs.dtsi (revision 7f71507851fc7764b36a3221839607d3a45c2025)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Salvator-X 2nd version board
4 *
5 * Copyright (C) 2015-2017 Renesas Electronics Corp.
6 */
7
8#include "salvator-common.dtsi"
9
10/ {
11	model = "Renesas Salvator-X 2nd version board";
12	compatible = "renesas,salvator-xs";
13};
14
15&extal_clk {
16	clock-frequency = <16640000>;
17};
18
19&i2c4 {
20	clock-frequency = <400000>;
21
22	versaclock6: clock-generator@6a {
23		compatible = "idt,5p49v6901";
24		reg = <0x6a>;
25		#clock-cells = <1>;
26		clocks = <&x23_clk>;
27		clock-names = "xin";
28		idt,shutdown = <0>;
29		idt,output-enable-active = <1>;
30	};
31};
32
33#ifdef SOC_HAS_SATA
34&pca9654 {
35	pcie-sata-switch-hog {
36		gpio-hog;
37		gpios = <7 GPIO_ACTIVE_HIGH>;
38		output-low; /* enable SATA by default */
39		line-name = "PCIE/SATA switch";
40	};
41};
42
43/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
44#endif /* SOC_HAS_SATA */
45
46#ifdef SOC_HAS_USB2_CH3
47&ehci3 {
48	dr_mode = "otg";
49	status = "okay";
50};
51
52&hsusb3 {
53	dr_mode = "otg";
54	status = "okay";
55};
56
57&ohci3 {
58	dr_mode = "otg";
59	status = "okay";
60};
61
62&pfc {
63	/*
64	 * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
65	 *   (when SW31 is the default setting on Salvator-XS).
66	 * - If SW31 is the default setting, you cannot use USB2.0 ch3 on
67	 *   r8a77951 with Salvator-XS.
68	 *   Hence the SW31 setting must be changed like 2) below.
69	 *   1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
70	 *	- Connect GP6_3[01] to ADV7842.
71	 *   2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
72	 *	- Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
73	 *	- Connect GP6_{04,21} to ADV7842.
74	 */
75	usb2_ch3_pins: usb2_ch3 {
76		groups = "usb2_ch3";
77		function = "usb2_ch3";
78	};
79};
80
81&usb2_phy3 {
82	pinctrl-0 = <&usb2_ch3_pins>;
83	pinctrl-names = "default";
84
85	status = "okay";
86};
87#endif /* SOC_HAS_USB2_CH3 */
88