xref: /linux/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board.
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11
12/*
13 * On-board switches' states:
14 * @SW_OFF: switch's state is OFF
15 * @SW_ON:  switch's state is ON
16 */
17#define SW_OFF		0
18#define SW_ON		1
19
20/*
21 * SW_CONFIG[x] switches' states:
22 * @SW_CONFIG2:
23 *	SW_OFF - SD0 is connected to eMMC
24 *	SW_ON  - SD0 is connected to uSD0 card
25 * @SW_CONFIG3:
26 *	SW_OFF - SD2 is connected to SoC
27 *	SW_ON  - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
28 */
29#define SW_CONFIG2	SW_OFF
30#define SW_CONFIG3	SW_ON
31
32/ {
33	compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
34
35	aliases {
36		i2c1 = &i2c1;
37		mmc0 = &sdhi0;
38#if SW_CONFIG3 == SW_OFF
39		mmc2 = &sdhi2;
40#else
41		ethernet0 = &eth0;
42		ethernet1 = &eth1;
43#endif
44	};
45
46	chosen {
47		bootargs = "ignore_loglevel";
48		stdout-path = "serial0:115200n8";
49	};
50
51	memory@48000000 {
52		device_type = "memory";
53		/* First 128MB is reserved for secure area. */
54		reg = <0x0 0x48000000 0x0 0x38000000>;
55	};
56
57	vcc_sdhi0: regulator0 {
58		compatible = "regulator-fixed";
59		regulator-name = "SDHI0 Vcc";
60		regulator-min-microvolt = <3300000>;
61		regulator-max-microvolt = <3300000>;
62		gpios = <&pinctrl RZG2L_GPIO(2, 1) GPIO_ACTIVE_HIGH>;
63		enable-active-high;
64	};
65
66#if SW_CONFIG2 == SW_ON
67	vccq_sdhi0: regulator1 {
68		compatible = "regulator-gpio";
69		regulator-name = "SDHI0 VccQ";
70		regulator-min-microvolt = <1800000>;
71		regulator-max-microvolt = <3300000>;
72		gpios = <&pinctrl RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>;
73		gpios-states = <1>;
74		states = <3300000 1>, <1800000 0>;
75	};
76#else
77	reg_1p8v: regulator1 {
78		compatible = "regulator-fixed";
79		regulator-name = "fixed-1.8V";
80		regulator-min-microvolt = <1800000>;
81		regulator-max-microvolt = <1800000>;
82		regulator-boot-on;
83		regulator-always-on;
84	};
85#endif
86
87	vcc_sdhi2: regulator2 {
88		compatible = "regulator-fixed";
89		regulator-name = "SDHI2 Vcc";
90		regulator-min-microvolt = <3300000>;
91		regulator-max-microvolt = <3300000>;
92		gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>;
93		enable-active-high;
94	};
95};
96
97#if SW_CONFIG3 == SW_ON
98&eth0 {
99	pinctrl-0 = <&eth0_pins>;
100	pinctrl-names = "default";
101	phy-handle = <&phy0>;
102	phy-mode = "rgmii-id";
103	status = "okay";
104
105	phy0: ethernet-phy@7 {
106		reg = <7>;
107		interrupts-extended = <&pinctrl RZG2L_GPIO(12, 0) IRQ_TYPE_EDGE_FALLING>;
108		rxc-skew-psec = <0>;
109		txc-skew-psec = <0>;
110		rxdv-skew-psec = <0>;
111		txen-skew-psec = <0>;
112		rxd0-skew-psec = <0>;
113		rxd1-skew-psec = <0>;
114		rxd2-skew-psec = <0>;
115		rxd3-skew-psec = <0>;
116		txd0-skew-psec = <0>;
117		txd1-skew-psec = <0>;
118		txd2-skew-psec = <0>;
119		txd3-skew-psec = <0>;
120	};
121};
122
123&eth1 {
124	pinctrl-0 = <&eth1_pins>;
125	pinctrl-names = "default";
126	phy-handle = <&phy1>;
127	phy-mode = "rgmii-id";
128	status = "okay";
129
130	phy1: ethernet-phy@7 {
131		reg = <7>;
132		interrupts-extended = <&pinctrl RZG2L_GPIO(12, 1) IRQ_TYPE_EDGE_FALLING>;
133		rxc-skew-psec = <0>;
134		txc-skew-psec = <0>;
135		rxdv-skew-psec = <0>;
136		txen-skew-psec = <0>;
137		rxd0-skew-psec = <0>;
138		rxd1-skew-psec = <0>;
139		rxd2-skew-psec = <0>;
140		rxd3-skew-psec = <0>;
141		txd0-skew-psec = <0>;
142		txd1-skew-psec = <0>;
143		txd2-skew-psec = <0>;
144		txd3-skew-psec = <0>;
145	};
146};
147#endif
148
149&extal_clk {
150	clock-frequency = <24000000>;
151};
152
153&i2c1 {
154	status = "okay";
155};
156
157#if SW_CONFIG2 == SW_ON
158/* SD0 slot */
159&sdhi0 {
160	pinctrl-0 = <&sdhi0_pins>;
161	pinctrl-1 = <&sdhi0_uhs_pins>;
162	pinctrl-names = "default", "state_uhs";
163	vmmc-supply = <&vcc_sdhi0>;
164	vqmmc-supply = <&vccq_sdhi0>;
165	bus-width = <4>;
166	sd-uhs-sdr50;
167	sd-uhs-sdr104;
168	max-frequency = <125000000>;
169	status = "okay";
170};
171#else
172/* eMMC */
173&sdhi0 {
174	pinctrl-0 = <&sdhi0_emmc_pins>;
175	pinctrl-1 = <&sdhi0_emmc_pins>;
176	pinctrl-names = "default", "state_uhs";
177	vmmc-supply = <&vcc_sdhi0>;
178	vqmmc-supply = <&reg_1p8v>;
179	bus-width = <8>;
180	mmc-hs200-1_8v;
181	non-removable;
182	fixed-emmc-driver-type = <1>;
183	max-frequency = <125000000>;
184	status = "okay";
185};
186#endif
187
188#if SW_CONFIG3 == SW_OFF
189&sdhi2 {
190	pinctrl-0 = <&sdhi2_pins>;
191	pinctrl-names = "default";
192	vmmc-supply = <&vcc_sdhi2>;
193	bus-width = <4>;
194	max-frequency = <50000000>;
195	status = "okay";
196};
197#endif
198
199&pinctrl {
200#if SW_CONFIG3 == SW_ON
201	eth0-phy-irq-hog {
202		gpio-hog;
203		gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>;
204		input;
205		line-name = "eth0-phy-irq";
206	};
207#endif
208
209	eth0_pins: eth0 {
210		txc {
211			pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>;  /* ET0_TXC */
212			power-source = <1800>;
213			output-enable;
214			input-enable;
215			drive-strength-microamp = <5200>;
216		};
217
218		tx_ctl {
219			pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>;  /* ET0_TX_CTL */
220			power-source = <1800>;
221			output-enable;
222			drive-strength-microamp = <5200>;
223		};
224
225		mux {
226			pinmux = <RZG2L_PORT_PINMUX(1, 2, 1)>,	/* ET0_TXD0 */
227				 <RZG2L_PORT_PINMUX(1, 3, 1)>,	/* ET0_TXD1 */
228				 <RZG2L_PORT_PINMUX(1, 4, 1)>,	/* ET0_TXD2 */
229				 <RZG2L_PORT_PINMUX(2, 0, 1)>,	/* ET0_TXD3 */
230				 <RZG2L_PORT_PINMUX(3, 0, 1)>,	/* ET0_RXC */
231				 <RZG2L_PORT_PINMUX(3, 1, 1)>,	/* ET0_RX_CTL */
232				 <RZG2L_PORT_PINMUX(3, 2, 1)>,	/* ET0_RXD0 */
233				 <RZG2L_PORT_PINMUX(3, 3, 1)>,	/* ET0_RXD1 */
234				 <RZG2L_PORT_PINMUX(4, 0, 1)>,	/* ET0_RXD2 */
235				 <RZG2L_PORT_PINMUX(4, 1, 1)>,	/* ET0_RXD3 */
236				 <RZG2L_PORT_PINMUX(4, 3, 1)>,	/* ET0_MDC */
237				 <RZG2L_PORT_PINMUX(4, 4, 1)>,	/* ET0_MDIO */
238				 <RZG2L_PORT_PINMUX(4, 5, 1)>;	/* ET0_LINKSTA */
239			power-source = <1800>;
240		};
241	};
242
243#if SW_CONFIG3 == SW_ON
244	eth1-phy-irq-hog {
245		gpio-hog;
246		gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>;
247		input;
248		line-name = "eth1-phy-irq";
249	};
250#endif
251
252	eth1_pins: eth1 {
253		txc {
254			pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>;	/* ET1_TXC */
255			power-source = <1800>;
256			output-enable;
257			input-enable;
258			drive-strength-microamp = <5200>;
259		};
260
261		tx_ctl {
262			pinmux = <RZG2L_PORT_PINMUX(7, 1, 1)>;	/* ET1_TX_CTL */
263			power-source = <1800>;
264			output-enable;
265			drive-strength-microamp = <5200>;
266		};
267
268		mux {
269			pinmux = <RZG2L_PORT_PINMUX(7, 2, 1)>,	/* ET1_TXD0 */
270				 <RZG2L_PORT_PINMUX(7, 3, 1)>,	/* ET1_TXD1 */
271				 <RZG2L_PORT_PINMUX(7, 4, 1)>,	/* ET1_TXD2 */
272				 <RZG2L_PORT_PINMUX(8, 0, 1)>,	/* ET1_TXD3 */
273				 <RZG2L_PORT_PINMUX(8, 4, 1)>,	/* ET1_RXC */
274				 <RZG2L_PORT_PINMUX(9, 0, 1)>,	/* ET1_RX_CTL */
275				 <RZG2L_PORT_PINMUX(9, 1, 1)>,	/* ET1_RXD0 */
276				 <RZG2L_PORT_PINMUX(9, 2, 1)>,	/* ET1_RXD1 */
277				 <RZG2L_PORT_PINMUX(9, 3, 1)>,	/* ET1_RXD2 */
278				 <RZG2L_PORT_PINMUX(10, 0, 1)>,	/* ET1_RXD3 */
279				 <RZG2L_PORT_PINMUX(10, 2, 1)>,	/* ET1_MDC */
280				 <RZG2L_PORT_PINMUX(10, 3, 1)>,	/* ET1_MDIO */
281				 <RZG2L_PORT_PINMUX(10, 4, 1)>;	/* ET1_LINKSTA */
282			power-source = <1800>;
283		};
284	};
285
286	sdhi0_pins: sd0 {
287		data {
288			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
289			power-source = <3300>;
290		};
291
292		ctrl {
293			pins = "SD0_CLK", "SD0_CMD";
294			power-source = <3300>;
295		};
296
297		cd {
298			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
299		};
300	};
301
302	sdhi0_uhs_pins: sd0-uhs {
303		data {
304			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
305			power-source = <1800>;
306		};
307
308		ctrl {
309			pins = "SD0_CLK", "SD0_CMD";
310			power-source = <1800>;
311		};
312
313		cd {
314			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
315		};
316	};
317
318	sdhi0_emmc_pins: sd0-emmc {
319		pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
320		       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
321		       "SD0_CLK", "SD0_CMD", "SD0_RST#";
322		power-source = <1800>;
323	};
324
325	sdhi2_pins: sd2 {
326		data {
327			pins = "P11_2", "P11_3", "P12_0", "P12_1";
328			input-enable;
329		};
330
331		ctrl {
332			pins = "P11_1";
333			input-enable;
334		};
335
336		mux {
337			pinmux = <RZG2L_PORT_PINMUX(11, 0, 8)>, /* SD2_CLK */
338				 <RZG2L_PORT_PINMUX(11, 1, 8)>, /* SD2_CMD */
339				 <RZG2L_PORT_PINMUX(11, 2, 8)>, /* SD2_DATA0 */
340				 <RZG2L_PORT_PINMUX(11, 3, 8)>, /* SD2_DATA1 */
341				 <RZG2L_PORT_PINMUX(12, 0, 8)>, /* SD2_DATA2 */
342				 <RZG2L_PORT_PINMUX(12, 1, 8)>, /* SD2_DATA3 */
343				 <RZG2L_PORT_PINMUX(14, 1, 7)>; /* SD2_CD# */
344		};
345	};
346};
347
348&rtc {
349	status = "okay";
350};
351
352&vbattb {
353	assigned-clocks = <&vbattb VBATTB_MUX>;
354	assigned-clock-parents = <&vbattb VBATTB_XC>;
355	quartz-load-femtofarads = <12500>;
356	status = "okay";
357};
358
359&vbattb_xtal {
360	clock-frequency = <32768>;
361};
362
363&wdt0 {
364	timeout-sec = <60>;
365	status = "okay";
366};
367