xref: /linux/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi (revision 06d07429858317ded2db7986113a9e0129cd599b) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board.
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11/*
12 * On-board switches' states:
13 * @SW_OFF: switch's state is OFF
14 * @SW_ON:  switch's state is ON
15 */
16#define SW_OFF		0
17#define SW_ON		1
18
19/*
20 * SW_CONFIG[x] switches' states:
21 * @SW_CONFIG2:
22 *	SW_OFF - SD0 is connected to eMMC
23 *	SW_ON  - SD0 is connected to uSD0 card
24 * @SW_CONFIG3:
25 *	SW_OFF - SD2 is connected to SoC
26 *	SW_ON  - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
27 */
28#define SW_CONFIG2	SW_ON
29#define SW_CONFIG3	SW_ON
30
31/ {
32	compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
33
34	aliases {
35		mmc0 = &sdhi0;
36#if SW_CONFIG3 == SW_OFF
37		mmc2 = &sdhi2;
38#else
39		eth0 = &eth0;
40		eth1 = &eth1;
41#endif
42	};
43
44	chosen {
45		bootargs = "ignore_loglevel";
46		stdout-path = "serial0:115200n8";
47	};
48
49	memory@48000000 {
50		device_type = "memory";
51		/* First 128MB is reserved for secure area. */
52		reg = <0x0 0x48000000 0x0 0x38000000>;
53	};
54
55	vcc_sdhi0: regulator0 {
56		compatible = "regulator-fixed";
57		regulator-name = "SDHI0 Vcc";
58		regulator-min-microvolt = <3300000>;
59		regulator-max-microvolt = <3300000>;
60		gpios = <&pinctrl RZG2L_GPIO(2, 1) GPIO_ACTIVE_HIGH>;
61		enable-active-high;
62	};
63
64#if SW_CONFIG2 == SW_ON
65	vccq_sdhi0: regulator1 {
66		compatible = "regulator-gpio";
67		regulator-name = "SDHI0 VccQ";
68		regulator-min-microvolt = <1800000>;
69		regulator-max-microvolt = <3300000>;
70		gpios = <&pinctrl RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>;
71		gpios-states = <1>;
72		states = <3300000 1>, <1800000 0>;
73	};
74#else
75	reg_1p8v: regulator1 {
76		compatible = "regulator-fixed";
77		regulator-name = "fixed-1.8V";
78		regulator-min-microvolt = <1800000>;
79		regulator-max-microvolt = <1800000>;
80		regulator-boot-on;
81		regulator-always-on;
82	};
83#endif
84
85	vcc_sdhi2: regulator2 {
86		compatible = "regulator-fixed";
87		regulator-name = "SDHI2 Vcc";
88		regulator-min-microvolt = <3300000>;
89		regulator-max-microvolt = <3300000>;
90		gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>;
91		enable-active-high;
92	};
93};
94
95#if SW_CONFIG3 == SW_ON
96&eth0 {
97	pinctrl-0 = <&eth0_pins>;
98	pinctrl-names = "default";
99	phy-handle = <&phy0>;
100	phy-mode = "rgmii-id";
101	status = "okay";
102
103	phy0: ethernet-phy@7 {
104		reg = <7>;
105		interrupt-parent = <&pinctrl>;
106		interrupts = <RZG2L_GPIO(12, 0) IRQ_TYPE_EDGE_FALLING>;
107		rxc-skew-psec = <0>;
108		txc-skew-psec = <0>;
109		rxdv-skew-psec = <0>;
110		txen-skew-psec = <0>;
111		rxd0-skew-psec = <0>;
112		rxd1-skew-psec = <0>;
113		rxd2-skew-psec = <0>;
114		rxd3-skew-psec = <0>;
115		txd0-skew-psec = <0>;
116		txd1-skew-psec = <0>;
117		txd2-skew-psec = <0>;
118		txd3-skew-psec = <0>;
119	};
120};
121
122&eth1 {
123	pinctrl-0 = <&eth1_pins>;
124	pinctrl-names = "default";
125	phy-handle = <&phy1>;
126	phy-mode = "rgmii-id";
127	status = "okay";
128
129	phy1: ethernet-phy@7 {
130		reg = <7>;
131		interrupt-parent = <&pinctrl>;
132		interrupts = <RZG2L_GPIO(12, 1) IRQ_TYPE_EDGE_FALLING>;
133		rxc-skew-psec = <0>;
134		txc-skew-psec = <0>;
135		rxdv-skew-psec = <0>;
136		txen-skew-psec = <0>;
137		rxd0-skew-psec = <0>;
138		rxd1-skew-psec = <0>;
139		rxd2-skew-psec = <0>;
140		rxd3-skew-psec = <0>;
141		txd0-skew-psec = <0>;
142		txd1-skew-psec = <0>;
143		txd2-skew-psec = <0>;
144		txd3-skew-psec = <0>;
145	};
146};
147#endif
148
149&extal_clk {
150	clock-frequency = <24000000>;
151};
152
153#if SW_CONFIG2 == SW_ON
154/* SD0 slot */
155&sdhi0 {
156	pinctrl-0 = <&sdhi0_pins>;
157	pinctrl-1 = <&sdhi0_uhs_pins>;
158	pinctrl-names = "default", "state_uhs";
159	vmmc-supply = <&vcc_sdhi0>;
160	vqmmc-supply = <&vccq_sdhi0>;
161	bus-width = <4>;
162	sd-uhs-sdr50;
163	sd-uhs-sdr104;
164	max-frequency = <125000000>;
165	status = "okay";
166};
167#else
168/* eMMC */
169&sdhi0 {
170	pinctrl-0 = <&sdhi0_emmc_pins>;
171	pinctrl-1 = <&sdhi0_emmc_pins>;
172	pinctrl-names = "default", "state_uhs";
173	vmmc-supply = <&vcc_sdhi0>;
174	vqmmc-supply = <&reg_1p8v>;
175	bus-width = <8>;
176	mmc-hs200-1_8v;
177	non-removable;
178	fixed-emmc-driver-type = <1>;
179	max-frequency = <125000000>;
180	status = "okay";
181};
182#endif
183
184#if SW_CONFIG3 == SW_OFF
185&sdhi2 {
186	pinctrl-0 = <&sdhi2_pins>;
187	pinctrl-names = "default";
188	vmmc-supply = <&vcc_sdhi2>;
189	bus-width = <4>;
190	max-frequency = <50000000>;
191	status = "okay";
192};
193#endif
194
195&pinctrl {
196	eth0-phy-irq-hog {
197		gpio-hog;
198		gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>;
199		input;
200		line-name = "eth0-phy-irq";
201	};
202
203	eth0_pins: eth0 {
204		txc {
205			pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>;  /* ET0_TXC */
206			power-source = <1800>;
207			output-enable;
208			input-enable;
209			drive-strength-microamp = <5200>;
210		};
211
212		tx_ctl {
213			pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>;  /* ET0_TX_CTL */
214			power-source = <1800>;
215			output-enable;
216			drive-strength-microamp = <5200>;
217		};
218
219		mux {
220			pinmux = <RZG2L_PORT_PINMUX(1, 2, 1)>,	/* ET0_TXD0 */
221				 <RZG2L_PORT_PINMUX(1, 3, 1)>,	/* ET0_TXD1 */
222				 <RZG2L_PORT_PINMUX(1, 4, 1)>,	/* ET0_TXD2 */
223				 <RZG2L_PORT_PINMUX(2, 0, 1)>,	/* ET0_TXD3 */
224				 <RZG2L_PORT_PINMUX(3, 0, 1)>,	/* ET0_RXC */
225				 <RZG2L_PORT_PINMUX(3, 1, 1)>,	/* ET0_RX_CTL */
226				 <RZG2L_PORT_PINMUX(3, 2, 1)>,	/* ET0_RXD0 */
227				 <RZG2L_PORT_PINMUX(3, 3, 1)>,	/* ET0_RXD1 */
228				 <RZG2L_PORT_PINMUX(4, 0, 1)>,	/* ET0_RXD2 */
229				 <RZG2L_PORT_PINMUX(4, 1, 1)>,	/* ET0_RXD3 */
230				 <RZG2L_PORT_PINMUX(4, 3, 1)>,	/* ET0_MDC */
231				 <RZG2L_PORT_PINMUX(4, 4, 1)>,	/* ET0_MDIO */
232				 <RZG2L_PORT_PINMUX(4, 5, 1)>;	/* ET0_LINKSTA */
233			power-source = <1800>;
234		};
235	};
236
237	eth1-phy-irq-hog {
238		gpio-hog;
239		gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>;
240		input;
241		line-name = "eth1-phy-irq";
242	};
243
244	eth1_pins: eth1 {
245		txc {
246			pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>;	/* ET1_TXC */
247			power-source = <1800>;
248			output-enable;
249			input-enable;
250			drive-strength-microamp = <5200>;
251		};
252
253		tx_ctl {
254			pinmux = <RZG2L_PORT_PINMUX(7, 1, 1)>;	/* ET1_TX_CTL */
255			power-source = <1800>;
256			output-enable;
257			drive-strength-microamp = <5200>;
258		};
259
260		mux {
261			pinmux = <RZG2L_PORT_PINMUX(7, 2, 1)>,	/* ET1_TXD0 */
262				 <RZG2L_PORT_PINMUX(7, 3, 1)>,	/* ET1_TXD1 */
263				 <RZG2L_PORT_PINMUX(7, 4, 1)>,	/* ET1_TXD2 */
264				 <RZG2L_PORT_PINMUX(8, 0, 1)>,	/* ET1_TXD3 */
265				 <RZG2L_PORT_PINMUX(8, 4, 1)>,	/* ET1_RXC */
266				 <RZG2L_PORT_PINMUX(9, 0, 1)>,	/* ET1_RX_CTL */
267				 <RZG2L_PORT_PINMUX(9, 1, 1)>,	/* ET1_RXD0 */
268				 <RZG2L_PORT_PINMUX(9, 2, 1)>,	/* ET1_RXD1 */
269				 <RZG2L_PORT_PINMUX(9, 3, 1)>,	/* ET1_RXD2 */
270				 <RZG2L_PORT_PINMUX(10, 0, 1)>,	/* ET1_RXD3 */
271				 <RZG2L_PORT_PINMUX(10, 2, 1)>,	/* ET1_MDC */
272				 <RZG2L_PORT_PINMUX(10, 3, 1)>,	/* ET1_MDIO */
273				 <RZG2L_PORT_PINMUX(10, 4, 1)>;	/* ET1_LINKSTA */
274			power-source = <1800>;
275		};
276	};
277
278	sdhi0_pins: sd0 {
279		data {
280			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
281			power-source = <3300>;
282		};
283
284		ctrl {
285			pins = "SD0_CLK", "SD0_CMD";
286			power-source = <3300>;
287		};
288
289		cd {
290			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
291		};
292	};
293
294	sdhi0_uhs_pins: sd0-uhs {
295		data {
296			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
297			power-source = <1800>;
298		};
299
300		ctrl {
301			pins = "SD0_CLK", "SD0_CMD";
302			power-source = <1800>;
303		};
304
305		cd {
306			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
307		};
308	};
309
310	sdhi0_emmc_pins: sd0-emmc {
311		pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
312		       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
313		       "SD0_CLK", "SD0_CMD", "SD0_RST#";
314		power-source = <1800>;
315	};
316
317	sdhi2_pins: sd2 {
318		data {
319			pins = "P11_2", "P11_3", "P12_0", "P12_1";
320			input-enable;
321		};
322
323		ctrl {
324			pins = "P11_1";
325			input-enable;
326		};
327
328		mux {
329			pinmux = <RZG2L_PORT_PINMUX(11, 0, 8)>, /* SD2_CLK */
330				 <RZG2L_PORT_PINMUX(11, 1, 8)>, /* SD2_CMD */
331				 <RZG2L_PORT_PINMUX(11, 2, 8)>, /* SD2_DATA0 */
332				 <RZG2L_PORT_PINMUX(11, 3, 8)>, /* SD2_DATA1 */
333				 <RZG2L_PORT_PINMUX(12, 0, 8)>, /* SD2_DATA2 */
334				 <RZG2L_PORT_PINMUX(12, 1, 8)>, /* SD2_DATA3 */
335				 <RZG2L_PORT_PINMUX(14, 1, 7)>; /* SD2_CD# */
336		};
337	};
338};
339