1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2LC SMARC EVK parts 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 10 11#include "rzg2lc-smarc-pinfunction.dtsi" 12#include "rz-smarc-common.dtsi" 13 14/ { 15 aliases { 16 serial1 = &scif1; 17 i2c2 = &i2c2; 18 }; 19 20 osc1: cec-clock { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <12000000>; 24 }; 25 26 hdmi-out { 27 compatible = "hdmi-connector"; 28 type = "d"; 29 30 port { 31 hdmi_con_out: endpoint { 32 remote-endpoint = <&adv7535_out>; 33 }; 34 }; 35 }; 36 37#if (SW_I2S0_I2S1) 38 /delete-node/ sound; 39 40 sound_card { 41 compatible = "audio-graph-card"; 42 label = "HDMI-Audio"; 43 dais = <&i2s2_port>; 44 }; 45#endif 46}; 47 48#if (SW_SCIF_CAN || SW_RSPI_CAN) 49&canfd { 50 pinctrl-0 = <&can1_pins>; 51 52 channel0 { 53 status = "disabled"; 54 }; 55}; 56#else 57&canfd { 58 /delete-property/ pinctrl-0; 59 /delete-property/ pinctrl-names; 60 status = "disabled"; 61}; 62#endif 63 64#if (!SW_I2S0_I2S1) 65&cpu_dai { 66 sound-dai = <&ssi0>; 67}; 68#endif 69 70&dsi { 71 status = "okay"; 72 73 ports { 74 port@1 { 75 dsi0_out: endpoint { 76 data-lanes = <1 2 3 4>; 77 remote-endpoint = <&adv7535_in>; 78 }; 79 }; 80 }; 81}; 82 83&du { 84 status = "okay"; 85}; 86 87&i2c1 { 88 adv7535: hdmi@3d { 89 compatible = "adi,adv7535"; 90 reg = <0x3d>; 91 92 interrupts-extended = <&pinctrl RZG2L_GPIO(43, 1) IRQ_TYPE_EDGE_FALLING>; 93 clocks = <&osc1>; 94 clock-names = "cec"; 95 avdd-supply = <®_1p8v>; 96 dvdd-supply = <®_1p8v>; 97 pvdd-supply = <®_1p8v>; 98 a2vdd-supply = <®_1p8v>; 99 v3p3-supply = <®_3p3v>; 100 v1p2-supply = <®_1p8v>; 101 102 adi,dsi-lanes = <4>; 103 104 ports { 105 #address-cells = <1>; 106 #size-cells = <0>; 107 108 port@0 { 109 reg = <0>; 110 adv7535_in: endpoint { 111 remote-endpoint = <&dsi0_out>; 112 }; 113 }; 114 115 port@1 { 116 reg = <1>; 117 adv7535_out: endpoint { 118 remote-endpoint = <&hdmi_con_out>; 119 }; 120 }; 121 122#if (SW_I2S0_I2S1) 123 port@2 { 124 reg = <2>; 125 codec_endpoint: endpoint { 126 remote-endpoint = <&i2s2_cpu_endpoint>; 127 }; 128 }; 129#endif 130 }; 131 }; 132}; 133 134&i2c2 { 135 pinctrl-0 = <&i2c2_pins>; 136 pinctrl-names = "default"; 137 clock-frequency = <400000>; 138 139 status = "okay"; 140 141 wm8978: codec@1a { 142 compatible = "wlf,wm8978"; 143 #sound-dai-cells = <0>; 144 reg = <0x1a>; 145 }; 146 147 versa3: clock-generator@68 { 148 compatible = "renesas,5p35023"; 149 reg = <0x68>; 150 #clock-cells = <1>; 151 clocks = <&x1>; 152 153 renesas,settings = [ 154 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf 155 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 156 80 b0 45 c4 95 157 ]; 158 159 assigned-clocks = <&versa3 0>, <&versa3 1>, 160 <&versa3 2>, <&versa3 3>, 161 <&versa3 4>, <&versa3 5>; 162 assigned-clock-rates = <24000000>, <11289600>, 163 <11289600>, <12000000>, 164 <25000000>, <12288000>; 165 }; 166}; 167 168#if PMOD_MTU3 169&mtu3 { 170 pinctrl-0 = <&mtu3_pins>; 171 pinctrl-names = "default"; 172 173 status = "okay"; 174}; 175 176&spi1 { 177 status = "disabled"; 178}; 179#endif 180 181/* 182 * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board 183 * SW1 should be at position 2->3 so that SER0_CTS# line is activated 184 * SW2 should be at position 2->3 so that SER0_TX line is activated 185 * SW3 should be at position 2->3 so that SER0_RX line is activated 186 * SW4 should be at position 2->3 so that SER0_RTS# line is activated 187 */ 188#if (!SW_SCIF_CAN && PMOD1_SER0) 189&scif1 { 190 pinctrl-0 = <&scif1_pins>; 191 pinctrl-names = "default"; 192 193 uart-has-rtscts; 194 status = "okay"; 195}; 196#endif 197 198&ssi0 { 199 pinctrl-0 = <&ssi0_pins>; 200 pinctrl-names = "default"; 201 202 status = "okay"; 203 204#if (SW_I2S0_I2S1) 205 i2s2_port: port { 206 i2s2_cpu_endpoint: endpoint { 207 remote-endpoint = <&codec_endpoint>; 208 dai-format = "i2s"; 209 210 bitclock-master = <&i2s2_cpu_endpoint>; 211 frame-master = <&i2s2_cpu_endpoint>; 212 }; 213 }; 214#endif 215}; 216 217#if (SW_RSPI_CAN) 218&spi1 { 219 /delete-property/ pinctrl-0; 220 /delete-property/ pinctrl-names; 221 status = "disabled"; 222}; 223#endif 224 225&vccq_sdhi1 { 226 gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; 227}; 228