xref: /linux/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi (revision 79de4d9ade7411ffdddf0b69c87020311731d155) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11/ {
12	aliases {
13		serial1 = &scif2;
14		i2c3 = &i2c3;
15	};
16
17	osc1: cec-clock {
18		compatible = "fixed-clock";
19		#clock-cells = <0>;
20		clock-frequency = <12000000>;
21	};
22
23	hdmi-out {
24		compatible = "hdmi-connector";
25		type = "d";
26
27		port {
28			hdmi_con_out: endpoint {
29				remote-endpoint = <&adv7535_out>;
30			};
31		};
32	};
33};
34
35&cpu_dai {
36	sound-dai = <&ssi0>;
37};
38
39&dsi {
40	status = "okay";
41
42	ports {
43		#address-cells = <1>;
44		#size-cells = <0>;
45
46		port@0 {
47			reg = <0>;
48			dsi0_in: endpoint {
49			};
50		};
51
52		port@1 {
53			reg = <1>;
54			dsi0_out: endpoint {
55				data-lanes = <1 2 3 4>;
56				remote-endpoint = <&adv7535_in>;
57			};
58		};
59	};
60};
61
62&i2c1 {
63	adv7535: hdmi@3d {
64		compatible = "adi,adv7535";
65		reg = <0x3d>;
66
67		interrupt-parent = <&pinctrl>;
68		interrupts = <RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>;
69		clocks = <&osc1>;
70		clock-names = "cec";
71		avdd-supply = <&reg_1p8v>;
72		dvdd-supply = <&reg_1p8v>;
73		pvdd-supply = <&reg_1p8v>;
74		a2vdd-supply = <&reg_1p8v>;
75		v3p3-supply = <&reg_3p3v>;
76		v1p2-supply = <&reg_1p8v>;
77
78		adi,dsi-lanes = <4>;
79
80		ports {
81			#address-cells = <1>;
82			#size-cells = <0>;
83
84			port@0 {
85				reg = <0>;
86				adv7535_in: endpoint {
87					remote-endpoint = <&dsi0_out>;
88				};
89			};
90
91			port@1 {
92				reg = <1>;
93				adv7535_out: endpoint {
94					remote-endpoint = <&hdmi_con_out>;
95				};
96			};
97		};
98	};
99};
100
101&i2c3 {
102	pinctrl-0 = <&i2c3_pins>;
103	pinctrl-names = "default";
104	clock-frequency = <400000>;
105
106	status = "okay";
107
108	wm8978: codec@1a {
109		compatible = "wlf,wm8978";
110		#sound-dai-cells = <0>;
111		reg = <0x1a>;
112	};
113};
114
115#if PMOD_MTU3
116&mtu3 {
117	pinctrl-0 = <&mtu3_pins>;
118	pinctrl-names = "default";
119
120	status = "okay";
121};
122
123#if MTU3_COUNTER_Z_PHASE_SIGNAL
124/* SDHI cd pin is muxed with counter Z phase signal */
125&sdhi1 {
126	status = "disabled";
127};
128#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */
129
130&spi1 {
131	status = "disabled";
132};
133#endif /* PMOD_MTU3 */
134
135/*
136 * To enable SCIF2 (SER0) on PMOD1 (CN7)
137 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
138 * SW2 should be at position 2->3 so that SER0_TX line is activated
139 * SW3 should be at position 2->3 so that SER0_RX line is activated
140 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
141 */
142#if PMOD1_SER0
143&scif2 {
144	pinctrl-0 = <&scif2_pins>;
145	pinctrl-names = "default";
146
147	uart-has-rtscts;
148	status = "okay";
149};
150#endif
151
152&ssi0 {
153	pinctrl-0 = <&ssi0_pins>;
154	pinctrl-names = "default";
155
156	status = "okay";
157};
158
159&vccq_sdhi1 {
160	gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
161};
162